SYSTEM WITH MEMORY DEVICE SIMULATION FOR STABLE READING PROCESSES

Abstract

A system comprises a storage device and a storage device emulator. The storage device includes a plurality of memory cells, an input / output multiplexer, an input / output read amplifier, and a memory element. The input / output multiplexer selects one of the memory cells in response to a selection signal. The input / output read amplifier generates a data output signal representing a bit stored in the selected memory cell. The storage device stores the data output signal in response to a data latch signal and outputs a bit corresponding to the data output signal. The storage device emulator mimics the behavior of the storage device and generates the data latch signal.

Description

REFERENCE TO RELATED REGISTRATION The present application claims priority over preliminary US application No. 63 / 737,831, filed on December 23, 2024, the contents of which are hereby incorporated in full by reference. BACKGROUND A memory device stores and retrieves data in a system, such as an integrated circuit (IC). It can be volatile, like dynamic random-access memory (DRAM) or static random-access memory (SRAM), or non-volatile, like a one-time programmable memory (OTP) device. A memory device can have multiple memory cells arranged in rows and columns, which store data as electrical charges or resistance states. Address decoders can select one or more memory cells simultaneously for read or write operations. For data retrieval, the memory device can utilize peripheral circuitry such as read amplifiers. A read amplifier can detect and amplify the small voltage or current differences that represent the stored data, thus enabling reliable data access to memory cells. BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure are best understood with reference to the following detailed description in conjunction with the accompanying figures: Fig. 1 is a schematic block diagram illustrating an exemplary system according to various embodiments of the present disclosure; Fig. 2 is a schematic block diagram illustrating another exemplary system 200 according to various embodiments of the present disclosure; Fig. 3 is a schematic block diagram illustrating another exemplary system according to various embodiments of the present disclosure; Fig. 4 is a schematic block diagram illustrating another exemplary system according to various embodiments of the present disclosure; Fig.Figure 5 is a schematic timing diagram illustrating an exemplary acquisition window of a system according to various embodiments of the present disclosure; Figure 6 is a schematic block diagram illustrating another exemplary system according to various embodiments of the present disclosure; Figure 7 is a schematic block diagram illustrating another exemplary system according to various embodiments of the present disclosure; Figure 8 is a schematic block diagram illustrating another exemplary system according to various embodiments of the present disclosure; Figure 9 is a schematic block diagram illustrating another exemplary system according to various embodiments of the present disclosure; and Figure 1.Figure 10 is a flowchart of an exemplary method for performing a read operation on a storage device according to various embodiments of the present disclosure. DETAILED DESCRIPTION The following disclosure provides numerous different embodiments or examples of the implementation of various features of the present subject matter. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, merely examples and are not to be understood as limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features, such that the first and second features do not directly touch each other. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves to simplify and clarify matters and does not in itself represent a relationship between the various discussed embodiments and / or configurations. A read amplifier, such as a differential or single-ended read amplifier, detects and amplifies small signal differences, such as voltage or current, from memory cells to determine stored data. A differential read amplifier can be configured to read stored data by comparing two signals, such as a reference signal and a data signal. While this method improves noise immunity and reliability, it may consume more power and require a larger circuit area compared to a single-ended approach. In contrast, a single-ended read amplifier can read data by comparing the signal from a memory cell to a reference level. This approach offers lower power consumption, a smaller circuit area, and a simpler design.However, such a single-ended reading amplifier may require a current mirror to generate a stable and accurate reference current, which can be difficult due to process, voltage, or temperature variations (PVT fluctuations). To overcome these disadvantages, certain systems and methods described herein include a storage device and a storage device emulation that mimics the behavior of the storage device. This approach can, in some cases, eliminate the need for a current mirror in the single-ended read amplifier of the storage device. In at least one embodiment, the storage device emulation enables the temporal coordination between a preload signal that initializes the single-ended read amplifier and a data latch signal that captures (or buffers) and outputs a data output signal from the single-ended read amplifier, in a manner described below. Fig. 1 is a schematic block diagram illustrating an exemplary system 100 according to various embodiments of the present disclosure. As shown in Fig. 1, the exemplary system 100 comprises a storage device 110 and a storage device emulator 120. The storage device 110 stores data during write operations and enables its retrieval during a read operation. During a read operation, the storage device 110 is initialized by a preload signal (PCH) (e.g., from a signal generator), for example, to a VDD level. In response to a latch signal (LAT_B), the storage device 110 detects (or latches) a bit (Q) corresponding to a bit stored in its memory cell and outputs it. The storage device emulation 120 mimics the behavior of the storage device 110 without storing any actual data. For example, during read operations, the storage device emulation 120 generates the data latch signal (LAT_B) based on the pre-charge signal (PCH) that initializes the storage device emulation 110, e.g., to a VDD level. The storage device emulation 120 essentially replicates the same electrical characteristics (e.g., charging effects, leakage conditions, parasitic capacitances, charge / discharge behavior, and signal propagation delays) as the storage device 110. This emulation ensures time synchronization so that the storage device 110 can correctly output the stored bit (Q). The description above shows that during a read operation, both the storage device 110 and the storage device emulation 120 are initialized by a preload signal (PCH). The storage device emulation 120 then generates a data latch signal (LAT_B), while the storage device 110, in response to the data latch signal (LAT_B), captures (or stores) and outputs a bit (Q) corresponding to a bit stored in its memory cell. This design eliminates the need for a reference current from a current mirror. Furthermore, since the latch signal (LAT_B) is time-based rather than current-based, the system 110 minimizes or is not affected by PVT fluctuations, resulting in more stable read operations. Fig. 2 shows a schematic block diagram illustrating another exemplary system 200 according to various embodiments of the present disclosure. As shown in Fig. 2, the example system 200 (e.g., system 100) has one or more storage devices, e.g., storage devices 210-230 and a storage device emulator 240. Since the storage devices 210-230 are similar in structure and functionality, only storage device 210 is described in detail. The storage device 210 comprises a plurality of memory cells 250, an input / output multiplexer (IO MUX), an input / output read amplifier (IO SA), and a memory element (FF). The memory cells 250 store data during write operations and enable its retrieval during read operations. The input / output multiplexer (IO MUX) selects one of the memory cells 250 in response to a selection signal (SEL1) (e.g.from an address decoder) and connects the selected memory cell 250 to the input / output read amplifier (IO SA). In at least one embodiment, the input / output read amplifier (IO SA) is a single-ended read amplifier. During read operations, the input-output read amplifier (IO SA) is initialized by a preload signal (PCH) (e.g., from a signal generator), for example, to VDD level, and generates a data output signal (SA_B) representing the bit stored in the selected memory cell 250. The memory element (FF) receives the data output signal (SA_B) at its data input terminal and, in response to a data latch signal (LAT_B) (e.g., from the memory device emulation 240) at its clock input terminal, detects and outputs a bit (Q) corresponding to the received data output signal (SA_B). In certain embodiments, the memory element (FF) comprises a flip-flop (e.g., D-, JK-, SR-, or T-type), a shift register, another latch type, or a combination thereof. The storage device emulation 240 mimics the behavior of the storage device 250 without storing actual data. For example, the storage device emulation 240 comprises several reference cells 260, a reference multiplexer (R MUX), a resistor element 270, and a reference read amplifier (R SA). The reference multiplexer (R MUX) selects one of the reference cells 260 in response to a selection signal (SEL2) (e.g., from an address decoder) and connects the selected reference cell 260 to the reference read amplifier (R SA). During read operations, the reference read amplifier (R SA) is initialized by the preload signal (PCH), e.g., to VDD level, and generates a data latch signal (LAT_B). The resistor element 270 is connected between the connection of the reference cells 260 to the reference multiplexer (R MUX) and a ground node (VSS).In this exemplary embodiment, the resistive element 270 comprises a potentiometer and receives a control signal (CTRL) (e.g., from a signal generator) that adjusts its resistance to a predetermined value. In an alternative embodiment, the resistive element 270 comprises a resistor with a fixed resistance value. In an exemplary read operation, each multiplexer (IO MUX, R-MUX) receives a corresponding selection signal (SEL1, SEL2) that establishes connections between a selected memory cell 250 and the input / output read amplifier (IO SA), as well as between a selected reference cell 260 and the reference read amplifier (R SA). Each read amplifier (IO SA, R SA) is then initialized by a preload signal (PCH) (e.g., from a signal generator), for example, to VDD level. Subsequently, each read amplifier (IO SA, R SA) generates a corresponding signal (SA_B, LAT_B). The memory element (FF) then receives the data output signal (SA_B) at its data input terminal and, in response to the data latch signal (LAT_B) at its clock input terminal, acquires and outputs a bit (Q) corresponding to the received data output signal (SA_B). Fig. 3 is a schematic block diagram illustrating another exemplary system 300 according to various embodiments of the present disclosure. As shown in Fig. 3, the exemplary system 300 (e.g., system 100, 200) comprises a storage device 310 and a storage device emulation 320. The storage device 310 includes a plurality of memory cells 330, an input-output multiplexer (IO MUX), an input-output read amplifier (IO SA), and a memory element (FF). The memory cells 330 store data during write operations and enable its retrieval during read operations. For example, the memory cells 330 are arranged in an array of rows and columns. The memory cells 330 in each row are connected to a respective word line (WL[0]-WL[n]). The 330 memory cells in each column are connected to a respective bit line (BL[0], BL[1]) and a respective source line (SL[0], SL[1]).The input / output multiplexer (IO MUX) selects one of the memory cells 330 in response to a selection signal (SEL1) (e.g., from an address decoder) and connects a bit line (BL[0], BL[1]) assigned to the selected memory cell 330 to the input / output read amplifier (IO SA). During read operations, the input / output read amplifier (IO SA) is initialized, e.g., to a VDD level, by a preload signal (PCH) (e.g., from a signal generator) and generates a data output signal (SA_B) representing the bit stored in the selected memory cell 330. The memory element (FF) receives the data output signal (SA_B) at its data input terminal and, in response to a data latch signal (LAT_B) (e.g. from the memory device emulation 320) at its clock input terminal, acquires and outputs a bit (Q) corresponding to the received data output signal (SA_B).In certain embodiments, the storage element (FF) comprises a flip-flop (e.g., of the D, JK, SR or T type), a shift register, another latch type, or a combination thereof. The storage device emulation 320 mimics the behavior of the storage device 310 without storing actual data. For example, the storage device emulation 320 comprises a plurality of reference cells 340, a reference multiplexer (R MUX), a resistor element 350, and a reference read amplifier (R SA). The reference cells 340 are arranged in an array of rows and columns. The reference cells 340 in each row are connected to a ground node (or VSS). The reference cells 340 in each column are connected to a respective bit line (BL[0]', BL[1]') and a respective source line (SL[0]', SL[1]'). The reference multiplexer (R MUX) selects one of the reference cells 340 in response to a selection signal (SEL2) (e.g., from an address decoder) and connects one of the bit lines (BL[0]', BL[1]') assigned to the selected reference cell 340 to the reference read amplifier (R SA). During read operations, the reference read amplifier (R SA) is initialized by the preload signal (PCH), e.g., to VDD level, and generates a data latch signal (LAT_B). The resistive element 350 is connected between the connection of the reference cells 340 to the reference multiplexer (R MUX) and the ground node (or VSS). In this exemplary embodiment, the resistive element 340 comprises a potentiometer and receives a control signal (CTRL) (e.g., from a signal generator) that adjusts its resistance to a predetermined value. In an alternative embodiment, the resistive element 350 comprises a resistor with a fixed resistance value. In an exemplary read operation, each multiplexer (IO MUX, R MUX) receives a corresponding selection signal (SEL1, SEL2), establishing connections between a selected memory cell 330 and the input / output read amplifier (IO SA), and between a selected reference cell 340 and the reference read amplifier (R SA). Each read amplifier (IO SA, R SA) is then initialized by a preload signal (PCH) (e.g., from a signal generator), for example, to VDD level. Subsequently, each read amplifier (IO SA, R SA) generates a corresponding signal (SA_B, LAT_B). The memory element (FF) then receives the data output signal (SA_B) at its data input terminal and, in response to the data latch signal (LAT_B) at its clock input terminal, acquires and outputs a bit (Q) corresponding to the received data output signal (SA_B). Although the storage device 310 is shown by way of example with a pair of memory cell columns 330, it is understood that the number of memory cell columns 330 can be arbitrarily decreased or increased after reading this disclosure. Fig. 4 shows a schematic block diagram of another exemplary system 400 according to various embodiments of the present disclosure. As shown in Fig. 4, the exemplary system 400 (e.g., system 100-300) comprises a storage device 410 and a storage device emulation 420. The storage device 410 includes a plurality of memory cells (e.g., memory cell 430), an input / output multiplexer (IO-MUX), an input / output read amplifier 440, and a memory element (FF). The memory cells 430 store data during write operations and enable its retrieval during read operations. In some embodiments, the memory cell 430 is a 1T1R memory cell (one transistor, one resistor memory cell) and comprises a selection transistor (T1) and a resistor (R).In these embodiments, the resistor (R) is connected between a bit line (BL) and the first source / drain terminal of the selector transistor (T1). The selector transistor (T1) also has a second source / drain terminal connected to a source line (SL) and a gate terminal connected to a word line (WL). Alternative configurations for memory cell 430 are provided in other embodiments. The input / output multiplexer (IO MUX) selects one of the memory cells (e.g., memory cell 430) in response to a selection signal (SEL1) (e.g., from an address decoder) and connects the bit line (BL) to the input / output read amplifier 440. During read operations, the input / output read amplifier 440 is initialized by a preload signal (PCH) (e.g., from a signal generator), e.g., to a VDD level, and generates a data output signal (SA_B) representing the bit stored in memory cell 430. In some embodiments, the input / output read amplifier 440 includes a pair of read amplifier transistors (T2, T3) and a read amplifier inverter (INV1). The read amplifier transistor (T2) comprises a first source / drain terminal connected to a VDD node, a second source / drain terminal connected to a charge / discharge node (N1), and a gate terminal that receives the pre-charge signal (PCH). The read amplifier transistor (T3) comprises a first source / drain terminal connected to the charge / discharge node (N1), a second source / drain terminal connected to the input / output multiplexer (IO MUX), and a gate terminal that receives a voltage input signal (VCL) (e.g., from a signal generator). The read amplifier inverter (INV1) is connected between the charge / discharge node (N1) and a data input terminal of the memory element (FF). Alternative configurations for the input / output read amplifier (IO SA) are provided in other embodiments. The memory element (FF) receives the data output signal (SA_B) at its data input terminal and, in response to a data latch signal (LAT_B) (e.g., from memory device emulation 420) at its clock input terminal, acquires and outputs a bit (Q) corresponding to the received data output signal (SA_B). In certain embodiments, the memory element (FF) comprises a flip-flop (e.g., of type D, JK, SR, or T), a shift register, another latch type, or a combination thereof. The storage device emulation 420 mimics the behavior of the storage device 410 without actually storing data. For example, the storage device emulation 420 comprises a plurality of reference cells (e.g., reference cell 450), a reference multiplexer (R-MUX), a resistor element 460, and a reference read amplifier 470. In some embodiments, the reference cell 450 is a single-transistor reference cell (1T) (i.e., without a resistor) and comprises a reference transistor (T4) whose first source / drain terminal is connected to the reference multiplexer (R-MUX), and whose second source / drain terminal and gate terminal are connected to each other and to a ground node (or VSS). Alternative configurations for the reference cell 450 are provided in other embodiments. The reference multiplexer (R MUX) selects one of the reference cells, e.g., reference cell 450, in response to a selection signal (SEL2) (e.g., from an address decoder) and connects reference cell 450 to the reference read amplifier 470. During read operations, the reference read amplifier 470 is initialized by the preload signal (PCH), e.g., to VDD level, and generates a data latch signal (LAT_B). In some embodiments, the reference read amplifier 470 includes a pair of read amplifier transistors (T5, T6) and a read amplifier inverter (INV2). The read amplifier transistor (T5) comprises a first source / drain terminal connected to the VDD node, a second source / drain terminal connected to a charge / discharge node (N2), and a gate terminal that receives the pre-charge signal (PCH). The read amplifier transistor (T6) comprises a first source / drain terminal connected to the charge / discharge node (N2), a second source / drain terminal connected to the output of the reference multiplexer (R MUX), and a gate terminal that receives the voltage input signal (VCL). The read amplifier inverter (INV2) is connected between the charge / discharge node (N2) and a clock input of the memory element (FF). Alternative configurations for the reference read amplifier 470 are provided in other embodiments. The resistive element 460 is connected between the junction of the first source / drain terminal of the reference transistor (T4) and the reference multiplexer (R MUX), and the ground node (or VSS). In this exemplary embodiment, the resistive element 460 comprises a potentiometer and receives a control signal (CTRL) (e.g., from a signal generator) that adjusts its resistance to a predetermined value. In an alternative embodiment, the resistive element 460 comprises a resistor with a fixed resistance value. In an exemplary read operation, each multiplexer (IO MUX, R MUX) receives a corresponding selection signal (SEL1, SEL2), thereby establishing connections between a selected memory cell (e.g., memory cell 430) and the input / output read amplifier 440, and between a selected reference cell (e.g., reference cell 450) and the reference read amplifier 470. Each load / discharge node (N1, N2) is then initialized by a pre-charge signal (PCH), e.g., to a VDD level. For example, Fig. 5 shows a schematic timing diagram illustrating an exemplary measurement window 510 of a system (e.g., System 100-400) according to various embodiments of the present disclosure. As shown in Fig. 5, when the pre-charge signal (PCH) changes from high to low, the read amplifier transistor (T2, T5) connects the charge / discharge node (N1, N2) to the VDD node and charges it to VDD level.Essentially simultaneously, the word line signal (WL) changes from low to high, thereby activating the selection transistor (T1) and connecting the resistor (R) to the ground node (or VSS) via the source line (SL). Subsequently, each read amplifier 440, 470 generates a corresponding signal (SA_B, LAT_B). The storage element (FF) then receives the data output signal (SA_B) at its data input terminal and, in response to the data latch signal (LAT_B) at its clock input terminal, acquires and outputs a bit (Q) corresponding to the data output signal (SA_B). As shown in Fig. 5, the load / discharge node (N1) essentially remains at the VDD level when memory cell 430 stores a logical "1". Consequently, the data output signal (SA_B) transitions from low to high earlier than the data latch signal (LAT_B). Conversely, when memory cell 430 stores a logical "0", the load / discharge node (N1) discharges from VDD to ground (or VSS). This causes the data output signal (SA_B) to transition from low to high later than the data latch signal (LAT_B). The acquisition time window 510 is defined by the time difference between the transition edge of the data output signal (SA_B) when memory cell 430 stores a logical "0" and the transition edge when it stores a logical "1". This time difference ensures reliable data acquisition and distinguishes between the two logical states. In certain embodiments, the position and / or size of the acquisition time window 510 can be adjusted to ensure that the transitions of the data output signal (SA_B) and the data latch signal (LAT_B) occur within the acquisition time window 510. For example, Fig. 6 shows a schematic block diagram illustrating another exemplary system 600 according to various embodiments of the present disclosure. As shown in Fig. 6, the example system 600 differs from system 400 in that it additionally includes first and second buffer circuits 610, 620, which form an adaptation circuit that compensates for timing deviations between the preload operations of the read amplifiers 440, 470 and the latch operations of the memory elements (FFs). For example, the buffer circuit 610 receives the preload signal (PCH) at its input terminal and provides a buffered version of the preload signal (PCH) at its output terminal, which is connected to the gate terminal of the read amplifier transistor (T2, T5). This buffering synchronizes the preload process across the read amplifiers 440 and 470, particularly for the input / output read amplifier 440, which is increasingly farther from the reference read amplifier 470, thus mitigating layout-related timing deviations. Similarly, the buffer circuit 620 is connected between the output terminal of the inverter (INV2) and the clock input terminals of the memory elements (FFs). It receives the latch signal (LAT_B) and controls the memory elements (FFs). This control synchronizes the latching process across the memory elements (FFs), particularly for those memory elements (FFs) that are increasingly farther from the reference read amplifier 470, thereby further mitigating layout-related timing deviations. In some embodiments, each buffer circuit 610, 620 comprises an even number of series-connected inverters. Alternative configurations for the matching circuit are provided in other embodiments. By adjusting the drive strength and delay characteristics of the buffer circuits 610, 620, the position of the measurement window 510 can be set so that the transition of the data output signal (SA_B) occurs within the measurement window 510. This approach helps to compensate for layout-dependent timing deviations, in particular the near-far effect, in which the input-output read amplifiers 440 of the storage device 410 experience different delays at different distances from the reference read amplifier 470. Fig. 7 shows a schematic block diagram of another exemplary system 700 according to various embodiments of the present disclosure. As shown in Fig. 7, the exemplary system 700 differs from the system 400 in that each of the read amplifiers 440, 470 of the system 700 additionally has a capacitive element 710, 720. The capacitive elements 710, 720 form a discharge delay circuit which slows down the discharge rates of the charge / discharge nodes (N1, N2). For example, the capacitive element 710 is connected between the charge / discharge node (N1) and a ground node (or VSS), while the capacitive element 720 is connected between the charge / discharge node (N2) and the ground node (or VSS). This design slows down the discharge rate of the charging / discharging nodes (N1, N2) and thereby extends the duration of the detection time window 510.By adjusting the discharge characteristics of the charging / discharging node (N1, N2), the acquisition time window 510 can be extended, ensuring that the transition of the data output signal (SA_B) takes place within the acquisition time window 510. In some embodiments, each capacitive element 710, 720 can be implemented with a metal-oxide-semiconductor (MOS) capacitor, a metal-oxide-metal (MOM) capacitor, a metal-insulator-metal (MIM) capacitor, other capacitor types, or a combination thereof. Alternative configurations for the discharge delay circuit are provided in other embodiments. Fig. 8 is a schematic block diagram illustrating another exemplary system 800 according to various embodiments of the present disclosure. As shown in Fig. 8, the exemplary system 800 differs from the system 400 in that it additionally comprises first and second buffer circuits 810, 820, which form an matching circuit that compensates for timing deviations between the pre-charge operations of the read amplifiers 440, 470 and the latch operations of the memory elements (FFs). For example, the buffer circuit 810 receives the pre-charge signal (PCH) at its input terminal and provides a buffered version of the pre-charge signal (PCH) at its output terminal, which is connected to the gate terminal of the read amplifier transistor (T2, T5).This buffering synchronizes the preloading process via the read amplifiers 440, 470, especially for the input / output read amplifiers 440, which are increasingly further away from the reference read amplifier 470, thereby mitigating layout-related timing deviations. Similarly, the buffer circuit 820 is connected between the output terminal of the inverter (INV2) and the clock input terminals of the memory elements. It receives the latch signal (LAT_B) and controls the memory elements (FFs). This control synchronizes the latching process across the memory elements (FFs), particularly for those memory elements (FFs) that are increasingly farther from the reference read amplifier 470, thereby further mitigating layout-related timing deviations. In some embodiments, each buffer circuit 810, 820 comprises an even number of series-connected inverters. Alternative configurations for the buffer circuits 810, 820 are provided in other embodiments. By adjusting the drive strength and delay characteristics of the buffer circuits 810 and 820, the position of the acquisition time window 510 can be set so that the transition of the data output signal (SA_B) occurs within the acquisition time window 510. This approach helps to compensate for layout-related timing deviations, in particular the near-far effect, where the input-output read amplifiers 440 experience different delays at different distances from the reference read amplifier 470. Furthermore, each read amplifier 440, 470 of the system 800 includes a capacitive element 830, 840. The capacitive elements 830, 840 form a discharge delay circuit that slows down the discharge rates of the charge / discharge nodes (N1, N2). For example, the capacitive element 830 is connected across the charge / discharge node (N1) and a ground node (or VSS), while the capacitive element 840 is connected across the charge / discharge node (N2) and the ground node (or VSS). This design slows down the discharge rate of the charge / discharge nodes (N1, N2) and thereby extends the duration of the acquisition time window 510. By adjusting the discharge characteristics of the charge / discharge node (N1, N2), the acquisition time window 510 can be extended, ensuring that the transition of the data output signal (SA_B) occurs within the acquisition time window 510. In some embodiments, each capacitive element 830, 840 can be implemented with a metal-oxide-semiconductor (MOS) capacitor, a metal-oxide-metal (MOM) capacitor, a metal-insulator-metal (MIM) capacitor, other capacitor types or a combination thereof. Fig. 9 shows a schematic block diagram of another exemplary system 900 according to various embodiments of the present disclosure. As shown in Fig. 9, the exemplary system 900 differs from the system 200 in that the resistive element 910 of the memory device emulation 240 is connected between the connection of the reference multiplexer (R MUX) and the reference read amplifier (R SA) and the ground node (or VSS). This design enables the reference multiplexer (R MUX) to better replicate the switching behavior of the input / output multiplexer (IO MUX) when selecting and connecting a memory cell to the input / output read amplifier (IO SA). By more accurately replicating the electrical characteristics of the IO MUX, the timing synchronization and signal consistency between the memory device and its emulation are improved, resulting in more stable and reliable read operations. Figure 10 is a flowchart of an exemplary method for performing a read operation on a storage device according to various embodiments of the present disclosure. For better understanding, the exemplary method 1000 is now described with reference to Figures 1-9. It is understood that the method 1000 is also applicable to structures other than those shown in Figures 1-9. Furthermore, in an alternative embodiment of the method 1000, additional operations may be performed before, during, and after the method 1000, and some of the operations described below may be substituted or omitted. In step 1010, a load / unload node (N1) of an input / output read amplifier (IO SA) of a memory device 410 is preloaded to VDD level. At this point, one of the memory cells, e.g., memory cell 430, of the memory device 410 is selected and connected to a ground node (or VSS). In step 1020, memory cell 430 is connected to the input / output read amplifier (IO SA), thus creating a path for data retrieval. Subsequently, in step 1030, the input / output read amplifier (IO SA) generates a data output signal (SA_B) representing a bit stored in memory cell 430. Subsequently, in step 1040, the memory element (FF) detects (latches) the data output signal (SA_B) in response to a data latch signal (LAT_B) and outputs a bit (Q) corresponding to the data output signal (SA_B).Subsequently, in step 1050, the storage device emulation 420 generates the data latch signal (LAT_B) by mimicking the behavior of the storage device 410, thus ensuring temporal synchronization and stable data retrieval. In one embodiment, a system comprises a storage device and a storage device emulator. The storage device includes a plurality of memory cells, an input-output multiplexer, an input-output read amplifier, and a memory element. Each memory cell stores one data bit. The input-output multiplexer is coupled to the memory cells and selects one of the memory cells in response to a selection signal. The input-output read amplifier generates a data output signal representing a bit stored in the selected memory cell. The memory element stores the data output signal in response to a data latch signal and outputs a bit corresponding to the data output signal. The storage device emulator mimics the behavior of the storage device and generates the data latch signal. In another embodiment, a memory device emulation mimics the behavior of a memory device and comprises a plurality of reference cells, a reference multiplexer, a resistive element, and a reference read amplifier. The reference multiplexer is coupled to the reference cells and, in response to a selection signal, selects one of the reference cells and connects it to the reference read amplifier. The resistive element is connected between the connection of the reference cells to the reference multiplexer and a ground or VSS node. The reference read amplifier generates a data latch signal. In a further embodiment, a method for performing a read operation on a storage device comprises: pre-charging a load / unload node of an input / output read amplifier of a storage device to VDD level; selecting one of the memory cells of the storage device; connecting the selected memory cell to the input / output read amplifier; generating a data output signal by the input / output read amplifier representing a bit stored in the selected memory cell; buffering the data output signal in response to a data latch signal; and generating the data latch signal by mimicking the behavior of the storage device. The foregoing describes features of several embodiments to help those skilled in the art better understand the aspects of this disclosure. Those skilled in the art should be aware that they can readily use this disclosure as a basis for developing or modifying other processes and structures to achieve the same purposes and / or the same advantages as the embodiments presented herein. They should also be aware that such equivalent designs do not deviate from the meaning and scope of this disclosure and that they can make various changes, substitutions, and modifications therein without deviating from the meaning and scope of this disclosure. QUOTES INCLUDED IN THE DESCRIPTION This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature US 63 / 737,831

[0001]

Claims

System comprising: a storage device, comprising: a plurality of memory cells, each configured to store a data bit; an input / output multiplexer coupled to the memory cells, configured to select one of the memory cells in response to an initial selection signal; an input / output read amplifier configured to generate a data output signal representing a bit stored in the selected memory cell; and a memory element configured to buffer the data output signal in response to a data latch signal and output a bit corresponding to the data output signal; and a storage device emulator configured to mimic the behavior of the storage device and generate the data latch signal. System according to claim 1, wherein the memory device emulation comprises: a plurality of reference cells; a reference multiplexer coupled to the reference cells, configured to select one of the reference cells in response to a second selection signal and to connect the selected reference cell to the reference read amplifier; a resistive element connected between the connection of the reference cells and the reference multiplexer and a ground or VSS node; and the reference read amplifier configured to generate the latch signal. System according to claim 1 or 2, wherein the resistance element has a resistance that changes depending on the control signal. System according to any one of claims 1 to 3, wherein the input / output read amplifier comprises: a first transistor connected between a VDD node and a charge / discharge node; a second transistor connected between the charge / discharge node and the input / output multiplexer; and an inverter connected between the charge / discharge node and a data input terminal of the storage element. System according to any one of claims 1 to 4, wherein the reference read amplifier comprises: a first transistor connected between a VDD node and a charge / discharge node; a second transistor connected between the charge / discharge node and the reference multiplexer; and an inverter connected between the charge / discharge node and a clock input of the memory element. System according to one of claims 1 to 5, further comprising an adjustment circuit for compensating for time deviations between preloading processes of the input / output read amplifier and the reference read amplifier as well as latching processes of the storage element. System according to any one of claims 1 to 6, wherein the matching circuit comprises: a first buffer circuit for receiving a preload signal and for providing a buffered version of the preload signal to the input / output read amplifier and the reference read amplifier; and a second buffer circuit between the reference read amplifier and the storage element. System according to one of claims 1 to 7, further comprising a discharge delay circuit for slowing down the discharge rate of the input / output read amplifier and the discharge rate of the reference read amplifier. System according to one of claims 6 to 8, wherein the discharge delay circuit comprises a plurality of capacitors, each of which is connected to a charge / discharge node of an input / output read amplifier and a reference read amplifier. A storage device emulation configured to mimic the behavior of a storage device, wherein the storage device emulation comprises: a plurality of reference cells; a reference multiplexer coupled to the reference cells, which selects one of the reference cells in response to a selection signal and connects the selected reference cell to a reference read amplifier; a resistive element connected between the connection of the reference cells to the reference multiplexer and a ground or VSS node; and the reference read amplifier, which generates a data latch signal. Storage device replica according to claim 10, wherein the resistance element has a resistance that varies in response to a control signal. Storage device emulation according to claim 10 or 11, wherein the reference read amplifier comprises: a first transistor between a VDD node and a charge / discharge node; a second transistor between the charge / discharge node and the reference multiplexer; and an inverter with the charge / discharge node. Storage device replica according to one of claims 10 to 12, further comprising an adjustment circuit for compensating for time deviations between a pre-loading process of the reference read amplifier and the generation of the data latch signal by the reference read amplifier. Storage device replica according to claim 13, wherein the matching circuit comprises: a first buffer circuit for receiving a preload signal and for providing a buffered version of the preload signal at an input of the reference read amplifier; and a second buffer circuit connected to an output of the reference read amplifier. Storage device emulation according to one of claims 10 to 14, further comprising a discharge delay circuit coupled to the reference read amplifier and slowing down the discharge rate of the reference read amplifier. Memory device replica according to claim 15, wherein the discharge delay circuit comprises a capacitor connected to a charge / discharge node of the reference read amplifier. A method for performing a read operation on a storage device, comprising: pre-charging a load / unload node of an input / output read amplifier of a storage device to VDD level; selecting one of the memory cells of the storage device; connecting the selected memory cell to the input / output read amplifier; generating a data output signal by the input / output read amplifier representing a bit stored in the selected memory cell; latching the data output signal in response to a data latch signal; and generating the data latch signal by mimicking the behavior of the storage device. The method of claim 17, wherein the imitation of the behavior of the storage device comprises: precharging a load / unload node of a reference read amplifier of a storage device emulation to VDD level; selecting one of the reference cells of the storage device emulation; connecting the selected reference cell to the reference read amplifier; generating the data latch signal by the input / output read amplifier. Method according to claim 18, wherein the precharging of the charge / discharge node of the input / output read amplifier and the precharging of the charge / discharge node of the reference read amplifier are substantially synchronized by means of an matching circuit. Method according to claim 18 or 19, further comprising delaying the discharge rate of the charge / discharge node of the input / output read amplifier and the discharge rate of the charge / discharge node of the reference read amplifier by means of a discharge delay circuit.

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