Semiconductor device and method for manufacturing the same

Abstract

In a contact hole, a first side surface of an interlayer insulating film is separated from a second side surface of a first conductive film, such that a portion of the upper surface of the first conductive film is exposed by the interlayer insulating film. In the contact hole, a third side surface of an insulating film is separated from the second side surface of the first conductive film, such that a portion of the lower surface of the first conductive film is exposed by the insulating film. A connector comprises a silicide layer formed on the second side surface of the first conductive film, a barrier metal film formed on the silicide layer, and a second conductive film formed on the barrier metal film.

Description

CROSS-REFERENCE TO RELATED REGISTRATIONS

[0001] The disclosure of Japanese patent application No. 2024-129919, filed on August 6, 2024, including the description, drawings and abstract, is incorporated herein by reference in its entirety. BACKGROUND

[0002] The present invention relates to a semiconductor device and a method for manufacturing the same, in particular a semiconductor device with contact holes formed in an interlayer insulating film, and a method for manufacturing the same.

[0003] Power devices include power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) with vertical trench-gate structures. Some semiconductor devices (semiconductor chips) equipped with power devices include a resistor area in addition to the cell area where the main device is located.

[0004] The techniques listed below are revealed.

[0005] [Patent Document 1] Japanese Publication No. 2023-128002

[0006] For example, patent document 1 discloses a semiconductor device equipped with an IGBT and a resistive element. This resistive element is formed on an insulating layer and covered by an interlayer insulating film. Contact holes are formed in the interlayer insulating film, and connectors are embedded in these contact holes. One end of the resistive element is electrically connected to the gate electrode of the IGBT via a connector and gate wiring, while the other end of the resistive element is electrically connected to the gate wiring via a connector. A gate pad is formed on a portion of the gate wiring to which the other end of the resistive element is connected. SUMMARY

[0007] The following uses Fig. 27 describes an example of a semiconductor device investigated by the present inventors. This semiconductor device comprises an IGBT and a resistive element. The resistive element is formed in a conductive film PL. One end of the resistive element is electrically connected to the gate electrode of the IGBT via a connector PG, and the other end of the resistive element is electrically connected to the gate pad via a connector PG. In other words, the resistive element is connected between the gate electrode and the gate pad of the IGBT. Fig. Figure 27 shows, for example, the structure of the PG connector, which is connected to one end of the resistor element.

[0008] As in Fig. As shown in Figure 27, the connector PG comprises a barrier metal film BM1, a barrier metal film BM2, and a conductive film CF, wherein the barrier metal film BM1 is in contact with the conductive film PL, which forms the resistive element. The conductive film PL, forming the resistive element, is made of a polycrystalline silicon film. The barrier metal film BM1 is a titanium film, the barrier metal film BM2 is a titanium nitride film, and the conductive film CF is a tungsten film. The contact between the polycrystalline silicon film and the barrier metal film BM1 forms a Schottky junction. Due to the presence of interfacial defects in the polycrystalline silicon film, variations occur in the Schottky barrier, leading to variations in the resistance value of the resistive element formed in the conductive film PL.For example, variations in resistance value affect the turn-on time of the IGBT, thereby reducing the reliability of the semiconductor device.

[0009] The main objective of the present application is to suppress the resistance value variations of the resistive element, as described above, and to improve the reliability of the semiconductor device. Other problems and novel features will become apparent from the description of this application and the accompanying drawings.

[0010] A brief overview of the typical embodiments disclosed in the present application is as follows.

[0011] In one embodiment, the semiconductor device comprises a semiconductor substrate having an upper surface and a lower surface, an insulating film formed on the upper surface of the semiconductor substrate, a first conductive film formed on the insulating film, an intermediate insulating film formed on the upper surface of the semiconductor substrate to cover the first conductive film, a contact hole formed in the intermediate insulating film, the first conductive film and the insulating film, and a plug embedded in the contact hole.In the contact hole, the first side of the interlayer insulating film is separated from the second side of the first conductive film, so that part of the upper surface of the first conductive film is exposed by the interlayer insulating film, and the third side of the insulating film is separated from the second side of the first conductive film, so that part of the lower surface of the first conductive film is exposed by the insulating film. The connector comprises a silicide layer formed on the second side of the first conductive film, a barrier metal film formed on the silicide layer, and a second conductive film formed on the barrier metal film.

[0012] The method for manufacturing a semiconductor device in one embodiment comprises the steps of: (a) manufacturing a semiconductor substrate having an upper surface and a lower surface, (b) forming an insulating film on the upper surface of the semiconductor substrate according to step (a), (c) forming a first conductive film on the insulating film according to step (b), (d) forming an interlayer insulating film on the upper surface of the semiconductor substrate to cover the first conductive film according to step (c), (e) performing anisotropic dry etching on the interlayer insulating film, the first conductive film and the insulating film to form a contact hole according to step (d), (f) performing isotropic etching on the interlayer insulating film and the insulating film according to step (e), and (g) embedding a connector in the contact hole according to step (f).In step (f), the first side of the interlayer insulating film is separated from the second side of the first conductive film, so that part of the upper surface of the first conductive film is exposed by the interlayer insulating film, and the third side of the insulating film is separated from the second side of the first conductive film, so that part of the lower surface of the first conductive film is exposed by the insulating film. Step (g) comprises: (g1) performing heat treatment on the semiconductor substrate in a hydrogen atmosphere according to step (f), (g2) forming a silicide layer on the second side of the first conductive film in the contact hole according to step (g1), (g3) forming a barrier metal film on the silicide layer according to step (g2), and (g4) forming a second conductive film on the barrier metal film according to step (g3).

[0013] A method for manufacturing a semiconductor device in one embodiment is a method for manufacturing a semiconductor device with a first region and a second region that is distinct from the first region. The method comprises (a) manufacturing a semiconductor substrate with an upper surface and a lower surface, (b) according to (a), forming a first insulating film over the interior of the semiconductor substrate from a position higher than the upper surface of the semiconductor substrate in the first region, (c) according to (b), forming a trench in the semiconductor substrate of the second region on the upper surface side of the semiconductor substrate, (d) according to (c), forming a gate insulating film in the trench, (e) according to (d), forming a gate electrode on the gate insulating film to fill the trench, (f) according to (e), forming a second insulating film with a thickness that is thinner than the first insulating film.on the upper surface of the semiconductor substrate of the first region and the second region to cover the first insulating film in the first region and the gate electrode in the second region, (g) according to (f), forming a first conductive film on the second insulating film in the first region and the second region, (h) according to (g), removing the first conductive film and the second insulating film, such that the first conductive film and the second insulating film are selectively left on the first insulating film, (i) according to (h), forming a first impurity region of a first conductivity type in the semiconductor substrate of the second region on the upper surface side of the semiconductor substrate, wherein a bottom of the first impurity region is positioned above a bottom of the trench, (j) according to (i), forming a second impurity region of a second conductivity type opposite to the first conductivity type,in the first contamination area, (k) according to (j), forming an interlayer insulating film on the upper surface of the semiconductor substrate of the first area and the second area to cover the first conductive film in the first area and the gate electrode, the first contamination area and the second contamination area in the second area, (1) according to (k), performing a planarization process on the interlayer insulating film of the first area and the second area by a CMP process to flatten the upper surface of the interlayer insulating film, (m) according to (1), performing anisotropic dry etching on the interlayer insulating film, the first conductive film, the second insulating film and the first insulating film to form a first contact hole in the interlayer insulating film, the first conductive film, the second insulating film and the first insulating film of the first area,wherein a base of the first contact hole is positioned in the first insulating film, and to form a second contact hole in the interlayer insulating film, the second contamination area and the first contamination area of ​​the second area, wherein a base of the second contact hole is positioned in the first contamination area, (n) according to (m), performing isotropic etching on the interlayer insulating film, the second insulating film and the first insulating film, and (o) according to (n), embedding a first plug in the first contact hole and a second plug in the second contact hole. By (n) in the first contact hole, a first side surface of the interlayer insulating film is separated from a second side surface of the first conductive film,such that part of an upper surface of the first conductive film is exposed from the interlayer insulating film. By (n) in the first contact hole, a third side surface of the first insulating film and the second insulating film is separated from the second side surface of the first conductive film, such that part of a lower surface of the first conductive film is exposed from the first insulating film and the second insulating film. By (n) in the second contact hole, a fourth side surface of the interlayer insulating film is separated from a fifth side surface of the second contaminant region, such that part of an upper surface of the second contaminant region is exposed from the interlayer insulating film. (o) comprises (o1) according to (n), performing heat treatment on the semiconductor substrate in a hydrogen atmosphere, (o2) according to (o1),Forming a first silicide layer on the second side surface of the first conductive film in the first contact hole and forming a second silicide layer on part of an upper surface of the second contaminant area and on the fifth side surface of the second contaminant area in the second contact hole, (o3) according to (o2), forming a first barrier metal film on the first silicide layer and the second silicide layer, and (o4) according to (o3), forming a second conductive film on the first barrier metal film.

[0014] According to one embodiment, the reliability of the semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a top view showing the entirety of a semiconductor device according to the embodiment. Fig. Figure 2 is a top view showing the semiconductor device according to the embodiment. Fig. Figure 3 is a top view showing the semiconductor device according to the embodiment. FIG, 4 is an equivalent circuit diagram of the semiconductor device according to the embodiment. Fig. Figure 5 is a cross-sectional view showing the semiconductor device according to the embodiment. Fig. Figure 6 is an enlarged cross-sectional view of a part of the semiconductor device according to the embodiment. Fig. Figure 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment. Fig. 8 is a cross-sectional view showing the manufacturing process according to Fig. 7 shows. Fig. 9 is a cross-sectional view showing the manufacturing process according to Fig. 8 shows. Fig. 10 is a cross-sectional view showing the manufacturing process according to Fig. 9 shows. Fig. 11 is a cross-sectional view showing the manufacturing process according to Fig. 10 shows. Fig. 12 is a cross-sectional view showing the manufacturing process according to Fig. 11 shows. Fig. 13 is a cross-sectional view showing the manufacturing process according to Fig. 12 shows. Fig. 14 is a cross-sectional view showing the manufacturing process according to Fig. 13 shows. Fig. 15 is a cross-sectional view showing the manufacturing process according to Fig. 14 shows. Fig. 16 is a cross-sectional view showing the manufacturing process according to Fig. 15 shows. Fig. 17 is a cross-sectional view showing the manufacturing process according to Fig. 16 shows. Fig. 18 is a cross-sectional view showing the manufacturing process according to Fig. 17 shows. Fig. 19 is a cross-sectional view showing the manufacturing process according to Fig. 18 shows. Fig. 20 is a cross-sectional view showing the manufacturing process according to Fig. 19 shows. Fig. 21 is a cross-sectional view showing the manufacturing process according to Fig. 20 shows. Fig. 22 is a cross-sectional view showing the manufacturing process according to Fig. 21 shows. Fig. 23 is a cross-sectional view showing the manufacturing process according to Fig. 22 shows. Fig. 24 is a cross-sectional view showing the manufacturing process according to Fig. 23 shows. Fig. 25 is a cross-sectional view showing the manufacturing process according to Fig. 24 shows. Fig. 26 is a cross-sectional view showing the manufacturing process according to Fig. 25 shows. Fig. Figure 27 is a cross-sectional view showing the semiconductor device in the example under investigation. DETAILED DESCRIPTION

[0015] The embodiment is described in detail below with reference to the drawings. In all drawings illustrating the embodiments, elements with the same functions are designated with the same reference numerals, and repetitive descriptions thereof are omitted. In the following embodiments, descriptions of the same or similar parts are generally not repeated, except where particularly necessary. <Struktur der Halbleitervorrichtung>

[0016] The semiconductor device 100 according to the embodiment is described below with reference to the Fig. 1 to Fig. 6 described.

[0017] Fig. Figure 1 is a top view showing the semiconductor chip, which is semiconductor device 100.

[0018] As in Fig. As shown in Figure 1, most of the semiconductor device 100 is covered with an emitter electrode EE, and several cells forming the IGBT are located beneath the emitter electrode EE. A gate wiring GW is formed around the emitter electrode EE. The central portion of the emitter electrode EE becomes an emitter pad (not shown), and the central portion of the gate wiring becomes a gate pad GP. By connecting external interconnects, such as wire bonds or terminals (copper plates), to the emitter pad and the gate pad GP, the semiconductor device 100 is electrically connected to other semiconductor chips or wiring substrates.

[0019] The semiconductor device 100 comprises areas 1A and 2A, which are distinct from each other. Area 1A in Fig. 1 is a resistive element area containing a resistive element Rg. Resistor Rg is used for the gate resistor, etc. Area 2A in Fig. 1 is a cell region in which several cells that form the IGBT are formed.

[0020] Fig. 2 is a main section plan view, corresponding to area 1A. Fig. Figure 3 is a main section plan view, corresponding to area 2A. Fig. Figure 4 is an equivalent circuit diagram of the semiconductor device 100. Fig. Figure 5 is a cross-sectional view along line AA of Fig. 2 and line BB from Fig. 3.

[0021] As in Fig. As shown in Figure 4, the IGBT comprises a collector electrode CE, an emitter electrode EE, and a gate electrode GE. One end of the resistive element Rg is connected to the gate electrode GE via the gate wiring GW. The other end of the resistive element Rg is connected to the gate pad GP via the gate wiring GW. The collector electrode CE is electrically connected to the collector area PC of the IGBT, and the emitter electrode EE is electrically connected to the emitter area NE.

[0022] As in Fig. As shown in Figure 2, the contact hole CH1 has a slot shape where the opening width in the first direction is wider than the opening width in the second direction, perpendicular to the first direction in a top view. That is, the contact hole CH1 forms a rectangular shape in a top view.

[0023] However, the planar shape of the contact hole CH1 is not limited to a slot shape; it can also be a point shape where the opening width in the first direction is the same as the opening width in the second direction. That is, the contact hole CH1, which forms a rectangular shape in plan view, can be arranged multiple times in the first direction.

[0024] It should be noted that the flat shape of contact hole CH1 often becomes a shape with rounded corners after the photolithography process. Therefore, in a top view, contact hole CH1 ultimately appears as a rectangle or circle with rounded corners.

[0025] As in Fig. As shown in Figure 3, contact hole CH2 has a slot shape where the opening width in the first direction is narrower than the opening width in the second direction in plan view. That is, contact hole CH2 forms a rectangular shape in plan view. Contact hole CH2 is located between two trenches TR extending in the second direction and intersects the emitter region NE, which extends in the first direction.

[0026] As in Fig. As shown in Figure 5, the semiconductor device 100 comprises a semiconductor substrate SUB with a low-concentration n-type drift region NV. Here, the n-type semiconductor substrate SUB itself forms the drift region NV. It should be noted that the drift region NV can be a laminate of an n-type silicon substrate and a semiconductor layer grown by introducing phosphorus (P) via epitaxial growth on the silicon substrate. In this application, such a laminate is also described as the semiconductor substrate SUB.

[0027] On the lower surface of the semiconductor substrate SUB, an n-type field-stop region (contamination region) NS is formed. The field-stop region NS is designed to prevent the depletion layer extending from the pn junction on the upper surface of the semiconductor substrate SUB from reaching the p-type collector region PC during IGBT turn-off.

[0028] On the lower surface of the semiconductor substrate SUB, a p-type collector region (impurity region) PC is formed. The collector region PC is located below the field stop region NS.

[0029] Below the lower surface of the semiconductor substrate SUB, a collector electrode CE is formed. The collector electrode CE is electrically connected to the collector area PC and supplies a collector potential to the collector area PC. The collector electrode CE is made of metal films such as AlSi film, Ti film, Ni film, and Au film. <widerstandselement>

[0030] The structure of region 1A is described below. In the semiconductor device 100, the conductive film PL formed in region 1A is used as the resistive element Rg.

[0031] As in Fig. As shown in Figure 5, a p-type well region PW is formed in the semiconductor substrate SUB on the upper surface. The well region PW is formed in the same process as the floating region PF of region 2A, but is physically separated from the floating region PF.

[0032] An insulating layer (IFL) is formed across the upper surface of the semiconductor substrate (SUB) and extends into the interior of the semiconductor substrate (SUB). In other words, an insulating layer (IFL) is formed within the semiconductor substrate (SUB), and the lower surface of the insulating layer (IFL) is positioned beneath the upper surface of the semiconductor substrate (SUB).

[0033] The insulating layer IFL comprises an insulating film IF1 and an insulating film IF2. Insulating film IF1 is formed within the semiconductor substrate SUB and is, for example, a silicon oxide film. Insulating film IF2 is formed on top of insulating film IF1 and is, for example, a silicon oxide film. Insulating film IF2 is thinner than insulating film IF1. The thickness of insulating film IF1 is, for example, 500 nm to 600 nm. The thickness of insulating film IF2 is, for example, 50 nm to 100 nm.

[0034] A conductive film (PL) is formed on the insulating layer (IFL). The conductive film (PL) is, for example, a polycrystalline silicon film into which p-type impurities are introduced. The thickness of the conductive film (PL) is, for example, 150 nm to 250 nm.

[0035] An intermediate insulating film IL is formed on the top surface of the semiconductor substrate SUB to cover the conductive film PL. The intermediate insulating film IL is, for example, a silicon oxide film. The intermediate insulating film IL undergoes a flattening process to reduce the thickness of its top surface. Therefore, the thickness of the intermediate insulating film IL on the top surface of the semiconductor substrate SUB is, for example, 600 nm to 800 nm, but the thickness of the intermediate insulating film IL on the top surface of the conductive film PL is, for example, 300 nm to 450 nm.

[0036] A contact hole CH1 is formed in the intermediate insulating film IL, the conductive film PL, and the insulating layer IFL. The bottom of contact hole CH1 is located in the insulating layer IFL (within insulating film IF1). The conductive film PL has a lower surface in contact with the insulating layer IFL (in other words, insulating film IF2), an upper surface positioned opposite the lower surface and in contact with the intermediate insulating film IL, and a side surface that connects the upper and lower surfaces within contact hole CH1. A connector PG1 is embedded in contact hole CH1.In contact hole CH1, the side surface of the intermediate insulating film IL is separated from the side surface of the conductive film PL, so that part of the upper surface of the conductive film PL is exposed to the intermediate insulating film IL, and the side surface of the insulating layer IFL is separated from the side surface of the conductive film PL, so that part of the lower surface of the conductive film PL is exposed to the insulating layer IFL. For example, the distance between the side of the conductive film PL and the side of the intermediate insulating film IL is 40 nm to 50 nm, and the distance between the side of the conductive film PL and the side of the insulating layer IFL is 30 nm to 40 nm.In other words, in the contact hole CH1, the opening width of the contact hole CH1 formed in the intermediate insulating film IL and the opening width of the contact hole CH1 formed in the insulating layer IFL are wider than the opening width of the contact hole CH1 formed in the conductive film PL.

[0037] The PG1 connector comprises a barrier metal film BM1, a silicide layer SC, a barrier metal film BM2 formed on the barrier metal film BM1 and the silicide layer SC, and a conductive film CF formed on the barrier metal film BM2. The barrier metal film BM1 is, for example, a titanium film, the silicide layer SC is, for example, a titanium silicide (TiSi) film, and the barrier metal film BM2 is, for example, a titanium nitride film. The conductive film CF is, for example, a tungsten film. The silicide layer SC is a compound of the barrier metal film BM1 and the polycrystalline silicon film, forming the conductive film PL.

[0038] In contact hole CH1, the silicide layer SC is formed on the side of the conductive film PL, on a portion of the upper surface of the conductive film PL exposed by the intermediate insulating film IL, and on a portion of the lower surface of the conductive film PL exposed by the insulating layer IFL. In contact hole CH1, the barrier metal film BM1 is formed on the side of the intermediate insulating film IL and on the side of the insulating layer IFL. As shown in Fig. As shown in Figure 6, in the direction perpendicular to the upper surface of the semiconductor substrate SUB, the width b of the silicide layer SC formed on the side of the conductive film PL is greater than the width a of the conductive film PL covered by the intermediate insulating film IL and the insulating layer IFL. This is because the thickness of the silicide layer SC formed at the corner of the conductive film PL is greater than the thickness of the silicide layer SC formed on the upper, lower, or side surface of the conductive film PL.

[0039] A gate wiring GW is formed on the intermediate insulating film IL. The conductive film PL is electrically connected to the gate wiring GW via the connector PG1. By configuring the electrical path in the middle of the gate wiring GW with the conductive film PL, the conductive film PL can be used as a resistive element (gate resistor) Rg. <Struktur der IGBT-Zelle>

[0040] The structure of area 2A is described below. An example is an IGBT with a vertical trench-gate structure.

[0041] As in Fig. As shown in Figure 5, a trench TR is formed on the upper surface of the semiconductor substrate SUB. The depth of the trench TR is, for example, 3 to 4 micrometers. A gate insulating film GI is formed within the trench TR. The gate electrode GE is formed on the gate insulating film GI to fill the trench TR. The gate insulating film GI is, for example, a silicon oxide film, and the gate electrode GE is, for example, a polycrystalline silicon film into which n-type impurities are introduced.

[0042] On the upper surface of the semiconductor substrate SUB, a hole barrier region (impurity region) NHB is formed within the semiconductor substrate SUB between a pair of gate electrodes GE. A p-type base region (impurity region) PB is formed within the hole barrier region NHB. An n-type emitter region (impurity region) NE is formed within the p-type base region PB. The base of the base region PB is positioned above the base of the trench TR, and the emitter region NE is positioned above the base of the base region PB.

[0043] Furthermore, a p-type floating region (contaminant region) PF is formed on the upper surface of the semiconductor substrate SUB, outside the area where the hole barrier region NHB is formed. A p-type base region PB is formed within the floating region PF. The floating region PF is deeper than the bottom of the trench TR to improve high-voltage resistance properties and is designed to cover the bottom of the trench TR.

[0044] The interlayer insulating film IL is also formed on the upper surface of the semiconductor substrate SUB in region 2A to cover the gate electrode GE, the emitter region NE, and the base region PB. Contact holes CH2 are formed in the interlayer insulating film IL, the emitter region NE, and the base region PB in region 2A. The bottom of contact hole CH2 is located in the base region PB. A connector PG2 is embedded in contact hole CH2. Connector PG2 is configured similarly to connector PG1 and comprises a barrier metal film BM1, a silicide layer SC, a barrier metal film BM2, and a conductive film CF.

[0045] A p-type high-concentration diffusion area (contamination area) PR is formed around the bottom of the contact hole CH2 in the base area PB. The high-concentration diffusion area PR is designed to reduce the contact resistance with the connector PG2 and prevent latch-up.

[0046] In area 2A, isotropic etching is performed on the interlayer insulating film IL to increase the contact area between the connector PG2 embedded in contact hole CH2 and the emitter area NE, thereby causing the side of the interlayer insulating film IL to recede. That is, in contact hole CH2, the side of the interlayer insulating film IL is spaced away from the side of the emitter area NE, so that a portion of the upper surface of the emitter area NE is exposed by the interlayer insulating film IL. In contact hole CH2, the silicide layer SC is formed on the upper surface of the emitter area NE that is exposed by the interlayer insulating film IL, and on the side surface of the emitter area NE.

[0047] An emitter electrode EE is formed on the interlayer insulating film IL. The emitter electrode EE is electrically connected via connector PG2 to the emitter region NE, the base region PB, and the high-concentration diffusion region PR, and supplies emitter potential to these regions. Although not shown here, the gate wiring GW is electrically connected via another connector to the gate electrode GE and supplies gate potential to the gate electrode GE.

[0048] An emitter electrode EE and gate wiring GW of this type consist, for example, of a TiW film and an aluminum film formed on the TiW film. The aluminum film is the main conductor film of the emitter electrode EE and gate wiring GW and is sufficiently thicker than the TiW film. <Hauptmerkmale der Ausführungsform der Halbleitervorrichtung>

[0049] The main features of the embodiment are described below using the Fig. 5 and Fig. 6 described. Fig. Figure 6 is an enlarged cross-sectional view around the contact hole CH1.

[0050] As in Fig. As shown in Figure 6, the connector PG1 in contact hole CH1 comprises a barrier metal film BM1, a silicide layer SC, a barrier metal film BM2 formed on the barrier metal film BM1 and the silicide layer SC, and a conductive film CF formed on the barrier metal film BM2. In contact hole CH1, a portion of the upper surface of the conductive film PL exposed by the intermediate insulating film IL, a portion of the lower surface of the conductive film PL exposed by the insulating layer IFL, and the side of the conductive film PL covered by the silicide layer SC are covered. In other words, a silicide layer SC is arranged between the polycrystalline silicon film PL, which forms the resistive element Rg, and the barrier metal film BM2.Therefore, it is possible to suppress the resistance value variation of the resistive element Rg due to the above-mentioned interface defects, thereby improving the reliability of the semiconductor device.

[0051] Here, in contact hole CH1, the length of the upper surface of the conductive film PL exposed by the intermediate insulating film IL (40 nm to 50 nm) and the length of the lower surface of the conductive film PL exposed by the insulating layer IFL (30 nm to 40 nm) are smaller compared to the thickness of the conductive film PL (150 nm to 250 nm). Therefore, the formation of the silicide layer SC on the side of the conductive film PL is effective in suppressing the resistance value variation of the resistive element Rg.

[0052] As in Fig. As shown in Figure 6, the width b of the silicide layer SC, which forms on the side of the conductive film PL, is also larger than the width a of the conductive film PL, which is covered by the intermediate insulating film IL and the insulating layer IFL. In other words, the contact area between the silicide layer SC covering the conductive film PL and the barrier metal film BM2 can be compared to the contact area between the conductive film PL and the barrier metal film BM1 in Figure 6. Fig. The example shown in section 27 can be enlarged, which allows the resistive element Rg to have a low resistance. <Herstellungsverfahren der Halbleitervorrichtung>

[0053] The manufacturing process of the semiconductor device 100 in the embodiment is described below using the Fig. 7 to Fig. 26 described.

[0054] First, as in Fig. Figure 7 shows a semiconductor substrate SUB with an n-type drift region NV fabricated. The semiconductor substrate SUB has an upper surface and a lower surface. Next, a silicon oxide film 10 is formed on the upper surface of the semiconductor substrate SUB, for example by thermal oxidation. Next, a silicon nitride film 11 is formed on the silicon oxide film 10, for example by the CVD process.

[0055] Next, as in Fig. Figure 8 shows that, by photolithography and dry etching, the silicon nitride film 11 and the silicon oxide film 10 in region 1A are selectively removed, and openings are formed in the silicon nitride film 11 and the silicon oxide film 10. Next, by further dry etching, a portion of the semiconductor substrate SUB exposed in the openings is etched, forming grooves in the semiconductor substrate SUB.

[0056] Next, as in Fig. Figure 9 shows that by performing thermal oxidation processing on the semiconductor substrate SUB, an insulating film IF1 is formed from the upper surface of the semiconductor substrate SUB to its interior. In this state, the insulating film IF1 is formed at a position higher than the upper surface of the semiconductor substrate SUB. That is, an insulating film IF1 with a LOCOS structure is formed on the semiconductor substrate SUB in region 1A. In this state, the thickness of the insulating film IF1 is, for example, 700 nm to 800 nm.

[0057] Next, as in Fig. As shown in Figure 10, the silicon nitride film 11 is removed by isotropic etching using a solution containing phosphoric acid. Then, using photolithography and ion implantation techniques, a p-type well region PW is formed in the semiconductor substrate SUB of region 1A, and a p-type floating region PF is formed in the semiconductor substrate SUB of region 2A. Next, using photolithography and ion implantation techniques, an n-type hole barrier region NHB is formed in the semiconductor substrate SUB of region 2A.

[0058] Next, as in Fig. Figure 11 shows a trench TR formed in the semiconductor substrate SUB of area 2A by photolithography and dry etching processing.

[0059] Next, as in Fig. Figure 12 shows that the silicon oxide film 10 is removed by isotropic etching using a solution containing hydrofluoric acid. At this time, since the insulating film IF1 is also subjected to isotropic etching, the upper surface of the insulating film IF1 recedes, and the thickness of the insulating film IF1 becomes thinner.

[0060] Next, as in Fig. Figure 13 shows that, by performing heat treatment on the semiconductor substrate SUB at, for example, 1000 degrees Celsius to 1200 degrees Celsius, impurities contained in the hole barrier region NHB, the floating region PF, and the trough region PW diffuse. Through this heat treatment, the hole barrier region NHB diffuses to near the bottom of the trench TR, and the floating region PF diffuses to a position deeper than the bottom of the trench TR, covering the bottom of the trench TR.

[0061] Although not shown in the figure, this heat treatment is performed in a state where a sacrificial silicon oxide film forms on the semiconductor substrate SUB, including the interior of the trench TR. After the heat treatment, the sacrificial silicon oxide film is removed by isotropic etching using a solution containing hydrofluoric acid. At this point, since the insulating film IF1 is also subjected to isotropic etching, the top surface of the insulating film IF1 recedes, and the thickness of the insulating film IF1 decreases. In this state, the thickness of the insulating film IF1 is, for example, 500 nm to 600 nm.

[0062] Next, as in Fig. Figure 14 shows that a gate insulating film GI is formed within the trench TR and on the semiconductor substrate SUB. The formation of the gate insulating film GI is carried out by thermal oxidation processing. The thickness of the gate insulating film GI is, for example, 100 nm.

[0063] Next, a gate electrode GE is formed to fill the interior of the trench TR. To form the gate electrode GE, a polycrystalline silicon film with introduced n-type impurities is first formed on the gate insulating film GI, for example, by the CVD process. Then, the polycrystalline silicon film formed outside the trench TR is removed by dry etching. The polycrystalline silicon film formed inside the trench TR remains as the gate electrode GE.

[0064] Next, as in Fig. As shown in Figure 15, an insulating film IF2 is formed on the insulating film IF1, the gate electrode GE, and the gate insulating film GI, which is formed outside the trench TR, for example by the CVD method. The thickness of the insulating film IF2 is, for example, 50 nm to 100 nm. Next, a conductive film PL is formed on the insulating film IF2, for example by the CVD method. The thickness of the conductive film PL is, for example, 150 nm to 250 nm.

[0065] Next, p-type impurities are introduced into the conductive film PL by ion implantation. Then, a resist pattern RP1 is formed on the conductive film PL in region 1A to selectively cover the conductive film PL located on the insulating film IF1.

[0066] Next, as in Fig. Figure 16 shows that by performing a dry etching process using the resist pattern RP1 as a mask, the conductive film PL and the insulating film IF2 are structured. As a result, a resistive element Rg is formed in region 1A. Furthermore, the structured insulating film IF2 and the insulating film IF1 form an insulating layer IFL. Additionally, in this dry etching process, the gate insulating film GI, which is formed outside the trench TR, is also removed. Subsequently, the resist pattern RP1 is removed by ashing.

[0067] Next, as in Fig. Figure 17 shows that a p-type base region PB (floating region PF and hole barrier region NHB) is formed on the upper surface of the semiconductor substrate SUB using photolithography and ion implantation techniques. The base region PB is positioned above the trench TR. Next, an n-type emitter region NE is formed within the base region PB using photolithography and ion implantation techniques. Heat treatment is then performed to activate the impurities contained in each impurity region.

[0068] Next, as in Fig. Figure 18 shows an intermediate insulating film IL formed on the upper surface of the semiconductor substrate SUB in areas 1A and 2A to cover the conductive film PL, the gate electrode GE, the base area PB and the emitter area NE.

[0069] Next, as in Fig. Figure 19 shows planarization of the upper surface of the interlayer insulating film IL. Planarization processing on the interlayer insulating film IL in regions 1A and 2A is carried out using the CMP method. After planarization processing, the thickness of the interlayer insulating film IL on the upper surface of the semiconductor substrate SUB is, for example, 600 nm to 800 nm, and the thickness of the interlayer insulating film IL on the upper surface of the conductive film PL is, for example, 300 nm to 450 nm.

[0070] Next, as in Fig. Figure 20 shows that contact holes CH1 in region 1A are formed in the intermediate insulating film IL, the conductive film PL, the insulating film IF2, and the insulating film IF1 by photolithography and anisotropic dry etching. Simultaneously, contact holes CH2 are formed in region 2A in the intermediate insulating film IL, the emitter region NE, and the base region PB. Next, a p-type high-concentration diffusion region PR is formed in the base region PB, located at the bottom of contact hole CH2 by ion implantation. Here, the bottom of contact hole CH1 is located in the insulating film IF1, and the bottom of contact hole CH2 is located in the base region PB. In anisotropic dry etching processes, etching gases such as SF6 or CH2F2 are used, but a problem has been confirmed in which F ions or C ions, which decompose in the plasma atmosphere, penetrate into the interior from the side of the conductive film PL.Additionally, the penetration of F ions or C ions into the emitter region NE was confirmed in area 2A.

[0071] Next, as in Fig. Figure 21 shows isotropic etching using a solution containing hydrofluoric acid on the interlayer insulating film IL and the insulating layer IFL (insulating film IF2 and insulating film IF1). This isotropic etching causes the side surface of the interlayer insulating film IL to move away from the side surface of the conductive film PL in contact hole CH1, so that part of the upper surface of the conductive film PL is exposed by the interlayer insulating film IL. Additionally, in contact hole CH1, the side surface of the insulating layer IFL (the side surface of insulating film IF1, the side surface of insulating film IF2) moves away from the side surface of the conductive film PL, so that part of the lower surface of the conductive film PL is exposed by the insulating layer IFL.Additionally, in the contact hole CH2, the side surface of the interlayer insulating film IL moves away from the side surface of the emitter region NE, so that part of the upper surface of the emitter region NE is exposed by the interlayer insulating film IL.

[0072] Next, as in Fig. Figure 22 shows hydrogen annealing performed on the semiconductor substrate SUB. The semiconductor substrate SUB is placed on a substrate provided in the chamber of a CVD device. The substrate temperature is then set to 600 °C to 650 °C, and heat treatment is performed on the semiconductor substrate SUB for approximately 30 seconds while hydrogen gas is introduced into the chamber. This hydrogen annealing process discharges F ions or C ions that have penetrated the conductive film PL and the emitter region NE from the conductive film PL and the emitter region NE. Fig. 22 black circles indicate F ions or C ions.

[0073] Next, as in Fig. Figure 23 shows hydrogen plasma treatment applied to the semiconductor substrate SUB. With the semiconductor substrate SUB mounted on the substrate of the CVD device mentioned above, the substrate temperature is set to 600 to 650 degrees Celsius, and hydrogen gas is introduced into the chamber while plasma is applied to the semiconductor substrate SUB. This hydrogen plasma treatment is performed for approximately 5 to 10 seconds. Hydrogen ions are then deposited in the contact hole CH1 on the side surface of the conductive film PL, a portion of the upper surface of the conductive film PL exposed by the intermediate insulating film IL, and a portion of the lower surface of the conductive film PL exposed by the insulating layer IFL. In other words, the unsaturated bonds (“dangling bonds”) on the surface of the polycrystalline silicon film forming the conductive film PL are terminated with hydrogen ions in the contact hole CH1.In . Fig. Figure 23 shows the white circles as hydrogen ions. Additionally, hydrogen ions are deposited in contact hole CH2 on a portion of the upper surface and side surface of the emitter region NE, which is exposed by the intermediate insulating film IL. Since the upper, side, and lower surfaces of the conductive film PL in contact hole CH1 are covered with hydrogen ions, impurities are prevented from adhering to the upper, side, and lower surfaces of the conductive film PL during the barrier metal film formation process BM1, as described later. For example, if a titanium (Ti) film is used as the barrier metal film BM1, chlorine (Cl) ions contained in the reaction gas titanium tetrachloride (TiC14) would be considered impurities. The hydrogen plasma treatment described above allows for the formation of a high-quality silicide layer SC free of impurities.

[0074] Next, as in Fig. Figure 24 shows the barrier metal film BM1 and the silicide layer SC formed in the contact holes CH1 and CH2. It should be noted that the barrier metal film BM1 is also formed on the intermediate insulating film IL outside the contact holes CH1 and CH2. With the semiconductor substrate SUB mounted on the substrate of the CVD apparatus mentioned above, the substrate temperature is set to 600 to 700 degrees Celsius, and a reaction gas is introduced into the chamber while the barrier metal film BM1 is deposited onto the semiconductor substrate SUB using the plasma CVD process. For example, the reaction gas is TiCl4 and H2, and the barrier metal film BM1 is a titanium (Ti) film. The film thickness of the barrier metal film BM1 is, for example, 10 nm.

[0075] Here, in the contact hole CH1, the barrier metal film BM1 is formed to cover a portion of the upper surface of the conductive film PL exposed by the intermediate insulating film IL, a portion of the lower surface of the conductive film PL exposed by the insulating layer IFL, the side surface of the conductive film PL, the side surface of the intermediate insulating film IL, and the side surface of the insulating layer IFL. Since the substrate temperature is set to 600 to 700 degrees Celsius, the silicide reaction proceeds during the deposition of the barrier metal film BM1. The silicide layer SC then forms on the upper surface of the conductive film PL exposed by the intermediate insulating film IL, the lower surface of the conductive film PL exposed by the insulating layer IFL, and the side surface of the conductive film PL.The silicide layer SC does not form on the side surface of the interlayer insulating film IL and the side surface of the insulating layer IFL, and the barrier metal film BM1 does form. In contact hole CH2, the silicide layer SC also forms at least on the upper surface and the side surface of the emitter region NE that is exposed by the interlayer insulating film IL. The silicide layer SC does not form on the side surface of the interlayer insulating film IL, and the barrier metal film BM1 does form. The silicide layer SC is, for example, a titanium silicide (TiSi) film, and its film thickness is 25 nm.

[0076] It should be noted that although the silicide layer SC is formed during the deposition process of the barrier metal film BM1, the silicide layer SC can be formed by performing a heat treatment that accelerates the silicide reaction to the desired film thickness after deposition of the barrier metal layer BM1. In other words, the barrier metal film BM1 is formed by the CVD process at a relatively low substrate temperature (400 to 500 degrees Celsius), and then a heat treatment is performed at 600 to 700 degrees Celsius to form the silicide layer SC.

[0077] It should be noted that if F ions or C ions remain in the conductive film PL or the emitter region NE, it becomes difficult to form the silicide layer SC on the conductive film PL or the emitter region NE. However, by performing the hydrogen curing treatment described above before forming the silicide layer SC, it becomes possible to form the silicide layer SC on the conductive film PL or the emitter region NE.

[0078] Next, as in Fig. Figure 25 shows the barrier metal film BM2 formed on the intermediate insulating film IL by the CVD process, including within the contact holes CH1 and CH2. The barrier metal film BM2 is, for example, a titanium nitride (TiN) film. The barrier metal film BM2 is in contact with the silicide layer SC, which is formed on the top surface, side surface, and bottom surface of the conductive film PL in the contact hole CH1. Furthermore, the barrier metal film BM2 is in contact with the barrier metal film BM1, which is formed on the side surface of the intermediate insulating film IL and the side surface of the insulating layer IFL in the contact hole CH1. In the contact hole CH2, it is in contact with the silicide layer SC, which is formed on the top surface and side surface of the emitter region NE, which is exposed by the intermediate insulating film IL.Furthermore, it is in contact with the barrier metal film BM1, which is formed on the side surface of the intermediate layer insulating film IL.

[0079] Next, the conductive film CF is formed on the barrier metal film BM2 to embed the inside of the contact holes CH1 and CH2. The conductive film CF is, for example, a tungsten (W) film and is formed using WF6 gas.

[0080] Next, as in Fig. Figure 26 shows that the conductive film CF, the barrier metal film BM2, and the barrier metal film BM1, which are formed outside the contact holes CH1 and CH2, are removed by polishing using the CMP process or anisotropic dry etching. As a result, the plug PG1, comprising the conductive film CF, the barrier metal film BM2, the silicide layer SC, and the barrier metal film BM1, is embedded in the contact hole CH1. Then, the plug PG2, comprising the conductive film CF, the barrier metal film BM2, the silicide layer SC, and the barrier metal film BM1, is embedded in the contact hole CH2.

[0081] Next, as in Fig. Figure 5 shows the gate wiring GW formed on the intermediate insulating film IL in area 1A, and the emitter electrode EE formed on the intermediate insulating film IL in area 2A. First, for example, a TiW film is formed on the intermediate insulating film IL by sputtering, and then an aluminum film is formed on the TiW film, also by sputtering. Next, the gate wiring GW and the emitter electrode EE are formed by structuring the TiW film and the aluminum film using photolithography and dry etching.

[0082] Next, the field-stop region NS, the collector region PC, and the collector electrode CE are formed on the lower surface of the semiconductor substrate SUB. First, a carrier tape is applied to the upper surface of the semiconductor substrate SUB, and the lower surface of the semiconductor substrate SUB is ground to reduce its thickness to, for example, 80 µm to 90 µm. Then, the grinding damage layer is removed from the lower surface of the semiconductor substrate SUB by performing an etching treatment using a solution containing hydrofluoric acid. Finally, the n-type field-stop region NS and the p-type collector region PC are formed from the lower surface of the semiconductor substrate SUB by performing ion implantation.Following these ion implantations, laser annealing is performed to activate the impurities contained in the field-stop region NS and the collector region PC. Next, metal films such as AlSi, Ti, Ni, and Au are formed on the lower surface of the semiconductor substrate SUB, for example, using sputtering. This metal film becomes the collector electrode CE.

[0083] As described above, the semiconductor device 100 is manufactured according to the embodiment.

[0084] Next, the features of the manufacturing process of the semiconductor device according to the embodiment are described.

[0085] In contact hole CH1, prior to the formation of the barrier metal film BM1 on a portion of the conductive film PL exposed by the intermediate insulating film IL and the insulating layer IFL, a hydrogen curing treatment is applied to this portion. This hydrogen curing treatment removes F or C ions that may have penetrated the conductive film PL during the anisotropic dry etching process described above, allowing the silicide layer SC to form on the surface of the conductive film PL. Electrically connecting the conductive film PL to the barrier metal film BM2 and the conductive film CF via the silicide layer SC then suppresses the variation in the resistance value of the resistive element Rg and improves the reliability of the semiconductor device.Furthermore, in contact hole CH2, prior to the formation of the barrier metal film EM1 on the upper surface and side face of the emitter region NE exposed by the intermediate insulating film IL, a hydrogen annealing treatment is applied to the upper surface and side face of the emitter region NE exposed by the intermediate insulating film IL. This hydrogen annealing treatment removes F or C ions that may have penetrated the emitter region NE during the anisotropic dry etching treatment described above, thus enabling the silicide layer SC to form on the upper surface and side face of the emitter region NE.

[0086] By performing the above hydrogen curing treatment, the silicide layer SC can be formed on the conductive film PL and the emitter region NE. Therefore, in the manufacturing process of the semiconductor device according to the embodiment, the hydrogen plasma treatment, which uses Fig. The section described in point 23 should be omitted.

[0087] However, by performing hydrogen plasma treatment between the aforementioned hydrogen curing process and the formation of the barrier metal film BM1, it is possible to improve the quality of the silicide layer SC, suppress the resistance value variation of the resistive element Rg, and improve the reliability of the semiconductor device.

[0088] As a modified example, prior to the hydrogen annealing process described above, sputter etching can be applied to a portion of the conductive film PL exposed by the intermediate insulating film IL and the insulating layer IFL. In the sputter etching process, the semiconductor substrate SUB is exposed to a plasma atmosphere containing an inert gas (Ar or N2). Since the top surface of the conductive film PL exposed by the intermediate insulating film IL is etched away, the F-ions or C-ions contained in the conductive film PL can be reduced.

[0089] Although the present invention has been described based on the above embodiments, it is not limited to these embodiments and various modifications can be made without deviating from its core.

[0090] For example, a diode element can be formed in the conductive film PL instead of the resistive element Rg.

[0091] Furthermore, although an IGBT is an example of a device configured in area 2A, the technology disclosed in the above embodiments is not limited to IGBTs and can also be applied to power MOSFETs with a vertical trench-gate structure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2024-129919

[0001] JP 2023-128002

[0005] < / widerstandselement>

Claims

[1] Semiconductor device comprising: a semiconductor substrate with an upper surface and a lower surface; an insulating film formed on the upper surface of the semiconductor substrate; a first conductive film formed on the insulating film; an intermediate insulating film formed on the upper surface of the semiconductor substrate to cover the first conductive film; a first contact hole formed in the interlayer insulating film, in the first conductive film, and in the insulating film; and a first plug embedded in the first contact hole, wherein in the first contact hole a first side surface of the interlayer insulating film is spaced apart from a second side surface of the first conductive film, such that part of an upper surface of the first conductive film is exposed from the interlayer insulating film, wherein in the first contact hole a third side surface of the insulating film is spaced apart from the second side surface of the first conductive film, such that part of a lower surface of the first conductive film is exposed from the insulating film, and the first plug includes: a first silicide layer formed on the second side surface of the first conductive film; a first barrier metal film formed on the first silicide layer; and a second conductive film formed on top of the first barrier metal film. [2] Semiconductor device according to claim 1, wherein the first silicide layer is formed in the first contact hole to cover a part of the upper surface of the first conductive film exposed by the first side surface of the interlayer insulating film and a part of the lower surface of the first conductive film exposed by the third side surface of the insulating film. [3] Semiconductor device according to claim 2, wherein in a direction perpendicular to the upper surface of the semiconductor substrate a first width of the first silicide layer formed on the second side surface of the first conductive film is greater than a second width of the first conductive film in a region between the interlayer insulating film and the insulating film. [4] Semiconductor device according to claim 2, wherein the first connector comprises a second barrier metal film formed on the first side surface of the interlayer insulating film and the third side surface of the insulating film in the first contact hole. [5] Semiconductor device according to claim 4, wherein the first conductive film is a polycrystalline silicon film. [6] Semiconductor device according to claim 5, wherein the second barrier metal film is a titanium film, a nickel film, a tantalum film or a tungsten film. [7] Semiconductor device according to claim 6, wherein the first silicide layer is an alloy film consisting of the polycrystalline silicon film and the second barrier metal film. [8] Semiconductor device according to claim 7, wherein the first barrier metal film is a titanium nitride film, and wherein the second conductive film is a tungsten film. [9] Semiconductor device according to claim 1, further comprising: a first area in which the first conductive film is formed; a second area that differs from the first area; a trench that is formed in the semiconductor substrate in the second region on an upper surface side of the semiconductor substrate; a gate insulating film formed in the trench; a gate electrode formed on the gate insulating film to fill the gap; a first impurity region of a first conductivity type, which is formed in the semiconductor substrate in the second region on the upper surface side of the semiconductor substrate, such that a bottom of the first impurity region is positioned above a bottom of the trench; and a second contamination area of ​​a second conductivity type, which is opposite to the first conductivity type formed in the first contamination area, wherein the interlayer insulating film is also formed on the upper surface of the semiconductor substrate in the second region to cover the gate electrode, the first contamination region and the second contamination region, wherein a second contact hole is formed in the interlayer insulating film, in the second contamination area and in the first contamination area in the second area, such that a bottom of the second contact hole is positioned in the first contamination area, wherein in the second contact hole a fourth side surface of the interlayer insulating film is spaced apart from a fifth side surface of the second contamination area, such that part of an upper surface of the second contamination area is exposed from the interlayer insulating film, where a second plug is embedded in the second contact hole, and the second plug includes: a second silicide layer formed on part of the upper surface of the second contaminated area and on the fifth side surface of the second contaminated area; a third barrier metal film formed on top of the second silicide layer; and a third conductive film formed on top of the third barrier metal film. [10] Semiconductor device according to claim 9, further comprising: a gate wiring that is formed on the interlayer insulating film in the first region and is electrically connected to the gate electrode; and an emitter electrode formed on the interlayer insulating film in the second area, wherein the first contamination area and the second contamination area are electrically connected to the emitter electrode via the second connector, and the first conductive film is electrically connected to the gate wiring via the first connector. [11] A method for manufacturing a semiconductor device, the method comprising: (a) Manufacturing a semiconductor substrate with an upper surface and a lower surface; (b) following (a), forming an insulating film on the semiconductor substrate; (c) following (b), forming a first conductive film on the insulating film; (d) following (c), forming an intermediate insulating film on the upper surface of the semiconductor substrate to cover the first conductive film; (e) following (d), performing anisotropic dry etching on the interlayer insulating film, on the first conductive film and on the insulating film to form a first contact hole; (f) following (e), performing isotropic etching on the interlayer insulating film and on the insulating film; and (g) after (f), filling the first contact hole with a first plug, wherein (f) a first side surface of the interlayer insulating film is spaced apart from a second side surface of the first conductive film, such that part of an upper surface of the first conductive film is exposed from the interlayer insulating film, wherein (f) a third side surface of the insulating film is spaced apart from the second side surface of the first conductive film, such that part of a lower surface of the first conductive film is exposed from the insulating film in the first contact hole, where (g) includes: (g1) according to (f), performing heat treatment on the semiconductor substrate in a hydrogen atmosphere; (g2) after (g1), formation of a first silicide layer on the second side surface of the first conductive film in the first contact hole; (g3) after (g2), formation of a first barrier metal film on the first silicide layer; and (g4) after (g3), forming a second conductive film on top of the first barrier metal film. [12] Method according to claim 11, wherein in (g2) the first silicide layer is formed in the first contact hole to cover a part of the upper surface of the first conductive film exposed by the first side surface of the interlayer insulating film and a part of the lower surface of the first conductive film exposed by the third side surface of the insulating film. [13] Method according to claim 12, wherein in (g2) the first silicide layer is formed by depositing a second barrier metal film in the first contact hole using a plasma CVD process with a substrate temperature set between 600 degrees Celsius and 700 degrees Celsius. [14] The method of claim 12, further comprising: (g5) between (g1) and (g2), applying hydrogen ions to a part of the upper surface of the first conductive film exposed by the first side surface of the interlayer insulating film, to the second side surface of the first conductive film and to a part of the lower surface of the first conductive film exposed by the third side surface of the insulating film, in the first contact hole. [15] The method of claim 12, further comprising: (g6) between (f) and (g1), performing a sputter etching process using an inert gas on a part of the upper surface of the first conductive film exposed by the first side surface of the interlayer insulating film, on the second side surface of the first conductive film and on a part of the lower surface of the first conductive film exposed by the third side surface of the insulating film in the first contact hole. [16] Method for manufacturing a semiconductor device having a first region and a second region which differs from the first region, the method comprising: (a) Manufacturing a semiconductor substrate with an upper surface and a lower surface; (b) according to (a), forming a first insulating film over the interior of the semiconductor substrate from a position higher than the top surface of the semiconductor substrate in the first region; (c) according to (b), forming a trench in the semiconductor substrate in the second region on an upper surface side of the semiconductor substrate; (d) after (c), forming a gate insulating film in the trench; (e) after (d), forming a gate electrode on the gate insulating film to fill the trench; (f) according to (e), forming a second insulating film with a thickness that is thinner than the first insulating film on the upper surface of the semiconductor substrate in the first region and in the second region to cover the first insulating film in the first region and the gate electrode in the second region; (g) after (f), forming a first conductive film on the second insulating film in the first area and in the second area; (h) after (g), removing the first conductive film and the second insulating film, so that the first conductive film and the second insulating film are selectively left on the first insulating film; (i) according to (h), forming a first impurity region of a first conductivity type in the semiconductor substrate in the second region on the upper surface side of the semiconductor substrate, such that a bottom of the first impurity region is positioned above a bottom of the trench; (j) after (i), forming a second contamination area of ​​a second conductivity type opposite to the first conductivity type in the first contamination area; (k) according to (j), forming an interlayer insulating film on the upper surface of the semiconductor substrate in the first region and in the second region to cover the first conductive film in the first region and the gate electrode, the first impurity region and the second impurity region in the second region; (1) according to (k), performing a planarization process on the interlayer insulating film in the first area and in the second area by a CMP process to flatten the upper surface of the interlayer insulating film; (m) according to (1), performing anisotropic dry etching on the interlayer insulating film, on the first conductive film, on the second insulating film and on the first insulating film to form a first contact hole in the interlayer insulating film, in the first conductive film, in the second insulating film and in the first insulating film in the first region, such that that a bottom of the first contact hole is positioned in the first insulating film, and to form a second contact hole in the interlayer insulating film, in the second contamination area and in the first contamination area in the second area, so that a bottom of the second contact hole is positioned in the first contamination area; (n) after (m), performing isotropic etching on the interlayer insulating film, on the second insulating film, and on the first insulating film; and (o) to (n), filling the first contact hole with a first plug and filling the second contact hole with a second plug, wherein (n) in the first contact hole a first side surface of the interlayer insulating film is separated from a second side surface of the first conductive film, such that part of an upper surface of the first conductive film is exposed from the interlayer insulating film, wherein by (n) in the first contact hole a third side surface of the first insulating film and the second insulating film are separated from the second side surface of the first conductive film, such that part of a lower surface of the first conductive film is exposed from the first insulating film and the second insulating film, wherein (n) in the second contact hole a fourth side surface of the interlayer insulating film is spaced apart from a fifth side surface of the second contamination area, such that part of an upper surface of the second contamination area is exposed from the interlayer insulating film, and where (o) includes: (o1) after (n), performing heat treatment on the semiconductor substrate in a hydrogen atmosphere; (o2) after (o1), forming a first silicide layer on the second side surface of the first conductive film in the first contact hole and forming a second silicide layer on part of an upper surface of the second contaminant area and on the fifth side surface of the second contaminant area in the second contact hole; (o3) after (o2), formation of a first barrier metal film on the first silicide layer and on the second silicide layer; and (o4) after (o3), forming a second conductive film on top of the first barrier metal film. [17] Method according to claim 16, wherein in (o2) the first silicide layer is formed in the first contact hole to cover a part of an upper surface of the first conductive film exposed by the first side surface of the interlayer insulating film and a part of a lower surface of the first conductive film exposed by the third side surface of the second insulating film. [18] Method according to claim 17, wherein in (o2) the first silicide layer and the second silicide layer are formed by depositing a second barrier metal film in the first contact hole and in the second contact hole using a plasma CVD process with a substrate temperature set between 600 degrees Celsius and 700 degrees Celsius. [19] The method of claim 17, further comprising: (o5) between (o1) and (o2), applying hydrogen ions to a part of an upper surface of the first conductive film exposed from the first side surface of the interlayer insulating film, to the second side surface of the first conductive film and to a part of a lower surface of the first conductive film exposed from the third side surface of the second insulating film, in the first contact hole and to a part of an upper surface of the second contaminant area and to a fifth side surface of the second contaminant area in the second contact hole. [20] The method of claim 19, further comprising: (o6) between (n) and (o1), performing a sputter etching process using an inert gas on a part of an upper surface of the first conductive film exposed by the first side surface of the interlayer insulating film, on the second side surface of the first conductive film and on a part of a lower surface of the first conductive film exposed by the third side surface of the second insulating film in the first contact hole, on a part of an upper surface of the second contaminant area and on a fifth side surface of the second contaminant area in the second contact hole.

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