Two-level printed circuit boards in a card-based computing device

Abstract

According to various embodiments, a processing subsystem comprises: a first printed circuit board (PCB) comprising an edge connector oriented perpendicular to a first coordinate axis and located at a first level on the first coordinate axis, and a second printed circuit board perpendicular to the first coordinate axis and located at a second level on the first coordinate axis, wherein the second level is different from the first level and the second printed circuit board has a top surface on which a processor is mounted.

Description

BACKGROUND Area of ​​the various designs

[0001] The various embodiments generally relate to computer systems and thermal solution technology, and in particular to two-level printed circuit boards in a card-based computing device. Description of the related technique

[0002] In modern computing devices, central processing units (CPUs), graphics processing units (GPUs), and other integrated circuits (ICs) require ever-increasing power and therefore generate ever-greater amounts of heat during operation. This heat must be dissipated by the computing device so that the integrated circuits and the computing device as a whole can function effectively. For example, a single high-performance chip, such as a CPU or GPU, can generate hundreds of watts of heat during operation, and if this heat is not dissipated by the computing device, the chip's temperature can rise to a level where it can be permanently damaged.To prevent thermal damage during operation, many computing devices, in addition to conventional cooling systems, employ clock speed throttling when the operating temperature of a particular processor exceeds a certain threshold. Accordingly, the processing speed and performance of the high-performance chip in these types of computing devices are limited by how effectively heat is dissipated from the chip.

[0003] In an effort to avoid clock speed throttling and the associated performance limitations, alternative cooling solutions have been implemented in computing devices. One effective technique for dissipating heat from a chip during operation is to increase the airflow around the chip and within the computing device.

[0004] Many card-based processing subsystems, such as a graphics card, which includes a graphics processing unit (GPU) and / or other high-performance chip on a printed circuit board (PCB), may require efficient heat dissipation from the chip through increased airflow. This can be hindered by the relatively large size of the PCB. More specifically, graphics cards and other card-based processing subsystems can be installed in a computing device via one of the PCIe (Peripheral Component Interconnect Express) slots located on the main PCB of the computing device. The various electronic components of a graphics card, including the GPU and / or other high-performance chip, are mounted on the graphics card's PCB according to PCIe specifications.The PCIe specifications include a height restriction for components that can be mounted on the back of the printed circuit board (PCB), resulting in the majority of electronic components being mounted on the top side. In this respect, the GPU and other relatively tall electronic components, such as power components, are typically mounted on the top side of the PCB, while only some relatively shorter electronic components, such as capacitors, are typically mounted on the back. Because most of the electronic components are located on only one side of the PCB (the top side) to comply with PCIe specifications, the PCB area of ​​a conventional graphics card cannot easily be reduced to improve overall airflow and heat dissipation during operation.

[0005] As the foregoing illustrates, more effective methods for dissipating heat from map-based processing subsystems during operation are needed in engineering. SUMMARY

[0006] According to various embodiments, a processing subsystem comprises: a first printed circuit board (PCB) comprising an edge connector oriented perpendicular to a first coordinate axis and located at a first level on the first coordinate axis, and a second printed circuit board perpendicular to the first coordinate axis and located at a second level on the first coordinate axis, wherein the second level is different from the first level and the second printed circuit board has a top surface on which a processor is mounted.

[0007] At least one technical advantage of the disclosed two-level printed circuit board (PCB) design compared to the prior art is that the disclosed design allows for a substantial reduction in the surface area of ​​the main PCB of a processing subsystem, such as a graphics card, compared to the PCB size in a conventional processing subsystem. Specifically, the two-level PCB design allows for the placement of relatively tall electronic components on the back side of the main PCB, resulting in a more even distribution of electronic components across both the top and back sides of the main PCB compared to a PCB in a conventional processing subsystem. This more even distribution of electronic components on both sides of the main PCB allows for a reduction in the main PCB's surface area.Consequently, a greater overall airflow can be achieved in a processing subsystem incorporating a two-level printed circuit board (PCB) design by improving airflow through a heat sink / heat exchanger due to reduced obstruction by the PCB and / or by improving airflow across the back and top surfaces of the main PCB and the processor and power components mounted on it. As a result, overall heat dissipation from the processing subsystem during operation can be improved, which can reduce the temperature of the processor and other attached electronic components and improve the overall computing performance of the processor and processing subsystem compared to what can be achieved with prior art designs. These technical advantages represent one or more technological advancements over the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] To better understand the features of the various embodiments mentioned above, a more detailed description of the inventive concepts summarized above can be provided by referring to various embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings only show typical embodiments of the concepts according to the invention and are therefore in no way to be considered as limiting the scope, and that other equally effective embodiments exist. Fig. 1 is a conceptual illustration of a computer system configured to implement one or more aspects of the various embodiments; Fig. Figure 2 is another illustration of the computer system from Fig. 1 according to various embodiments; Fig. Figure 3 illustrates a conventional card-based processing subsystem that, according to the state of the art, includes multiple fans; Fig. Figure 4 is an illustration of a two-level printed circuit board-based processing subsystem comprising multiple fans, according to various embodiments; Fig. Figure 5 is an illustration of a side view of the two-level printed circuit board-based processing subsystem of Fig. 4 according to different embodiments; Fig. Figure 6 illustrates a perspective side view of the two-level map-based processing subsystem of Fig. 4 according to different embodiments; Fig. Figure 7 illustrates a conventional card-based processing subsystem that includes a heat sink in accordance with the state of the art; Fig. Figure 8 is an illustration of a two-level printed circuit board-based processing subsystem comprising a heat sink, according to various embodiments; and Fig. Figure 9 is an illustration of a two-level printed circuit board card-based processing subsystem comprising multiple fans and heat sinks, according to various embodiments.

[0009] For the sake of clarity, identical reference numerals have been used, where applicable, to identify identical elements common to all figures. It is understood that features of one embodiment may be incorporated into other embodiments without further reference. DETAILED DESCRIPTION

[0010] The following description sets out numerous specific details to provide a more thorough understanding of the various embodiments. However, it will be obvious to a person skilled in the art that the concepts according to the invention can also be implemented without one or more of these specific details. System overview

[0011] Fig. Figure 1 is a conceptual illustration of a computer system 100 configured to implement one or more aspects of the various embodiments. As shown, the system 100 comprises a central processing unit (CPU) 102 and system memory 104, which communicate via a bus path that may include a memory bridge 105. The CPU 102 comprises one or more processor cores and, when operating, is the main processor of the system 100, controlling and coordinating the operations of the other system components. The system memory 104 stores software applications and data for use by the CPU 102. The CPU 102 executes software applications and, optionally, an operating system. The memory bridge 105, which may be, for example, a northbridge chip, is connected via a bus or other communication path (e.g., a HyperTransport link) to an I / O (input / output) bridge 107. The I / O bridge 107, which may be, for example, a memory chip, is connected to the system's memory via a bus or other communication path (e.g., a HyperTransport link). B.which may be a Southbridge chip, receives user input from one or more user input devices 108 (e.g. keyboard, mouse, joystick, digitizer tablets, touchpads, touchscreens, still or video cameras, motion sensors and / or microphones) and forwards the input to the CPU 102 via the memory bridge 105.

[0012] A display processor 112 is connected to the memory bridge 105 via a bus or other communication path (e.g., a PCI Express, Accelerated Graphics Port, or HyperTransport connection). In one embodiment, the display processor 112 is a graphics subsystem comprising at least one graphics processing unit (GPU) and graphics memory. The graphics memory includes a display memory (e.g., a frame buffer) used to store pixel data for each pixel of an output image. The graphics memory can be integrated into the same device as the GPU, connected to the GPU as a separate device, and / or implemented in system memory 104.

[0013] The display processor 112 periodically delivers pixels to a display device 110 (e.g., a screen or a conventional CRT, plasma, OLED, SED, or LCD-based monitor or television). In addition, the display processor 112 can output pixels to film recording devices adapted to reproduce computer-generated images on photographic film. The display processor 112 can supply the display device 110 with an analog or digital signal. In various embodiments, a graphical user interface is displayed via the display device 110 for one or more users, and the one or more users can input data into the graphical user interface and receive visual output from it.

[0014] A system disk 114 is also connected to the I / O bridge 107 and can be configured to store content, applications, and data for use by the CPU 102 and the display processor 112. The system disk 114 provides non-volatile storage for applications and data and can include fixed or removable hard disk drives, flash memory devices, and CD-ROM, DVD-ROM, Blu-ray, HD-DVD, or other magnetic, optical, or solid-state storage devices.

[0015] A switch 116 provides connections between the I / O bridge 107 and other components, such as a network adapter 118 and various add-on cards 120 and 121. The network adapter 118 enables the system 100 to communicate with other systems via an electronic communications network and can include wired or wireless communication over local area networks and wide area networks, such as the Internet.

[0016] Other components (not shown), including USB or other connection devices, movie recording devices, and the like, can also be connected to the I / O bridge 107. For example, an audio processor can be used to generate analog or digital audio output from instructions and / or data provided by the CPU 102, system memory 104, or system disk 114. The communication paths connecting the various components in Fig. 1. Connecting devices together can be implemented using any suitable protocols such as PCI (Peripheral Component Interconnect), PCI-Express (PCI-E), AGP (Accelerated Graphics Port), HyperTransport or any other bus or point-to-point communication protocols, and the connections between different devices can use different protocols, as is known in the art.

[0017] In one embodiment, the display processor 112 is configured as a processing subsystem comprising circuits optimized for graphics and video processing, such as video output circuits, and forming a graphics processing unit (GPU). In another embodiment, the display processor 112 is configured as a processing subsystem comprising circuits optimized for general-purpose processing. In yet another embodiment, the display processor 112 can be integrated with one or more other system elements, such as the memory bridge 105, the CPU 102, and the I / O bridge 107, to form a system-on-a-chip (SoC). In still further embodiments, the display processor 112 is omitted, and the software executed by the CPU 102 provides the functions of the display processor 112.

[0018] Pixel data can be provided directly to the display processor 112 by the CPU 102. In some embodiments, instructions and / or data representing a scene are provided to a render farm or a set of server computers, each similar to the System 100, via the network adapter 118 or the system hard disk 114. The render farm produces one or more rendered images of the scene using the provided instructions and / or data. These rendered images can be stored on computer-readable media in a digital format and optionally returned to the System 100 for display. Similarly, stereo image pairs processed by the display processor 112 can be output to other systems for display, stored on the system hard disk 114, or placed on computer-readable media in a digital format.

[0019] Alternatively, the CPU 102 provides the display processor 112 with data and / or instructions defining the desired output images, from which the display processor 112 generates the pixel data of one or more output images, including characterizing and / or adjusting the offset between stereo image pairs. The data and / or instructions defining the desired output images can be stored in system memory 104 or in the graphics memory of the display processor 112. In one embodiment, the display processor 112 includes 3D rendering capabilities for generating pixel data for output images from instructions and data defining the geometry, lighting, shading, texturing, motion, and / or camera parameters for a scene. The display processor 112 can also include one or more programmable execution units capable of executing shader programs, tone mapping programs, and the like.

[0020] Furthermore, in other embodiments, the CPU 102 or the display processor 112 can be replaced or supplemented by any technically feasible form of processor (processing device) configured for data processing and program code execution. Such a processing device could, for example, be a central processing unit (CPU), a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), etc. In various embodiments, each of the operations and / or functions described herein can be performed by the CPU 102, the display processor 112, or one or more other processing devices, or any combination of these different processors.

[0021] The CPU 102, the render farm and / or the display processor 112 can apply any surface or volume rendering technique known in the art to produce one or more rendered images from the provided data and instructions, including rasterization, scanline rendering, REYES or micropolygon rendering, ray casting, ray tracing, image-based rendering techniques and / or combinations of these and other rendering or image processing techniques known in the art.

[0022] It is clear that the system shown here is for illustrative purposes only and that variations and modifications are possible. The connection topology, including the number and arrangement of the bridges, can be modified as desired. In some embodiments, for example, the system memory 104 is directly connected to the CPU 102 without a bridge, while other devices communicate with the system memory 104 via the memory bridge 105 and the CPU 102. In other alternative topologies, the display processor 112 is connected to the I / O bridge 107 or directly to the CPU 102 without the memory bridge 105. In still other embodiments, the I / O bridge 107 and the memory bridge 105 can be integrated on a single chip. The specific components shown here are optional; for example, any number of expansion cards or peripheral devices can be supported.In some embodiments, the switch 116 is omitted, and the network adapter 118 and the add-on cards 120, 121 are connected directly to the I / O bridge 107.

[0023] Fig. Figure 2 is another illustration of the computer system 100. Fig. 1 according to various embodiments. As shown, the computer system 100 comprises a chassis 201 (also referred to as a "case" or "enclosure") with one or more system fans 202 mounted thereon and one or more cooling inlets 203 formed therein. The cooling fans 202 are configured to draw cooling air into the chassis 201, for example, via the cooling inlets 203, in order to dissipate the heat generated by various electronic components of the computer system 100. The computer system 100 further comprises a power supply 204 mounted in the chassis 201, several chassis expansion slots 205, which are typically located on a rear side of the chassis 201, and a main circuit board 206 arranged in the chassis 201.

[0024] The computer system 100 further includes various external connectors (omitted for clarity) located on the rear and / or front of the chassis 201, such as a power connector, Universal Serial Bus (USB) connectors, an audio input jack, an audio output jack, one or more video output jacks, and / or other connectors. In some embodiments, one or more of these external connections are associated with the main circuit board 206 or with an expansion card that is coupled to the main circuit board 206 and installed in a chassis expansion slot 205 of the chassis, such as a card-based processing subsystem 220.

[0025] In the Fig. In the illustrated embodiment 2, the main circuit board 206 is configured with a central processing unit (CPU) and one or more card edge connectors, such as PCIe (Peripheral Component Interconnect Express) slots, each positioned to correspond to another chassis expansion slot 205. For clarity, the CPU and card edge connectors of the main circuit board 206 are shown in Fig. 2 omitted. In general, the computer system 100 is configured with one or more expansion cards or other card-based processing subsystems, each installed in a separate chassis expansion slot 205 and communicatively connected to the main circuit board 206 via a corresponding edge connector. Examples of such card-based processing subsystems are card-based processing subsystems 220, such as wireless adapters, sound cards, graphics cards, network adapters 118, add-in cards 120, 121, or the display processor 112. Fig. 1 and / or the like. In the Fig. In the illustrated embodiment 2, a single card-based processing subsystem 220 is connected to the main circuit board 206, whereas in other embodiments a plurality of card-based processing subsystems 220 may be connected to the main circuit board 206.

[0026] In some embodiments, the computer system 100 further comprises one or more peripheral devices (not shown) that are communicatively connected to the main circuit board 206 and / or a specific expansion card connected to the main circuit board 206. In some embodiments, the computer system 100 comprises, for example, one or more keyboards, mice, joysticks, digitizing tablets, touchpads, touchscreens, display devices, external hard drives, still or video cameras, motion sensors, microphones, and / or the like.

[0027] In the Fig. In the illustrated embodiment 2, the computer system 100 is depicted as a desktop computer system in a tower configuration. In other embodiments, the computer system 100 can have any configuration, which may include a card-based processing subsystem, such as a tower server computer system, a blade server computer system, a rack server computer system, a laptop computer, and the like.

[0028] Fig. Figure 3 illustrates a conventional card-based processing subsystem 300, which, according to the prior art, includes multiple fans. The conventional card-based processing subsystem 300 can be found in the [reference to be added] Fig. 1-2 illustrated computer system 100 can be implemented. Fig. Figure 3 shows a view of the underside of the conventional card-based processing subsystem 300. As illustrated, the processing subsystem 300 comprises a single printed circuit board 302, a first fan 350, and a second fan 360.

[0029] The individual printed circuit board 302 is typically aligned in a single plane that is perpendicular to a first coordinate axis (e.g., the Z-axis). In the example of Fig. Figure 3 illustrates the conventional map-based processing subsystem 300 upside down for clarity, with the first coordinate axis running from top to bottom. Fig. 3 increases in value. As used here, the dimension associated with the first coordinate axis is generally referred to as "height," thus measuring the "height" of a component or other feature relative to and on the basis of the first coordinate axis. Thus, in Fig. 3 a back side of the individual circuit board 302 is visible, while a top side of the individual circuit board 302 is in Fig. 3 is not visible. The size of the surface area of ​​each printed circuit board 302 is defined by the dimensions of each printed circuit board 302 along a second coordinate axis (e.g., the Y-axis) and a third coordinate axis (e.g., the X-axis). As shown, the size of the surface area of ​​each printed circuit board 302 extends from the left side of the first fan 350 to the left side of the second fan 360.

[0030] The single printed circuit board 302 comprises various subsections, including an edge connector 310 (indicated by the dashed box) and a main printed circuit board 320 (which comprises a remaining portion of the single printed circuit board 302). The edge connector 310 is configured to couple / connect to a corresponding chassis expansion slot 205 to provide communication between the processing subsystem 300 and the main printed circuit board 206 of the computer system 100. The main printed circuit board 320 comprises various components mounted on the rear and top surfaces of the main printed circuit board 320. In particular, the processor (e.g., a graphics processor or some other type of processing device) is typically mounted on the top surface of the main printed circuit board 320.The processing subsystem 300 can include a PCIe processing subsystem 300 connected via the edge connector 310 to a PCIe chassis expansion slot 205 of the main circuit board 206 of the computer system 100. Accordingly, the various components mounted on the main circuit board 320 are required to comply with the PCIe specifications / restrictions, which impose a maximum height limit for components that can be mounted on the rear side of the individual circuit board 302 (referred to here as "rear-mounted components"). For example, the maximum height of components on the rear side of a standard PCIe can be 2.67 mm. In other embodiments, the maximum height of the components on the rear side may be a different value.

[0031] According to the PCIe specifications, the height of a back-mounted component on the individual printed circuit board 302 is measured relative to a back surface of the edge connector 310. Since the individual printed circuit board 302 is typically oriented on a single plane perpendicular to the first coordinate axis, the entire individual printed circuit board 302 is located on a first level on the first coordinate axis. Thus, the edge connector 310 and the main printed circuit board 320 are both located on the same first level of the first coordinate axis. Therefore, to determine compliance with the PCIe specifications, the height of a back-mounted component can be determined based on the back surface of the main printed circuit board 320. For example, the main printed circuit board 320 may include a first component 330 mounted on the back of the main printed circuit board 320, which has a first height (h1).The first height (h1) can be measured from a bottom surface of the first component 330, which is mounted on the back surface of the main printed circuit board 320 (located at the same first level as the edge connector 310), to a top surface of the first component 330. The resulting height measurement of each back-mounted component must be less than or equal to the maximum height limit defined in the PCIe specifications.

[0032] As a result of the PCIe specification above, relatively tall components, such as power components, are typically mounted on the top side of the main PCB 320. Furthermore, the processor and memory are also typically mounted on the top side of the main PCB 320. In contrast, only some shorter components, such as capacitors, can be mounted on the back side of the main PCB 320. This results in an uneven distribution of components between the top and back sides of the main PCB 320, with the majority of components typically located on the top side.Consequently, the size of the surface area of ​​the individual printed circuit board 302 of the conventional card-based processing subsystem 300 cannot be significantly reduced to increase airflow and improve heat dissipation from the conventional card-based processing subsystem 300.

[0033] Two-level printed circuit boards in a processing subsystem Fig. Figure 4 illustrates a two-level card-based processing subsystem 400, which, according to various embodiments, includes multiple fans. The card-based processing subsystem 400 can be described in the Fig. 1-2 illustrated computer system 100 can be implemented. Fig. Figure 4 shows a view of the underside of the processing subsystem 400. As shown, the processing subsystem 400 comprises a first circuit board 410, a second circuit board 420, a first fan 450 and a second fan 460.

[0034] The first fan 450 and the second fan 460 can be mechanically connected / coupled to the first circuit board 410 and / or the second circuit board 420. The first fan 450 and the second fan 460 are oriented to generate an airflow and push cooling air (or another suitable cooling fluid) around the second circuit board 420 and through the processing subsystem 400 in an axial direction (a vertical direction through the axes of the fans). In other embodiments, the first fan 450 and the second fan 460 can be oriented to provide an airflow and push cooling air (or another suitable cooling medium) around the second circuit board 420 and through the processing subsystem 400 in a centrifugal / radial direction (a horizontal direction).

[0035] The first circuit board 410 comprises a card edge connector 410, and the second circuit board 420 comprises a main circuit board 420. The card edge connector 410 is adaptable and configured to couple / connect to a corresponding chassis expansion slot 205 of the main circuit board 206 of the computer system 100 to provide communication between the processing subsystem 400 and the main circuit board 206. The main circuit board 420 comprises various components mounted on its rear and top surfaces. These components include various electrical circuit components, ranging from relatively tall to relatively short.The relatively taller components can include processors (such as a CPU or GPU), some types of power components (such as inductors), special types of capacitors (such as can capacitors or conductive polymer aluminum solid capacitors (OS-CON)), and similar items. Power components can include inductors, MOSFETs, and the like. The relatively shorter components can include MOSFETs, resistors, general-purpose capacitors, regulators, and similar items. It should be noted that while MOSFETs are power components that are relatively short, MOSFETs and inductors are typically placed side-by-side in a printed circuit board (PCB) design.Thus, although MOSFETs can fit on the back of a printed circuit board and comply with the maximum component height on the back side, MOSFETs are typically not mounted on the back side of the board because the inductors would not fit on the back side of the board and comply with the maximum component height on the back side. Typically, the processor (not shown) is mounted on the top side of the main printed circuit board 420. However, in some embodiments, at least one processor (e.g., a CPU or GPU) is mounted on the back side of the main printed circuit board 420. In other embodiments, at least one processor is mounted on the top side of the main printed circuit board 420 and at least one other processor is mounted on the back side of the main printed circuit board 420.

[0036] In the example of Fig. Figure 4 illustrates the processing subsystem 400 upside down for clarity, with a first coordinate axis (e.g., the Z-axis) running from top to bottom. Fig. 4 increases in value. Therefore, in Fig. 4 a back side of the main circuit board 420 is visible, while a top side of the main circuit board 420 is in Fig. 4 is not visible. In the example of Fig. Figure 4 comprises the first coordinate axis as the Z-axis, the second as the Y-axis, and the third as the X-axis, which are largely arbitrary and based on an exemplary orientation of the processing subsystem 400 within the computer system 100. In other embodiments, the orientation of the processing subsystem 400 within the computer system 100 differs from the example in Figure 4. Fig. 4, and the first coordinate axis includes the X or Y axis, the second coordinate axis includes the X or Z axis, and the third coordinate axis includes the Y or Z axis.

[0037] The first printed circuit board 410 (edge ​​connector 410) and the second printed circuit board 420 (main printed circuit board 420) comprise separate and distinct circuit boards connected by a board-to-board connector (not shown). The first printed circuit board 410 is oriented on a first plane perpendicular to the first coordinate axis and located on a first level of the first coordinate axis. The second printed circuit board 420 is oriented on a second plane perpendicular to the first coordinate axis and located on a second level of the first coordinate axis. This second level differs from the first level on the first coordinate axis. In terms of relative orientation, the back side of the second printed circuit board 420 faces the first printed circuit board 410, and the top side of the second printed circuit board 420 faces away from the first printed circuit board 410. In the example of Fig. 4. In a system where the first coordinate axis (e.g., the Z-axis) increases in value from top to bottom, the second level will have a corresponding second value (e.g., a second Z-value) that is greater than a first value (e.g., a first Z-value) corresponding to the first level. However, if the value of the first coordinate axis (e.g., the Z-axis) increases from top to bottom... Fig. If the value decreases by 4, the second level has a corresponding second value (e.g., a second Z-value) that is smaller than a first value (e.g., a first Z-value) that corresponds to the first level.

[0038] The processing subsystem 400 can include a PCIe processing subsystem 400 connected to a PCIe chassis expansion slot 205 via the edge connector 410. Accordingly, the various components mounted on the main circuit board 420 must comply with the PCIe specifications / requirements, which include a maximum height limit for components that can be mounted on the rear of the main circuit board 420. Advantageously, the second level of the main circuit board 420 allows for the mounting of taller components on the rear of the main circuit board 420 compared to previous designs, while still meeting the PCIe height limitation specification based on and referenced by the first level of the edge connector 410.Specifically, the maximum height of the back-mounted components on the main circuit board 420 is measured relative to the surface of the edge connector 410 at the first level on the first coordinate axis according to PCIe specifications. By moving the main circuit board 420 to a different second level on the first coordinate axis, the actual height of the back-mounted components on the main circuit board 420 can be increased while still complying with the PCIe height limitation specification based on the first level of the edge connector 410.The increase in the actual physical height of the rear-mounted components achieved by the two-level printed circuit board design of the Processing Subsystem 400, while still complying with the PCIe height limitation specification, is equal to the absolute height difference / absolute height delta between the first level and the second level along the first coordinate axis (referred to here as the "height delta").

[0039] For example, the main circuit board 420 can include a second component 430 mounted on the back of the main circuit board 420 at a second height (h2). The second height (h2) is measured from the bottom of the second component 430, mounted on the back of the main circuit board 420 at the second level, to the top of the second component 430. The second height (h2) is the "actual height" (actual physical height) of the second component 430. However, the "specification height" of the second component 430 for determining compliance with the PCIe height limitation specification differs from the "actual height" of the second component 430. The "specification height" of the second component 430 for determining compliance with the PCIe height limitation specification is measured from the back surface of the edge connector 410 at the first level to the top of the second component 430.Generally, the "specified height" of a rear-mounted component is less than the "actual height" of the same rear-mounted component. As a result, components with a greater actual height can now be mounted on the rear side compared to previous designs.

[0040] Consequently, the two-level PCB design now allows for the mounting of relatively taller components on the back of the main PCB 420 while still meeting PCIe specifications. The level delta between the first and second levels along the first coordinate axis defines the increase in back-mounted component height achieved by the two-level PCB design while still adhering to the PCIe height limitation specification. This results in a more even distribution of components on the back and top of the main PCB 420, allowing for a greater number of components to be mounted on the back of the main PCB 420 compared to previous designs. This more even distribution of components on the back and top of the main PCB 420 also allows for a reduction in the surface area of ​​the PCB 420 compared to previous designs.The surface area of ​​the main circuit board 420 is defined by its dimensions along the second and third coordinate axes. As shown, the surface area of ​​the main circuit board 420 extends from the right side of the first fan 450 to the left side of the second fan 460. Specifically, the surface area of ​​the main circuit board 420 in the two-level circuit board design of the processing subsystem 400 is significantly smaller than the surface area of ​​the main circuit board 320 in the conventional processing subsystem 300. By reducing the surface area of ​​the main circuit board 420, the airflow within the processing subsystem 400 is increased, thereby improving heat dissipation and the processing performance of the processing subsystem 400.

[0041] Fig. Figure 5 is a side view of the map-based two-level processing subsystem 500. Fig. 4, according to various embodiments. The card-based processing subsystem 500 can be implemented in the embodiment described in the Fig. The computer system 100 illustrated in Figures 1-2 is implemented. As shown, the processing subsystem 500 comprises a first circuit board 510, a second circuit board 520, a board-to-board connector 530, a first fan 550, and a second fan 560. The first circuit board 510, the second circuit board 520, the first fan 550, and the second fan 560 are used in connection with Fig. 4 explained and will not be explained in detail here.

[0042] The first printed circuit board 510 comprises an edge connector 510, and the second printed circuit board 520 comprises a main printed circuit board 520. The board-to-board connector 530 connects the edge connector 510 to the main printed circuit board 520 to provide communication between the edge connector 510 and the main printed circuit board 520. Specifically, the board-to-board connector 530 transmits high-speed signals and power to and from the edge connector 510 and the main printed circuit board 520. The use of the board-to-board connector 530 allows the edge connector 510 and the main printed circuit board 520 to be divided into two separate printed circuit boards located at two different levels along the first coordinate axis. Specifically, the height of the board-to-board connector 530 along the first coordinate axis (e.g.,the Z-axis) corresponds to the level delta between the first level of the first circuit board 510 (edge ​​connector 510) and the second level of the second circuit board 520 (main circuit board 520) along the first coordinate axis and is used to define it.

[0043] As shown, the main circuit board 520 includes several top-mounted components, such as a first top-mounted component 580 and a second top-mounted component 582. The top-mounted components can include relatively large components, such as power components. The first top-mounted component 580 can include a processor, such as a GPU or another type of processing device. The main circuit board 520 also includes several back-mounted components, such as a first back-mounted component 570 and a second back-mounted component 572. The back-mounted components can also include relatively large components, such as power components.

[0044] In conventional designs, the power-intensive processor and all power components are typically placed on the top side of the main circuit board, resulting in a power concentration around the processor, which further increases heat generation. This concentrated power zone around the processor on the top side of the main circuit board raises the processor's temperature and hinders heat dissipation. An additional technical advantage of the revealed two-level circuit board design is that some of the power components can now be placed on the back side of the main circuit board. This reduces the power concentration on the top side of the main circuit board near the processor, thus automatically reducing the amount of heat generated near the processor and further improving the computing performance of the processing subsystem.

[0045] Fig. Figure 6 is an illustration of a perspective side view of the map-based two-level processing subsystem from Fig. 4 according to various embodiments. As shown, the processing subsystem 500 comprises a first printed circuit board 510, a second printed circuit board 520, a board-to-board connector 530, a first fan 550 and a second fan 560.

[0046] Fig. Figure 7 illustrates a conventional card-based processing subsystem that includes a heat sink, in accordance with the prior art. The conventional card-based processing subsystem 700 can be found in the [reference to be added]. Fig. The computer system 100 shown in 1-2 will be implemented. Fig. Figure 7 shows a perspective side view of the conventional card-based processing subsystem 700. As shown, the processing subsystem 700 comprises a single printed circuit board 702 and a top-mounted heat sink / heat exchanger 750, which has multiple cooling fins. The single printed circuit board 702 has a top and a back and includes an edge connector and a main printed circuit board. In the example of Fig. 7 is the conventional map-based processing subsystem 700 oriented correctly, with the first coordinate axis running from bottom to top. Fig. 7 increases in value. Therefore, the top side of the individual circuit board 702 is in Fig. 7 visible, while the back of the individual circuit board 702 in Fig. 7 is not visible.

[0047] As shown, an inlet airflow 760 enters the upper surface of the heat sink 750 from the right side, and an outlet airflow 780 exits the upper surface of the heat sink 750 from the left side, thus enabling passive cooling of the individual printed circuit board 702. The source of the inlet airflow 760 can be, for example, a server fan or another external airflow source. The direction of the inlet airflow 760 is only exemplary, and in other embodiments, the inlet airflow 760 can originate from a different direction. An upper surface airflow 770 exits the upper surface of the heat sink 750 at the top of the individual printed circuit board 702 to dissipate heat from the top of the individual printed circuit board 702. Thus, the conventional processing subsystem 700 can passively cool the top of the individual printed circuit board 702 via the upper surface of the heat sink 750.However, passive cooling of the back of the individual 702 circuit board, including the back of the main circuit board, is difficult because there is little space for airflow on the back of the individual 702 circuit board.

[0048] Fig. Figure 8 illustrates a two-level printed circuit board-based processing subsystem 800, which includes a heat sink, according to various embodiments. The processing subsystem 800 can be described in the Fig. 1-2 illustrated computer system 100 can be implemented. Fig. Figure 8 shows a perspective side view of the 800 processing subsystem.

[0049] As shown, the processing subsystem 800 comprises a first printed circuit board 810 (edge ​​connector 810), a second printed circuit board 820 (main printed circuit board 820), a board-to-board connector 830, a top-side heat sink / heat exchanger 850 comprising multiple cooling fins, a first rear-side heat sink / heat exchanger 852 comprising multiple cooling fins, and a second rear-side heat sink / heat exchanger 854 comprising multiple cooling fins. The top-side heat sink 850, the first rear-side heat sink 852, and the second rear-side heat sink 854 are each coupled directly or indirectly (thermally and / or mechanically) to the main printed circuit board 820 to provide passive cooling of the main printed circuit board 820. The main printed circuit board 820 has a top and a back side.

[0050] In the example of Fig. In Figure 8, the processing subsystem 800 is oriented correctly, with the first coordinate axis running from bottom to top. Fig. The value increases by 8. Thus, the top side of the main circuit board is 820 in Fig. 8 visible, while the back of the main circuit board 820 in Fig. 8 is not visible. With regard to the relative orientation, the back of the second circuit board 820 faces the first circuit board 810 and the board-to-board connector 830, while the top of the second circuit board 820 faces away from the first circuit board 410 and the board-to-board connector 830, while the board-to-board connector 830 is arranged between the first circuit board 410 and the second circuit board 820 along the first coordinate axis.

[0051] As shown, an inlet airflow 860 enters from the right side of the top heat sink 850 and the first rear heat sink 852, and an outlet airflow 880 exits from the left side of the top heat sink 850 and the second rear heat sink 854, passively cooling the top and rear surfaces of the main circuit board 820. The source of the inlet airflow 860 can be, for example, a server fan or another external airflow source. The direction of the inlet airflow 860 is only exemplary, and in other embodiments, the inlet airflow 860 may originate from a different direction. Additionally, an outlet airflow 870 exits the top heat sink 850 from the top surface of the main circuit board 820 to dissipate heat from the top surface of the main circuit board 820. Thus, the processing subsystem 800 can passively cool the top side of the main circuit board 820 via the top-side heat sink 850.Additionally, a rear airflow 872 exits from the first rear heat sink 852 and the second rear heat sink 854 on the rear side of the main circuit board 820 to dissipate heat from the rear side of the main circuit board 820. This allows the processing subsystem 800 to passively cool the rear side of the main circuit board 820 via the first rear heat sink 852 and the second rear heat sink 854.

[0052] As shown, the gap between the first printed circuit board 810 (edge ​​connector 810) and the second printed circuit board 820 (main printed circuit board 820), created by the two-level PCB architecture, allows airflow to be directed to the rear of the main printed circuit board 820, enabling passive cooling of the various rear-mounted components. Furthermore, the raised second level of the main printed circuit board 820 (along the first coordinate axis), created by the two-level PCB design architecture, allows for the addition of additional heat sinks to the processing subsystem 800. For example, the first rear-mounted heat sink 852 can be coupled (thermally and / or mechanically) to the right underside of the top-mounted heat sink 850 and / or to the right side of the main printed circuit board 820 (thermally and / or mechanically).As another example, the second rear heat sink 854 can be coupled (thermally and / or mechanically) to the lower left side of the top heat sink 850 and / or (thermally and / or mechanically) to the left side of the main circuit board 820.

[0053] Due to the raised second level of the main circuit board 820 (along the first coordinate axis), the first rear heat sink 852 and the second rear heat sink 854 can each be connected to the underside of the top heat sink 850 and extend towards and beneath the second level of the main circuit board 820 (along the first coordinate axis). In some embodiments, the first rear heat sink 852 and the second rear heat sink 854 can each extend towards and reach the first level of the edge connector 810 (along the first coordinate axis). In these embodiments, the processing subsystem 800 is enclosed on the top side by the top heat sink 850, on the right side by the first rear heat sink 852, and on the left side by the second rear heat sink 854.

[0054] In some embodiments, the heat sink 850 is directly (thermally and / or mechanically) connected to the processor (e.g., a GPU) mounted on the top side of the main circuit board 820 to provide additional passive cooling of the processor. In these embodiments, the back side of the main circuit board 820 comprises all relatively tall components, so that only relatively short components are mounted on the top side of the main circuit board 820. For example, the back side of the main circuit board 820 can comprise all components that are taller than the processor (along the first coordinate axis), making the processor the tallest component mounted on the top side of the main circuit board 820, thus allowing the heat sink 850 to be directly (thermally and / or mechanically) coupled to the processor on the top side.In earlier designs, the taller components mounted on the top of the main circuit board could prevent such direct coupling of the top surface with the processor.

[0055] In the above embodiments, which relate to the Fig. Referring to Figures 4-6, the two-level printed circuit board processing subsystem 400 comprises a thermal solution with one or more axial fans and / or radial fans. In other embodiments, however, the processing subsystem 400 may also comprise at least one passive thermal solution, such as a finned heat sink, which is (thermally and / or mechanically) connected to the one or more fans and / or the main printed circuit board. In the embodiments described above, which refer to Fig. Reference to Figure 8, the two-level printed circuit board processing subsystem 800 comprises a thermal solution with at least one heat sink / heat exchanger having multiple cooling fins. In other embodiments, however, each heat sink / heat exchanger in the processing subsystem 800 can be replaced by a different type of passive thermal solution. In further embodiments, each heat sink / heat exchanger can comprise a vapor chamber and heat tubes that employ evaporative cooling to transfer heat from the main printed circuit board to the cooling fins. In further embodiments, the processing subsystem 800 can also comprise at least one fan (axial or radial) that is (thermally and / or mechanically) connected to the at least one heat sink and / or the main printed circuit board.In some embodiments, for example, an inlet fan (axial or radial) can be coupled to the right side of the top heat sink 850 and / or the first rear heat sink 852 to increase the inlet airflow 860.

[0056] Fig. Figure 9, for example, illustrates a two-level printed circuit board-based processing subsystem 900, comprising multiple fans and heat sinks, according to various embodiments. The processing subsystem 900 can be found in the embodiment shown in the Fig. Figures 1-2 illustrate the implementation of computer system 100. As shown, the processing subsystem 900 comprises a first circuit board 910, a second circuit board 920, a first fan 950, and a second fan 960. The first circuit board 910, the second circuit board 920, the first fan 950, and the second fan 960 are used in connection with Fig.Section 4 explains these points and will not be discussed in detail here. The processing subsystem 900 also includes at least one heat sink / exchanger, such as a first heat sink / exchanger 952, which comprises several cooling fins, and / or a second heat sink / exchanger 962, which also comprises several cooling fins. The first heat sink / exchanger 952 can be coupled directly or indirectly (thermally and / or mechanically) to the second circuit board 920 and / or the first fan 950. The second heat sink / exchanger 962 can be coupled directly or indirectly (thermally and / or mechanically) to the second circuit board 920 and / or the second fan 960.

[0057] In summary, a processing subsystem, such as a PCIe graphics card, comprises a two-level printed circuit board (PCB) architecture consisting of a first PCB (an edge connector) and a second PCB (main PCB). The first PCB (edge ​​connector) is oriented on a first plane perpendicular to a first coordinate axis and is located at a first level on the first coordinate axis. The second PCB (main PCB) includes various components mounted on it, including a processor, such as a GPU. The second PCB is oriented on a second plane perpendicular to the first coordinate axis and is located at a second level on the first coordinate axis. This second level differs from the first level on the first coordinate axis.The processing subsystem also includes a board-to-board connector that communicatively couples / connects the first printed circuit board (edge ​​connector) and the second printed circuit board (main printed circuit board).

[0058] The PCIe specifications define a maximum component height that can be mounted on the back of the main PCB, measured relative to the first level of the edge connector on the first coordinate axis. In earlier designs, the main PCB was located at the same first level of the edge connector on the first coordinate axis, which, due to the PCIe specifications, meant that only relatively shorter components could be mounted on the back of the main PCB.In the disclosed two-level printed circuit board design architecture, however, the main circuit board is located on a second level on the first coordinate axis, which differs from the first level of the edge connector on the first coordinate axis, thus allowing taller components to be placed on the back of the main circuit board compared to previous approaches, while still meeting PCIe specifications.

[0059] In alternative embodiments, the processing subsystem comprises a multi-level printed circuit board (PCB) design architecture that includes three or more different PCB levels. For example, the multi-level PCB design architecture may include a first edge connector, a first main PCB, a first board-to-board connector that communicatively couples / connects the first edge connector and the first main PCB, a second main PCB, and a second board-to-board connector that communicatively couples / connects the first edge connector and the second main PCB.The first edge connector is aligned on a first plane perpendicular to a first coordinate axis and located at a first level on the first coordinate axis. The first main circuit board is aligned on a second plane perpendicular to the first coordinate axis and located at a second level on the first coordinate axis. The second main circuit board is aligned on a third plane perpendicular to the first coordinate axis and located at a third level on the first coordinate axis. The first, second, and third levels are each distinct levels on the first coordinate axis. In other embodiments, the multi-level circuit board design architecture can be implemented differently.

[0060] At least one technical advantage of the disclosed two-level printed circuit board (PCB) design over the prior art is that it allows the surface area of ​​the main PCB of a processing subsystem, such as a graphics card, to be significantly reduced compared to the PCB size in a conventional processing subsystem. Specifically, the two-level PCB design allows for the placement of relatively taller electronic components on the back side of the main PCB, resulting in a more even distribution of electronic components across both the top and back sides of the main PCB compared to the PCB in a conventional processing subsystem. This more even distribution of electronic components on both sides of the main PCB allows for a reduction in the main PCB's surface area.Consequently, a greater overall airflow can be achieved throughout a processing subsystem incorporating a two-level PCB design by improving airflow through a heat sink / heat exchanger due to reduced obstruction by the PCB and / or by improving airflow across the back and top surfaces of the main PCB and the processor and power components mounted on it. As a result, overall heat dissipation from the processing subsystem during operation can be improved, which can reduce the temperature of the processor and other attached electronic components and improve the overall computing performance of the processor and processing subsystem compared to what can be achieved with prior art designs. These technical advantages represent one or more technological advancements over the prior art.

[0061] Aspects of the subject matter described here are set out in the following numbered clauses. 1. In some embodiments, a processing subsystem comprises a first printed circuit board (PCB) comprising an edge connector oriented perpendicular to a first coordinate axis and located at a first level on the first coordinate axis, and a second printed circuit board perpendicular to the first coordinate axis and located at a second level on the first coordinate axis, wherein the second level is different from the first level and the second printed circuit board has a top surface on which a processor is mounted. 2. Processing subsystem according to clause 1, wherein the second printed circuit board has a back side facing the first printed circuit board and wherein the top side of the second printed circuit board faces away from the first printed circuit board. 3. Processing subsystem according to clause 1 or 2, further comprising a board-to-board connector that electronically couples the first printed circuit board and the second printed circuit board. 4. Processing subsystem according to one of clauses 1-3, wherein a level difference between the second level and the first level along the first coordinate axis corresponds to a height of the board-to-board connector along the first coordinate axis. 5. Processing subsystem according to one of clauses 1-4, wherein the board-to-board connector between the first printed circuit board and the second printed circuit board is arranged along the first coordinate axis. 6. Processing subsystem according to any of clauses 1-5, wherein a first component is mounted on the back of the second printed circuit board, the first component meets a height limitation specification and the height limitation specification at the first level is based on the first coordinate axis. 7. Processing subsystem according to one of clauses 1-6, wherein a specification height of the first component is measured based on the first level on the first coordinate axis to determine if the height limitation specification is met, an actual height of the first component is measured based on the second level on the first coordinate axis, and the actual height of the first component is greater than the specification height of the first component. 8. Processing subsystem according to any one of clauses 1-7, wherein the first component comprises a performance component. 9. Processing subsystem according to any one of clauses 1-8, further comprising at least one fan connected to the second circuit board. 10. Processing subsystem according to one of clauses 1-9, wherein the at least one fan is an axial or radial fan. 11. Processing subsystem according to one of clauses 1-10, further comprising at least one heat sink coupled to the second printed circuit board, wherein the at least one heat sink has multiple ribs. 12. Processing subsystem according to any of clauses 1-11, wherein the processing subsystem comprises a Peripheral Component Interconnect Express (PCIe) card and the edge connector can be adapted to connect to a PCIe slot of a main printed circuit board. 13. Processing subsystem according to any of clauses 1-12, wherein the processor includes a graphics processing unit. 14. Processing subsystem according to any of clauses 1-13, wherein the second printed circuit board further comprises a first component mounted on a rear side of the second printed circuit board and which satisfies a PCIe height limitation specification, and the PCIe height limitation specification at the first level is based on the first coordinate axis. 15. Processing subsystem according to any of clauses 1-14, further comprising at least one heat sink connected to the processor. 16. In some embodiments, a computer system comprises a chassis, a main printed circuit board arranged in the chassis, and a processing subsystem in the chassis which is communicatively coupled to the main printed circuit board and comprises a first printed circuit board (PCB) comprising an edge connector oriented perpendicular to a first coordinate axis and located at a first level on the first coordinate axis, and a second printed circuit board oriented perpendicular to the first coordinate axis and located at a second level on the first coordinate axis, the second level being different from the first level and the second printed circuit board having a top surface on which a processor is mounted. 17. Computer system according to clause 16, wherein the second printed circuit board has a back side facing the first printed circuit board and wherein the top side of the second printed circuit board faces away from the first printed circuit board. 18. Computer system according to clause 16 or 17, wherein the processing subsystem further comprises a board-to-board connector that electronically couples the first printed circuit board and the second printed circuit board. 19. Computer system according to one of clauses 16-18, wherein a level difference between the second level and the first level along the first coordinate axis corresponds to a height of the board-to-board connector along the first coordinate axis. 20. Computer system according to one of clauses 16-19, wherein the board-to-board connector between the first printed circuit board and the second printed circuit board is arranged along the first coordinate axis.

[0062] Any and all combinations of any claim elements mentioned in any of the claims and / or any elements described in this application fall in any way within the considered scope of the present disclosure and protection.

[0063] The descriptions of the various embodiments serve for illustrative purposes but do not claim to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be obvious to the person skilled in the art without departing from the scope and spirit of the described embodiments.

[0064] Aspects of the present embodiments can be embodied as a system, method, or computer program product. Accordingly, aspects of the present disclosure can take the form of a purely hardware variant, a purely software variant (including firmware, resident software, microcode, etc.), or an embodiment that combines software and hardware aspects, which may be generally referred to herein as a "module" or "system." Furthermore, any hardware and / or software technique, process, function, component, machine, module, or system described in the present disclosure can be implemented as a circuit or a set of circuits. Additionally, aspects of the present disclosure can take the form of a computer program product embodied in one or more computer-readable media containing computer-readable program code.The software constructs and units (e.g., engines, modules, GUIs, etc.) are stored in various embodiments in the memory(s) illustrated in the relevant system figure(s) and are executed by the processor(s) illustrated in the same system figures.

[0065] Any combination of one or more non-transient computer-readable media may be used. The computer-readable medium may be a computer-readable signaling medium or a computer-readable storage medium. A computer-readable storage medium may be, for example, but not exclusively, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a suitable combination thereof.More specific examples (a non-exhaustive list) of computer-readable storage medium include: an electrical connection with one or more wires, a portable computer disk, a hard disk, random-access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only storage device (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. For the purposes of this document, computer-readable storage medium can be any tangible medium capable of containing or storing a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0066] Aspects of the present disclosure are described above with reference to flowchart diagrams and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the disclosure. It is understood that each block of the flowchart diagrams and / or block diagrams, and combinations of blocks in the flowchart diagrams and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be fed to a processor of a general-purpose computer, a specialized computer, or other programmable data processing device to create a machine. When executed by the processor of the computer or other programmable data processing device, the instructions enable the implementation of the functions / actions specified in the flowchart and / or block diagram.Such processors can be, without restriction, general-purpose processors, special-purpose processors, application-specific processors, or field-programmable gate arrays.

[0067] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, procedures, and computer program products according to the various embodiments of the present disclosure. In this respect, each block in the flowchart or block diagrams can represent a module, segment, or part of the code comprising one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions specified in the block may occur out of the order shown in the figures. For example, two blocks shown consecutively may in reality be executed essentially simultaneously, or the blocks may sometimes be executed in reverse order, depending on the functionality involved.It is also noted that each block in the block diagrams and / or flowcharts, as well as combinations of blocks in the block diagrams and / or flowcharts, can be implemented by special hardware-based systems that perform the specified functions or actions, or by combinations of special hardware and computer instructions.

[0068] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be developed without deviating from its basic scope, and the scope of the disclosure is determined by the following claims.

Claims

[1] Processing subsystem, comprising: a first printed circuit board (PCB) comprising an edge connector oriented perpendicular to a first coordinate axis and located at a first level on the first coordinate axis; and a second circuit board that runs perpendicular to the first coordinate axis and is located on a second level on the first coordinate axis, the second level being different from the first level and the second circuit board having a top surface on which a processor is mounted. [2] Processing subsystem according to claim 1, wherein the second printed circuit board has a back side facing the first printed circuit board and wherein the top side of the second printed circuit board faces away from the first printed circuit board. [3] Processing subsystem according to claim 1 or 2, further comprising a board-to-board connector that electronically couples the first printed circuit board and the second printed circuit board. [4] Processing subsystem according to claim 3, wherein a level difference between the second level and the first level along the first coordinate axis corresponds to a height of the board-to-board connector along the first coordinate axis. [5] Processing subsystem according to claim 3 or 4, wherein the board-to-board connector between the first printed circuit board and the second printed circuit board is arranged along the first coordinate axis. [6] Processing subsystem according to one of the preceding claims, wherein a first component is mounted on the back of the second printed circuit board, the first component meets a height limitation specification and the height limitation specification at the first level is based on the first coordinate axis. [7] Processing subsystem according to claim 6, wherein: a specification height of the first component is measured based on the first level on the first coordinate axis to determine whether the height limitation specification is met; an actual height of the first component is measured on the basis of the second level on the first coordinate axis, and the actual height of the first component is greater than the specified height of the first component. [8] Processing subsystem according to claim 6 or 7, wherein the first component comprises a power component. [9] The processing subsystem according to one of the preceding claims further comprises at least one fan connected to the second circuit board. [10] Processing subsystem according to claim 9, wherein the at least one fan is an axial or radial fan. [11] Processing subsystem according to one of the preceding claims, further comprising at least one heat sink coupled to the second printed circuit board, wherein the at least one heat sink comprises several ribs. [12] Processing subsystem according to any one of the preceding claims, wherein: the processing subsystem includes a Peripheral Component Interconnect Express (PCIe) card; and The edge connector can be adapted so that it can be connected to a PCIe slot on a main circuit board. [13] Processing subsystem according to claim 12, wherein the processor comprises a graphics processing unit. [14] Processing subsystem according to claim 12 or 13, wherein: the second printed circuit board further comprises a first component that is mounted on a back side of the second printed circuit board and that meets a PCIe height limitation specification; and The PCIe height limitation specification is based on the first level on the first coordinate axis. [15] Processing subsystem according to one of the preceding claims, further comprising at least one heat sink coupled to the processor. [16] Computer system, comprising: a chassis; a main circuit board located inside the chassis; and a processing subsystem within the chassis that is communicatively connected to the main circuit board and includes: a first printed circuit board (PCB) comprising an edge connector oriented perpendicular to a first coordinate axis and located at a first level on the first coordinate axis; and a second circuit board that runs perpendicular to the first coordinate axis and is located on a second level on the first coordinate axis, the second level being different from the first level and the second circuit board having a top surface on which a processor is mounted. [17] Computer system according to claim 16, wherein the second printed circuit board has a back side facing the first printed circuit board and wherein the top side of the second printed circuit board faces away from the first printed circuit board. [18] Computer system according to claim 16 or 17, wherein the processing subsystem further comprises a board-to-board connector that electronically couples the first printed circuit board and the second printed circuit board. [19] Computer system according to claim 18, wherein a level difference between the second level and the first level along the first coordinate axis corresponds to a height of the board-to-board connector along the first coordinate axis. [20] Computer system according to claim 18 or 19, wherein the board-to-board connector between the first printed circuit board and the second printed circuit board is arranged along the first coordinate axis.

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