METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE WITH REDUCED INTERFACIAL THICKNESS

Abstract

A method for fabricating a semiconductor device comprises: forming a semiconductor structure on a semiconductor substrate, the semiconductor structure comprising: a first and a second source / drain region arranged on the semiconductor substrate in a first direction and spaced apart from each other in a second direction transverse to the first direction, and several channel structure elements arranged between and connected to the first and second source / drain regions and spaced apart from each other in the first direction; forming an interface material layer to cover the channel structure elements; forming a metal oxide layer on the interface material layer;Converting a section of the interface material layer into a metal silicate layer to form multiple interface structure elements, each covering the channel structure elements, with the metal silicate layer being formed between the metal oxide layer and each of the interface structure elements; and removing the metal oxide layer and the metal silicate layer.

Description

BACKGROUND

[0001] For several decades, the semiconductor industry has been working intensively on the development of integrated high-performance IC chips. An IC chip can contain multiple semiconductor devices (for example, nanolayer field-effect transistors, etc.). To increase the functional density (that is, the number of semiconductor devices per unit area) and the economic benefit of an IC chip, a continuous reduction of the smallest possible component sizes of the IC chip is necessary. However, miniaturizing the component sizes of the IC chip can lead to quality problems (for example, an interface layer located between a silicon channel and a gate dielectric may have more defects due to its reduced quality). These quality problems can adversely affect the performance of the semiconductor devices in the IC chip and the production yield of the IC chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Aspects of this disclosure are best understood with reference to the following detailed description, when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale. Rather, the dimensions of the various structural elements may be enlarged or reduced as necessary for the sake of clarity in this discussion. Fig. Figure 1 is a flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments. Fig. 2 to 10B are schematic views showing some intermediate stages of the process described in Fig. 1 illustrates the method shown according to some embodiments. DETAILED DESCRIPTION

[0003] The following disclosure provides many different embodiments or examples for implementing various features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, the formation of a first structural element over or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, so that the first and second structural elements are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not automatically create a relationship between the various designs and / or facilities discussed.

[0004] Furthermore, spatially relative terms, such as "on," "above," "upper," "lower," "top," and the like, may be used in this text to simplify the description and to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated by 90 degrees, or in other orientations), and the spatially relative descriptors used in this text may be interpreted accordingly. It should be noted that the one or more elements or features in the figures are exaggerated for the sake of clarity and are not to scale.

[0005] For the purposes of this specification and the accompanying claims, unless otherwise stated, all numbers expressing amounts, sizes, dimensions, proportions, shapes, formulations, parameters, percentages, quantities, properties and other numerical values ​​used in the specification and the claims shall in all cases be understood as modified by the term "approximately", even if the term "approximately" does not expressly appear next to the value, amount or range.Accordingly, unless otherwise specified, the numerical parameters given in the following specification and the attached claims are not exact and need not be exact, but may be approximate and / or larger or smaller as desired to reflect tolerances, conversion factors, rounding, measurement errors and the like, and other factors known to the skilled person, depending on the desired properties to be obtained with the subject matter disclosed in the present text.For example, when referring to a value, the term "approximately" may be meant to indicate that variations of ± 10% in some aspects, ± 5% in some aspects, ± 2.5% in some aspects, ± 1% in some aspects, ± 0.5% in some aspects, and ± 0.1% in some aspects of the stated amount are taken into account, since such variations are to be expected when carrying out the disclosed processes or in the practical application of the disclosed compositions.

[0006] The term “source / drain region” or “source / drain regions” can refer to a source or a drain individually or together, depending on the context.

[0007] An integrated circuit (IC) chip, which contains multiple semiconductor devices (for example, nanolayer field-effect transistors, etc.), is a crucial component in electronic products. A continuous reduction in the smallest possible feature sizes of IC chips is a trend in the semiconductor industry because it increases the functional density of the IC chip (i.e., the number of semiconductor devices per unit area) and improves the device performance of the semiconductor devices. For example, as an IC chip becomes smaller, the equivalent oxide thickness (EOT) of each semiconductor device decreases, and the drive current of each semiconductor device increases proportionally, which contributes to improved device performance.

[0008] However, reducing the size of the IC chip's structural elements can introduce several problems. For example, a common method for reducing the end-of-phase (EOT) (such as shortening the wet process time used to form an interface layer, for instance, made of silicon oxide) can lead to more defects (such as oxygen deficiencies), poor uniformity, and a higher adhesion density (an increase in adhesion-assisted tunneling) in the interface layer. In this case, electrons in a silicon channel covered by the interface layer can migrate through the defects in the interface layer to a metal gate located on the interface layer opposite the silicon channel, resulting in higher leakage current and a degradation of the IC chip's performance or the device performance of semiconductor devices.As another example, a process for forming the metal gate (made of aluminum or titanium, for instance) and / or a silicon cap layer placed on the metal gate can attract oxygen atoms into the interface layer, allowing the interface layer to be cleaned in subsequent thermal processes. This would lead to an increase in the adhesion density of the interface layer, which can negatively affect its quality.

[0009] The present disclosure relates to a semiconductor device and a method for its manufacture. Fig. 1 is a flowchart that describes a process 100A for producing a in Fig. 10A and Fig. Semiconductor device 200A shown in 10B is illustrated according to some embodiments. Fig. Figures 2 to 9E illustrate schematic views of some intermediate stages of procedure 100A. For the sake of clarity, in Fig. Sections 2 to 9E may have been omitted. Additional steps may be provided before, after, or during procedure 100A, and some of the steps described here may be replaced by other steps or omitted.

[0010] With reference to Fig. 1 and that in Fig. In the illustrated example 2, process 100A begins at step S01, where several semiconductor workpieces 1 are formed. One of the semiconductor workpieces 1 is in Fig. Figure 2 shows that step S01 can comprise substep (i) of forming a nanolayer stack (not shown) over a semiconductor substrate 11 and substep (ii) of etching sections of the nanolayer stack to form the semiconductor workpieces 1. In some embodiments, the semiconductor substrate 11 can, for example, contain an elemental semiconductor or a composite semiconductor. The elemental semiconductor contains a single atomic species, such as silicon or germanium from Group XIV of the periodic table, and can have a crystalline, polycrystalline, or amorphous structure. Other suitable materials for the elemental semiconductor are also within the intended scope of protection of this disclosure.The composite semiconductor contains two or more elements, examples of which may include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and gallium indium arsenide phosphide. Other suitable materials for the composite semiconductor are also within the intended scope of protection of this disclosure. The composite semiconductor may have a gradient profile, wherein its composition ratio changes from one location to another within the composite semiconductor. The composite semiconductor may be formed on a silicon substrate and may be strained. In some embodiments, the semiconductor substrate 11 may have a multilayer composite semiconductor structure.In some embodiments, the nanolayer stack comprises multiple sacrificial layers (not shown) and multiple channel layers (not shown) alternately stacked on the semiconductor substrate 11. In some embodiments, the sacrificial layers may comprise silicon germanium. Other suitable materials for the sacrificial layers are also within the intended scope of protection of this disclosure. In some embodiments, the channel layers may contain silicon. Other suitable materials for the channel layers are also within the intended scope of protection of this disclosure. The sacrificial layers and the channel layers may be formed by any suitable deposition process, for example, chemical vapor deposition (CVD) (for example, ultra-high vacuum CVD (UHV CVD)), or other suitable deposition processes.In some embodiments, the sacrificial layers and the channel layers can be formed by a suitable epitaxial growth process, for example, molecular beam epitaxy (MBE), or other suitable epitaxial growth processes. In some embodiments, the semiconductor workpieces 1 are spaced apart from one another in an X-direction parallel to a top surface of the semiconductor substrate 11. In some embodiments, each of the semiconductor workpieces 1 comprises a section of the semiconductor substrate 11 and a semiconductor stack 12' arranged on the section of the semiconductor substrate 11 in a Z-direction transverse to the X-direction.In some embodiments, the semiconductor stack 12' comprises several sacrificial layer sections 121', which are respective parts of the sacrificial layers of the nanolayer stack, and several channel layer sections 122', which are respective parts of the channel layers of the nanolayer stack, wherein the sacrificial layer sections 121' and the channel layer sections 122' are stacked alternately on top of each other along the Z-direction.

[0011] With reference to Fig. 1 and that in Fig. In the illustrated example 3, process 100A then proceeds to step S02, where several dummy gate structures 13 are formed on the semiconductor workpieces 1 in the Z direction. The dummy gate structures 13 are spaced apart from each other in a Y direction transverse to the X and Z directions. Each of the dummy gate structures 13 comprises a dummy gate dielectric 131, a dummy gate 132, a mask layer 133, and a mask layer 134, which are formed sequentially on the semiconductor workpieces 1 in the Z direction. Step S02 can include substep (i) of sequentially depositing respective material layers for the dummy gate dielectric 131, the dummy gate 132, the mask layer 133 and the mask layer 134 on the semiconductor workpieces 1 and substep (ii) of structuring the material layers by a photolithographic process to obtain the dummy gate dielectric 131, the dummy gate 132, the mask layer 133 and the mask layer 134.In some embodiments, partial step (i) can be carried out by a suitable deposition process, for example CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), plasma-enhanced ALD (PEALD), or other suitable deposition processes. Other suitable processes are also within the intended scope of protection of this disclosure.

[0012] The dummy gate dielectric 131 is arranged on the semiconductor workpieces 1 and may contain silicon oxide. Other suitable materials for forming the dummy gate dielectric 131 are also within the intended scope of protection of this disclosure. In some embodiments, the dummy gate dielectric 131 can serve as an etch stop layer.

[0013] The dummy gate 132 is arranged on the dummy gate dielectric 131 opposite the semiconductor workpieces 1. In some embodiments, the dummy gate 132 may contain polysilicon. Other suitable materials for forming the dummy gate 132 are also within the intended scope of protection of this disclosure.

[0014] The mask layer 133 is arranged on the dummy gate 132 opposite the dummy gate dielectric 131 and can be formed from a nitride-based material (for example, silicon nitride). The mask layer 134 is arranged on the mask layer 133 opposite the dummy gate 132 and can be formed from an oxide-based material (for example, silicon oxide). Other suitable materials for forming the mask layer 133 and the mask layer 134 are also within the intended scope of protection of this disclosure.

[0015] With reference to Fig. 1 and that in Fig. In the illustrated example 4, the process 100A then proceeds to step S03, where several dummy spacers 14 are formed to laterally cover the dummy gate structures 13, followed by a recessing of the semiconductor stack 12' (see Fig. 3) to form multiple source / drain trenches 15. Step S03 may include: substep (i) of conformally forming at least one dummy spacer material layer (not shown) over the in Fig. The structure shown in Figure 3 comprises substep (ii) of anisotropic etching of the at least one dummy spacer material layer such that horizontal sections of the at least one dummy spacer material layer are etched away to form the dummy spacers 14, and then substep (iii) of performing a photolithography process to recess the semiconductor stack 12', thereby forming the source / drain trenches 15 and several stacked structures 12, two adjacent structures of which are spaced apart by a corresponding source / drain trench 15. Each of the stacked structures 12 comprises several sacrificial structure elements 121 and several channel structure elements 122, arranged to alternate with the sacrificial structure elements 121 in the Z-direction.

[0016] In some embodiments, the at least one dummy spacer material layer for forming the dummy spacers 14 can, for example, comprise silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or combinations thereof. Other suitable materials for forming the dummy spacers 14 are also within the intended scope of protection of this disclosure. In some embodiments, the at least one dummy spacer material layer can be formed by a suitable deposition process, for example, CVD, PECVD, PVD, ALD, PEALD, or other suitable deposition processes. Other suitable processes for forming the dummy spacers 14 are also within the intended scope of protection of this disclosure.In some embodiments, each of the dummy spacers 14 can have an inner dummy spacer 141, which laterally covers a corresponding dummy gate structure 13, and an outer dummy spacer 142, which is arranged on a side wall of the inner dummy spacer 141. The source / drain grooves 15 are spaced apart from each other in the Y direction. Each of the source / drain grooves 15 can penetrate an upper section 111 of the semiconductor substrate 11 and can terminate at a lower section 112 of the semiconductor substrate 11.

[0017] With reference to Fig. 1 and that in Fig. In the illustrated example 5, the procedure 100A then proceeds to step S04, where several internal spacers 16 are formed.Step S04 may comprise: substep (i) of lateral recessing of the sacrificial structure elements 121 by an isotropic etching process to remove side sections of the sacrificial structure elements 121 based on a relatively high etch selectivity of the sacrificial structure elements 121 with respect to the channel structure elements 122, in order to form lateral recesses (not shown); substep (ii) of conformal forming of a material layer for internal spacers (not shown) to cover the semiconductor substrate 11, the channel structure elements 122, the dummy gate structures 13, and the dummy spacers 14 and to fill the lateral recesses; and substep (iii) of isotropic etching of the material layer for internal spacers to form the internal spacers 16 in the lateral recesses to laterally cover the sacrificial structure elements 121. After this step, several fin structures 10 are formed accordingly.The fin structures 10 are arranged on the semiconductor substrate 11 and are spaced apart from each other in the Y direction. Each of the fin structures 10 comprises a corresponding stacked structure 12 arranged on the semiconductor substrate 11, a corresponding dummy gate structure 13 arranged in the Z direction on the corresponding stacked structure 12, and the inner spacers 16 that laterally cover the sacrificial structure elements 121.

[0018] In some embodiments, the isotropic etching process for laterally removing the sacrificial structural elements 121 can be an isotropic dry etching process, an isotropic wet etching process, or a combination thereof. In some embodiments, the material layer for internal spacers for forming the internal spacers 16 can, for example, contain silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, materials with a low dielectric constant (k-value), or combinations thereof. Other suitable materials for forming the internal spacers 16 are also within the intended scope of protection of this disclosure. In some embodiments, the material layer for internal spacers can be formed by a suitable deposition process, for example, CVD, PECVD, PVD, ALD, PEALD, or other suitable deposition processes.Other suitable processes for forming the inner spacers 16 are also within the intended scope of protection of the present disclosure.

[0019] With reference to Fig. 1 and that in Fig. In the illustrated example 6, process 100A then proceeds to step S05, where several first layers 17, several second layers 18, and several source / drain structural elements 19 are formed sequentially. Step S05 can comprise substeps (i) to (iii).

[0020] In sub-step (i) the first layers 17 are formed in lower trench sections 15a of the source / drain trenches 15 (see Fig. 5) In some embodiments, the first layers 17 may be formed from a semiconductor material, for example, silicon. Other suitable materials for forming the first layers 17 are also within the intended scope of protection of this disclosure. In some embodiments, the first layers 17 may be formed, for example, by a deposition process (for example, CVD), an epitaxial growth process (for example, MBE), an epitaxial deposition / partial etching process (for example, a cyclic deposition-etch process (CDE process)), or a selective epitaxial growth process (SEG process). Other suitable processes for forming the first layers 17 are also within the intended scope of protection of this disclosure.

[0021] In step (ii), the second layers 18 are formed on top of the first layers 17 in the source / drain channels 15. In some embodiments, the second layers 18 can be formed from a dielectric material, for example, silicon oxide or silicon nitride. Other suitable materials for forming the second layers 18 are also within the scope of protection provided by this disclosure. In some embodiments, the second layers 18 can be formed by a suitable deposition process, for example, CVD, ALD, or other suitable deposition processes. Other suitable processes for forming the second layers 18 are also within the scope of protection provided by this disclosure.

[0022] In sub-step (iii) the source / drain structural elements 19 are formed on the second layers 18 in the upper trench sections 15b of the source / drain trenches 15 (see Fig. 5) In some embodiments, the source / drain structural elements 19 can be formed from silicon phosphide, silicon germanium, or silicon germanium boron. Other suitable materials for forming the source / drain structural elements 19 are also within the intended scope of protection of this disclosure. In some embodiments, the source / drain structural elements 19 can be formed by a suitable epitaxial growth process (for example, MBE). Other suitable processes for forming the source / drain structural elements 19 are also within the intended scope of protection of this disclosure. In some embodiments, the first layers 17, the second layers 18, and the source / drain structural elements 19 together serve as source / drain regions.

[0023] With reference to Fig. 1 and that in Fig. In the illustrated example 7, process 100A then proceeds to step S06, where several contact etch stop structural elements 20 and several inter-layer dielectric (ILD) structural elements 21 are formed on the source / drain structural elements 19. Step S06 can comprise substeps (i) to (iii).

[0024] In sub-step (i) a contact etch stop layer (not shown) is applied to form the contact etch stop structural elements 20 on the surface in Fig. The structure shown in Figure 6 is formed by a surface deposition process, for example, CVD or molecular layer deposition (MLD). Other suitable processes for forming the contact etch stop layer are also within the intended scope of protection of this disclosure. In some embodiments, the contact etch stop layer may, for example, contain silicon nitride, carbon-doped silicon nitride, or a combination thereof. Other suitable materials for forming the contact etch stop layer are also within the intended scope of protection of this disclosure.

[0025] In step (ii), a layer of dielectric material (not shown) is successively formed on the structure obtained in step (i) by a surface deposition process, for example CVD or MLD, to form the ILD structural elements 21. Other suitable processes for forming the layer of dielectric material are also within the intended scope of protection of this disclosure. In some embodiments, the layer of dielectric material may, for example, comprise silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. Other suitable materials for forming the layer of dielectric material are also within the intended scope of protection of this disclosure.

[0026] In step (iii), a planarization process is carried out to remove excess portions of the contact etch stop layer, the dielectric material layer, the mask layer 133, the mask layer 134, and portions of the dummy spacers 14 to obtain the contact etch stop structural elements 20 and the ILD structural elements 21. In some embodiments, the planarization process may, for example, be chemical-mechanical polishing (CMP). Other suitable planarization processes are also within the intended scope of protection of this disclosure.

[0027] With reference to Fig. 1 and that in Fig. In the illustrated example 8, the process 100A then proceeds to step S07, where the sacrificial structural elements 121, the dummy gate dielectrics 131 and the dummy gates 132 (see Fig. 7) are removed to form several first cavities 22 and several second cavities 23. Step S07 can be performed by one or more etching processes. The etching processes can include a wet etching process, a dry etching process, or a combination thereof. Other suitable etching processes are also within the intended scope of protection of this disclosure. The first cavities 22 are defined by the inner dummy spacers 141 and an uppermost of the channel structure elements 122, and the second cavities 23 are defined by the inner spacers 16 and the channel structure elements 122. In some embodiments, two adjacent channel structure elements 122 can be separated by a distance (d) in the range of about 8 Å to about 12 Å.

[0028] With reference to Fig. 1 and that in Fig. In the example illustrated in Figures 9A to 9E, the process 100A then proceeds to step S08, where several interface structure elements 24 are formed. Step S08 comprises substeps (i) to (iv).

[0029] In sub-step (i), as in Fig. As shown in Figure 9B, an interface material layer 24' is formed by subjecting the channel structure elements 122 and the upper section 111 of the semiconductor substrate 11 to surface oxidation. Fig. Figure 9B shows only that the interface material layer 24' is formed by the surface oxidation of the channel structure elements 122. The interface material layer 24' covers each of the channel structure elements 122. In some embodiments, the interface material layer 24' can, for example, contain silicon dioxide (SiO2, i.e., stoichiometric silicon dioxide). In some embodiments, the interface material layer 24' can be formed by the Fig. The structure shown in Figure 8 is impregnated in a heated chemical agent to obtain the interfacial material layer 24' with a saturation thickness. In some embodiments, the chemical agent may, for example, comprise carbonated deionized water (DICO2), deionized water, ozonated deionized water, an aqueous ammonia solution, hydrochloric acid, sulfuric acid, hydrogen peroxide, or combinations thereof. Other suitable chemical agents are also within the intended scope of protection of this disclosure. In some embodiments, the Fig. The structure shown in Figure 8 is impregnated in the heated chemical agent at a temperature in the range of approximately 50 °C to approximately 75 °C. If the temperature is lower than approximately 50 °C, the saturation thickness of the interface material layer 24' is difficult to achieve. If the temperature is above approximately 75 °C, the composition ratio of the chemical agent may need to be changed, and the saturation thickness of the interface material layer 24' will be difficult to achieve. In some embodiments, the Fig. The structure shown in Figure 8 is to be impregnated in the heated chemical medium for a period of time ranging from about 60 seconds to about 200 seconds. If the period is less than about 60 seconds, the saturation thickness of the interface material layer 24' is difficult to achieve. In some embodiments, the saturation thickness of the interface material layer 24' can be in the range of about 8 Å to about 15 Å.

[0030] In sub-step (ii), as in Fig. As shown in Figure 9C, a metal oxide layer 25 is conformally formed on the structure obtained after partial step (i). In some embodiments, the metal oxide layer 25 can, for example, contain yttrium oxide, scandium oxide, lutetium oxide, lanthanum oxide, zinc oxide, or combinations thereof. Other suitable metal oxide materials are also within the intended scope of protection of this disclosure. In some embodiments, the metal oxide layer 25 can be conformally formed by a suitable deposition process, for example, CVD or ALD. In this case, the metal oxide layer 25 can be conformally formed by CVD or ALD on any geometric structure (i.e., without structural loading). Other suitable processes for forming the metal oxide layer 25 are also within the intended scope of protection of this disclosure.In some embodiments, the metal oxide layer 25 can have a thickness in the range of about 3 Å to about 15 Å. If the thickness of the metal oxide layer 25 is less than about 3 Å, the metal oxide layer 25 may have poor coverage on the structure obtained after step (i). If the thickness of the metal oxide layer 25 is greater than about 15 Å, the metal oxide layer 25 may not be readily removable (as described in step (iv)). In some embodiments, the metal oxide layer 25 can have a carbon concentration of less than about 1%. If the carbon concentration in the metal oxide layer 25 is greater than about 1%, the reliability of the correspondingly formed semiconductor device 200A may be impaired. In some embodiments, the metal oxide layer 25 can provide oxygen atoms to compensate for oxygen defects 24a in the interface material layer 24'.

[0031] In sub-step (iii), as in Fig. As shown in Figure 9D, a metal silicate layer 26 and the interfacial structure elements 24 are formed, the metal silicate layer 26 being formed between each of the interfacial structure elements 24 and the metal oxide layer 25. The metal silicate layer 26 is formed by the consumption of silicon atoms from the interfacial material layer 24' and contains metal atoms originating from the metal oxide layer 25. In some embodiments, the metal silicate layer 26 can form spontaneously due to the consumption of silicon atoms on a surface of the interfacial material layer 24' (silicon atoms can be attracted to and trapped by the metal oxide layer 25). In some embodiments, heat treatment can be performed on the structure obtained after partial step (ii) to facilitate the formation of the metal silicate layer 26. In some embodiments, the heat treatment can be a tempering treatment.In some embodiments, the tempering treatment can be carried out at a temperature in the range of approximately 500 °C to approximately 800 °C. If the tempering temperature is lower than approximately 500 °C, the uniformity of the metal silicate layer 26 may be impaired. If the tempering temperature is higher than approximately 800 °C, metal atoms from the metal oxide layer 25 may diffuse into the channel structure elements 122. In some embodiments, the tempering treatment duration may range from approximately 10 seconds to approximately 60 seconds. Similarly, the uniformity of the metal silicate layer 26 may be impaired if the tempering treatment duration is less than approximately 10 seconds. If the tempering treatment duration is greater than approximately 60 seconds, the metal atoms from the metal oxide layer 25 may diffuse into the channel structure elements 122.In some embodiments, the metal silicate layer 26 can have a thickness in the range of about 3 Å to about 5 Å. In some embodiments, after this partial step, the thickness of the interface material layer 24' is reduced due to the formation of the metal silicate layer 26, and some of the oxygen vacancies 24a of the interface material layer 24' can be occupied by oxygen atoms 24b originating from the metal oxide layer 25.

[0032] In sub-step (iv), as in Fig. As shown in Figure 9E, the metal oxide layer 25 and the metal silicate layer 26 are removed by a wet treatment to reveal the Fig. The structure shown in Figure 9A is formed. In some embodiments, the wet treatment is carried out using a wet chemical agent, for example, hot deionized water (HDI), a mixture of hydrochloric acid, hydrogen peroxide, and deionized water (in a mixing ratio in the range of about 1:1:2 to about 1:1:10), dilute hydrochloric acid (dHCl, a mixture of hydrochloric acid and deionized water with a mixing ratio in the range of about 1:20 to about 1:100), or carbonated deionized water (DICO2). Other suitable wet chemical agents used in the wet treatment are also within the intended scope of protection of this disclosure.In some embodiments, after this partial step, the thicknesses of the interface structure elements 24 thus formed are reduced compared to the thickness of the interface material layer 24' because a section of the interface material layer 24' is converted into the metal silicate layer 26, which is then removed. It should be noted that the removal of the metal silicate layer 26 may depend on the temperature and the duration of the wet treatment. Furthermore, a slight extension of the wet treatment duration may not affect the quality of the interface structure elements 24 thus formed.

[0033] After step S08, the interface material layer 24' is formed into the interface structure elements 24. Each of the interface structure elements 24 has a thickness that is less than the thickness of the interface material layer 24'. In some embodiments, the thickness of each of the interface structure elements 24 is in the range of about 5 Å to about 12 Å. In some embodiments, the thickness difference between the interface material layer 24' and each of the interface structure elements 24 is in the range of about 4 Å to about 10 Å. The interface structure elements 24 thus formed contain silicon dioxide (SiO2) in a stoichiometric state (i.e., SiO2 with a silicon-to-oxygen ratio of 1:2) and possess high thermal stability and are formed with good robustness, with each silicon atom covalently bonded to four oxygen atoms in a tetrahedral arrangement.Furthermore, each of the interfacial structure elements 24 can have hydroxyl bonds (-OH bonds) on its surface due to the use of hydrogen peroxide in the wet treatment (i.e., sub-step (iv)), which is beneficial to improving the uniformity of the gate dielectric structure elements 27 that are subsequently formed on the interfacial structure elements 24 (i.e., step S09).

[0034] By providing the interface structure elements 24 with reduced thickness, good robustness and high thermal stability, the EOT of the semiconductor device 200A can be reduced, the uniformity of the gate dielectric structure elements 27 can be improved, and the gate leakage current of the semiconductor device 200A can be reduced.

[0035] With reference to Fig. 1 and that in Fig. 10A and Fig. In the illustrated example 10B, the process 100A then proceeds to step S09, where the gate dielectric structural elements 27 and several metal gate structural elements 28 are successively formed in the first cavities 22 and the second cavities 23 (see Fig. 9A). Fig. Figure 10B illustrates a cross-sectional view along line II of Fig. 10A. Step S09 may include substeps (i) and (ii).

[0036] In sub-step (i), a film of dielectric material (not shown) for forming the gate dielectric structural elements 27 and a film of conductive material (not shown) for forming the metal gate structural elements 28 are successively formed in the first cavities 22 and the second cavities 23 and over the dummy spacers 14, the contact etch stop structural elements 20, and the ILD structural elements 21. In some embodiments, the film of dielectric material may be formed from a material with a high k-value. In some embodiments, the high k-value material may be an insulating material with a wide band gap and good thermal stability. In some embodiments, the high k-value material may be magnesium oxide, calcium oxide, aluminum oxide, zirconium silicate, scandium oxide, or combinations thereof.Other suitable materials with a high k-value for forming the dielectric film are also within the intended scope of protection of this disclosure. In some embodiments, the dielectric film can be formed by a suitable deposition process, for example, CVD or ALD. Other suitable processes for forming the dielectric film are also within the intended scope of protection of this disclosure. In some embodiments, the conductive film can contain, for example, aluminum, copper, tungsten, cobalt, ruthenium, titanium, tantalum, molybdenum, nickel, platinum, or combinations thereof. In some embodiments, the conductive film can be made of an N-type metal, a P-type metal, or a combination thereof.Other suitable materials for forming the conductive film are also within the intended scope of protection of this disclosure. In some embodiments, the conductive film can be formed by a suitable deposition process, for example, CVD, PVD, or electroless plating. Other suitable processes for forming the conductive film are also within the intended scope of protection of this disclosure.

[0037] In sub-step (ii) a planarization process (for example CMP or other suitable planarization processes) is carried out to remove an excess section of the film of dielectric material and an excess section of the film of conductive material over the dummy spacers 14, the contact etch stop structural elements 20 and the ILD structural elements 21 to obtain the gate dielectric structural elements 27 and the metal gate structural elements 28.

[0038] After step S09, the semiconductor device 200A is obtained. In some embodiments, the semiconductor device 200A can be a nanolayer field-effect transistor. In some embodiments, each of the interface structure elements 24 is surrounded and covered by a corresponding gate dielectric structure element 27. In some embodiments, as in Fig.As shown in Figure 10B, each of the channel structure elements 122 can have a thickness (T) in the range of about 5 nm to about 8 nm. In some embodiments, each of the channel structure elements 122 can have a width (W) in the range of about 15 nm to about 50 nm. In some embodiments, each of the upper sections 111 of the semiconductor substrate 11 is located between two corresponding adjacent insulation sections 29. In some embodiments, each of the insulation sections 29 can be a section of shallow trench insulation (STI), deep trench insulation (DTI), or other suitable insulation structure elements.

[0039] In a semiconductor device of this disclosure, each of several interface structure elements can be smaller in size (for example, relatively thin) and of improved quality (for example, fewer defects and high thermal stability). This facilitates the improvement of the quality of several gate dielectric structure elements subsequently formed on the interface structure elements, thereby reducing the EOT (end-of-temperature) and gate leakage current of the semiconductor device without reducing the thickness of the gate dielectric structure elements. Furthermore, the thickness of each interface structure element does not undesirably increase after a thermal gate loop process for forming the gate dielectric structure elements and several metal gate structure elements.The formation of the interface structure elements involves the sequential deposition of an interface material layer and a metal oxide layer on several silicon channel structure elements to form a metal silicate layer on the silicon channel structure elements, followed by the removal of the metal oxide layer and the metal silicate layer.

[0040] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device comprises: forming a semiconductor structure on a semiconductor substrate, wherein the semiconductor structure comprises: a first source / drain region and a second source / drain region arranged on the semiconductor substrate in a first direction normal to the semiconductor substrate and spaced apart from each other in a second direction transverse to the first direction, and several channel structure elements arranged between and connected to the first source / drain region and the second source / drain region and spaced apart from each other in the first direction; forming an interface material layer to cover the several channel structure elements; forming a metal oxide layer on the interface material layer;Converting a section of the interface material layer into a metal silicate layer to form multiple interface structure elements, each covering the multiple channel structure elements, with the metal silicate layer being formed between the metal oxide layer and each of the multiple interface structure elements; and removing the metal oxide layer and the metal silicate layer.

[0041] According to some embodiments of the present disclosure, the interface material layer comprises silicon dioxide.

[0042] According to some embodiments of the present disclosure, the metal oxide layer contains yttrium oxide, scandium oxide, lutetium oxide, lanthanum oxide, zinc oxide or combinations thereof.

[0043] According to some embodiments of the present disclosure, the metal oxide layer is formed by atomic layer deposition or chemical evaporation.

[0044] According to some embodiments of the present disclosure, the metal oxide layer has a thickness in the range of about 3 Å to about 15 Å.

[0045] According to some embodiments of the present disclosure, the metal oxide layer has a carbon concentration of less than about 1%.

[0046] According to some embodiments of the present disclosure, the metal silicate layer has a thickness in the range of about 3 Å to about 5 Å.

[0047] According to some embodiments of the present disclosure, the interface material layer has a thickness in the range of about 8 Å to about 15 Å.

[0048] According to some embodiments of the present disclosure, each of the interface structure elements has a thickness in the range of about 5 Å to about 12 Å.

[0049] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device comprises: forming a semiconductor structure on a semiconductor substrate, wherein the semiconductor structure has: a first source / drain region and a second source / drain region arranged on the semiconductor substrate in a first direction normal to the semiconductor substrate and spaced apart from each other in a second direction transverse to the first direction, and several channel structure elements arranged between and connected to the first source / drain region and the second source / drain region and spaced apart from each other in the first direction; performing, on the several channel structure elements, a surface oxidation to form an interface material layer covering each of the several channel structure elements; forming a metal oxide layer on the interface material layer;Converting a section of the interface material layer into a metal silicate layer to form multiple interface structure elements, each covering the multiple channel structure elements, with the metal silicate layer being formed between the metal oxide layer and each of the multiple interface structure elements; and removing the metal oxide layer and the metal silicate layer.

[0050] According to some embodiments of the present disclosure, the surface oxidation is carried out by impregnating the semiconductor structure in a heated chemical agent comprising carbonized deionized water, deionized water, ozonated deionized water, an aqueous ammonia solution, hydrochloric acid, sulfuric acid, hydrogen peroxide or combinations thereof.

[0051] According to some embodiments of the present disclosure, the surface oxidation is carried out at a temperature in the range of about 50 °C to about 75 °C.

[0052] According to some embodiments of the present disclosure, the surface oxidation is carried out for a period of time in the range of about 60 seconds to about 200 seconds.

[0053] According to some embodiments of the present disclosure, the metal oxide layer and the metal silicate layer are removed by impregnating the semiconductor structure in a chemical agent comprising hot deionized water, a mixture of hydrochloric acid, hydrogen peroxide and deionized water, dilute hydrochloric acid or carbonated deionized water.

[0054] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device comprises: forming a semiconductor structure on a semiconductor substrate, wherein the semiconductor structure comprises: a first source / drain region and a second source / drain region arranged on the semiconductor substrate in a first direction normal to the semiconductor substrate and spaced apart from each other in a second direction transverse to the first direction, and several channel structure elements arranged between and connected to the first source / drain region and the second source / drain region and spaced apart from each other in the first direction; forming an interface material layer to cover each of the several channel structure elements; forming a metal oxide layer on the interface material layer;Performing a thermal treatment on the interface material layer and the metal oxide layer to form a metal silicate layer and several interface structure elements, each covering the several channel structure elements, with the metal silicate layer being formed between the metal oxide layer and each of the several interface structure elements; and removing the metal oxide layer and the metal silicate layer.

[0055] According to some embodiments of the present disclosure, the surface oxidation is carried out by impregnating the semiconductor structure in a heated chemical agent comprising carbonized deionized water, deionized water, ozonated deionized water, an aqueous ammonia solution, hydrochloric acid, sulfuric acid, hydrogen peroxide or combinations thereof.

[0056] According to some embodiments of the present disclosure, the surface oxidation is carried out at a temperature in the range of about 50 °C to about 75 °C.

[0057] According to some embodiments of the present disclosure, the surface oxidation is carried out over a period of time ranging from about 60 seconds to about 200 seconds.

[0058] According to some embodiments of the present disclosure, the metal oxide layer and the metal silicate layer are removed by impregnating the semiconductor structure in a chemical agent comprising hot deionized water, a mixture of hydrochloric acid, hydrogen peroxide and deionized water, dilute hydrochloric acid or carbonated deionized water.

[0059] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device comprises: forming a semiconductor structure on a semiconductor substrate, wherein the semiconductor structure comprises: a first source / drain region and a second source / drain region arranged on the semiconductor substrate in a first direction normal to the semiconductor substrate and spaced apart from each other in a second direction transverse to the first direction, and several channel structure elements arranged between and connected to the first source / drain region and the second source / drain region and spaced apart from each other in the first direction; forming an interface material layer to cover each of the several channel structure elements; forming a metal oxide layer on the interface material layer;Performing a thermal treatment on the interface material layer and the metal oxide layer to form a metal silicate layer and several interface structure elements, each covering the several channel structure elements, with the metal silicate layer being formed between the metal oxide layer and each of the several interface structure elements; and removing the metal oxide layer and the metal silicate layer.

[0060] According to some embodiments of the present disclosure, the thermal treatment is carried out at a temperature in the range of about 500 °C to about 800 °C.

[0061] According to some embodiments of the present disclosure, the heat treatment is carried out over a period of time ranging from about 10 seconds to about 600 seconds.

[0062] According to some embodiments of the present disclosure, the thermal treatment is a tempering treatment.

[0063] According to some embodiments of the present disclosure, the thickness difference between the interface material layer and each of the interface structure elements is in the range of about 4 Å to about 10 Å.

[0064] According to some embodiments of the present disclosure, the method for manufacturing the semiconductor device further comprises: after removing the metal oxide layer and the metal silicate layer, forming several gate dielectric structural elements, each of which covers the interface structural elements and contains magnesium oxide, calcium oxide, aluminum oxide, zirconium silicate, scandium oxide or combinations thereof.

[0065] The above outlines features of various embodiments so that the person skilled in the art can better understand the aspects of the present disclosure. It is clear to the person skilled in the art that they can readily use the present disclosure as a basis for designing or modifying processes or structures to achieve the same purposes and / or advantages as in the embodiments presented in this text. It should also be clear to the person skilled in the art that such equivalent designs do not depart from the essence and scope of protection of the present disclosure, and that they can make various changes, substitutions, and modifications to the present invention without departing from the essence and scope of protection of the present disclosure.

Claims

[1] Method for manufacturing a semiconductor device, comprising: Forming a semiconductor structure on a semiconductor substrate, wherein the semiconductor structure has: a first source / drain region and a second source / drain region, which are arranged on the semiconductor substrate in a first direction normal to the semiconductor substrate and which are spaced apart from each other in a second direction transverse to the first direction, and several channel structure elements that are arranged between and connected to the first source / drain region and the second source / drain region and that are spaced apart from each other in the first direction; Forming an interface material layer to cover each of the multiple channel structure elements; Formation of a metal oxide layer on the interface material layer; Converting a section of the interface material layer into a metal silicate layer to form multiple interface structure elements, each covering the multiple channel structure elements, with the metal silicate layer being formed between the metal oxide layer and each of the multiple interface structure elements; and Removal of the metal oxide layer and the metal silicate layer. [2] Method according to claim 1, wherein the interface material layer contains silicon dioxide. [3] Method according to claim 1 or 2, wherein the metal oxide layer contains yttrium oxide, scandium oxide, lutetium oxide, lanthanum oxide, zinc oxide or combinations thereof. [4] Method according to any of the preceding claims, wherein the metal oxide layer is formed by atomic layer deposition or chemical evaporation. [5] Method according to any of the preceding claims, wherein the metal oxide layer has a thickness in the range of 3 Å to 15 Å. [6] Method according to any of the preceding claims, wherein the metal oxide layer has a carbon concentration of less than 1%. [7] Method according to any of the preceding claims, wherein the metal silicate layer has a thickness in the range of 3 Å to 5 Å. [8] Method according to any of the preceding claims, wherein the interface layer has a thickness in the range of 8 Å to 15 Å. [9] Method according to claim 8, wherein each of the interface structure elements has a thickness in the range of 5 Å to 12 Å. [10] Method for manufacturing a semiconductor device, comprising: Forming a semiconductor structure on a semiconductor substrate, wherein the semiconductor structure has: a first source / drain region and a second source / drain region, which are arranged on the semiconductor substrate in a first direction normal to the semiconductor substrate and which are spaced apart from each other in a second direction transverse to the first direction, and several channel structure elements that are arranged between and connected to the first source / drain region and the second source / drain region and that are spaced apart from each other in the first direction; Perform a surface oxidation on the multiple channel structure elements to form an interfacial material layer that covers each of the multiple channel structure elements; Formation of a metal oxide layer on the interface material layer; Converting a section of the interface material layer into a metal silicate layer to form multiple interface structure elements, each covering the multiple channel structure elements, with the metal silicate layer being formed between the metal oxide layer and each of the multiple interface structure elements; and Removal of the metal oxide layer and the metal silicate layer. [11] Method according to claim 10, wherein the surface oxidation is carried out by impregnating the semiconductor structure in a heated chemical medium comprising carbonized deionized water, deionized water, ozonized deionized water, an aqueous ammonia solution, hydrochloric acid, sulfuric acid, hydrogen peroxide or combinations thereof. [12] Method according to claim 10 or 11, wherein the surface oxidation is carried out at a temperature in the range of 50 °C to 75 °C. [13] Method according to any one of the preceding claims 10 to 12, wherein the surface oxidation is carried out over a period of time in the range of 60 seconds to 200 seconds. [14] Method according to any one of the preceding claims 10 to 13, wherein the metal oxide layer and the metal silicate layer are removed by impregnating the semiconductor structure in a chemical agent comprising hot deionized water, a mixture of hydrochloric acid, hydrogen peroxide and deionized water, dilute hydrochloric acid or carbonized deionized water. [15] Method for manufacturing a semiconductor device, comprising: Forming a semiconductor structure on a semiconductor substrate, wherein the semiconductor structure has: a first source / drain region and a second source / drain region, which are arranged on the semiconductor substrate in a first direction normal to the semiconductor substrate and which are spaced apart from each other in a second direction transverse to the first direction, and several channel structure elements that are arranged between and connected to the first source / drain region and the second source / drain region and that are spaced apart from each other in the first direction; Forming an interface material layer to cover each of the multiple channel structure elements; Formation of a metal oxide layer on the interface material layer; Performing a thermal treatment on the interface material layer and the metal oxide layer to form a metal silicate layer and several interface structure elements, each covering the several channel structure elements, wherein the metal silicate layer is formed between the metal oxide layer and each of the several interface structure elements; and Removal of the metal oxide layer and the metal silicate layer. [16] Method according to claim 15, wherein the thermal treatment is carried out at a temperature in the range of 500 °C to 800 °C. [17] Method according to claim 15 or 16, wherein the thermal treatment is carried out over a period of 10 seconds to 600 seconds. [18] Method according to any one of the preceding claims 15 to 17, wherein the thermal treatment is a tempering treatment. [19] Method according to any one of the preceding claims 15 to 18, wherein the thickness difference between the interface material layer and each of the interface structure elements is in the range of 4 Å to 10 Å. [20] Method according to any one of the preceding claims 15 to 19, further comprising, after removing the metal oxide layer and the metal silicate layer, forming several gate dielectric structural elements, each of which covers the interface structural elements and contains magnesium oxide, calcium oxide, aluminum oxide, zirconium silicate, scandium oxide or combinations thereof.

Images