Semiconductor structure and method for its manufacture

Abstract

A method for fabricating a semiconductor structure comprises the following: fabricating a fin structure; creating a first and a second source / drain groove in the fin structure; fabricating a first and a second semiconductor material layer in the first and the second source / drain groove, respectively; and fabricating a first and a second source / drain element over the first and the second semiconductor material layer in the first and the second source / drain groove, respectively.The process further comprises the following: inverting the semiconductor structure; fabricating a hard mask layer on a back side of the substrate; etching the hard mask layer and the substrate to create a first opening that exposes the first semiconductor material layer; fabricating an insulating layer on a side wall of the first opening; removing the first semiconductor material layer to create a second opening that exposes the first source / drain element; and depositing a conductive material in the first and second openings to establish a first source / drain contact.

Description

background

[0001] The IC (integrated semiconductor circuit) industry has experienced exponential growth. Technological advances in IC materials and designs have produced generations of ICs, each generation featuring smaller and more complex circuits than the previous one. Throughout IC evolution, feature density (i.e., the number of interconnected devices per unit area of ​​the chip) has generally increased, while feature size (i.e., the smallest component or trace that can be produced by a manufacturing process) has decreased. This miniaturization process generally offers advantages by increasing production efficiency and reducing associated costs, but it has also increased the complexity of machining and manufacturing ICs. For these improvements to be realized, similar advancements in IC machining and fabrication are necessary.

[0002] As IC technologies evolve toward smaller technology nodes, multigate metal-oxide-semiconductor field-effect transistors (multigate MOSFETs or multigate devices) have been introduced to improve gate control by increasing gate-channel coupling, reducing turn-off current, and mitigating short-channel effects (SCEs). A multigate device generally refers to a device that has a gate structure, or part thereof, that extends over more than one side of a channel region. Gate-all-around transistors (GAA transistors) are examples of multigate devices that are widely used and are promising candidates for high-power and low-leakage applications. A GAA transistor has a gate structure that can extend completely or partially around a channel region to provide access to the channel region on two or more sides.While existing GAA transistors may be generally suitable for their intended purposes, they are not yet satisfactory in every respect. Brief description of the drawings

[0003] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. The Fig. Figures 1 to 4 are perspective views of a workpiece at different manufacturing stages according to some embodiments of the present disclosure. The Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A, Fig. 18A, Fig. 19A, Fig. 20A and Fig. 21A are xz-sectional views of the workpiece at different manufacturing stages along a line A - A' of Fig. 4 according to some embodiments of the present disclosure. The Fig. 5B, Fig. 6B, Fig. 7B, Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 13B, Fig. 14B, Fig. 15B, Fig. 16B, Fig. 17B, Fig. 18B, Fig. 19B, Fig. 20B and Fig. 21B are yz-sectional views of the workpiece at different manufacturing stages along a line B - B' of Fig. 4 according to some embodiments of the present disclosure. Fig. 21C is a yz-sectional view of the workpiece at a manufacturing stage along a line C - C' of Fig. 4 according to some embodiments of the present disclosure. Fig. Figure 22 is an xz-sectional view of a workpiece at a manufacturing stage along line A - A' of Fig. 4 according to some alternative embodiments of the present disclosure. The Fig. 23A, Fig. 24A, Fig. 25A, Fig. 26A, Fig. 27A, Fig. 28A and Fig. 29A are xz-sectional views of the workpiece at various manufacturing stages along the line A - A' of Fig. 4 according to some alternative embodiments of the present disclosure. The Fig. 23B, Fig. 24B, Fig. 25B, Fig. 26B, Fig. 27B, Fig. 28B and Fig. 29B are yz-sectional views of the workpiece at various manufacturing stages along the line B - B' of Fig. 4 according to some alternative embodiments of the present disclosure. Fig. 29C is a yz-sectional view of the workpiece at a manufacturing stage along the line C - C' of Fig. 4 according to some alternative embodiments of the present disclosure. Detailed description

[0004] The disclosure below provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on top of a second element in the description below may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present disclosure.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0005] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of one element or structural element to one or more other elements or structural elements depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90° or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0006] The present disclosure relates generally to semiconductor structures and in particular to semiconductor structures with field-effect transistors (FETs), such as three-dimensional GAA transistors. In general, a GAA transistor can have a plurality of vertically stacked nanostructures (e.g., nanosheets, nanowires, or nanorods) in a channel region of the transistor, thereby enabling better gate control, lower leakage current, and improved scalability for various IC applications.

[0007] A nanostructured transistor (e.g., a nanosheet transistor, a nanowire transistor, a multi-bridge-channel transistor, a nanoribbon FET, a GAA transistor structure), as described below, can be structured using a suitable method. For example, the structures can be structured using one or more photolithography processes, such as dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithography and self-aligning processes, enabling the creation of structures with, for example, pitches smaller than those achievable with a single direct photolithography process. For example, in one embodiment, a sacrificial layer is fabricated over a substrate and then structured using a photolithography process. Spacers are fabricated along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed, and the remaining spacers can then be used to structure the GAA structure.

[0008] As the feature size is reduced in a highly advanced technology node, a backside metal trace located on the rear of the device is provided so that the frontside and backside metal traces can work together to provide a better connection. The critical polysilicon pitch (CPP; the pitch between a gate and an adjacent gate) and critical dimension (CD) of a backside source / drain (S / D) contact of the GAA transistor are reduced as the size of the GAA transistor is further reduced. Because the CPP and CD of the backside S / D contact are reduced, the resistance of the backside S / D contact increases, and precise overlay control of the photolithography process used to fabricate the backside S / D contact is required to avoid creating a short circuit between the gate and the backside S / D contact.Therefore, a novel structure and a novel manufacturing process are needed to reduce the resistance of the backside S / D contact and to mitigate the need for overlay control to create the backside S / D contact.

[0009] Embodiments of the present disclosure offer advantages over the prior art, but it is understood that other embodiments may offer other advantages, not all advantages are necessarily discussed here, and no specific advantage is required for all embodiments. For example, embodiments discussed here relate to structures and methods that include the fabrication of semiconductor material layers (e.g., SiGe layers) beneath the S / D elements of the GAA transistor. The rear S / D contact can be fabricated as follows: creating a first opening to expose the semiconductor material layer; selectively removing the semiconductor material layer to create a second opening that exposes the S / D element; and depositing a conductive material in the first and second openings.Since the second opening is created by selectively removing the semiconductor material layer, the space occupied by the semiconductor layer can be fully utilized to create the backside S / D contact. This reduces the resistance of the backside S / D contact and ensures a reliable connection to the small S / D element. It also prevents the backside S / D contact from contacting other conductive components, thus avoiding the formation of a short circuit. Furthermore, because the first opening is used to expose the semiconductor material layer, it can be made larger than the semiconductor material layer, further reducing the resistance of the backside S / D contact created within it.If an overlay misalignment occurs, the first opening that is larger than the semiconductor material layer can still expose the semiconductor material layer, thus mitigating the need for overlay control.

[0010] The various aspects of the present revelation will now be described in more detail with reference to the figures. To avoid misunderstandings, the x-direction, y-direction, and z-direction are consistently perpendicular to each other in the figures. Unless otherwise indicated, similar reference numerals throughout this revelation denote similar structural elements.

[0011] The Fig. Figures 1 to 4 are perspective views of a workpiece 100 at various stages of manufacture according to several embodiments. Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A, Fig. 18A, Fig. 19A, Fig. 20A and Fig. 21A are xz-sectional views of workpiece 100 at different manufacturing stages along a line A - A' of Fig. 4 according to some embodiments. The Fig. 5B, Fig. 6B, Fig. 7B, Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 13B, Fig. 14B, Fig. 15B, Fig. 16B, Fig. 17B, Fig. 18B, Fig. 19B, Fig. 20B and Fig. 21B are yz-sectional views of workpiece 100 at different manufacturing stages along a line B - B' of Fig. 4 according to some embodiments. Fig. 21C is a yz-sectional view of workpiece 100 at a manufacturing stage along a line C - C' of Fig. 4 according to some embodiments.

[0012] In Fig. In some embodiments, the workpiece 100 comprises a substrate 102 and a stack 104 above the substrate 102. In some embodiments, the substrate 102 contains a semiconductor material, such as solid silicon (Si). In other embodiments, the substrate 102 may contain other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or a III-V semiconductor material. Exemplary III-V semiconductor materials include GaAs, InP, GaP, GaN, GaAsP, AlInAs, AlGaAs, GaInP, and InGaAs. The substrate 102 may also include an insulating layer, such as a silicon oxide layer, to obtain a silicon-on-insulator (SOI) structure or a germanium-on-insulator (GOI) structure.

[0013] In some embodiments, the substrate 102 can have one or more well regions for fabricating different types of devices. The well regions can be, for example, n-well regions doped with an n-doped element, such as phosphorus (P) or arsenic (As), or p-well regions doped with a p-doped element, such as boron (B) or indium (In). The n- and p-well regions can be produced by ion implantation or thermal diffusion. Since, after completion of the fabrication processes, the workpiece 100 has been fabricated into a semiconductor structure 100, the workpiece 100 can be referred to, depending on the context, as the semiconductor structure 100.

[0014] In some embodiments, the stack 104 can contain semiconductor layers 106 and semiconductor layers 108. In some embodiments, the semiconductor layers 106 and the semiconductor layers 108 are stacked alternately in the z-direction. The semiconductor layers 106 and the semiconductor layers 108 can have different semiconductor compositions. In some embodiments, the semiconductor layers 106 are made of silicon germanium (SiGe), and the semiconductor layers 108 are made of silicon (Si). In these embodiments, the additional germanium content in the semiconductor layers 106 allows for the selective removal or omission of the semiconductor layers 106 without significantly damaging the semiconductor layers 108, so that the semiconductor layers 106 can also be referred to as sacrificial layers.

[0015] In some embodiments, the semiconductor layers 106 and 108 are epitaxially grown over or on the substrate 102 using an epitaxial growth process such as vapor phase epitaxy (VPE), metal-organic CVD (MOCVD), or molecular beam epitaxy (MBE). However, other deposition processes can also be used, such as chemical vapor deposition (CVD), low-pressure phosphorylated condensation (LPCVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), ultra-high vacuum CVD (UHV-CVD), remote plasma CVD (RPCVD), a combination thereof, or the like. The semiconductor layers 106 and 108 are deposited alternately and sequentially to produce the stack 104. It should be noted that in Fig. 1. Although three semiconductor layers 106 and three semiconductor layers 108 are arranged alternately and vertically (or stacked), this is for illustrative purposes only and is not intended to be limiting beyond what is expressly stated in the claims. The number of layers depends on the desired number of channel elements for the semiconductor device. In some embodiments, there may be 2 to 10 semiconductor layers 106 alternating with 2 to 10 semiconductor layers 108 in the stack 104.

[0016] For structuring purposes, the workpiece 100 can also have a hard mask layer 110 over the stack 104. The hard mask layer 110 can be a single-layer or a multi-layer structure. In some embodiments, the hard mask layer 110 is a single-layer structure and contains a silicon germanium layer. In some embodiments, the hard mask layer 110 is a multi-layer structure and contains a silicon nitride layer and a silicon oxide layer over the silicon nitride layer. In other embodiments, the hard mask layer 110 is a multi-layer structure and contains a silicon germanium layer and a silicon layer over the silicon germanium layer.

[0017] In Fig. 2. According to some embodiments, the substrate 102, the stack 104, and the hard mask layer 110 are then structured to produce a fin structure 112A and a fin structure 112B (which may be collectively referred to as fin structures 112) over the substrate 102. In some embodiments, each of the fin structures 112 has a base part (base fins 102A and 102B) made from a portion of the substrate 102 and a stack part made from the stack 104 over the base part, as shown in Fig. Figure 2 shows the stacked portion containing semiconductor layers 106 and 108, which are stacked alternately over substrate 102. In some embodiments, the base fins 102A and 102B protrude from substrate 102. Each fin structure 112 can extend longitudinally in the x-direction and vertically in the z-direction over substrate 102 and can be arranged in the y-direction. In some embodiments, the widths of the fin structures 112 are equal along the y-direction. Although two fin structures 112A and 112B are fabricated and shown here, more fin structures, such as three or more, can be fabricated.

[0018] The fin structures 112 can be structured using suitable processes, including photolithography and etching. Suitable processes may include dual or multiple structuring processes. For example, in some embodiments, a layer of material is produced over a substrate and then structured using a photolithography process. Spacers are produced along the structured material layer using a self-aligning process. Subsequently, the material layer is removed, and the remaining spacers or mandrels can then be used to structure the fin structures 112 by etching the stack 104 and the substrate 102. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. In some embodiments, the photolithography processes include photoresist coating (e.g.,Centrifugal coating), pre-curing, mask adjustment, exposure, post-exposure curing, photoresist development, washing, and drying (e.g., post-curing). In other embodiments, the photolithography processes can be implemented or replaced by other suitable methods, such as maskless photolithography, electron beam writing, and ion beam writing.

[0019] In Fig. 3. In some embodiments, insulation structures 114 are fabricated. After the fin structures 112 have been fabricated, the hard mask layer 110 is removed over the fin structures 112, and the insulation structures 114 are fabricated over the substrate 102. In some embodiments, the insulation structures 114 are fabricated between the fin structures 112. In other embodiments, the insulation structures 114 are fabricated around the fin structures 112. In particular, the insulation structures 114 are fabricated between and around the base fins (e.g., the base fins 102A and 102B) of the fin structures 112. The insulation structures 114 can also be referred to as an STI element (STI: shallow trench insulation).

[0020] In some embodiments, a dielectric material for the insulating structures 114 is first deposited over the workpiece 100. In particular, the dielectric material is deposited over the fin structures 112 and the substrate 102 to cover them. In some embodiments, the dielectric material is produced such that it encloses the fin structures 112. In some embodiments, the dielectric material can comprise silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxide nitride (SiON), fluorosilicate glass (FSG), a low-k dielectric material, a combination thereof, and / or other suitable materials. Exemplary low-k dielectric materials include carbon-doped silicon dioxide and Black Diamond. ®(Applied Materials, Santa Clara, California), Xerogel, Aerogel, amorphous fluorocarbon, Parylene, BCB-based dielectric materials (BCB: Benzocyclobutene), SiLK (Dow Chemicals, Midland, Michigan), polyimides, other suitable dielectric low-k materials or combinations thereof.

[0021] In some embodiments, the dielectric material is deposited by a deposition process, such as CVD, subatmospheric pressure CVD (SACVD), flowable CVD (FCVD), ALD, spin coating, and / or another suitable process. The deposited dielectric material is then thinned and planarized, for example, by a CMP process (CMP: chemical-mechanical polishing), until a top surface of the hard mask layer 110 is exposed (not shown). The planarized dielectric material is further recessed by a dry etching process, a wet etching process, and / or a combination thereof to produce the insulation structures 114. In some embodiments, the stacked portions of the fin structures 112 project beyond the insulation structures 114, while the base fins 102A and 102B are enclosed by the insulation structures 114, as shown in Fig. Figure 3 shows. In other words, the top surfaces (or uppermost faces) of the substrate 102 are higher than the top surfaces of the insulation structures 114. In some embodiments, a coating layer can be conformally deposited over the substrate 102 prior to the fabrication of the insulation structures 114 using a deposition process such as CVD, ALD, high-density plasma CVD (HDP-CVD), MOCVD, RPCVD, PECVD, LPCVD, atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), FCVD, or combinations thereof.

[0022] In Fig. 4. According to some embodiments, dummy gate structures 116 can be produced over the fin structures 112 and the insulation structures 114. In some embodiments, the dummy gate structures 116 can be configured to extend longitudinally in the y-direction and enclose the top and side surfaces of the fin structures 112, as shown in Fig. Figure 4 shows that in some embodiments, a dielectric dummy gate material for dielectric dummy gate layers 118 is first deposited over the fin structures 112 and the insulation structures 114 to produce the dummy gate structures 116. In some embodiments, the dielectric dummy gate layers 118 can, for example, contain a dielectric material such as a nitride (e.g., SiN, SiON), a carbide (e.g., SiC), an oxide (e.g., SiO2), or other suitable materials.

[0023] In some embodiments, a dummy gate electrode material for dummy gate electrode layers 120 is deposited over the dielectric dummy gate material. The dummy gate electrode material can comprise a conductive material selected from the group consisting of polysilicon, tungsten (W), aluminum (Al), copper (Cu), alco-cubic acid (AlCu), titanium (Ti), tiAlN, TaC, TaCN, TaSiN, manganese (Mn), zirconium (Zr), titanium dioxide (TiN), TaN, cobalt (TaN), nickel (Co), nickel (Ni), and / or combinations thereof. The dummy gate electrode material and / or the dielectric dummy gate material can be deposited by a thermal oxidation process and / or a deposition process, e.g., by physical vapor deposition (PVD), CVD, PECVD, and ALD.

[0024] Subsequently, hard mask layers 122 are fabricated over the dummy gate electrode material. In some embodiments, the hard mask layers 122 can be fabricated using photolithography and removal processes (e.g., etching processes). In some embodiments, the hard mask layers 122 can contain photoresist materials or hard mask materials. In some embodiments, each of the hard mask layers 122 can have multiple layers, such as a silicon nitride layer and a silicon oxide layer. After fabrication of the hard mask layers 122, a removal process (e.g., etching) can be performed to remove portions of the dummy gate electrode material for the dummy gate electrode layers 120 and portions of the dielectric dummy gate material for the dielectric dummy gate layers 118 that are not directly beneath the hard mask layers 122, thereby forming the dummy gate structures 116.Each of the dummy gate structures 116 comprises the dielectric dummy gate layer 118, the dummy gate electrode layer 120, and the hard mask layer 122. The dielectric dummy gate layers 118 can also be referred to as dummy interface layers.

[0025] The dummy gate structures 116 can undergo a gate replacement process by subsequent processing to produce metal gates, such as high-k metal gates, as will be explained in more detail later. Fig. Figure 4 shows two dummy gate structures 116. In some embodiments, more or fewer dummy gate structures can be produced for one or more transistors that share source / drain regions.

[0026] Let's stay with Fig. 4. After the dummy gate structures 116 have been fabricated, gate spacers 124 are fabricated on side walls of the dummy gate structures 116 and above the top surfaces of the fin structures 112, according to some embodiments. In some embodiments, the gate spacers 124 are fabricated on opposite side walls of the fin structures 112, on opposite side walls of the dummy gate structures 116, and above the top surface of the uppermost semiconductor layer 108, as shown in Fig. Figure 4 shows that the gate spacers 124 can contain silicon nitride (Si3N4), silicon oxide (SiO2), silicon carbide (SiC), silicon oxide carbide (SiOC), silicon oxide nitride (SiON), silicon carbon nitride (SiCN), silicon oxide carbonitride (SiOCN), carbon-doped oxide, nitrogen-doped oxide, porous oxide, or combinations thereof. In some embodiments, the gate spacers 124 contain a dielectric low-k material, such as one of those mentioned here. The gate spacers 124 can have a single-layer or multi-layer structure.

[0027] In some embodiments, the gate spacers 124 can be manufactured as follows: conformal deposition of a spacer layer of dielectric material over the fin structures 112 and the dummy gate structures 116; and subsequent performance of an anisotropic etching process to remove upper portions of the spacer layer from the top surfaces of the insulating structures 114, the fin structures 112, and the dummy gate structures 116. After the anisotropic etching process, the portions of the spacer layer on the sidewall surfaces of the fin structures 112 and the dummy gate structures 116 largely remain and become the gate spacers 124. In some embodiments, the anisotropic etching process is a dry etching process (e.g., a plasma etching process).Additionally or alternatively, the production of the gate spacers 124 can also include chemical oxidation, thermal oxidation, CVD, PVD, ALD, HDP-CVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, FCVD and / or other suitable processes. The gate spacers 124 can also be referred to synonymously as upper spacers.

[0028] In the Fig. 5A and Fig. In some embodiments, the fin structures 112 are recessed to create source / drain channels 126 in the fin structures 112 for source / drain regions (or to create them so that they extend through the semiconductor layers 106 and 108). The source / drain channels 126 are created on opposite sides of the dummy gate structures 116 in the x-direction. In particular, the source / drain channels 126 can be created by performing one or more etching processes to remove portions of the semiconductor layers 106 and 108 and the substrate 102 (e.g., the base fins 102A and 102B) that do not vertically overlap or are not covered by the dummy gate structures 116 and the gate spacers 124.

[0029] In some embodiments, a single etchant can be used to remove the substrate 102 and the semiconductor layers 106 and 108. In other embodiments, several etchants can be used to perform the etching process. In some embodiments, portions of the substrate 102 are etched such that the source / drain channels 126 extend into the substrate 102 and each has a concave surface in the substrate 102, as shown in Fig. 5A is shown. In some embodiments, parts of the gate spacers 124 on opposite side walls of the fin structures 112 in the y-direction are removed. In these embodiments, the heights of the gate spacers 124 on opposite side walls of the fin structures 112 in the y-direction are reduced (see Fig. 21C).

[0030] In the Fig. 6A and Fig. In some embodiments, internal spacers 128 are produced between the semiconductor layers 108 and between the semiconductor layer 108 and the substrate 102. In some embodiments, the semiconductor layers 106 exposed in the source / drain channels 126 are partially recessed by a selective etching process, while the semiconductor layers 108 are not etched. In particular, a selective etching process is carried out that selectively etches side parts of the semiconductor layers 106 under the gate spacers 124 through the source / drain channels 126, whereby the semiconductor layers 108 and the substrate 102 are only minimally (or substantially not) etched. After the selective etching process, internal spacer recesses are produced vertically between the semiconductor layers 108 and between the semiconductor layers 108 and the substrate 102, under the gate spacers 124.The selective etching process can be a dry etching process, a wet etching process, another suitable etching process, or a combination thereof.

[0031] In some embodiments, a spacer layer is conformally produced in the source / drain channels 126 and the internal spacer recesses. Specifically, a deposition process such as CVD, PVD, ALD, HDP-CVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, FCVD, another suitable process, or a combination thereof is performed to produce the spacer layer in the source / drain channels 126 and the internal spacer recesses. The spacer layer partially (and in some embodiments completely) fills the source / drain channels 126 and completely fills the internal spacer recesses. The deposition process is configured to ensure that the spacer layer fills the internal spacer recesses. Furthermore, the spacer layer is also conformally produced on the gate spacers 124 and the isolation structures 114.

[0032] The spacer layer may contain a material different from the materials of the semiconductor layers 108 and the gate spacers 124 in order to achieve a desired etch selectivity during the etching process. In some embodiments, the spacer layer contains a dielectric material comprising Si, O, C, N, another suitable material, or a combination thereof (e.g., SiO₂, SiON, SiOC, SiCN, SiOCN). In some embodiments, the spacer layer contains a low-k dielectric material, such as one of those mentioned here. In some embodiments, the spacer layer contains a dielectric material with a k-value (dielectric constant) that is higher or lower than that of the gate spacers 124.

[0033] In some embodiments, internal spacers 128 are then fabricated to fill the internal spacer recesses between the semiconductor layers 108 and between the semiconductor layer 108 and the substrate 102. In particular, an etching process is performed to selectively etch the spacer layer to fabricate the internal spacers 128, whereby the semiconductor layers 108, the substrate 102, the dummy gate structures 116, and the gate spacers 124 are only minimally (or essentially not) etched. The etching process can be an anisotropic etching process, so that portions of the spacer layer that do not vertically overlap or are not covered by the dummy gate structures 116 and the gate spacers 124 are removed. The spacer layer on the gate spacers 124 and the insulating structures 114 are also removed.

[0034] In some embodiments, the sidewalls of the internal spacers 128 are aligned with the sidewalls of the gate spacers 124 and the semiconductor layers 108. Therefore, the internal spacers 128 are manufactured on opposite sides of the dummy gate structure 116. In other embodiments, the sidewalls of the internal spacers 128 have concave surfaces exposed by the source / drain channels 126. In some embodiments, the sidewalls of the internal spacers 128 that are in contact with the semiconductor layers 106 have convex surfaces.

[0035] In the Fig. 7A and Fig. 7B According to some embodiments, semiconductor material layers 130 and lower insulating layers 132 are produced in the lower parts of the source / drain channels 126. In some embodiments, the semiconductor material layers 130 are produced above the substrate 102, which is exposed in the source / drain channels 126, and the lower insulating layers 132 are produced above the semiconductor material layers 130. In these embodiments, the semiconductor material layers 130 are arranged vertically between the lower insulating layers 132 and the substrate 102 in the z-direction and on opposite sides of the dummy gate structure 116 in the x-direction, and they are in contact with it.

[0036] In some embodiments, the top surfaces of the semiconductor material layers 130 are higher than or at the same level as the top surface of the substrate 102 and lower than the bottom surfaces of the lowest semiconductor layers 108. In some embodiments, the top surfaces of the semiconductor material layers 130 are higher than the top surfaces of the insulating structures 114. In some embodiments, the material of the semiconductor material layers 130 is SiGe, and the material of the substrate 102 is silicon, in order to achieve the desired etch selectivity during the removal of the semiconductor material layers 130, which will be discussed in more detail later. In some embodiments, the semiconductor material layers 130 can be produced by an epitaxial growth process such as VPE, MOCVD, or MBE, but other deposition processes can also be used, such as CVD, LPCVD, PECVD, ALD, UHV-CVD, RPCVD, a combination thereof, or the like.

[0037] In some embodiments, the lower insulating layers 132 are fabricated on the semiconductor material layers 130. In some embodiments, the lower insulating layers 132 have a dumbbell shape (dogbone shape), that is, each of the lower insulating layers 132 has end portions that are thicker than a middle portion between the end portions. In some embodiments, the end portions are in contact with the bottommost internal spacers 128. In some embodiments, the top surfaces of the lower insulating layers 132 are lower than the bottom surfaces of the bottommost semiconductor layers 108, and the bottom surfaces of the lower insulating layers 132 are higher than the top surface of the substrate 102. In other embodiments, the top surfaces of the lower insulating layers 132 are located above the top surface of the substrate 102, and the bottom surfaces of the lower insulating layers 132 are located below the top surface of the substrate 102.

[0038] In some embodiments, the dielectric material of the lower insulating layers 132 can comprise Si3N4, SiO2, SiC, SiOC, SiON, SiCN, SiOCN, high-k dielectrics, other suitable materials, or combinations thereof. In some embodiments, the lower insulating layers 132 can be deposited by CVD, PVD, ALD, HDP-CVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, or other suitable processes or combinations thereof.

[0039] In the Fig. 8A and Fig. In some embodiments, source / drain elements 134 are produced in the source / drain channels 126 and on the lower insulation layers 132. The source / drain elements 134 can be produced in the fin structures 112 and on the opposite sides of the dummy gate structures 116 in the x-direction. In some embodiments, the source / drain elements 134 are connected to and in contact with the semiconductor layers 108. That is, the source / drain elements 134 are attached to the opposite sides of the semiconductor layers 108. The source / drain elements 134 can also be referred to as a source / drain or source / drain regions. In some embodiments, one or more source / drain elements 134 can, depending on the context, individually or collectively designate a source or a drain.In some embodiments, the semiconductor layers 108 serve as channels for connecting one source / drain element 134 to another source / drain element 134. Therefore, the semiconductor layers 108 can also be referred to as channels, channel layers, or channel elements.

[0040] In some embodiments, each of the source / drain elements 134 contains first epitaxial layers 136, which are produced on the end portions of the semiconductor layers 108, and a second epitaxial layer 138, which is produced on the first epitaxial layers 136, as shown in Fig. Figure 8A shows that in some embodiments, the first epitaxial layers 136 have a non-contiguous shape, such that they are spaced apart and do not physically contact or fuse with each other. In some embodiments, the first epitaxial layers 136 may have a height approximately equal to or greater than the thickness of the adjacent semiconductor layers 108. For example, the first epitaxial layers 136 may extend above and / or below the adjacent semiconductor layers 108. In other embodiments, the first epitaxial layers 136 may extend onto the internal spacers 128 and / or the gate spacers 124. In some embodiments, the first epitaxial layers 136 may have a shape similar to a segment of a circle, a segment of an ellipse, a triangle, or another shape.In some embodiments, the lowest first epitaxial layers 136 are in contact with the lower insulating layers 132. In some embodiments, the second epitaxial layer 138, which is produced on the first epitaxial layers 136, can have top surfaces that extend higher than the top surfaces of the uppermost semiconductor layers 108 (e.g., in the z-direction).

[0041] In other embodiments, the first epitaxial layers 136 are produced in the form of a continuous layer. The first epitaxial layers 136 can extend continuously along the sidewalls of the source / drain channels 126. For example, the first epitaxial layers 136 can cover sidewalls of the semiconductor layers 108 in the source / drain channels 126 as well as sidewalls of the internal spacers 128 located between the semiconductor layers 108. The first epitaxial layers 136 can extend continuously along surfaces from a sidewall of the semiconductor layers 108 closest to the substrate 102 to a sidewall of the semiconductor layers 108 furthest from the substrate 102.

[0042] In some embodiments, the first epitaxial layers 136 and the second epitaxial layers 138 contain the same semiconductor material, but with different component concentrations. The semiconductor material can be silicon, germanium, silicon germanium, another suitable semiconductor material, or combinations thereof. In some embodiments where the source / drain elements 134 are configured to form p-GAA transistors, the first epitaxial layers 136 and the second epitaxial layers 138 contain p-doped silicon germanium, but with different p-concentrations. For example, the first epitaxial layers 136 can have a p-doped concentration (e.g., a boron concentration) of about 1 × 10⁻⁶. 20 / cm 3 up to about 5 × 10 20 / cm 3 have, and the second epitaxial layers 138 can have a p-dotande concentration (e.g. a boron concentration) of about 5 × 10 20 / cm 3up to about 2 × 10 21 / cm 3 have.

[0043] In some embodiments where the source / drain elements 134 are configured to form n-GAA transistors, the first epitaxial layers 136 and the second epitaxial layers 138 contain n-doped silicon, but with different n concentrations. For example, the first epitaxial layers 136 can have an n-doped concentration (e.g., a phosphorus or an arsenic concentration) of about 1 × 10 20 / cm 3 up to about 5 × 10 20 / cm 3 have, and the second epitaxial layers 138 can have an n-dotande concentration (e.g., a phosphorus or an arsenic concentration) of about 5 × 10 20 / cm 3 up to about 2 × 10 21 / cm 3 have.

[0044] In some embodiments, the first epitaxial layers 136 are grown epitaxially from the end portions of the semiconductor layers 108, exposed by the source / drain channels 126, using an epitaxial growth process. In some embodiments, the second epitaxial layers 138 are grown epitaxially from the first epitaxial layers 136, exposed by the source / drain channels 126, using an epitaxial growth process. The epitaxial growth process for producing the first epitaxial layers 136 and the second epitaxial layers 138 can be VPE, MOCVD, MBE, or another deposition process, such as CVD, LPCVD, PECVD, ALD, UHV-CVD, RPCVD, a combination thereof, or the like. In some embodiments, the first epitaxial layers 136 and the second epitaxial layers 138 are doped in situ or ex situ.In some embodiments, one or more annealing processes can be performed to activate the dopants in the first epitaxial layers 136 and the second epitaxial layers 138. The annealing processes can include rapid thermal annealing (RTA) and / or laser annealing.

[0045] In the Fig. 9A and Fig. 9B According to some embodiments, a contact etch stop layer (CESL) 140 is produced over the source / drain elements 134 and an interlayer dielectric layer (ILD layer) 142 is produced over the CESL 140 to fill the space between the gate spacers 124. In some embodiments, the CESL 140 is produced conformally on the side walls of the gate spacers 124 and over the top surfaces of the source / drain elements 134, as shown in Fig. Figure 9A shows that the ILD layer 142 is fabricated over and between the CESLs 140 to fill the spaces between the CESLs 140 or between the gate spacers 124.

[0046] CESL 140 can contain a material different from that of ILD layer 142. CESL 140 can contain La₂O₃, Al₂O₃, SiOCN, SiOC, SiCN, SiO₂, SiC, ZnO, ZrN, Zr₂Al₃O₄, TiO₂, TaO₂, ZrO₂, HfO₂, Si₃N₄, Y₂O₃, AlON, TaCN, ZrSi, or other suitable materials. CESL 140 can be manufactured by CVD, PVD, ALD, HDP-CVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, FCVD, or other suitable methods. The ILD layer 142 can contain tetraethyl orthosilicate oxide (TEOS oxide), undoped silicate glass or doped silicon dioxide, such as borophosphosilicate glass (BPSG), FSG, phosphosilicate glass (PSG), borosilicate glass (BSG), a low-k dielectric material, another suitable dielectric material, or a combination thereof. The ILD layer 142 can be fabricated by CVD, PVD, ALD, HDP-CVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, FCVD, or other suitable methods.

[0047] After deposition of the CESLs 140 and the ILD layers 142, a CMP process and / or another planarization process is performed on the CESLs 140, the ILD layers 142, the gate spacers 124, and the hard mask layer 122 until the top surfaces of the dummy gate electrode layers 120 are exposed. In some embodiments, portions of the dummy gate electrode layers 120 are removed after the planarization process.

[0048] In the Fig. 10A and Fig. In some embodiments, the dummy gate structures 116 are selectively removed using suitable photolithography and etching processes. In some embodiments, the photolithography process may include: producing a photoresist layer (resist), exposing the resist with a structure, performing a post-curing process, and developing the resist to produce a masking element that leaves an area containing the dummy gate structures 116. The dummy gate structures 116 are then selectively etched through the masking element. The gate spacers 124 may be used as the masking element or part thereof. By selecting suitable etching chemicals, etch selectivity can be achieved, and the dummy gate structures 116 can be removed without significantly affecting the CESL 140 and the ILD layer 142. The removal of the dummy gate structures 116 creates gate grooves 144, as shown in the Fig. 10A and Fig. Figure 10B shows that the gate grooves 144 expose the top surfaces of the uppermost semiconductor layers 108, which are located beneath the dummy gate structures 116.

[0049] Let's stick with the Fig. 10A and Fig. 10B. According to some embodiments, the semiconductor layers 106 are selectively removed through the gate grooves 144, for example by a wet or dry etching process, in order to enlarge the gate grooves 144. After the semiconductor layers 106 have been selectively removed, the semiconductor layers 108 are exposed in the gate grooves 144 and form the stacked nanostructures. Therefore, the semiconductor layers 108 can be referred to as nanostructures. This process can also be described as a conductor / nanowire / nanosheet delamination process or a conductor / nanowire / nanosheet fabrication process.

[0050] In some embodiments, the semiconductor layers 108 are stacked one above the other in the z-direction and spaced apart from each other. In particular, the semiconductor layers 108 are suspended above the substrate 102 in the z-direction and arranged vertically, forming vertical stacks. In some embodiments, during the removal of the semiconductor layers 106, portions of the semiconductor layers 108 exposed in the gate grooves 144 can be partially removed. For example, each of the semiconductor layers 108 can have end portions covered by the internal spacers 128 and the gate spacers 124, and a middle portion between the end portions exposed by the gate grooves 144. The middle portions exposed in the gate grooves 144 can be partially etched during the removal of the semiconductor layers 106, so that the end portions have a greater thickness than the middle portion.For example, after the removal of the semiconductor layers 106, each of the semiconductor layers 108 can have a dumbbell shape (or dog bone shape), as in . Fig. 10A is shown.

[0051] In the Fig. 11A and Fig. In some embodiments, gate structures 150 are fabricated in the gate grooves 144 to enclose each of the exposed semiconductor layers 108. In some embodiments, the gate structures 150 extend in the y-direction. In some embodiments, the source / drain elements 134 are fabricated on opposite sides of the gate structures 150 in the x-direction.

[0052] In some embodiments, the gate structures 150 each have interface layers 152 that are produced on the surfaces of the semiconductor layers 108 to enclose the exposed semiconductor layers 108, and that are produced on the exposed surfaces of the base fins 102A and 102B. In some embodiments, the interface layers 152 may contain a dielectric material such as SiO2, HfSiO, or SiON. The interface layers 152 may be produced by chemical oxidation, thermal oxidation, CVD, PVD, ALD, HDP-CVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, FCVD, and / or by another suitable method.

[0053] In some embodiments, the gate structures 150 each have a dielectric gate layer 154 and a gate electrode layer 156 above the dielectric gate layer 154. In some embodiments, the dielectric gate layers 154 are produced on the interface layers 152 to enclose the semiconductor layers 108. In further embodiments, the dielectric gate layers 154 are also produced on the side walls of the internal spacers 128 and the gate spacers 124 and above the top surfaces of the insulating structures 114 and the interface layers 152, which are produced on the base fins 102A and 102B.

[0054] In some embodiments, the dielectric gate layers 154 can contain a dielectric material such as SiOCN, SiOC, SiCN, SiO2, SiN, SiC, or other suitable materials. In some embodiments, the dielectric gate layers 154 can contain a high-k dielectric material having a dielectric constant higher than that of SiO2, which is approximately 3.9. For example, the dielectric gate layers 154 can contain hafnium oxide (HfO2), which has a dielectric constant of approximately 18 to approximately 40. Alternatively, the dielectric gate layers can contain 154 other high-k dielectrics, such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O3, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, SiON or combinations thereof, or other suitable materials.The dielectric gate layers 154 can be produced by CVD, PVD, ALD, HDP-CVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, FCVD, oxidation and / or other suitable methods.

[0055] In some embodiments, the gate electrode layers 156 are fabricated to fill the remaining gaps of the gate grooves 144, and they are fabricated over the dielectric gate layers 154 such that they enclose the dielectric gate layers 154, the interface layers 152, and the semiconductor layers 108. The gate electrode layers 156 each have a single-layer or multi-layer structure. In some embodiments, the gate electrode layers 156 each include a capping layer, a barrier layer, exit-work metal layers, and a filler material. The gate electrode layers 156 can be fabricated by a deposition process such as CVD, PVD, ALD, HDP-CVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, FCVD, or the like, but any suitable deposition process can be used.

[0056] The capping layer can be made of a metallic material such as TaN, Ti, TiAlN, TiAl, Pt, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ru, Mo, or WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, oxide nitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof, or the like. The barrier layer can be made of a material different from that of the capping layer. In some embodiments, the barrier layer can be made of a material that is incorporated into one or more of the metallic material layers.The metallic material may include, for example, TiN, TaN, Ti, TiAlN, TiAl, Pt, TaC, TaCN, TaSiN, Mn, Zr, Ru, Mo or WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, oxide nitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof or the like.

[0057] The exit work layers can contain conductive materials, such as n- and / or p-type exit work materials, adapted to have a desired exit work (e.g., an n- or p-type exit work). In some embodiments, the n- and p-type exit work metal layers can contain a material such as W, Al, Cu, TiN, Ti, TiAlN, TiAl, Pt, Ta, TaN, Co, Ni, TaC, TaCN, TaSiN, TaSi2, NiSi2, Mn, Zr, ZrSi2, Ru, AlCu, Mo, MoSi2, or WN, other suitable exit work materials, or combinations thereof. In some embodiments, the filler material can comprise a suitable conductive material such as Al, W, and / or Cu.

[0058] In the Fig. 12A and Fig. In some embodiments, source / drain contacts 160 and corresponding silicide layers 162 are produced on the front face of workpiece 12B. In some embodiments, the source / drain contacts 160 are produced such that they extend through the ILD layer 142, the CESLs 140, and parts of the source / drain elements 134 to contact and electrically connect the source / drain elements 134. The production of the source / drain contacts 160 may include creating contact openings that extend through the ILD layer 142 and the CESLs 140 and partially into the source / drain elements 134 to expose the source / drain elements 134.

[0059] In some embodiments, silicide layers 162 are then produced on the exposed surfaces of the source / drain elements 134 in the contact openings. In some embodiments, the silicide layers 162 are produced by producing metal layers on the source / drain elements 134 and heating the workpiece 100 to cause the components of the source / drain elements 134 to react with the metallic components of the metal layers. In some embodiments, the silicide layers 162 can contain titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel-platinum silicide (NiPtSi), nickel-platinum germanium silicide (NiPtGeSi), nickel-germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds.

[0060] Subsequently, in some embodiments, a conductive material for the source / drain contacts 160 can be deposited in the contact openings and on the silicide layers 162 by a deposition process to create the source / drain contacts 160. That is, the contact openings are filled with the conductive material to create the source / drain contacts 160. The source / drain contacts 160 can contain a conductive material such as Al, Cu, W, Co, Ti, Ta, Ru, Rh, Ir, Pt, Mo, TiN, TiAl, TiAlN, TaN or TaC, combinations thereof, or the like, but any suitable material can be deposited by a deposition process such as sputtering, CVD, PVD, ALD, HDP-CVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, FCVD, electroplating, electroless plating, or the like. In some embodiments, the source / drain contacts 160 may each comprise a single conductive material layer or multiple conductive layers.In some embodiments, the second epitaxial layers 138 and the uppermost first epitaxial layers 136 are partially omitted by the creation of the contact openings for the source / drain contacts 160, and thus the source / drain contacts 160 and the silicide layers 162, which are produced in the contact openings, are in contact with the second epitaxial layers 138 and the uppermost first epitaxial layers 136, as in . Fig. 12A is shown.

[0061] Let's stick with the Fig. 12A and Fig. 12B. On the front side of the workpiece 100, a front-side interconnect structure 164 is fabricated according to some embodiments. For simplicity and clarity, the front-side interconnect structure 164 is shown as a dashed box. In some embodiments, the front-side interconnect structure 164 has one or more intermetal dielectric (IMD) layers fabricated over the ILD layer 142, the source / drain contacts 160, and the gate structures 150. In some embodiments, the method and material used to fabricate the IMD layers are the same as or similar to those used for the ILD layer 142 and are not repeated here. In some embodiments, the IMD layers may contain multiple dielectric materials.

[0062] In some embodiments, the front-facing interconnect structure 164 includes a plurality of vias (e.g., source / drain vias, gate vias, vias connecting different metal layers, and the like) and a plurality of metal layers (e.g., comprising a metal conductor) fabricated in the IMD layers. The plurality of vias and the plurality of metal layers connect the gate structures 150 and the source / drain contacts 160 to various circuit components to interconnect the semiconductor device. In some embodiments, the method and material used in fabricating the plurality of vias and the plurality of metal layers are the same as or similar to those used for the source / drain contacts 160 and are not repeated here.

[0063] In the Fig. 13A and Fig. In some embodiments, the workpiece 100 is turned over, and a portion of the substrate 102 is removed from the back of the workpiece 100. In some embodiments, a support wafer can be bonded to the front of the workpiece 100 before turning. In some embodiments, the substrate 102 is then thinned (or partially removed) from the back of the workpiece 100 using a selective etching process or a CMP process. It should be noted that, for the sake of simplicity, the front interconnect structure 164, which is fabricated on the front of the workpiece 100, is shown in the Fig. 13A and Fig. Figure 13B and the following figures are omitted.

[0064] Let's stick with the Fig. 13A and Fig. 13B. According to some embodiments, after thinning the substrate 102, a hard mask layer 170 is produced on the back side of the workpiece 100 (i.e., on the thinned substrate 102), and a hard mask layer 172 is produced on the hard mask layer 170. In some embodiments, the material for the hard mask layers 170 and 172 may comprise silicon nitride (Si3N4), SiO2, SiC, SiOC, SiON, SiCN, SiOCN, high-k dielectrics, other suitable materials, or combinations thereof. In some embodiments, the material for the hard mask layer 170 is different from the material for the hard mask layer 172. In some embodiments, the hard mask layers 170 and 172 can be produced by CVD, PVD, ALD, HDP-CVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD or FCVD or by other suitable methods.

[0065] Furthermore, in the Fig. 13A and Fig. In some embodiments, an opening 174 is created on the back side of the workpiece 100 to expose one of the semiconductor material layers 130. For clarity and simplicity, the semiconductor material layers 130 exposed by the opening 174 are referred to below as a single semiconductor material layer 130A. In some embodiments, one or more photolithography and etching processes are performed to etch the hard mask layers 170 and 172 and the substrate 102 to create the opening 174 that exposes the semiconductor material layer 130A. In some embodiments, the etching processes may be dry etching, wet etching, other suitable etching processes, or combinations thereof. In some embodiments, the width of the opening 174 in the x-direction is greater than the width of the semiconductor material layer 130A to fully expose the semiconductor material layer 130A, as shown in Fig. Figure 13A shows that in some embodiments the width of the opening 174 is greater than the width of the semiconductor material layer 130A, causing the opening 174 to overlap the internal spacers 128 vertically. In other embodiments, the width of the opening 174 is greater than the width of the semiconductor material layer 130A in the y-direction.

[0066] In some embodiments, the end part of the semiconductor material layer 130A protrudes from the underside of the opening 174, as shown in Fig. Figure 13A shows that the end part of the semiconductor material layer 130A is exposed in the opening 174, and the other part of the semiconductor material layer 130A is still enclosed by the substrate 102. In other embodiments, the semiconductor material layer 130A is also partially etched, so that the surface of the semiconductor material layer 130A exposed in the opening 174 is essentially coplanar with the bottom of the opening 174.

[0067] In the Fig. 14A and Fig. In some embodiments, an inhibitor 176 is introduced into the opening 174. In some embodiments, the inhibitor 176 is introduced into the opening 174 and is then absorbed on the surface of the semiconductor material layer 130A, which is exposed in the opening 174. The inhibitor 176 can prevent the deposition or growth of a material for an insulating layer 178 (see Fig. 15A and Fig. 15B). In some embodiments, the materials of the semiconductor material layers 130, the inhibitor 176, and the insulating layer 178 are arranged such that the insulating layer 178 is not produced on the semiconductor material layer 130A, which absorbs the inhibitor 176. Since the inhibitor 176 is absorbed on the surface of the semiconductor material layer 130A, it prevents the insulating layer 178 (see Fig. 15A and Fig. 15B) is deposited on or grown from the surface of the semiconductor material layer 130A, which is exposed in the opening 174.

[0068] In the Fig. 15A and Fig. In some embodiments, the insulating layer 178 is produced on the hard mask layer 172 and in the opening 174. In some embodiments, the insulating layer 178 is produced conformally on the top surface of the hard mask layer 172 and on the side wall of the opening 174. In some embodiments, since the inhibitor 176 is absorbed on the surface of the semiconductor material layer 130A, the insulating layer 178 is produced on the portion of the underside of the opening 174 formed by the substrate 102, and it is not produced on the surface of the semiconductor material layer 130A exposed in the opening 174. Therefore, the insulating layer 178 is produced on the side wall of the opening 174 and on the portion of the underside of the opening 174 formed by the substrate 102 and surrounding the semiconductor material layer 130A, as shown in Fig. 15A is shown. Fig. In embodiment 15A, the side wall of the opening 174 contains the materials of the hard mask layers 170 and 172 and the substrate 102. In some embodiments, the opening 174 also extends through and exposes parts of the insulating structures 114, so that the side wall of the opening 174 also contains the material of the insulating structures 114. In these embodiments, the insulating layer 178 is also produced on the material of the insulating structures 114.

[0069] In some embodiments, the insulating layer 178 can be divided into a main part 178A and a projecting part 178B below the main part 178A. In some embodiments, the projecting part 178B is produced on the portion of the underside of the opening 174 formed by the substrate 102, and the main part 178A is produced above the projecting part 178B and on the side wall of the opening 174. In some embodiments, the dimensions of the projecting part 178B are larger than those of the main part 178A in the x and y directions. In some embodiments, the projecting part 178B also has a pointed part 178C that is positioned above and slightly overlaps the semiconductor material layer 130A, while most of the surface of the semiconductor material layer 130A remains exposed in the opening 174, as shown in Fig. Figure 15A shows this. In some embodiments, the thickness of the tip part 178C in the z-direction is smaller than the thickness of the other part of the projection part 178B.

[0070] In some embodiments, the insulating layer 178 is conformally produced on the top surface of the hard mask layer 172, on the side wall of the opening 174, and on the portion of the bottom surface of the opening 174 formed by the substrate 102. Since the inhibitor 176 is absorbed on the surface of the semiconductor material layer 130A, the semiconductor material layer 130A remains exposed in the opening 174 after the insulating layer 178 has been produced. The insulating layer 178 can contain La₂O₃, Al₂O₃, SiOCN, SiOC, SiCN, SiO₂, SiC, ZnO, ZrN, Zr₂Al₃O₉, TiO₂, TaO₂, ZrO₂, HfO₂, Si₃N₄, Y₂O₃, AlON, TaCN, ZrSi, or other suitable materials. The insulating layer 178 can be produced by CVD, PVD, ALD, HDP-CVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD or FCVD or by other suitable methods.Since the insulating layer 178 is selectively produced on materials other than the semiconductor material layer 130A, which absorbs the inhibitor 176, the insulating layer 178 can also be described as a selective insulator. In some embodiments, a cleaning process is carried out after the insulating layer 178 has been produced in order to remove the inhibitor 176 from the opening 174, such as from the surface of the semiconductor material layer 130A.

[0071] In the Fig. 16A and Fig. In some embodiments, the semiconductor material layer 130A is removed through opening 174 to create an opening 180, such that openings 174 and 180 collectively expose the lower insulating layer 132 beneath the semiconductor material layer 130A. For clarity and simplicity, the lower insulating layer 132 exposed by opening 180 is referred to below as the lower insulating layer 132A. In some embodiments, a selective etching process is performed to remove the semiconductor material layer 130A through opening 174. In some embodiments, a selective etching process is performed that selectively etches the semiconductor material layer 130A, while the insulating layer 178, the lower insulating layer 132A, the insulating structures 114, and the substrate 102 are only minimally (or essentially not) etched.The selective etching processes for the semiconductor material layer 130A can be dry etching processes, wet etching processes, other suitable etching processes or combinations thereof.

[0072] In the Fig. 17A and Fig. In some embodiments, the lower insulating layer 132A is removed through openings 174 and 180 to enlarge opening 180, so that openings 174 and 180 collectively expose the source / drain element 134 beneath the lower insulating layer 132A. In some embodiments, during the removal of the lower insulating layer 132A, opening 180 is slightly enlarged in the x and y directions. In some embodiments, the uppermost internal spacers 128 (the spacers 128 closest to the substrate 102) are also exposed through opening 180.

[0073] In some embodiments, a selective etching process is performed to remove the lower insulating layer 132A through the opening 180 in order to enlarge the opening 180. In some embodiments, a selective etching process is performed that selectively etches the lower ILD layer 142, while the insulating layer 178, the internal spacers 128, the gate spacers 124, the insulating structures 114, and the substrate 102 are only minimally (or essentially not) etched. The selective etching processes for the lower insulating layer 132A can be dry etching processes, wet etching processes, other suitable etching processes, or combinations thereof. In other embodiments, the lower insulating layer 132A is removed at a different manufacturing stage. For example, the lower insulating layer 132A can be formed together with horizontal parts of a dielectric material layer 182 during the manufacture of a dielectric sidewall layer 184 (see Fig. 19A and Fig. 19B) will be removed.

[0074] In some embodiments, after the removal of the semiconductor material layer 130A and the lower insulating layer 132A, the opening 180 is created in the position previously occupied by the semiconductor material layer 130A and the lower insulating layer 132A. The source / drain element 134 is then exposed beneath the lower insulating layer 132A by the openings 174 and 180. In some embodiments, the widths of the opening 174 are larger than the widths of the opening 180 in the x and y directions.

[0075] By producing the semiconductor material layer 130 under the source / drain element 134 (before turning the workpiece 100) and by removing the semiconductor material layer 130 with a selective etching process, the opening 180 and a source / drain contact 190 (see Fig. 21A to 21C), which is produced in the opening 180, is manufactured using a self-adjusting process, which prevents the opening 180 and the source / drain contact 190 produced therein from contacting other conductive components. In this way, the entire space occupied by the semiconductor material layer 130 can be effectively used to produce the source / drain contact. Therefore, the dimensions of the source / drain contact can be increased as much as possible to reduce resistance, while simultaneously avoiding the problem of short circuits with other conductive components.

[0076] In the Fig. 18A and Fig. In some embodiments, the dielectric material layer 182 is produced in the openings 174 and 180 and on the source / drain element 134 beneath the lower insulating layer 132A. In particular, the dielectric material layer 182 is produced conformally on the insulating layer 178, the side wall of the opening 180, and the top surface of the source / drain element 134 exposed by the opening 180, with the insulating layer 178 being produced on the side wall of the opening 174 and on the top surface of the hard mask layer 172. In some embodiments, the dielectric material layer 182 may comprise Si3N4, SiO2, SiC, SiOC, SiON, SiCN, SiOCN, high-k dielectrics, other suitable materials, or combinations thereof. In some embodiments, the dielectric material layer 182 can be deposited by CVD, PVD, ALD, HDP-CVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD or APCVD, with other suitable methods or combinations thereof.

[0077] In the Fig. 19A and Fig. In some embodiments, horizontal portions of the dielectric material layer 182 are removed to produce the dielectric sidewall layer 184. In some embodiments, an anisotropic etching process is carried out to remove the horizontal portions of the dielectric material layer 182 to expose the source / drain element 134 beneath the lower insulating layer 132A, while the vertical portions of the dielectric material layer 182 remain to form the dielectric sidewall layer 184, as shown in Fig. Figure 19A shows this. In some embodiments, the first epitaxial layers 136 and the second epitaxial layers 138 are also omitted during the anisotropic etching process. For example, the uppermost first epitaxial layers 136 (the first epitaxial layers 136 closest to the substrate 102) and the second epitaxial layers 138 are partially etched during the anisotropic etching process, thereby enlarging the opening 180 into the source / drain element 134. In some embodiments, the anisotropic etching process is a dry etching process (e.g., a plasma etching process).

[0078] In some embodiments, after the anisotropic etching process, the dielectric sidewall layer 184 is produced on the insulating layer 178 (which is produced on the sidewall of the opening 174) and on the sidewall of the opening 180. In some embodiments, the dielectric sidewall layer 184 is in contact with the uppermost internal spacers 128 (the internal spacers 128 that are closest to the substrate 102). In some embodiments, a first part of the dielectric sidewall layer 184, which is produced on the projecting part 178B of the insulating layer 178, is thinner than the other part of the dielectric sidewall layer 184.

[0079] As explained above, in some embodiments the lower insulating layer 132A, together with the horizontal parts of the dielectric material layer 182, can be removed during the production of the dielectric sidewall layer 184. In these embodiments, after the production of the dielectric sidewall layer 184, the lower part of the dielectric sidewall layer 184, which is in contact with the source / drain element 134, is produced from the lower insulating layer 132A, and the upper part of the dielectric sidewall layer 184 above its lower part is produced from the dielectric material layer 182.

[0080] In the Fig. 20A and Fig. In some embodiments, a silicide layer 186 is produced on the upper surface of the source / drain element 134, which has been exposed by the openings 174 and 180. In some embodiments, the method and material used to produce the silicide layer 186 are the same as or similar to those used for the silicide layers 162, and they are not repeated here.

[0081] Let's stick with the Fig. 20A and Fig. 20B. According to some embodiments, a conductive material 188 is deposited on the back side of the workpiece 100 and in the openings 174 and 180. In some embodiments, the conductive material 188 may comprise a conductive material such as Al, Cu, W, Co, Ti, Ta, Ru, Rh, Ir, Pt, Mo, TiN, TiAl, TiAlN, TaN or TaC, combinations thereof, or the like, but it may be any suitable material deposited by a deposition process such as sputtering, CVD, PVD, ALD, HDP-CVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, FCVD, electroplating, electroless plating, or the like. However, any suitable materials and processes may be used for depositing the conductive material 188. In some embodiments, the conductive material 188 may comprise a single conductive material layer or multiple conductive layers.

[0082] In the Fig. In some embodiments, as described in 21A to 21C, a planarization process (e.g., a CMP process and / or another planarization process) is performed on the back side of the workpiece 100 until the top surface of the hard mask layer 170 is exposed to create a source / drain contact 190. In some embodiments, the hard mask layer 172 and the portions of the insulating layer 178, the dielectric sidewall layer 184, and the conductive material 188 above the hard mask layer 172 are removed by the planarization process, and the remaining portions of the insulating layer 178, the dielectric sidewall layer 184, and the conductive material 188 form the source / drain contact 190. Since the source / drain contact 190 is created on the back side of the workpiece 100, it can also be referred to as a back-side source / drain contact.

[0083] In some embodiments, the source / drain contact 190 has a first part 190A, which is formed in the opening 174, and a second part 190B, which is formed in the opening 180. In some embodiments, the first part 190A is formed by the insulating layer 178; the upper part of the dielectric sidewall layer 184, which is enclosed by the insulating layer 178; and the upper part of the conductive material 188, which is enclosed by the insulating layer 178 and the upper part of the dielectric sidewall layer 184, as shown in the Fig. 21A and Fig. 21C is shown. In some embodiments, the second part 190B is arranged below the first part 190A, contacts the source / drain element 134, and is formed by the lower part of the dielectric sidewall layer 184, which is produced on the sidewall of the opening 180, and the lower part of the conductive material 188, which is enclosed by the lower part of the dielectric sidewall layer 184, as shown in the Fig. 21A and Fig. 21C is shown.

[0084] In some embodiments, the widths of the first part 190A are greater than the widths of the second part 190B in the x and y directions. Since in some embodiments the first part 190A is wider than the second part 190B and the insulating layer 178 is produced on the periphery of the first part 190A, a portion of the substrate 102 is layered vertically in the z direction between the insulating layer 178 and the second semiconductor layers 108, as shown in Fig. Figure 21A shows that in some embodiments, part of the substrate 102 is layered vertically in the z-direction between the insulating layer 178 and the internal spacers 128. In other embodiments, parts of the insulating structures 114 are layered vertically in the z-direction between the insulating layer 178 and the gate spacers 124, as shown in Figure 21A. Fig. 21C is shown.

[0085] As explained above, the second part 190B of the source / drain contact 190 (i.e., the rear source / drain contact) is produced in the opening 180, and the opening 180 is created in the space previously occupied by the semiconductor material layer 130A. Since the semiconductor material layer 130A can be removed by some kind of selective etching process, the space previously occupied by the semiconductor material layer 130A can be fully utilized to produce the second part 190B of the source / drain contact 190, thereby reducing the resistance of the source / drain contact 190.

[0086] Since the semiconductor material layer 130A is removed by the selective etching process, the opening 180 is prevented from exposing other conductive components (e.g., the gate structures 150). This prevents the second part 190B of the source / drain contact 190 from contacting the other conductive components, thus avoiding a short circuit between the source / drain contact 190 and the other conductive components. Furthermore, because the opening 180 is created by selectively removing the semiconductor material layer 130A instead of using a photolithography process, even with a small source / drain element 134, the source / drain contact 190 produced in the opening 180 can still be reliably connected to the source / drain element 134.

[0087] Since the opening 174 is created in such a way as to expose the semiconductor material layer 130A, the opening 174 can be made larger, thereby avoiding contact with other conductive components. Thus, the first part 190A of the (rear) source / drain contact 190, which is formed in the opening 174, can have a larger cross-sectional area in order to reduce the resistance of the source / drain contact 190.

[0088] As explained above, the insulating layer 178 is produced on the periphery of the first part 190A of the (rear) source / drain contact 190. That is, the insulating layer 178 covers the corner of the first part 190A and separates the conductive material 188 from the other components. In this way, the insulating layer 178 can prevent leakage from the source / drain contact 190, such as leakage between the source / drain contact 190 and the gate structures 150. If, for example, the insulating layer 178 is omitted, the dielectric sidewall layer on the corner of the first part 190A may disappear, or it may be too thin to separate the conductive material from the substrate 102 due to the removal of the horizontal parts of the dielectric sidewall layer. In this case, it is likely that a leakage loss will occur between the corner of the first part 190A and the gate structures 150 through the substrate 102.However, by creating the insulating layer 178, the corner of the first part 190A can be protected, and the path of leakage loss can be blocked by the insulating layer 178. Thus, the insulating layer 178 can prevent leakage from the source / drain contact 190.

[0089] If the overlay misalignment occurs during the creation of the first opening that exposes the semiconductor material layer, the first opening, which is larger than the semiconductor material layer, can still expose the semiconductor material layer, and thus the need for overlay control can be mitigated. Fig. Figure 22 is an xz-sectional view of a workpiece 200 at a manufacturing stage along line A - A' of Fig. 4 according to some alternative embodiments. The one in Fig. The workpiece 200 shown in section 22 can be replaced by the workpiece 100, which is in the Fig. 13A and Fig. 13B is shown to be similar, except that the ones in the Fig. 13A and Fig. Opening 174 shown in 13B through a Fig. Opening 274, shown in section 22, is replaced.

[0090] In Fig. According to some embodiments, the opening 274 is created in 22 to expose the semiconductor material layer 130A. Fig. 22 During the creation of the opening 274, an overlay offset occurs, and therefore the semiconductor material layer 130A exposed in the opening 274 is not located in the center of the underside of the opening 274 in the x-direction (and, in some embodiments, in the y-direction). Similar to the opening 174, however, the opening 274 has widths in the x- and / or y-direction that are greater than those of the semiconductor material layer 130A. Therefore, despite the overlay offset, the opening 274 can still completely expose the semiconductor material layer 130A. Then the opening 180, which replaces the semiconductor material layer 130A, can be created without difficulty. Subsequently, the components in the Fig. The manufacturing steps shown in 14A to 21C are carried out to complete the production of workpiece 200. In this way, since the process can be carried out without problems if an overlay misalignment occurs, the need for overlay control can be mitigated, thus saving time and costs in the manufacturing process.

[0091] The Fig. 23A, Fig. 24A, Fig. 25A, Fig. 26A, Fig. 27A, Fig. 28A and Fig. 29A are xz-sectional views of a workpiece 300 at different manufacturing stages along the line A - A' of Fig. 4 according to some alternative embodiments. The Fig. 23B, Fig. 24B, Fig. 25B, Fig. 26B, Fig. 27B, Fig. 28B and Fig. 29B are yz-sectional views of workpiece 300 at various manufacturing stages along line B - B' of Fig. 4 according to some alternative embodiments. Fig. 29C is a yz-sectional view of workpiece 300 at a manufacturing stage along line C - C' of Fig. 4 according to some alternative embodiments. Since, after completion of the manufacturing processes, the workpiece 300 has been manufactured into a semiconductor structure 300, the workpiece 300 can be referred to as the semiconductor structure 300, depending on the context.

[0092] In the Fig. 23A and Fig. 23B The manufacturing stage shown in these figures follows the one shown in the Fig. 13A and Fig. The manufacturing stage shown in Figure 13B is shown. It should be noted that, for the sake of clarity and simplicity, the following steps are not shown: Fig. 13A and Fig. 13B shown opening 174 in the Fig. 23A and Fig. 23B and in subsequent figures is designated as an opening 374. In the Fig. 23A and Fig. In some embodiments, the semiconductor material layer 130A is removed through opening 374 to create an opening 380, so that openings 374 and 380 collectively expose the lower insulating layer 132A.

[0093] In some embodiments, a selective etching process is performed to remove the semiconductor material layer 130A through the opening 374. In some embodiments, a selective etching process is performed that selectively etches the semiconductor material layer 130A, while the lower insulating layer 132A, the insulating structures 114, and the substrate 102 are only minimally (or essentially not) etched. The selective etching processes for the semiconductor material layer 130A can be dry etching processes, wet etching processes, other suitable etching processes, or combinations thereof. In these embodiments, the opening 380 is created in the position previously occupied by the semiconductor material layer 130A.

[0094] In other embodiments, after the creation of the opening 380, a further selective etching process is carried out to remove the lower insulating layer 132A, thereby enlarging the opening 380 and exposing the source / drain element 134 beneath the lower insulating layer 132A. This further selective etching process is similar to or comparable with the manufacturing step described in the Fig. 17A and Fig. 17B has been described, and the description is not repeated here. In these embodiments, the opening 380 is created at the location previously occupied by the semiconductor material layer 130A and the lower insulating layer 132A.

[0095] In the Fig. 24A and Fig. In some embodiments, a carbon layer 376 is produced on the underside of the opening 380 and above the source / drain element 134, beneath the lower insulating layer 132A. In some embodiments, the carbon layer 376 is an amorphous carbon layer. In some embodiments, the carbon layer 376 is produced on the underside of the opening 380 and on the lower insulating layer 132A, as shown in Fig. 24A is shown. In embodiments in which the lower insulating layer 132A has been removed prior to the production of the carbon layer 376, the carbon layer 376 is produced on the top of the opening 380 and on the exposed surface of the source / drain element 134.

[0096] In some embodiments, the carbon layer 376 is produced by a deposition process such as CVD, PVD, ALD, HDP-CVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, or APCVD, or by other suitable methods or combinations thereof. In some embodiments, the parameters of the deposition process are configured such that the carbon layer 376 is deposited more from bottom to top than laterally. In this way, the carbon layer 376 can be produced as a horizontal layer without forming a vertical part on the side wall of the openings 374 and 380. In some embodiments, the production of the carbon layer 376 further includes an etching process combined with the deposition process to control the shape of the carbon layer 376.

[0097] In the Fig. 25A and Fig. According to some embodiments, an insulating layer 378 is produced on the hard mask layer 172 and in the openings 374 and 380. In some embodiments, the insulating layer 378 is produced conformally on the top surface of the hard mask layer 172, the side wall of the opening 374, and the side wall of the opening 380. In particular, for the opening 380, the insulating layer 378 is produced on a portion of the side wall that is not covered by the carbon layer 376.

[0098] In some embodiments, the carbon layer 376 can suppress the deposition or growth of the insulating layer 378 material on the carbon layer 376. This results in the insulating layer 378 being formed on the side walls of the openings 374 and 380 without being formed on the surface of the carbon layer 376. That is, the insulating layer 378 has a vertical portion that is formed on the side walls of the openings 374 and 380, but not on the surface of the carbon layer 376, as shown in Fig. Figure 25A shows that after the insulating layer 378 has been produced, the carbon layer 376 is still exposed in the opening 380. In some embodiments, the method and material used in producing the insulating layer 378 are the same as or similar to those used for the insulating layer 178, and they are not repeated here.

[0099] In the Fig. 26A and Fig. In some embodiments, the carbon layer 376 is removed through opening 374 and opening 380, thus exposing the lower insulating layer 132A. In embodiments where the lower insulating layer 132A was removed before the carbon layer 376 was formed, the source / drain element 134 beneath the lower insulating layer 132A is exposed after the carbon layer 376 is removed. In these embodiments, the uppermost internal spacers 128 (the spacers 128 closest to the substrate 102) are also exposed through opening 380.

[0100] In some embodiments, a selective etching process is performed to remove the carbon layer 376 through the opening 380. In some embodiments, a selective etching process is performed that selectively etches the carbon layer 376, while the insulating layer 378, the lower insulating layer 132A, the source / drain element 134, the internal spacers 128, the gate spacers 124, the insulating structures 114, and the substrate 102 are only minimally etched (or essentially not at all). The selective etching processes for the carbon layer 376 can be dry etching processes, wet etching processes, other suitable etching processes, or combinations thereof. In other embodiments, the lower insulating layer 132A is removed after the carbon layer 376 has been removed.For example, after removing the carbon layer 376, a further selective etching process is carried out to remove the lower insulating layer 132A, to enlarge the opening 380 and to expose the source / drain element 134.

[0101] Let's stick with the Fig. 26A and Fig. 26B. According to some embodiments, a dielectric material layer 382 is produced in the openings 374 and 380 and on the lower insulating layer 132A. In particular, the dielectric material layer 382 is conformally produced on the insulating layer 378, which is produced on the side walls of the openings 374 and 380 and on the top of the hard mask layer 172, on the top of the lower insulating layer 132A exposed by the opening 380, and on a portion of the side wall of the opening 380 exposed after removal of the carbon layer 376. In embodiments in which the lower insulating layer 132A has been removed prior to the production of the dielectric material layer 382, ​​the dielectric material layer 382 is produced not on the top side of the lower insulating layer 132A but on the surface of the internal spacers 128 and the source / drain element 134, which has been exposed by the opening 380.In some embodiments, the method and material used in producing the dielectric material layer 382 are the same as or similar to those used for the dielectric material layer 182, and they are not repeated here.

[0102] In the Fig. 27A and Fig. 27B According to some embodiments, horizontal parts of the dielectric material layer 382 are removed to produce a dielectric sidewall layer 384. In some embodiments, an anisotropic etching process is carried out to remove the horizontal parts of the dielectric material layer 382, ​​while its vertical parts remain to form the dielectric sidewall layer 384, as in Fig. Figure 27A shows this. In some embodiments, the lower insulating layer 132A is also partially removed during the anisotropic etching process to expose the source / drain element 134, and then the first epitaxial layers 136 and the second epitaxial layers 138 are left untreated. For example, during the anisotropic etching process, the uppermost first epitaxial layers 136 (the first epitaxial layers 136 closest to the substrate 102) and the second epitaxial layers 138 are partially etched, thereby enlarging the opening 380 into the source / drain element 134. In some embodiments, the anisotropic etching process is a dry etching process (e.g., a plasma etching process).

[0103] In some embodiments, after the anisotropic etching process, the dielectric sidewall layer 184 is produced such that it has a first part 384A and a second part 384B, which is spaced apart from and arranged below the first part 384A. In some embodiments, the first part 384A is produced in the opening 374 and is produced on the upper part of the insulating layer 378, which is produced on the sidewall of the opening 374. In some embodiments, the second part 384B is produced in the opening 380 and is produced below the insulating layer 378, on the sidewalls of the uppermost internal spacers 128, and on a lower part of the sidewall of the opening 380 that is not covered by the insulating layer 378. In some embodiments, the dielectric sidewall layer 384 is not produced on the surface of the lower part of the insulating layer 378, which is produced on the sidewall of the opening 380.In some embodiments, the upper part of the side wall of the opening 380 is covered by the lower part of the insulating layer 378, and the lower part of the side wall of the opening 380 is covered by the second part 384B.

[0104] In some embodiments, the second part 384B of the dielectric sidewall layer 384 contains the materials from the dielectric material layer 382 and the lower insulating layer 132A. For example, the second part 384B comprises an upper part formed by the material of the dielectric material layer 382 and a lower part formed by the material of the lower insulating layer 132A, as shown in Fig. 27A is shown. In embodiments in which the lower insulating layer 132A has been removed before the dielectric material layer 382 has been produced, the second part 384B is formed from the material of the dielectric material layer 382.

[0105] In the Fig. 28A and Fig. In some embodiments, a silicide layer 386 is produced on the upper surface of the source / drain element 134, which has been exposed by the openings 374 and 380. In some embodiments, the method and material used in producing the silicide layer 386 are the same as or similar to those used for the silicide layers 162, and they are not repeated here.

[0106] Let's stick with the Fig. 28A and Fig. 28B. According to some embodiments, a conductive material 388 is deposited on the back side of the workpiece 300 and in the openings 374 and 380. In some embodiments, the method and material used in producing the conductive material 388 are the same as or similar to those used for the conductive material 188 and are not repeated here. In some embodiments, the conductive material 388 may comprise a single conductive layer or multiple conductive layers.

[0107] In the Fig. In some embodiments, as described in 29A to 29C, a planarization process (e.g., a CMP process and / or another planarization process) is performed on the back side of the workpiece 300 until the top surface of the hard mask layer 170 is exposed to create a source / drain contact 390. In some embodiments, the hard mask layer 172 and the portions of the insulating layer 378, the dielectric sidewall layer 384, and the conductive material 388 above the hard mask layer 172 are removed by the planarization process, and the remaining portions of the insulating layer 378, the dielectric sidewall layer 384, and the conductive material 388 form the source / drain contact 390. Since the source / drain contact 390 is created on the back side of the workpiece 300, it can also be referred to as a back-side source / drain contact.

[0108] In some embodiments, the source / drain contact 390 has a first part 390A, which is formed in the opening 374, and a second part 390B, which is formed in the opening 380. In some embodiments, the first part 390A is formed by the upper part of the insulating layer 178; the first part 384A of the dielectric sidewall layer 384, which is enclosed by the upper part of the insulating layer 378; and the upper part of the conductive material 388, which is enclosed by the upper part of the insulating layer 378 and the first part 384A of the dielectric sidewall layer 384, as shown in the Fig. 29A and Fig. 29C. In some embodiments, the second part 390B is arranged below the first part 390A, is in contact with the source / drain element 134, and is formed by the lower part of the insulating layer 378, the second part 384B of the dielectric sidewall layer 384, and the lower part of the conductive material 388, which is enclosed by the second part 384B and the lower part of the insulating layer 378, as shown in the Fig. 29A and Fig. 29C is shown.

[0109] In some embodiments, the widths of the first part 390A are greater than the widths of the second part 390B in the x and y directions. Since in some embodiments the first part 390A is wider than the second part 390B and the upper part of the insulating layer 378 is produced on the periphery of the first part 390A, a portion of the substrate 102 is layered vertically in the z direction between the upper part of the insulating layer 378 and the second semiconductor layers 108, as shown in Fig. Figure 29A shows that in some embodiments, part of the substrate 102 is layered vertically in the z-direction between the upper part of the insulating layer 378 and the internal spacers 128. In other embodiments, parts of the insulating structures 114 are layered vertically in the z-direction between the upper part of the insulating layer 378 and the gate spacers 124.

[0110] As explained above, the second part 390B of the source / drain contact 390 (i.e., the rear source / drain contact) is produced in the opening 380, and the opening 380 is created in the space previously occupied by the semiconductor material layer 130A. Furthermore, the opening 374 is larger than the opening 380, and thus the first part 390A produced in the opening 374 is larger than the second part 390B produced in the opening 380. Therefore, similar to the source / drain contact 190, the resistance of the source / drain contact 390 can be reduced, a short circuit between the source / drain contact 390 and other conductive components can be avoided, and even with a small source / drain element 134, the source / drain contact 390 can still be reliably connected to the source / drain element 134.

[0111] As explained above, the insulating layer 378 is produced on the periphery of the first part 390A of the (rear) source / drain contact 390. That is, the insulating layer 378 covers the corner of the first part 390A and separates the conductive material 388 from the other components. Therefore, similar to the source / drain contact 190, the insulating layer 378 can prevent leakage from the source / drain contact 390, such as leakage between the source / drain contact 390 and the gate structures 150. And since the opening 374 is larger than the opening 380, as referred to in Fig. As explained in section 22, the person in the Fig. The manufacturing process shown in Figures 23A to 29C can be carried out without problems if an overlay misalignment occurs. This can reduce the need for overlay control, saving time and costs in the manufacturing process.

[0112] The embodiments disclosed herein relate to semiconductor structures and their fabrication methods, and in particular to semiconductor structures and methods that include the fabrication of semiconductor material layers (e.g., SiGe layers) beneath source / drain elements. A backside source / drain contact can be fabricated in a first opening and a second opening below the first opening by selectively removing the semiconductor material layer. This selective removal allows the entire space occupied by the semiconductor material layer to be used for fabricating the backside source / drain contact, thereby reducing its resistance and reliably connecting the small source / drain element. Furthermore, this selective removal prevents the backside source / drain contact from contacting the gate, thus avoiding the formation of a short circuit.Furthermore, an insulating layer applied to the periphery of the rear S / D contact can prevent leakage. Additionally, the first opening is larger than the second, thus reducing the resistance of the rear S / D contact and mitigating the need for overlay control.

[0113] In one exemplary aspect, the present disclosure relates to a method for fabricating a semiconductor structure. The method comprises: fabricating a fin structure having first and second semiconductor layers stacked alternately over a substrate; creating a first and a second source / drain channel in the fin structure; and fabricating a first and a second semiconductor material layer in the first and second source / drain channels, respectively. The method further comprises: fabricating a first and a second source / drain element over the first and second semiconductor material layers in the first and second source / drain channels, respectively; removing the first semiconductor layers; and fabricating a gate structure to enclose the second semiconductor layers.The process further comprises: inverting the semiconductor structure; fabricating a hard mask layer on one back side of the substrate; and etching the hard mask layer and the substrate to create a first opening that exposes the first semiconductor material layer. The first width of the first opening is greater than the second width of the first semiconductor material layer. The process further comprises: fabricating an insulating layer on one side wall of the first opening; removing the first semiconductor material layer to create a second opening that exposes the first source / drain element; and depositing a conductive material in the first and second openings to establish a first source / drain contact.

[0114] In another exemplary aspect, the present disclosure relates to a method for fabricating a semiconductor structure. The method comprises: fabricating a fin structure extending in a first horizontal direction over a substrate and having first and second semiconductor layers stacked alternately in a vertical direction; fabricating, over the fin structure, a dummy gate structure extending in a second horizontal direction; and fabricating a first and a second semiconductor material layer on opposite sides of the dummy gate structure in the first horizontal direction. The method further comprises: fabricating a first and a second insulating layer on the first and second semiconductor material layers, respectively; and fabricating a first and a second source / drain element on the first and second insulating layers, respectively.The first and second source / drain elements are attached to opposite sides of the second semiconductor layers. The process further comprises: inverting the semiconductor structure; fabricating a first hard mask layer on one back side of the substrate and a second hard mask layer on top of the first hard mask layer; and etching the second hard mask layer, the first hard mask layer, and the substrate to create a first opening that exposes the first semiconductor material layer. In the first and second horizontal directions, the widths of the first opening are greater than the widths of the first semiconductor material layer.The process further comprises: producing an insulating layer on a first sidewall of the first opening; removing the first semiconductor material layer to create a second opening that exposes the first insulating layer; removing the first insulating layer to enlarge the second opening; and depositing a conductive material in the first and second openings to establish a first source / drain contact.

[0115] In a further exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure comprises: a substrate; nanostructures beneath the substrate; a gate structure enclosing each of the nanostructures; a first and a second source / drain element attached to opposite sides of the nanostructures in a first horizontal direction; and a hard mask layer over the substrate. The nanostructures are spaced apart from each other in a vertical direction. The semiconductor structure further comprises a source / drain contact extending through the hard mask layer and the substrate and in contact with the first source / drain element. The source / drain contact has a first part in contact with the first source / drain element and a second part on the first part.In the first and a second horizontal direction, the widths of the second part are greater than the widths of the first part, with the second horizontal direction being perpendicular to the first. The second part of the source / drain contact has a second conductive part and a second insulating layer that surrounds the second conductive part. A portion of the substrate is layered vertically between the second insulating layer and the nanostructures.

[0116] In another exemplary aspect, the present disclosure relates to a method for fabricating a semiconductor structure. The method comprises: fabricating a fin structure having first and second semiconductor layers stacked alternately over a substrate; creating a first and a second source / drain groove in the fin structure; partially removing the first semiconductor layers to create spacer recesses; and fabricating spacers in the spacer recesses. The method further comprises: fabricating a first and a second semiconductor material layer in the first and second source / drain grooves, respectively; and fabricating a first and a second source / drain element over the first and second semiconductor material layers, respectively.The process further comprises: inverting the semiconductor structure; fabricating a hard mask layer on one back side of the substrate; and etching the hard mask layer and the substrate to create a first opening that exposes the first semiconductor material layer. The process further comprises: fabricating an insulating layer on one side wall of the first opening; removing the first semiconductor material layer to create a second opening; and depositing a conductive material in the first and second openings to establish a first source / drain contact.

[0117] In some embodiments, the method further comprises the following: introducing an inhibitor into the first semiconductor material layer before the insulating layer is produced; and removing the inhibitor from the first opening after the insulating layer has been produced. After removing the inhibitor, the first semiconductor material layer is removed.

[0118] In some embodiments, the method further includes the fabrication of a first insulating layer on the first semiconductor material layer. The first insulating layer is positioned between the first semiconductor material layer and the first source / drain element. After the first semiconductor material layer is removed, the first insulating layer is exposed through the second opening.

[0119] In some embodiments, the method further comprises: removing the first insulating layer to enlarge the second opening to expose the first source / drain element; producing a carbon layer on a bottom side of the second opening and on the first source / drain element, wherein the insulating layer is produced after the carbon layer has been produced and is produced on the side wall of the first opening and a side wall of the second opening; and removing the carbon layer after the insulating layer has been produced.

[0120] Features of various embodiments have been described above so that those skilled in the art can better understand the aspects of the present disclosure. It should be clear to those skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other methods and structures to achieve the same objectives and / or to obtain the same advantages as in the embodiments presented here. Those skilled in the art should also recognize that such equivalent interpretations do not deviate from the fundamental concept and scope of protection of the present disclosure and that they can make various changes, substitutions, and modifications without deviating from the fundamental concept and scope of protection of the present disclosure.

Claims

[1] Method for fabricating a semiconductor structure, comprising: Fabricating a fin structure over a substrate, wherein the fin structure has first and second semiconductor layers that are stacked alternately; Creating a first and a second source / drainage trench in the fin structure; Creating a first and a second semiconductor material layer in the first and second source / drain trench, respectively; Creating a first and a second source / drain element above the first and second semiconductor material layers in the first and second source / drain trench, respectively; Removal of the first semiconductor layers; Creating a gate structure to enclose the second semiconductor layers; Reversals of the semiconductor structure; Creating a hard mask layer on one side of the substrate; Etching the hard mask layer and the substrate to create a first opening that exposes the first semiconductor material layer, wherein a first width of the first opening is greater than a second width of the first semiconductor material layer; Creating an insulating layer on one side wall of the first opening; Removing the first semiconductor material layer to create a second opening that exposes the first source / drain element; and Deposition of a conductive material in the first and second openings to establish an initial source / drain contact. [2] The method of claim 1, further comprising: Prior to the production of the insulating layer, an inhibitor is introduced into the first semiconductor material layer; and After the insulating layer has been produced, the inhibitor is removed from the first opening, whereby the first semiconductor material layer is removed after the removal of the inhibitor. [3] The method of claim 1 or 2, further comprising: conformal deposition of a dielectric material layer in the first and second openings; and Removing horizontal parts of the dielectric material layer to create a dielectric sidewall layer on the sidewalls of the insulating layer and the second opening. [4] Method according to claim 3, wherein the insulating layer has a protrusion on one underside of the first opening, and a first part of the dielectric sidewall layer on the projection of the insulating layer is thinner than a second part of the dielectric sidewall layer. [5] A method according to any of the preceding claims, further comprising: Prior to depositing the conductive material, a silicide layer is applied to a surface of the first source / drain element that has been exposed by the first and second openings. [6] A method according to any of the preceding claims, further comprising: After removing the first semiconductor material layer, a carbon layer is produced on a bottom side of the second opening and above the first source / drain element, wherein the insulating layer is produced after the carbon layer is produced and is produced on the side wall of the first opening and on a side wall of the second opening; and After creating the insulating layer, remove the carbon layer. [7] A method according to any of the preceding claims, further comprising: Partial removal of the first semiconductor layers to create internal spacer recesses; and Manufacturing internal spacers in the internal spacer recesses, with the first opening and the internal spacers overlapping vertically. [8] A method according to any of the preceding claims, further comprising: Before turning the semiconductor structure, an interlayer dielectric layer (ILD layer) is produced over the first and second source / drain elements; Etching the ILD layer to create a third opening that exposes the second source / drain element; and Establish a second source / drain contact in the third opening. [9] Methods for fabricating a semiconductor structure, comprising: Producing a fin structure extending in a first horizontal direction over a substrate, wherein the fin structure has first and second semiconductor layers that are stacked alternately in a vertical direction; Create, above the fin structure, a dummy gate structure that extends in a second horizontal direction; Creating a first and a second semiconductor material layer on opposite sides of the dummy gate structure in the first horizontal direction; Creating a first and a second insulating layer on the first and second semiconductor material layers, respectively; Manufacturing a first and a second source / drain element on the first and second insulating layers respectively, wherein the first and the second source / drain element are attached to opposite sides of the second semiconductor layers; Reversals of the semiconductor structure; Producing a first hard mask layer on one back side of the substrate and a second hard mask layer on top of the first hard mask layer; Etching the second hard mask layer, the first hard mask layer and the substrate to create a first opening that exposes the first semiconductor material layer, wherein in the first and second horizontal directions the widths of the first opening are greater than the widths of the first semiconductor material layer; Creating an insulating layer on a first side wall of the first opening; Removing the first semiconductor material layer to create a second opening that exposes the first insulating layer; Removing the first layer of insulation to enlarge the second opening; and Deposition of a conductive material in the first and second openings to establish an initial source / drain contact. [10] The method of claim 9, further comprising: After removing the first semiconductor material layer, a carbon layer is produced on the first insulating layer, wherein the insulating layer is produced after the carbon layer and is produced on the first side wall of the first opening and on a second side wall of the second opening; and After creating the insulating layer, remove the carbon layer. [11] The method of claim 9 or 10, further comprising: conformal deposition of a dielectric material layer in the first and second openings; and Removing horizontal portions of the dielectric material layer to create a dielectric sidewall layer. [12] Method according to claim 11, wherein the dielectric sidewall layer has a first and a second part, wherein the first part is produced on an upper part of the insulating layer, which is produced on the first side wall of the first opening, and the second part is produced on a lower side wall of the second side wall of the second opening and under a lower part of the insulating layer, which is produced on an upper side wall of the second side wall of the second opening. [13] Method according to claim 12, wherein a surface of the lower part of the insulating layer does not have the dielectric sidewall layer. [14] Method according to any one of claims 9 to 13, further comprising: Prior to the production of the insulating layer, an inhibitor is introduced into the first semiconductor material layer through the first opening; and After the insulating layer has been produced, the inhibitor is removed from the first opening, whereby the first semiconductor material layer is removed after the removal of the inhibitor. [15] Method according to any one of claims 9 to 14, further comprising: Removing the dummy gate structure and the first semiconductor layers to create a gate trench; and Creating a metal gate structure in the gate trench to enclose each of the second semiconductor layers. [16] Method according to any one of claims 9 to 15, further comprising: Performing a planarization process on the back of the substrate to expose the first hard mask layer, so that the second hard mask layer and parts of the insulating layer and conductive material above the first hard mask layer are removed. [17] Semiconductor structure with: a substrate; Nanostructures beneath the substrate, wherein the nanostructures are spaced apart from each other in a vertical direction; a gate structure that encloses each of the nanostructures; a first and a second source / drain element, which are attached to opposite sides of the nanostructures in a first horizontal direction; a hard mask layer over the substrate; and a source / drain contact extending through the hard mask layer and the substrate and in contact with the first source / drain element, wherein the source / drain contact has a first part in contact with the first source / drain element and a second part on the first part, wherein in the first and a second horizontal direction, the widths of the second part are greater than the widths of the first part, the second horizontal direction being perpendicular to the first horizontal direction. the second part of the source / drain contact has a second conductive part and a second insulating layer that surrounds the second conductive part, and Part of the substrate is layered vertically between the second insulating layer and the nanostructures. [18] Semiconductor structure according to claim 17, further comprising: a dielectric sidewall layer that encloses a first conductive part of the first part of the source / drain contact and the second conductive part, and is arranged between the second conductive part and the second insulating layer. [19] Semiconductor structure according to claim 18, wherein the second insulating layer has a protruding part on an underside of the second part of the source / drain contact and a main part above the protruding part, and a first part of the dielectric sidewall layer between the projecting part of the second insulating layer and the second conductive part is thinner than a second part of the dielectric sidewall layer between the main part of the second insulating layer and the second conductive part. [20] Semiconductor structure according to any one of claims 17 to 19, wherein the first part of the source / drain contact comprises: a first conductive part and a first insulating layer enclosing an upper part of the first conductive part; and Beneath the first insulating layer is a first dielectric sidewall layer that encloses a lower part of the first conductive part.

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