METHODS, DEVICES AND MANUFACTURES FOR ATTENTING INTERFERENCE IN DOPPLER DISTANCE REPRESENTATIONS

Abstract

An exemplary setup includes an interface circuit arrangement for receiving digital samples representing a frame of chirps.The device includes a programmable circuit arrangement that can be programmed by instructions to: determine a distance Fourier transform (FT) representation of the frame of chirps; determine a reconstructed chirp for a chirp in the frame of chirps that contains a faulty sample; determine a first Doppler distance representation of the frame of chirps based on the distance FT representation, where the distance FT representation contains the reconstructed chirp; and determine a second Doppler distance representation as an element-wise minimum between the first Doppler distance representation and a third Doppler distance representation of the frame of chirps, where the third Doppler distance representation is based on the digital samples, the digital samples containing a reconstructed sample that substitutes for the faulty sample of the chirp. Other examples are described.

Description

TECHNICAL AREA

[0001] This description generally concerns Doppler multi-access radar and, in particular, methods, equipment, and manufacturing articles for attenuating interference in Doppler distance representations. BACKGROUND

[0002] Doppler Division Multiple Access (DDMA) is a method for dividing a Doppler dimension, or Doppler domain, into multiple subdivisions and assigning a transmitter to each subdivision. This can be achieved by generating a sequence of chirps such that there is a linear increment (or decrement) in the incipient phase of each chirp. Different transmitters can exhibit different rates of phase increment or decrement. For each chirp, multiple transmitters are activated. When received and processed according to a two-dimensional Fast Fourier Transform (FFT), DDMA signals from different transmitters will each occupy a different band in the Doppler domain.In this way, DDMA enables the simultaneous use of multiple transmitters within a single chirp, while preventing the multiple transmitters from interfering with each other in the Doppler domain, and also provides the ability to separate data from each transmitter. SUMMARY

[0003] For methods, devices and manufacturing articles for attenuating interference in Doppler distance representations, an exemplary device includes an interface circuit arrangement for receiving digital samples representing a frame of chirps.The device includes a programmable circuit arrangement for the following: determining a distance Fourier transform (FT) representation of the frame of chirps; determining a reconstructed chirp for a chirp in the frame of chirps that contains a faulty sample; determining a first Doppler distance representation of the frame of chirps based on the distance FT representation, wherein the distance FT representation contains the reconstructed chirp; and determining a second Doppler distance representation as an element-wise minimum between the first Doppler distance representation and a third Doppler distance representation of the frame of chirps, wherein the third Doppler distance representation is based on the digital samples, the digital samples containing a reconstructed sample that substitutes for the faulty sample of the chirp.The programmable circuit arrangement can consist of one or more programmable circuits that can be programmed by instructions. Other examples are described.

[0004] For methods, devices, and manufacturing articles for attenuating interference in Doppler distance representations, an exemplary non-volatile computer-readable medium includes instructions for instructing the programmable circuit arrangement to determine, for a distance Fourier transform (FT) representation of a frame of chirps, a reconstructed chirp for a chirp of the frame of chirps that includes a faulty sample, wherein the frame of chirps from an environment is received by an integrated radar circuit and represented by digital samples. The non-volatile computer-readable medium includes instructions for instructing a programmable circuit arrangement to determine a first Doppler distance representation of the frame of chirps based on the distance FT representation, wherein the distance FT representation includes the reconstructed chirp.The non-volatile, computer-readable medium contains instructions for instructing a programmable circuit arrangement to determine a second Doppler distance representation as an element-wise minimum between the first Doppler distance representation and a third Doppler distance representation of the chirp frame, wherein the third Doppler distance representation is based on the digital samples, the digital samples including a reconstructed sample that substitutes for the faulty chirp sample. The programmable circuit arrangement can be one or more programmable circuits that can be programmed by instructions. Other examples are described.

[0005] For methods, devices, and manufacturing articles for attenuating interference in Doppler distance representations, an exemplary method includes receiving, with an interface circuit arrangement, digital samples representing a frame of chirps. The method includes replacing, by executing a command with a programmable circuit arrangement, a chirp of the frame containing a faulty sample with a chirp of zero value in the digital samples. The method includes determining, by executing a command with the programmable circuit arrangement, a distance Fourier transform (FT) representation of the frame of chirps based on the digital samples, wherein the digital samples contain the chirp of zero value, and the distance FT representation has a first dimension and a second dimension.The procedure involves, for each indice across the second dimension of the distance FT representation, determining a Doppler FT representation by executing an instruction with the programmable circuitry. The procedure further involves, for each Doppler FT representation: setting to zero any value that does not meet a threshold of a peak value in the respective Doppler FT representation by executing an instruction with the programmable circuitry; and determining an inverse distance FT representation to generate a reconstructed chirp by executing an instruction with the programmable circuitry. The procedure further involves replacing the chirp, including the faulty sample, in the distance FT representation with the reconstructed chirp by executing an instruction with the programmable circuitry.The method involves determining, by executing an instruction with the programmable circuit arrangement, a Doppler distance representation of the frame of chirps based on the distance FT representation, where the distance FT representation contains the reconstructed chirp. The programmable circuit arrangement can be one or more programmable circuits that can be programmed by instructions. Other examples are described. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a block diagram of an exemplary radar system including exemplary radar circuits. Fig. Figure 2 is a block diagram of an exemplary integrated circuit (IC) of a radar transceiver, which represents any one of the radar circuits from Fig. 1 can implement. Fig. 3A is a time history diagram of an example frame of example chirps. Fig. Figure 3B is a diagram of an exemplary processing flow for generating an exemplary Doppler distance representation of a received frame of reflected chirps. Fig. Figure 4A is a time history diagram of an interference that can occur in radar applications. Fig. 4B is a graphical representation of digital samples, corresponding to the time-series diagram from Fig. 4A corresponds. Fig. Figure 5 is a diagram of an exemplary processing flow for generating an initial exemplary Doppler distance representation of a received frame of reflected chirps to attenuate interference along one distance dimension. Fig. Figure 6 is a diagram of an exemplary processing flow for generating a second exemplary Doppler distance representation of the received frame of reflected chirps in order to attenuate interference along one Doppler dimension. Fig. Figure 7 is a diagram of an exemplary processing flow for generating a third exemplary Doppler distance representation of the received frame of reflected chirps in order to attenuate interference along the distance dimension and the Doppler dimension. Fig. Figure 8 is a diagram of an exemplary processing flow for reconstructing faulty ADC samples along the distance dimension and the Doppler dimension. Fig. Figure 9 is a flowchart representing exemplary machine-readable instructions or exemplary operations that can be performed using an exemplary programmable circuit arrangement implementation of the radar transceiver IC. Fig. 2 can be executed, instantiated and / or performed to determine a Doppler distance representation to attenuate interference along the distance dimension and the Doppler dimension. Fig. Figure 10 is a flowchart representing exemplary machine-readable instructions or exemplary operations that can be performed using an exemplary programmable circuit arrangement implementation of the radar transceiver IC. Fig. 2 can be executed, instantiated and / or performed to determine a reconstructed chirp for a reflected chirp including a faulty sample. Fig. Figure 11 is a flowchart representing exemplary machine-readable instructions or exemplary operations that can be performed using an exemplary programmable circuit arrangement implementation of the radar transceiver IC. Fig. 2 can be executed, instantiated and / or performed to determine a Doppler distance representation to attenuate interference along the distance dimension and the Doppler dimension. Fig. Figure 12 is a block diagram of an exemplary processing platform including a programmable circuit arrangement for executing, instantiating, or performing the exemplary machine-readable instructions or performing the exemplary operations from Fig. 9, Fig. 10 and Fig. 11 is structured to accommodate the radar transceiver IC from Fig. 2 to implement. Fig. Figure 13 is a block diagram of an exemplary implementation of the programmable circuit arrangement from Fig. 12. Fig. Figure 14 is a block diagram of another exemplary implementation of the programmable circuit arrangement from Fig. 12. Fig. Figure 15 is a block diagram of an exemplary software / firmware / instruction distribution platform (e.g., one or more servers) for distributing software, instructions, or firmware (e.g., according to the exemplary machine-readable instructions from Fig. 9, Fig. 10 and Fig. 11) to client devices associated with end users or consumers (e.g. for licensing, sale or use), retailers (e.g. for sale, resale, licensing or sublicensing) or original equipment manufacturers (OEMs) (e.g. for incorporation into products for distribution to, for example, retailers or other end users, such as direct customers).

[0006] The drawings are not necessarily to scale. Generally, the same reference numbers in the drawing(s) and this description refer to the same or similar (with respect to functional and / or structural) features or parts. Although the drawings show areas with clear lines and boundaries, some or all of these lines and boundaries may be idealized. In reality, the boundaries or lines may be unobservable, blended, or irregular. DETAILED DESCRIPTION

[0007] Fig. Figure 1 is a block diagram of an exemplary radar system 100 including exemplary radar circuits 102 A , 102 B , 102 C , 102 D , 102 E , 102 F , 102 G , 102 H In the example from Fig. 1 The radar system 100 also includes an exemplary processor circuit 104. In the example from Fig. 1. One or more of the radar circuits 102 A , 102 B , 102 C , 102 D , 102 E , 102 F , 102 G , 102 H The processor circuit 104 can be referred to as a radar front end, and the processor circuit 104 can be referred to as a radar back end. In some examples, one or more of the radar circuits 102 are used. A , 102 B , 102 C , 102 D , 102 E , 102 F , 102 G , 102 H and the processor circuit 104 are implemented separately and can be configured to be coupled together. Additionally or alternatively, one or more of the radar circuits 102 are A , 102 B , 102 C , 102 D , 102 E , 102 F , 102 G , 102 Himplemented with an instance of the processor circuit 104, for example in a single-chip package or on a system-on-a-chip (SoC) (e.g., a single IC). In examples where one or more of the radar circuits 102 A , 102 B , 102 C , 102 D , 102 E , 102 F , 102 G , 102 H Implemented with an instance of the processor circuit 104 on a SoC, one or more of the radar circuits 102 can A , 102 B , 102 C , 102 D , 102 E , 102 F , 102 G , 102 H corresponding to a sub-circuit of the IC that forms the SoC.

[0008] In the illustrated example from Fig. 1 is the processor circuit 104 with each of the radar circuits 102 A , 102 B , 102 C , 102 D , 102 E , 102 F , 102 G , 102H (e.g. via an interface) which can enable any suitable communication technology (e.g. a serial interface, a parallel interface, etc.), and is for receiving data from and / or sending data to each of the radar circuits 102 A , 102 B , 102 C , 102 D , 102 E , 102 F , 102 G , 102 H structured. In some examples, the interface between the processor circuit 104 and each of the radar circuits 102 can be structured. A , 102 B , 102 C , 102 D , 102 E , 102 F , 102 G , 102 H a high-speed serial interface, such as a low-voltage differential signaling (LVDS) interface. Additionally or alternatively, the interface between the processor circuit 104 and each of the radar circuits 102 can beA , 102 B , 102 C , 102 D , 102 E , 102 F , 102 G , 102 H a lower-speed interface, such as a Serial Peripheral Interface (SPI).

[0009] In the illustrated example from Fig. 1. One or more of the radar circuits 102 A , 102 B , 102 C , 102 D , 102 E , 102 F , 102 G , 102 H Implement DDMA, as described here. For example, one or more of the radar circuits 102 A , 102 B , 102 C , 102 D , 102 E , 102 F , 102 G , 102 HGenerate a sequence of chirps, sometimes called a frame of chirps, and transfer it to an environment such that there is a linear increment (or decrement) in the incipient phase of each chirp. In the example from Fig. 1 include one or more of the radar circuits 102 A , 102 B , 102 C , 102 D , 102 E , 102 F , 102 G , 102 H A functionality for generating one or more chirp signals, as described here. Furthermore, each of the radar circuits includes 102 A , 102 B , 102 C , 102 D , 102 E , 102 F , 102 G , 102 H also a functionality for generating one or more digital intermediate frequency (IF) signals (sometimes referred to as dechirped signals, beat signals or tubular radar signals) from reflected chirps.

[0010] In the illustrated example from Fig. 1 includes each of the radar circuits 102 A , 102 B , 102 C , 102 D , 102 E , 102 F , 102 G , 102 H A functionality for performing at least part of the signal processing of received radar signals (e.g., the reflected chirps, the digital IF signals, etc.) and for delivering the results of the signal processing to the processor circuit 104. In some examples, each of the radar circuits 102 includes A , 102 B , 102 C , 102 D , 102 E , 102 F , 102 G , 102 H A functionality for performing a distance Fourier transform (distance FT) on each received frame (e.g., each sequence of chirps in the frame). Additionally or alternatively, each of the radar circuits includes 102 A , 102 B , 102 C , 102D , 102 E , 102 F , 102 G , 102 H A functionality to perform a Doppler FT on each received frame (e.g., after performing the distance FTs and on one of the results). In some of the examples provided here, the distance FT and / or Doppler FT may be a distance Fast Fourier Transform (distance FFT) and / or a Doppler FFT.

[0011] In the illustrated example from Fig. 1. The processor circuit 104 includes functionality for processing data from one or more of the radar circuits 102. A , 102 B , 102 C , 102 D , 102 E , 102 F , 102 G , 102 HThe data received can be used, for example, to determine the distance, speed, and / or angle of any objects detected by the radar system 100. Additionally or alternatively, the processor circuit 104 includes functionality for performing post-processing of information regarding the detected objects, such as tracking objects or determining the rate and direction of motion. In some examples, the processor circuit 104 performs velocity disambiguation and / or collision detection.

[0012] In the illustrated example from Fig. 1 The processor circuit 104 includes one or more processors or combinations of processors for processing data from one or more of the radar circuits 102 A , 102 B , 102 C , 102 D , 102 E , 102 F , 102 G , 102 Hbe received. In the example from Fig. 1. The processor circuit 104 also supplies data to one or more of the radar circuits 102. A , 102 B , 102 C , 102 D , 102 E , 102 F , 102 G , 102 H The processor circuit 104 can, for example, include a digital signal processor (DSP), a microcontroller, a SoC that combines both a DSP and a microcontroller, a field-programmable gate array (FPGA) and / or any combination of the foregoing.

[0013] In the illustrated example from Fig. 1. The Radar System 100 can be implemented in a variety of applications, such as in driver assistance systems (ADAS) and motor vehicles for measuring distance, speed, acceleration, and angle. In some examples, the Radar System 100 can be implemented in other vehicles (e.g., aircraft or ships), industrial applications, imaging radar, robotics, automation (e.g., industrial automation, building automation, etc.), security and monitoring (e.g., building security), people counting, or medical devices for blood pressure monitoring, emotional monitoring, and sleep monitoring. In the example from Fig. Figure 1 shows the radar system 100 implemented in an exemplary automotive application. For example, the radar circuits 102 A , 102 B , 102 C , 102 D , 102 E , 102 F , 102 G , 102 Hpositioned around a vehicle to provide automotive driver assistance. Fig. Figure 1 shows an exemplary use case with eight radar circuits, while some vehicles may only have corner radar circuits. A , 102 C , 102 F , 102 H or a front radar circuit 102 E exhibit.

[0014] Fig. Figure 2 is a block diagram of an exemplary radar transceiver IC (IC: Integrated Circuit) 200, which can be any of the radar circuits 102. A , 102 B , 102 C , 102 D , 102 E , 102 F , 102 G , 102 H out of Fig. 1 can be implemented. In the example from Fig. 2 includes the radar transceiver IC 200, an integrated radar circuit, an exemplary chirp synthesis circuit 202, and exemplary transmitters 2041-204 N, exemplary transmitting antennas 2061-206 N , exemplary receiving antennas 2081-208 M , exemplary recipients 2101-210 M , an exemplary interface circuit arrangement 212 and an exemplary processor circuit 214. Furthermore, the example from Fig. 2 the transmitters 2041-204 N each exemplary phase shifter 2161-216 N and exemplary power amplifiers (PAs) 2181-218 N .

[0015] In the illustrated example from Fig. 2 include receivers 2101-210 M Examples of low-noise amplifiers (LNAs): 2201-220 M , exemplary mixers 2221-222 M and exemplary analog-to-digital converters (ADCs) 2241-224 M In the example from Fig. 2. The radar transceiver IC 200 contains four of the transmitters 2041-204. N, the transmitting antennas 2061-206 N , the receiving antennas 2081-208 M and the recipient 2101-210 M (e.g., N equals M equals four). In some examples, the radar transceiver IC 200 includes other numbers of any transmitters 2041-204. N , the transmitting antennas 2061-206 N , the receiving antennas 2081-208 M or the recipient 2101-210 M .

[0016] In some examples, the radar transceiver IC 200 and the processor IC 214 are implemented separately and may be configured to be coupled together. Additionally or alternatively, the radar transceiver IC 200 and the processor IC 214 are implemented, for example, in a single-chip package or on a system-on-a-chip (SoC). In examples where the radar transceiver IC 200 and the processor IC 214 are implemented on an SoC, the radar transceiver IC 200 may correspond to a sub-circuit of the IC that forms the SoC.

[0017] In the illustrated example from Fig. 2 The chirp synthesis circuit 202 is implemented by an analog and / or digital circuit arrangement. In the example from Fig. 2 is the chirp synthesis circuit 202 with transmitters 2041-204 Ncoupled. For example, the chirp synthesis circuit 202 is coupled with the phase shifters 2161-216. N the transmitter 2041-204 N coupled. Furthermore, in the example from Fig. 2 the Chirp synthesis circuit 202 with receivers 2101-210 M coupled. For example, the Chirp synthesis circuit 202 is coupled with the mixers 2221-222. M the receiver 2101-210 M coupled. In some examples, the chirp synthesis circuit 202 is coupled with the processor circuit 214.

[0018] In the illustrated example from Fig. 2 is each of the phase shifters 2161-216 N implemented through an analog and / or digital circuit arrangement. In the example from Fig. 2 is each of the phase shifters 2161-216 N coupled with the Chirp synthesis circuit 202. Furthermore, in the example from Fig. 2 the phase shifters 2161-216 Nwith the PAs 2181-218 N coupled (e.g., respective phase shifters are coupled with respective PAs). In the example from Fig. 2 is each of the PAs 2181-218 N implemented through an analog and / or digital circuit arrangement. Furthermore, in the example from Fig. 2 the PAs 2181-218 N with the phase shifters 2161-216 N and the transmitting antennas 2061-206 N coupled.

[0019] In modern applications, radar circuits, such as the radar transceiver IC 200 from Fig. 2. Multiple transmitters and multiple receivers. DDMA provides a method for dividing a Doppler domain spectrum into multiple subdivisions and assigning each of the multiple transmitters to a respective subdivision. For example, DDMA is widely used in automotive FMCW radar applications (FMCW: Frequency Modulated Continuous Wave). In DDMA, multiple transmitters transmit a frame of chirps simultaneously, with each transmitter conveying a linear phase shift (Φ) across the chirps of the frame. For the k-th indexed transmitter, the following holds: Φk=2πkNTX, where N TX the number of transmitters and k is an index value in a range of [1:N] corresponding to a transmitter emitting a signal with a phase change Φ k is transferred. Therefore, the phase changes for the N TXTransmitters are linear with a direct proportionality to transmitter indices. DDMA leads to the Doppler domain spectrum, which is in N TX The bands are divided, with each target detected by a radar circuit being assigned to N TX Peaks or representations lead and each peak (e.g. image) to one of the N TX Sender corresponds.

[0020] In the illustrated example from Fig. 2 implements the radar transceiver IC 200 DDMA. For example, the chirp synthesis circuit 202 includes functionality for receiving chirp parameter values ​​(e.g., from the processor circuit 214) for a sequence of chirps in a radar frame. In some examples, the chirp parameters are defined by the radar system architecture and may include, for example, a transmitter activation parameter to specify which of the transmitters 2041-204 NTo be activated, it must include a chirp frequency start value, a chirp frequency slope, an ADC sampling time, a ramp end time, and a transmitter start time. In the example from Fig. 2. The chirp synthesis circuit 202 also includes functionality for generating signals (e.g., a chirp, a frame of chirps, etc.) for transmission based on the chirp parameter values ​​(which are received, for example, by the processor circuit 214). In some examples, the chirp synthesis circuit 202 includes a phase-locked loop (PLL) oscillator with a voltage-controlled oscillator (VCO). In additional or alternative examples, the chirp synthesis circuit 202 includes a local oscillator (LO).

[0021] In the illustrated example from Fig. 2 Each of the phase shifters 2161-216 receives NThe output signal provided by the chirp synthesis circuit 202 (e.g., a chirp, a frame of chirps, etc.) is modulated to produce a frame of chirps with a linear phase change across the chirps. For example, for a first example indexed transmitter 2041, a first example indexed phase shifter 2161 applies a first phase change Φ1 between successive chirps of a frame. Therefore, the first indexed phase shifter 2161 produces a frame of chirps where the phase changes between successive chirps of the frame are the same (e.g., for TX1 ΔΦ). C1-C2 = ΔΦ C2-C3 = ΔΦ C3-C4 ... = ΔΦ C(N-1)-(CN ). Furthermore, for example, for an Nth exemplary indexed channel, 204 applies. N an Nth exemplary indexed phase shifter 216 Nan Nth phase change Φ N between successive chirps of a frame. Therefore, the Nth indexed phase shifter generates 216 N a frame of chirps where the phase changes between successive chirps of the frame are the same (e.g. for TX) N ΔΦ C1-C2 = ΔΦ C2-C3 = ΔΦ C3-C4 ... = ΔΦ C(N-1)-CN ).

[0022] Fig. 3A is a time-series diagram 302 of an example frame 304 of example chirps 3061-306 N In the example from Fig. 3A presents the time-course diagram 302 frequency versus time. As in Fig. As illustrated in Figure 3A, a chirp is a signal where the signal's frequency varies linearly over time. In the example from Fig. 3A refers to frame 304 as a series of (e.g., N) chirps that are equidistant in time. Therefore, in some examples, frame 304 is referred to as an FMCW frame. In the example from Fig. 3A Frame 304 contains a linear increment (or decrement) of the phase of each chirp of Frame 304. Therefore, the phase change between successive chirps of Frame 304 is the same (e.g., ΔΦ). C1-C2 = ΔΦ C2-C3 = ΔΦ C3-C4 ... = ΔΦ C(N-1)-CN ). If frame 304 of the Chirps 3061-306 N When transmitted into an environment and reflected by an object, a received frame can be processed according to a two-dimensional FFT and represented as a Doppler distance representation.

[0023] Returning to Fig. 2. Transmitters 2041-204 N Frames from Chirps simultaneously, with each of the transmitters 2041-204 NA phase change (Φ) is mediated across the chirps of the frame, as described previously. In the example from Fig. 2 is each of the LNAs 2201-220 M implemented through an analog and / or digital circuit arrangement. In the example from Fig. 2 are the LNAs 2201-220 M with the mixers 2221-222 M and the receiving antennas 2081-208 M coupled. Furthermore, each of the mixers 2221-222 is M implemented through an analog and / or digital circuit arrangement. In the example from Fig. 2 are the mixers 2221-222 M with the Chirp synthesis circuit 202, the LNAs 220 i -220 M and the ADCs 2241-224 M coupled.

[0024] In the illustrated example from Fig. 2 is each of the ADCs 2241-224 M implemented through an analog and / or digital circuit arrangement. In the example from Fig. 2 are the ADCs 2241-224M with the mixers 2221-222 M and coupled to the interface circuit arrangement 212. Furthermore, the interface circuit arrangement 212 is implemented by an analog and / or digital circuit arrangement. For example, the interface circuit arrangement 212 is implemented according to a communication technology, such as a serial interface (e.g., SPI, LVDS interface, etc.), a parallel interface, etc., and is structured to enable communication according to the communication technology. In the example from Fig. 2 is the interface circuit arrangement 212 with the ADCs 2241-224 M and coupled to the processor circuit 214.

[0025] In the illustrated example from Fig. In 2, the processor circuit 214 is coupled to the interface circuit arrangement 212. In some examples, the processor circuit 214 is coupled to the chirp synthesis circuit 202. In the example from Fig. 2. The processor circuit 214 is implemented by an analog and / or digital circuit arrangement. For example, the processor circuit 214 can be implemented by a DSP, a microcontroller, an FFT engine, a combined DSP and microcontroller processor, an FPGA, or an application-specific integrated circuit (ASIC).

[0026] In the illustrated example from Fig. 2. The processor circuit 214 can be instantiated by a programmable circuit arrangement (e.g., at least one programmable circuit), such as a central processing unit (CPU) executing initial instructions, an FPGA, a programmable logic device (PLD), a generic array logic (GAL) device, a programmable array logic (PAL) device, a complex programmable logic device (CPLD), a simple programmable logic device (SPLD), a microcontroller unit (MCU), a programmable system-on-a-chip (PSoC), etc. (where, for example, an instance of this is created, launched for an arbitrary duration, materialized, implemented, etc.). Additionally or alternatively, the processor circuit 214 can be composed of Fig. 2. The processor circuitry 214 may be instantiated by (i) an ASIC or (ii) an FPGA that is structured or configured to perform operations corresponding to the first instructions in response to the execution of the second instructions (e.g., creating, launching, materializing, implementing, etc., an instance of this). Accordingly, part or all of the processor circuitry 214 may be instantiated at the same time or at different times. For example, part or all of the processor circuitry 214 may be instantiated in one or more threads that are executed concurrently on hardware or sequentially on hardware.Furthermore, in some examples, part or all of the processor circuitry 214 can be implemented by a microprocessor circuit arrangement that executes instructions or an FPGA circuit arrangement that performs operations to implement one or more virtual machines or containers.

[0027] In the illustrated example from Fig. 2 Each of the receiving antennas 2081-208 receives M Signals received from an environment within the field of view of the radar transceiver IC 200. For example, each of the receiving antennas 2081-208 receives M Frames of chirps reflected from the environment. Because the frames of chirps are reflected from the environment, there is a time delay or phase shift between the transmitted frame of chirps and the reflected frame of chirps. In the example from Fig. 2 each of the LNAs 2201-220 MThe received frames reflect chirps and forwards the amplified received frames to mixers 2221-222. M further. In the example from Fig. 2 each of the mixers 2221-222 M The amplified received frames are combined with the chirp frame provided by the chirp synthesis circuit 202 to produce received IF frames of reflected chirps. Additionally, each of the ADCs 2241-224 samples M The received IF frames of reflected chirps are processed to generate digital samples of the analog signals.

[0028] In the illustrated example from Fig. 2 The interface circuit arrangement 212 receives digital samples from the ADCs 2241-224 M and forwards the digital samples to processor circuit 214 for processing. In the example from Fig. 2. The radar transceiver IC 200 has an R MAX -specification, where R MAXrefers to the maximum range at which the radar transceiver IC 200 can detect a target. The radar transceiver IC 200 implements IF filtering to eliminate reflected signals with a delay greater than τ. MAX to filter out, where τ MAX twice R MAX divided by the speed of light (τMAX=2∗RMAXc) IF filtering ensures that the signal has a reduced or minimal bandwidth while still allowing signals from targets of interest to be detected, thus helping to minimize the ADC sampling rate. IF filtering also helps to minimize interference from other radars.

[0029] In some examples, the radar transceiver IC 200 includes a digital front-end (DFE) circuit arrangement between the ADCs 2241-224. Mand the interface circuit arrangement 212. For example, the DFE circuit arrangement receives IF signals from receivers 2101-210. M and performs, for example, decimation filtering or other processing operations on the digital IF signals to reduce the data transfer rate of the digital IF signals. Additionally or alternatively, the DFE circuitry performs other operations on the digital IF signals, such as DC offset removal or compensation (e.g., digital compensation) of non-idealities in receivers 2101-210. M , such as a non-ideality of an inter-receiver gain factor imbalance, a non-ideality of an inter-receiver phase imbalance, and the like.

[0030] In the illustrated example from Fig. 2 The processor circuit 214 receives digital samples, representing a frame of reflected chirps, from the interface circuit arrangement 212. In the example from Fig. In section 2, the processor circuit 214 is structured to perform at least part of the signal processing on the digital IF signals resulting from a received radar frame. In some examples, the processor circuit 214 is structured to transmit the results of the signal processing. For example, the processor circuit 214 transmits the results of the signal processing to a processing unit (e.g., the processor circuit 104).

[0031] In the illustrated example from Fig. 2. The processor circuit 214 includes functionality for performing a distance FFT on each received frame of reflected chirps. For example, the position of signal power peaks across the distance dimension of a distance FFT directly corresponds to the distance of a target from the radar transceiver IC 200. In the example from Fig. 2. The processor circuit 214 also includes functionality for performing a Doppler FFT on the results of distance FFTs. In some examples, the processor circuit 214 receives control information (e.g., chirp timing, power levels, triggering of monitoring functions, etc.) via an SPI bus. For example, based on the control information, the processor circuit 214 provides data parameters or supplies control signals to the chirp synthesis circuit 202.

[0032] Fig. Figure 3B is a diagram of an exemplary processing flow 308 for generating an exemplary Doppler distance representation 310 of a received frame of reflected chirps. For example, the processing flow 308 for generating a Doppler distance representation 310 (sometimes called a Doppler distance heatmap) involves the processor circuit 214 processing digital samples representing a received frame of reflected chirps to generate an exemplary matrix 312 of distance FFTs. In the example from Fig. 3B corresponds to rows of matrix 312 of distance FFTs of the respective chirps in the received frame of reflected chirps and to columns of matrix 312 of the distance dimension of the distance FFTs. In this way, targets detected in the received frame of reflected chirps are separated according to distance.

[0033] In the illustrated example from Fig. 3B, the processor circuit 214 generates the Doppler distance representation 310 by processing the distance FFT representation of the received frame of reflected chirps (e.g., matrix 312) over the distance dimension (e.g., columns of matrix 312). For example, the processor circuit 214 performs an FFT (e.g., a Doppler FFT) over the distance dimension of the distance FFT representation. In this way, targets detected in the received frame of reflected chirps are separated by velocity. Accordingly, the Doppler distance representation 310 of the received frame of reflected chirps resolves targets in both the distance and Doppler (e.g., velocity) dimensions.

[0034] In the illustrated example from Fig. 3B is the Doppler distance representation 310 a three-dimensional graph that represents a distance in meters (m) against a velocity in meters per second (m / s), where signals in the two-dimensional distance-velocity field have an associated amount that provides a third dimension. Signal peaks in the Doppler range representation 310 correspond to targets in a field of view of the radar transceiver IC 200. For example, the Doppler range representation 310 includes a first exemplary representation 314 of a first object in a field of view of the radar transceiver IC 200 and a second exemplary representation 316 of a second object in a field of view of the radar transceiver IC 200. For simplicity, the Doppler range representation 310 corresponds to an implementation of the radar transceiver IC 200 with a single transmitter (e.g., the first indexed transmitter 2041) without DDMA modulation.For example, the Doppler distance representation 310 represents the first representation 314 of a first object and the second representation 316 of the second object. In the case of DDMA modulation, the Doppler distance representation 310 would contain N instances of the first object and the second object with Doppler offsets corresponding to the mediated phase shifts at transmitters 2041-204. N are equivalent to.

[0035] Fig. Figure 4A is a time-history diagram 402 of an interference that can occur in radar applications. The time-history diagram 402 represents interference during the detection of an exemplary chirp 404. In the example from Fig. Figure 4A shows the time-course diagram 402, frequency versus time. As in Fig. As illustrated in Figure 4A, the Chirp 404 is a signal where the signal frequency varies linearly with time. In the example from Fig. 4A represents an exemplary delay window 406 (e.g., by τ). MAX (represented) around the Chirp 404 are signals that are in the same band as the Chirp 404. For example, the delay window 406 corresponds to a difference of a few tens of megahertz (MHz) in frequency relative to the frequency of the Chirp 404 at a given time.

[0036] Based on a downconversion and low-pass filtering (e.g., performed by the radar transceiver IC 200), only parts of a signal within the delay window 406 are in the same band as the chirp 404. Therefore, only parts of chirps that overlap with the delay window 406 are in the same band as the chirp 404. In the example from Fig. 4A Interference always occurs when an exemplary crossing chirp 408 is in a band with the chirp 404 (e.g., intersects the delay window 406). Fig. 4B is a graphical illustration of 410 digital samples, which correspond to the time-series diagram 402 from Fig. 4A corresponds. In the example from Fig. 4B Example digital samples 412, corresponding to the part of the chirp 404 that overlaps with the crossing chirp 408, become faulty. If the signal power of the crossing chirp 408 is greater than the signal power of the chirp 404 (e.g., a few tens of decibels (dB) greater than that of the chirp 404), then the degree to which the digital samples 412 become faulty increases.

[0037] In radar applications (e.g., automotive applications), interference from other radars can severely impair performance. As radar penetration and the level of automation increase, the degree to which interference between radars impairs performance will also increase. To enable the coexistence of multiple radars, radar interference must be attenuated. Many studies have been conducted to explore interference attenuation techniques. These include the IMIKO project, carried out by the Cooperation in Radar for Autonomous Electric Cars; the MOre Safety for All by Radar Interference Mitigation (MOSARIM) project, conducted in the European Union; and radar interference studies conducted by the National Highway Traffic Safety Administration (NHTSA) in the United States.

[0038] In general, interference mitigation techniques involve detection and reconstruction. Detection involves identifying digital samples that are corrupted by interference. Many detection techniques are possible. One example is calculating the average value of the digital samples in a chirp and identifying samples that exceed the average value by more than a threshold as corrupted samples. Reconstruction involves reconstructing corrupted digital samples. Reconstruction can reduce interference-induced artifacts in Doppler distance representations (e.g., heatmaps). A reconstruction technique involves setting corrupted digital samples in a chirp to zero, performing a distance FFT on the digital samples, including the samples with zero values, and identifying a peak value in the distance FFT.The distance FFT is a matrix of complex numbers. Therefore, the peak value in the distance FFT corresponds to the maximum value of the absolute value of the distance FFT.

[0039] Based on the peak value, the reconstruction technique involves setting values ​​in the distance FFT that are outside a threshold of the peak value to zero and performing an inverse distance FFT to generate reconstructed digital samples. For example, the reconstruction technique involves setting values ​​in the distance FFT that are more than the threshold below the peak value to zero. After the reconstructed digital samples have been generated, the reconstruction technique involves replacing the erroneous digital samples with the reconstructed digital samples. The reconstruction technique described above can be used for all chirps in a frame of chirps to generate a frame of chirps including the reconstructed samples.After samples for all chirps of a frame have been reconstructed, a signal processor can perform a distance FFT on the frame of chirps including the reconstructed samples and a Doppler FFT on the distance FFT to generate a Doppler distance representation.

[0040] The reconstruction technique described above attenuates interference resulting from interfering chirps with a significantly different slope than the monitored chirp (also known as a sweeping noise generator). However, different types of noise generators are possible. For example, the reconstruction technique described above does not attenuate interference resulting from interfering chirps with a similar slope to the monitored chirp (also known as a parallel noise generator). In the examples described here, the processor circuit 214 reduces interference artifacts in Doppler distance representations caused by both sweeping noise generators and parallel noise generators.For example, the processor circuit 214 reconstructs chirps along the distance dimension and along the Doppler dimension to generate a hybrid Doppler distance representation, which improves the overall performance of the radar transceiver IC 200.

[0041] Returning to the illustrated example from Fig. 2. Processor circuit 214 generates two Doppler distance representations of a received frame of chirps and computes an element-wise minimum between the two Doppler distance representations to produce a resulting Doppler distance representation of the received frame of chirps that attenuates interference along the distance dimension and the Doppler dimension. For example, processor circuit 214 generates a first Doppler distance representation of a frame of chirps that attenuates interference along the distance dimension and generates a second Doppler distance representation of the frame of chirps that attenuates interference along the Doppler dimension. Fig. Figure 5 is a diagram of an exemplary processing flow 500 for generating an initial exemplary Doppler distance representation 502 of a received frame of reflected chirps to attenuate interference along a distance dimension.

[0042] In the illustrated example from Fig. Section 5 includes a first exemplary process 504 in which the processor circuit 214 reconstructs faulty digital samples based on a distance FFT, setting values ​​outside a threshold of a peak value to zero. For example, the first process 504 includes the processor circuit 214 setting exemplary faulty ADC samples 506 of chirps in an exemplary matrix 508 of chirp ADC samples to zero. For example, the faulty ADC samples 506 are ADC samples of matrix 508 that have been identified as being affected by interference (e.g., by a detection technique). In the example from Fig. 5 correspond to rows of the matrix 508, each chirp reflected in the received frame, and to columns of the matrix 508 ADC samples over time.

[0043] In the illustrated example from Fig. In section 5, the first process 504 involves the processor circuit 214 performing a distance FFT on matrix 508 (with the ADC samples having a value of zero), identifying a peak value in the distance FFT representation of matrix 508. In the example from Fig. 5 is the distance FFT representation of matrix 508, a matrix of complex numbers. Therefore, the first process 504 involves the processor circuit 214 converting the distance FFT representation of matrix 508 (e.g., by calculating the absolute value) into a matrix of real positive numbers for the purpose of identifying the peak value. In the example from Fig. 5. The first process 504 also includes the processor circuit 214 setting to zero any values ​​of the distance FFT representation of matrix 508 that do not meet a threshold of the peak value (e.g., more than one threshold below, more than one threshold above, etc. of it).

[0044] For example, the first process 504 involves the processor circuit 214 setting to zero any values ​​of the distance FFT representation of matrix 508 that are more than the threshold below the peak value (e.g., do not meet it). In the example from Fig. 5 is the threshold 3 dB. The first process 504 also involves the processor circuit 214 performing an inverse distance FFT on the distance FFT representation of matrix 508 (with the values ​​set to zero) to generate exemplary reconstructed ADC samples 510 for the faulty ADC samples 506. In the example from Fig. The first process 504 includes the processor circuit 214 replacing the faulty ADC samples 506 in the matrix 508 with the reconstructed ADC samples 510.

[0045] In the illustrated example from Fig. Section 5 includes a second exemplary process 512, in which the processor circuit 214 performs a distance FFT on the matrix 508 (with the reconstructed ADC samples 510). In the example from Fig. The second process, 512, involves performing a Doppler FFT on the distance FFT representation of matrix 508 (using the reconstructed ADC samples 510) to generate the first Doppler distance representation 502. The first Doppler distance representation 502 is a three-dimensional graph representing distance in meters versus velocity in meters per second, where signals in the two-dimensional distance-velocity field have an associated magnitude that provides a third dimension. In general, the first Doppler distance representation 502 is a matrix of complex numbers. Therefore, the processor circuit arrangement 214 can determine an absolute value of the first Doppler distance representation 502 to convert it into a magnitude before subsequent processing.

[0046] In the illustrated example from Fig. Figure 5 contains the first Doppler distance representation 502, a first exemplary representation 514 of a first object in a field of view of the radar transceiver IC 200, and a second exemplary representation 516 of a second object in a field of view of the radar transceiver IC 200. For simplicity, the Doppler distance representation 502 corresponds to an implementation of the radar transceiver IC 200 with a single transmitter (e.g., the first indexed transmitter 2041) without DDMA modulation. For example, the Doppler distance representation 502 represents the first representation 514 of the first object and the second representation 516 of the second object. In the case of DDMA modulation, the Doppler distance representation 502 would contain N instances of the first object and the second object with Doppler offsets corresponding to the mediated phase shifts of transmitters 2041-204. N are equivalent to.

[0047] Furthermore, the processing flow 500 corresponds to operations performed by the processor circuit 214 to generate the first Doppler distance representation 502 for a frame of reflected chirps received at a single receiver (e.g., the first indexed receiver 2101). In reality, the processor circuit 214 performs the processing flow 500 for frames of reflected chirps received at each of the receivers 2101-210. M of the radar transceiver IC 200, where the M Doppler distance representations contain M instances of the first object and the second object. In such examples, the processor circuit 214 sums the first Doppler distance representations 502 for each of the receivers 2101-210 M , to generate a composite first Doppler distance representation.

[0048] Returning to the illustrated example from Fig. 2. Processor circuit 214 generates a second Doppler distance representation of the frame of chirps, which attenuates interference along the Doppler dimension. For example, Fig. 6 A diagram of an exemplary processing flow 600 for generating a second exemplary Doppler distance representation 602 of the received frame of reflected chirps in order to attenuate interference along one Doppler dimension. In the example from Fig. Section 6 includes a first example process 604 in which the processor circuit 214 sets chirps of matrix 508, which contain the faulty ADC samples 506, to example chirps 606 with a value of zero. For example, the processor circuit 214 sets values ​​of the rows of matrix 508, which contain the faulty ADC samples 506, to zero in order to generate the chirps 606 with a value of zero.

[0049] In the illustrated example from Fig. In section 6, the first process 604 involves the processor circuit 214 performing a distance FFT on matrix 508 (with chirps 606 having zero values) to generate an exemplary distance FFT representation 608 of matrix 508. For example, the processor circuit 214 performs a distance FFT on the non-zero chirps (e.g., the non-zero rows) of matrix 508 to generate the distance FFT representation 608. In the example from Fig. Section 6 includes a second exemplary process 610 in which the processor circuit 214 performs a Doppler FFT for each column of the distance FFT representation 608 and identifies a peak value in the Doppler FFT representation of each column of the distance FFT representation 608. For example, the distance FFT representation 608 and the Doppler FFT representation of each column thereof are matrices of complex numbers. Therefore, the second process 610 includes the processor circuit 214 converting the distance FFT representation 608 and / or the Doppler FFT representation of each column thereof (e.g., by taking the absolute value) into at least one matrix of real positive numbers for the purpose of identifying the peak value.

[0050] In the illustrated example from Fig. In the second process 610, the processor circuit 214 sets to zero any Doppler FFT values ​​of each column of the distance FFT representation 608 that do not meet a threshold of the peak value (e.g., are more than one threshold below, more than one threshold above, etc.). For example, the second process 610 involves the processor circuit 214 setting to zero any Doppler FFT values ​​of each column of the distance FFT representation 608 that are more than one threshold below the peak value (e.g., do not meet it). In the example from Fig. 6 is the threshold 3 dB. The second process 610 also involves the processor circuit 214 performing an inverse Doppler FFT on the Doppler FFT representation of each column of the distance FFT representation 608 to generate exemplary reconstructed chirps 612 for the chirps of matrix 508, which include the faulty ADC samples 506. In the example from Fig. The second process 610 includes the processor circuit 214 replacing the chirps 606 with zero value of the distance FFT representation 608 of the matrix 508 with reconstructed chirps 612.

[0051] In the illustrated example from Fig. Figure 6 includes a third exemplary process 614 in which the processor circuit 214 performs a Doppler FFT on the distance FFT representation 608 (using the reconstructed chirps 612) to generate the second Doppler distance representation 602. The second Doppler distance representation 602 is a three-dimensional graph representing a distance in meters versus a velocity in meters per second, where signals in the two-dimensional distance-velocity field have an associated magnitude that provides a third dimension. In general, the second Doppler distance representation 602 is a matrix of complex numbers. Therefore, the processor circuit arrangement 214 can determine an absolute value of the second Doppler distance representation 602 to convert it into a magnitude before subsequent processing.

[0052] In the illustrated example from Fig. Figure 6 includes the second Doppler distance representation 602, a first exemplary representation 616 of a first object in a field of view of the radar transceiver IC 200, and a second exemplary representation 618 of a second object in a field of view of the radar transceiver IC 200. For simplicity, the Doppler distance representation 602 corresponds to an implementation of the radar transceiver IC 200 with a single transmitter (e.g., the first indexed transmitter 2041) without DDMA modulation. For example, the Doppler distance representation 602 represents the first representation 616 of the first object and the second representation 618 of the second object. In the case of DDMA modulation, the Doppler distance representation 602 would include N instances of the first object and the second object with Doppler offsets corresponding to the mediated phase shifts of transmitters 2041-204. N are equivalent to.

[0053] Furthermore, the processing flow 600 corresponds to operations performed by the processor circuit 214 to generate the second Doppler distance representation 602 for a frame of reflected chirps received at a single receiver (e.g., the first indexed receiver 2101). In reality, the processor circuit 214 performs the processing flow 600 for frames of reflected chirps received at each of the receivers 2101-210. M of the radar transceiver IC 200, where the M Doppler distance representations contain M instances of the first object and the second object. In such examples, the processor circuit 214 sums the second Doppler distance representations 602 for each of the receivers 2101-210 M , to generate a composite second Doppler distance representation.

[0054] Returning to the illustrated example from Fig. 2. The processor circuit 214 generates a third Doppler distance representation as an element-wise minimum between a first Doppler distance representation of a frame of chirps, which attenuates interference along the distance dimension (e.g., the first Doppler distance representation 502), and a second Doppler distance representation of the frame of chirps, which attenuates interference along the Doppler dimension (e.g., the second Doppler distance representation 602). For example, Fig. 7 A diagram of an exemplary processing flow 700 for generating a third exemplary Doppler distance representation 702 of the received frame of reflected chirps in order to attenuate interference along the distance dimension and the Doppler dimension. In the example from Fig. 7 the processor circuit 214 generates the third Doppler distance representation 702 by calculating an element-wise minimum between a first exemplary Doppler distance representation 704 and a second exemplary Doppler distance representation 706.

[0055] In the illustrated example from Fig. 7 becomes the first Doppler distance representation 704 according to processing flow 500 from Fig. 5 is generated. For example, the first Doppler distance representation 704 corresponds to the first Doppler distance representation 502 from Fig. 5. In the example from Fig. 7 becomes the second Doppler distance representation 706 according to the processing flow 600 from Fig. 6 is generated. For example, the second Doppler distance representation 706 corresponds to the second Doppler distance representation 602 from Fig. 6. As in Fig. Figure 7 illustrates that the first Doppler distance representation 704 includes first exemplary interference artifacts 708 across distance bins and the second Doppler distance representation 706 includes second exemplary interference artifacts 710 across Doppler bins.

[0056] By calculating the third Doppler distance representation 702 as an element-wise minimum between the first Doppler distance representation 704 and the second Doppler distance representation 706, the processor circuit 214 reduces the first interference artifacts 708 and the second interference artifacts 710. For example, the element-wise minimum between the first Doppler distance representation 704 and the second Doppler distance representation 706 does not preserve the first interference artifacts 708 or the second interference artifacts 710. Therefore, based on the third Doppler distance representation 702, the processor circuit 214 can better detect a first exemplary representation 712 of a first object, a second exemplary representation 714 of a second object, and a third exemplary representation 716 of a third object.Accordingly, the third Doppler distance representation 702, produced by the processor circuit 214, is a better approximation of an exemplary ideal Doppler distance representation 718 of the received frame of reflected chirps than the first Doppler distance representation 704 or the second Doppler distance representation 706.

[0057] As previously described, Doppler Distance Representation 502 and Doppler Distance Representation 602 correspond to implementations of the radar transceiver IC 200 with a single transmitter (e.g., the first indexed transmitter 2041) without DDMA modulation. In the case of DDMA modulation, Doppler Distance Representation 502 and Doppler Distance Representation 602 would contain N instances of the first object, the second object, and the third object with Doppler offsets corresponding to the mediated phase shifts of transmitters 2041–204. Ncorresponding. In addition, the processor circuit 214 actually performs processing flow 500 and processing flow 600 for frames of reflected chirps received at the radar transceiver IC 200. In reality, the processor circuit 214 sums the first Doppler range representations 502 for each of the receivers 2101-210. M , to generate a composite first Doppler distance representation. In addition, the processor circuit 214 actually sums the second Doppler distance representations 602 for each of the receivers 2101-210. M, to generate a composite second Doppler distance representation. In reality, when processing flow 700 is performed, processor circuit 214 generates the third Doppler distance representation 702 as an element-wise minimum between the composite first Doppler distance representation and the composite second Doppler distance representation.

[0058] Returning to the illustrated example from Fig. 2. By generating the first Doppler distance representation 502 and the second Doppler distance representation 602, as described previously, the processor circuit 214 improves the dynamic range for distance bins and the dynamic range for Doppler bins of the Doppler distance representations. For example, by generating the first Doppler distance representation 502, as described previously, the processor circuit 214 improves the dynamic range for individual distance bins of the first Doppler distance representation 502. Furthermore, by generating the second Doppler distance representation 602, as described previously, the processor circuit 214 improves the dynamic range for individual Doppler bins of the second Doppler distance representation 602. Therefore, by generating the third Doppler distance representation 702, as described previously (e.g.,Performing a reconstruction along the distance dimension and the Doppler dimension), an overall performance of the radar transceiver IC 200.

[0059] In the illustrated example from Fig. 2. The processor circuit 214 also or alternatively performs a process for reconstructing faulty ADC samples along the distance dimension and along the Doppler dimension. For example, Fig. Figure 8 shows a diagram of an exemplary processing flow for reconstructing faulty ADC samples along the distance dimension and the Doppler dimension. In the example from Fig. Figure 8 contains an example matrix 802 of chirp ADC samples and example samples 804 with a value of zero, which correspond to faulty ADC samples. For example, the faulty ADC samples are ADC samples from matrix 802 that have been identified as being caused by interference (e.g., by a detection technique).

[0060] In the illustrated example from Fig. 8 rows of matrix 802 correspond to the respective chirps reflected in the received frame, and 8 columns of matrix 802 correspond to ADC samples over time. In the example from Fig. Section 8 includes a first exemplary process 806 in which the processor circuit 214 performs a two-dimensional FFT on the matrix 802. For example, the processor circuit 214 performs a distance FFT along rows of the matrix 802 and performs a Doppler FFT along columns of the distance FFT representation of the matrix 802.

[0061] In the illustrated example from Fig. The two-dimensional FFT representation of matrix 802 is a complex matrix. Therefore, processor circuit 214 converts the two-dimensional FFT representation of matrix 802 into a real positive matrix to generate an example Doppler distance representation 808. For example, processor circuit 214 temporarily converts the two-dimensional FFT representation of matrix 802 into a real positive matrix for the purpose of determining a peak value of the Doppler distance representation 808, as described below. For example, processor circuit 214 converts the two-dimensional FFT representation of matrix 802 into a real positive matrix by taking the absolute value of the two-dimensional FFT representation of matrix 802.In some examples, the processor circuit 214 converts the two-dimensional FFT representation of matrix 802 into a real positive matrix by taking the logarithm of the absolute value of the two-dimensional FFT representation of matrix 802.

[0062] In the illustrated example from Fig. In step 8, the processor circuit 214 generates the Doppler distance representation 808 of the matrix 802 based on the first process 806. In the example from Fig. Section 8 includes a second exemplary process 810 in which the processor circuit 214 identifies an exemplary peak value 812 in the Doppler distance representation 808 (after conversion to a real positive matrix). Furthermore, the second process 810 includes the processor circuit 214 setting to zero values ​​of the Doppler distance representation 808 that do not meet a threshold of the peak value 812 (e.g., are more than one threshold below, more than one threshold above, etc.). For example, the second process 810 includes the processor circuit 214 setting to zero values ​​of the Doppler distance representation 808 that are more than one threshold below the peak value 812 (e.g., do not meet it). In the example from Fig. 8 is the threshold 6 dB.

[0063] In the illustrated example from Fig. In step 8, the processor circuit 214 generates an exemplary Doppler distance representation 814 with a value of zero, based on the second process 810. For example, the Doppler distance representation 814 with a value of zero includes the peak value 812, exemplary satisfying values ​​816 that meet the threshold, and exemplary values ​​818 of zero that correspond to values ​​of the Doppler distance representation 808 that do not meet the threshold. In the example from Fig. 8 includes a third exemplary process 820, in which the processor circuit 214 performs an inverse two-dimensional FFT on the Doppler distance representation 814 with a value of zero.

[0064] For example, the processor circuit 214 performs an inverse Doppler FFT along columns of the Doppler distance representation 814 with zero values ​​and an inverse distance FFT along rows of the Doppler distance representation 814 with zero values ​​to generate an exemplary matrix 822 of reconstructed chirp ADC samples. In the example from Fig. Matrix 8 contains 822 reconstructed ADC samples 824, which correspond to samples 804 with a value of zero in matrix 802. In the example from Fig. Section 8 includes a fourth exemplary process 826, in which the processor circuit 214 replaces the samples 804 with a value of zero in the matrix 802 with reconstructed ADC samples 824. In this way, faulty ADC samples in the matrix 802 are replaced by the reconstructed ADC samples 824.

[0065] In the illustrated example from Fig. 8. Processor circuit 214 can perform a two-dimensional FFT on the matrix output by processing flow 800. For example, processor circuit 214 performs a distance FFT on matrix 802 (using the reconstructed ADC samples 824) and a Doppler FFT on the distance FFT representation of matrix 802 to generate a Doppler distance representation of the frame of reflected chirps. As in Fig. Figure 8 illustrates that the processing flow reconstructs 800 faulty ADC samples along the distance dimension and the Doppler dimension.

[0066] Fig. Figure 9 is a flowchart representing exemplary machine-readable instructions or exemplary operations 900, which are implemented using an exemplary programmable circuit arrangement implementation of the radar transceiver IC 210. Fig. 2 can be executed, instantiated, and / or performed to determine a Doppler distance representation for attenuating interference along the distance dimension and the Doppler dimension. The exemplary machine-readable instructions and / or the exemplary operations 900 from Fig. 9 begin at block 902, where at least one of the transmitters 2041-204 N transmits a frame of chirps into an environment. For example, the first indexed transmitter, 2041, transmits a frame of chirps into the environment. In some examples, any number of transmitters, 2041-204, transmits. N a frame of Chirps into the environment.

[0067] In the illustrated example from Fig. At least one of receivers 2101-210 receives signal 9 at block 904. Ma frame of reflected chirps from the environment. For example, the first indexed receiver 2101 receives a frame of reflected chirps from the environment. In some examples, any number of receivers 2101-210 receive a frame. M a frame of reflected chirps from the environment. In the example from Fig. At block 906, interface circuit arrangement 212 receives digital samples representing the frame of reflected chirps. For example, interface circuit arrangement 212 receives digital samples from the first indexed receiver 2101. In some examples, interface circuit arrangement 212 receives digital samples from any number of receivers 2101-210. M .

[0068] In the illustrated example from Fig. In block 908, processor circuit 214 determines a reconstructed sample for a faulty sample of a reflected chirp from the frame of reflected chirps based on the digital samples. For example, for the reflected chirp, processor circuit 214 sets the faulty sample to zero, determines a distance FT representation of the reflected chirp, and sets to zero any values ​​in the distance FT representation that do not meet a threshold of a peak value in the distance FT representation (e.g., are outside of it). For example, the distance FT representation is a distance FT representation of the reflected chirp. In the example from Fig. 9. The distance FT representation is a matrix of complex numbers. Therefore, the processor circuit 214 converts the distance FT representation (e.g., by calculating the absolute value) into a matrix of real positive numbers before determining the peak value. In the example from Fig. 9. Processor circuit 214 sets to zero values ​​in the distance FT representation with absolute values ​​that are more than the threshold below the peak value (e.g., do not meet it). Additionally, processor circuit 214 determines, for example, an inverse distance FT representation of the distance FT representation of the reflected chirp to generate the reconstructed sample.

[0069] Using the reconstructed sample, processor circuit 214 replaces the faulty sample in the reflected chirp with the reconstructed sample. In some examples, processor circuit 214 determines reconstructed samples for each faulty sample in the frame of reflected chirps at block 908. For example, processor circuit 214 determines reconstructed samples for each faulty sample in the frame of reflected chirps according to processing flow 500. Fig. 5. In the example from Fig. In block 910, processor circuit 214 determines a first Doppler distance representation of the frame of reflected chirps based on the digital samples, where the digital samples include the reflected chirp with the reconstructed sample. For example, processor circuit 214 determines a distance FT representation of the frame of reflected chirps based on the digital samples. Furthermore, processor circuit 214 determines a Doppler FT representation of the distance FT representation to determine the first Doppler distance representation. For example, the Doppler FT representation is a Doppler FT representation of the distance FT representation.

[0070] In the illustrated example from Fig. In section 9, processor circuit 214 at block 912 determines a reconstructed chirp for the reflected chirp, including the faulty sample, based on a distance-FT representation of the frame of reflected chirps, where the distance-FT representation is based on the digital samples. In some examples, processor circuit 214 at block 912 determines reconstructed chirps for each reflected chirp that includes a faulty sample. For example, according to processing flow 600, processor circuit 214 determines reconstructed chirps for each reflected chirp that includes a faulty sample. Fig. 6. Exemplary machine-readable instructions and / or exemplary operations for implementing Block 912 are provided in conjunction with Fig. 10 illustrated and described.

[0071] In the illustrated example from Fig. In section 9, processor circuit 214 at block 914 determines a second Doppler distance representation of the frame of reflected chirps based on the distance FT representation of the frame of reflected chirps. For example, processor circuit 214 performs a Doppler FT along the distance dimension (also called distance bins) of the distance FT representation of the frame of reflected chirps to determine the second Doppler distance representation. In the example from Fig. Block 9 contains the distance-FT representation of the reconstructed chirp. At block 916, processor circuit 214 determines a third Doppler distance representation as an element-wise minimum between the first and second Doppler distance representations. Therefore, the third Doppler distance representation contains comparatively fewer interference artifacts than the first or second Doppler distance representations. Consequently, subsequent processing based on the third Doppler distance representation will produce more accurate results.

[0072] Fig. 10 is a flowchart representing exemplary machine-readable instructions or exemplary operations 912, which are implemented using an exemplary programmable circuit arrangement implementation of the radar transceiver IC 200. Fig. 2 can be executed, instantiated, and / or performed to determine a reconstructed chirp for a reflected chirp, including a faulty sample. The exemplary machine-readable instructions and / or the exemplary operations 912 from Fig. The 10 examples begin at block 1002, where processor circuit 214 replaces the reflected chirp, including the faulty sample, with a chirp with a value of zero in the digital samples. In other words, the chirp with a value of zero replaces the reflected chirp, including the faulty sample, in the digital samples. In some examples, at block 1002, processor circuit 214 replaces every reflected chirp that contains a faulty sample with a chirp with a value of zero.

[0073] In the illustrated example from Fig. In section 10, processor circuit 214 at block 1004 determines a distance FT representation of the frame of reflected chirps based on the digital samples, where the digital samples include the chirp with value zero. As described here, the distance FT representation has a first dimension (e.g., a height specifying a number of rows) and a second dimension (e.g., a width specifying a number of columns). In the example from Fig. In block 1006, processor circuit 214 determines a Doppler FT representation for each indice across the second dimension of the distance FT representation. For example, processor circuit 214 determines a Doppler FT representation for each column of the distance FT representation.

[0074] In the illustrated example from Fig. The distance FT representation and the Doppler FT representation of each column thereof are matrices of complex numbers. Therefore, the processor circuit 214 converts the distance FT representation and / or the Doppler FT representation of each column thereof (e.g., by taking the absolute value) into at least one matrix of real positive numbers before the peak value is determined. In the example from Fig. In step 10, processor circuit 214 at block 1008 sets a value to zero for each Doppler FT representation that does not meet the threshold of a peak value in the respective Doppler FT representation. In the example from Fig. In step 10, processor circuit 214 sets to zero any value for the respective Doppler FT representations that lies below the threshold below the peak value in the respective Doppler FT representations (e.g., does not meet the threshold). In some examples, processor circuit 214 at block 1008 sets all values ​​that do not meet the threshold to zero.

[0075] In the illustrated example from Fig. At block 1010, processor circuit 214 determines an inverse Doppler FT representation for each Doppler FT representation to generate the reconstructed chirp. At block 1012, processor circuit 214 replaces the reflected chirp in the distance FT representation of the frame of reflected chirps with the reconstructed chirp. For example, processor circuit 214 replaces the reflected chirp containing the faulty sample with the reconstructed chirp. In other words, the reconstructed chirp replaces the reflected chirp, including the faulty sample, in the distance FT representation. In some examples, processor circuit 214 at block 1012 replaces all reflected chirps containing a faulty sample with reconstructed chirps.After block 1012, the exemplary machine-readable instructions and / or exemplary operations 912 return to the exemplary machine-readable instructions and / or exemplary operations 1000 at block 914.

[0076] Fig. Figure 11 is a flowchart representing exemplary machine-readable instructions or exemplary operations 1100, which are implemented using an exemplary programmable circuit arrangement implementation of the radar transceiver IC 200. Fig. 2 can be executed, instantiated, and / or performed to determine a Doppler distance representation for attenuating interference along the distance dimension and the Doppler dimension. The exemplary machine-readable instructions and / or the exemplary operations 1100 from Fig. 11 begin at block 1102, where at least one of the transmitters 2041-204 N(Transmitter circuit arrangement) transmits a frame of chirps into an environment. For example, the first indexed transmitter 2041 transmits a frame of chirps into the environment. In some examples, any number of transmitters 2041-204 transmits N a frame of Chirps into the environment.

[0077] In the illustrated example from Fig. At least one of receivers 2101-210 receives signal 11 at block 1104. M (Receiver circuit arrangement) a frame of reflected chirps from the environment. For example, a first exemplary indexed receiver 2101 receives a frame of reflected chirps from the environment. In some examples, any number of receivers 2101-210 receive M a frame of reflected chirps from the environment. In the example from Fig. At block 1106, interface circuit arrangement 212 receives digital samples representing the frame of reflected chirps. For example, interface circuit arrangement 212 receives digital samples from the first indexed receiver 2101. In some examples, interface circuit arrangement 212 receives digital samples from any number of receivers 2101-210. M In the example from Fig. In block 1108, processor circuit 214 sets a faulty sample of a reflected chirp from the frame of reflected chirps in the digital samples to zero. In some examples, processor circuit 214 sets all faulty samples in the frame of reflected chirps in the digital samples to zero.

[0078] In the illustrated example from Fig. In section 11, processor circuit 214 at block 1110 determines a distance-FT representation of the frame of reflected chirps based on the digital samples. In the example from Fig. In block 1112, processor circuit 214 determines a Doppler FT representation of the distance FT representation to generate a first Doppler distance representation of the frame of reflected chirps. At block 1114, processor circuit 214 determines a peak value of the first Doppler distance representation. In the example from Fig. 11 is the first Doppler distance representation of a matrix of complex numbers. Therefore, the processor circuit 214 converts the first Doppler distance representation (e.g., by calculating the absolute value) into a matrix of real positive numbers before determining the peak value.

[0079] In the illustrated example from Fig. In step 11, processor circuit 214 at block 1116 sets a value of the first Doppler distance representation with an absolute value that does not meet a peak value threshold to zero. In the example from Fig. In step 11, processor circuit 214 sets to zero any value in the first Doppler distance representation that lies below the threshold by more than the peak value in the first Doppler distance representation (e.g., does not meet the threshold). In some examples, processor circuit 214 sets to zero all values ​​in the first Doppler distance representation that do not meet the threshold.

[0080] In the illustrated example from Fig. In block 1118, processor circuit 214 computes an inverse Doppler FT of the first Doppler distance representation to generate the distance FT representation. In block 1120, processor circuit 214 computes an inverse distance FT of the distance FT representation to generate a reconstructed sample for the erroneous sample. In some examples, processor circuit 214 computes an inverse Doppler FT and an inverse distance FT to generate reconstructed samples for all erroneous samples of the frame of reflected chirps. In block 1122, processor circuit 214 replaces the erroneous sample with the reconstructed sample in the digital samples. In other words, the reconstructed sample replaces the erroneous chirp sample in the digital samples. In some examples, processor circuit 214 replaces all erroneous samples with a reconstructed sample.

[0081] In the illustrated example from Fig. In block 1124, processor circuit 214 determines a second Doppler distance representation of the frame of reflected chirps based on the digital samples, where the digital samples include the reflected chirp with the reconstructed sample. For example, processor circuit 214 determines a distance FT representation of the frame of reflected chirps based on the digital samples. Furthermore, processor circuit 214 determines, for example, a Doppler FT representation of the distance FT representation to generate the second Doppler distance representation of the frame of reflected chirps.

[0082] Fig. Figure 12 is a block diagram of an exemplary programmable circuit arrangement platform 1200, which is used to execute and / or instantiate one or more of the exemplary machine-readable instructions or exemplary operations from Fig. 9, Fig. 10 and Fig. 11 is structured to accommodate the radar transceiver IC 200 from Fig. 2 to implement. The Programmable Circuit Assembly Platform 1200 can be, for example, a server, a PC, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a mobile phone, a smartphone, a tablet such as an iPad™), a personal digital assistant (PDA), an internet device, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a game console, a personal video recorder, a set-top box, a headset (e.g., an augmented reality (AR) headset, a virtual reality (VR) headset, etc.), or any other wearable device, or any other type of computing device or electronic device.

[0083] The programmable circuit assembly platform 1200 of the illustrated example includes a programmable circuit assembly 1212. The programmable circuit assembly 1212 of the illustrated example is hardware. For example, the programmable circuit assembly 1212 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, or microcontrollers from any desired family or manufacturer. The programmable circuit assembly 1212 can be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuit assembly 1212 implements the exemplary chirp synthesis circuit 202 and the exemplary processor circuit 214.

[0084] The programmable circuit arrangement 1212 of the illustrated example includes a local memory 1213 (e.g., a cache, registers, etc.). The programmable circuit arrangement 1212 of the illustrated example communicates via a bus 1218 with a main memory 1214, 1216, which includes volatile memory 1214 and non-volatile memory 1216. The volatile memory 1214 can be implemented by one or more synchronous SDRAM, dynamic DRAM, RAMBUS® dynamic RDRAM, or any other type of RAM device. The non-volatile memory 1216 can be implemented by one or a combination of flash memory or any other desired type of memory device. Access to the main memory 1214, 1216 of the illustrated example is controlled by a memory controller 1217.In some examples, the memory control 1217 can be implemented by one or more integrated circuits, logic circuits, microcontrollers of any desired family or manufacturer, or any other type of circuit arrangement to manage the flow of data to and from the main memory 1214, 1216.

[0085] The programmable circuit arrangement platform 1200 of the illustrated example also includes an interface circuit arrangement 1220. The interface circuit arrangement 1220 can be implemented by hardware according to any type of interface standard, such as an Ethernet interface, a Universal Serial Bus (USB) interface, a Bluetoothe interface, a Near Field Communication (NFC) interface, a Peripheral Component Interconnect (PCI) interface, or a Peripheral Component Interconnect Express (PCIe) interface.

[0086] In the illustrated example, one or more input devices 1222 are connected to the interface circuit arrangement 1220. The input device(s) 1222 allow a user (e.g., a human user, a machine user, etc.) to input one or a combination of data or commands into the programmable circuit arrangement 1212. The input device(s) 1222 can be implemented by, for example, one or a combination of an audio sensor, a microphone, a (photo or video) camera, a keyboard, a button, a mouse, a touchscreen, a trackpad, a trackball, an isopoint device, or a speech recognition system.

[0087] One or more output devices 1224 are also connected to the interface circuit arrangement 1220 of the illustrated example. The output device(s) 1224 can be implemented, for example, by one or a combination of display devices (e.g., a light-emitting diode (LED), an organic light-emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switching (IPS) display, a touchscreen, etc.), a tactile output device, a printer, or a loudspeaker. Accordingly, the interface circuit arrangement 1220 of the illustrated example includes one or a combination of a graphics driver card, a graphics driver chip, or a graphics processing unit (GPU) circuit arrangement.

[0088] The interface circuit arrangement 1220 of the illustrated example also includes a communication device, such as one or a combination of a transmitter, a receiver, a transceiver, a modem, a residential gateway, a wireless access point, or a network interface, to enable the exchange of data with external machines (e.g., computing devices of any type) through a network 1226. Communication can be effected by, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a beyond-line-of-sight (BLS) wireless system, a line-of-sight (LLS) wireless system, a mobile phone system, an optical link, etc. In this example, the interface circuit arrangement 1220 implements the exemplary transmitters 2041-204. N , the exemplary transmitting antennas 2061-206 N, the exemplary receiving antennas 2081-208 M , the exemplary recipients 2101-210 M and the exemplary interface circuit arrangement 212.

[0089] The programmable circuit arrangement platform 1200 of the illustrated example also includes one or more mass storage disks or devices 1228 for storing firmware, software, and / or data. Examples of such mass storage disks or devices 1228 include one or more magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray discs, CDs, DVDs, etc.), RAID systems, or solid-state storage disks or devices, such as flash memory devices and SSDs.

[0090] The machine-readable instructions 1232, which are derived from the machine-readable instructions from Fig. 9, Fig. 10 and Fig. 11 can be implemented, can be stored in one or a combination of the mass storage device 1228, the volatile memory 1214, the non-volatile memory 1216 or on at least one non-transient computer-readable storage medium, such as a CD or DVD, which may be removable.

[0091] Fig. Figure 13 is a block diagram of an exemplary implementation of the programmable circuit arrangement 1212 from Fig. 12. In this example, the programmable circuit arrangement 1212 is made from Fig. 12 is implemented by a microprocessor 1300. For example, the microprocessor 1300 can be a general-purpose microprocessor (e.g., a general-purpose microprocessor circuit arrangement). The microprocessor 1300 executes some or all of the machine-readable instructions in the flowcharts. Fig. 9, Fig. 10 and Fig. 11 for effectively instantiating the circuit arrangement from Fig. 2 as logic circuits for performing operations that correspond to these machine-readable instructions. In some such examples, the circuit arrangement consists of Fig. 2 instantiated by the hardware circuitry of the microprocessor 1300 in combination with the machine-readable instructions. For example, the microprocessor 1300 can be implemented by a multi-core hardware circuit arrangement, such as a CPU, DSP, GPU, XPU, etc. Although it can include any number of exemplary cores 1302 (e.g., 1 core), the microprocessor 1300 in this example is a multi-core semiconductor device including N cores. The cores 1302 of the microprocessor 1300 can operate independently or can work together to execute machine-readable instructions. For example, machine code corresponding to a firmware program, an embedded software program, or a software program can be executed by one of the cores 1302 or by several of the cores 1302 simultaneously or at different times.In some examples, the machine code corresponding to the firmware program, the embedded software program, or the software program is divided into threads and executed in parallel by two or more of the 1302 cores. The software program may correspond to some or all of the machine-readable instructions or operations defined by the flowcharts from [reference to flowchart]. Fig. 9, Fig. 10 and Fig. 11 will be represented.

[0092] The 1302 cores can communicate via a first exemplary bus 1304. In some examples, the first bus 1304 can be implemented as a communication bus to initiate communication associated with one or more of the 1302 cores. For example, the first bus 1304 can be implemented as an I2C (Inter-Integrated Circuit) bus and / or an SPI (Serial Peripheral Interface) bus and / or a PCI bus and / or a PCIe bus. Additionally or alternatively, the first bus 1304 can be implemented as any other type of computational or electrical bus. The 1302 cores can receive data, instructions, or signals from one or more external devices through the exemplary interface circuit arrangement 1306. The 1302 cores can output data, instructions, and signals to the one or more external devices through the interface circuit arrangement 1306.Although the 1302 cores of this example include an exemplary local memory 1320 (e.g., a Level 1 (L1) cache, which can be partitioned into an L1 data cache and an L1 instruction cache), the 1300 microprocessor also includes an exemplary shared memory 1310 that the cores can share (e.g., a Level 2 (L2) cache) for high-speed access to data and instructions. Data and instructions can be transferred by one or a combination of writing to or reading from the shared memory 1310. The local memory 1320 of each of the 1302 cores and the shared memory 1310 can be part of a hierarchy of memory devices that includes multiple levels of cache memory and main memory (e.g., main memory 1214, 1216). Fig. 12) includes. Higher storage levels in the hierarchy have lower access times and smaller storage capacities than lower storage levels. Changes to the various levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherence policy.

[0093] Each Core 1302 can be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuit arrangement. Each Core 1302 includes a Control Unit Circuit Arrangement 1314, an Arithmetic and Logic (AL) Circuit Arrangement 1316 (sometimes called an ALU), multiple Registers 1318, Local Memory 1320, and a second example bus 1322. Other structures may be present. For example, each Core 1302 may include a Vector Unit Circuit Arrangement, a SIMD (Single Instruction Multiple Data) Circuit Arrangement, a Load / Store Unit (LSU) Circuit Arrangement, a Branch / Jump Unit Circuit Arrangement, a Floating Point Unit (FPU) Circuit Arrangement, etc. The control unit circuit arrangement 1314 includes semiconductor-based circuits structured for controlling (e.g., coordinating) data movements within the corresponding core 1302.The AL circuit arrangement 1316 comprises semiconductor-based circuits structured to perform one or more mathematical or logical operations on the data within the corresponding core 1302. In some examples, the AL circuit arrangement 1316 performs integer-based operations. In other examples, the AL circuit arrangement 1316 also performs floating-point operations. In further examples, the AL circuit arrangement 1316 may include a first AL circuit arrangement that performs integer-based operations and a second AL circuit arrangement that performs floating-point operations. In some examples, the AL circuit arrangement 1316 may be referred to as an arithmetic logic unit (ALU).

[0094] The 1318 registers are semiconductor-based structures for storing data and instructions, such as the results of one or more of the operations performed by the AL circuit arrangement 1316 of the corresponding 1302 core. The 1318 registers can include, for example, one or more vector registers, SIMD registers, general-purpose registers, flag registers, segment registers, machine-specific registers, instruction pointer registers, control registers, debug registers, memory management registers, machine check registers, etc. The 1318 registers can be arranged in a bank, as shown in Fig. Figure 13 shows this. Alternatively, the registers 1318 can be organized in any other arrangement, format, or structure, such as by being distributed across the entire core 1302 to reduce access time. The second bus 1322 can be implemented using an I2C bus, an SPI bus, a PCI bus, and / or a PCIe bus.

[0095] Each Core 1302, or more generally, the Microprocessor 1300, may include additional or alternative structures to those shown and described above. For example, it may include one or more clock circuits, one or more power supplies, one or more power supply gates, one or more cache home agents (CHAs), one or more converged / common mesh stops (CMSs), one or more shifters (e.g., barrel shifters), or another circuit arrangement. The Microprocessor 1300 is a semiconductor device manufactured to include many interconnected transistors for implementing the structures described above in one or more integrated circuits (ICs) contained within one or more packages.

[0096] The Microprocessor 1300 can include or work in conjunction with one or more accelerators (e.g., accelerator circuitry, hardware accelerators, etc.). In some examples, accelerators are implemented by a logic circuitry to perform certain tasks faster and more efficiently than is possible with a general-purpose processor. Examples of accelerators include ASICs and FPGAs, such as those described here. A GPU, DSP, or other programmable device can also be an accelerator. Accelerators can reside on the Microprocessor 1300, in the same chip package as the Microprocessor 1300, or in one or more packages separate from the Microprocessor 1300.

[0097] Fig. Figure 14 is a block diagram of another exemplary implementation of the programmable circuit arrangement 1212 from Fig. 12. In this example, the programmable circuit arrangement 1212 is implemented by an FPGA circuit arrangement 1400. For example, the FPGA circuit arrangement 1400 can be implemented by an FPGA. The FPGA circuit arrangement 1400 can be used, for example, to perform operations that could otherwise be performed by the exemplary microprocessor 1300. Fig. 13 corresponding machine-readable instructions are executed. However, once the FPGA 1400 circuit assembly is configured, it instantiates the operations or functions corresponding to the machine-readable instructions in hardware and can therefore often execute the operations / functions faster than would be possible with a general-purpose microprocessor running the corresponding software.

[0098] More precisely, unlike the previously described microprocessor 1300, it includes Fig. 13 (which is a multi-purpose device that can be programmed to execute some or all of the machine-readable instructions provided by one or more flowcharts from Fig. 9, Fig. 10 and Fig. 11 are represented, whose intermediate connections and logic circuit arrangement are fixed after manufacturing), the FPGA circuit arrangement 1400 of the example from Fig. 14 Intermediate connections and logic circuit arrangements that, after manufacturing, can be configured, structured, programmed, or interconnected in various ways, or a combination thereof, to, for example, implement some or all of the operations / functions corresponding to the machine-readable instructions provided by one or more flowcharts. Fig. 9, Fig. 10 and Fig. 11 are represented, to instantiate. In particular, the FPGA circuit arrangement 1400 can be viewed as an array of logic gates, interconnects, and switches. The switches can be programmed to change how the logic gates are interconnected by the interconnects, effectively forming one or more dedicated logic circuits (except and until the FPGA circuit arrangement 1400 is reprogrammed). The configured logic circuits allow the logic gates to interact in different ways to perform different operations on data received from the input circuit arrangement. These operations may correspond to some or all of the instructions (e.g., from the software and / or firmware) provided by the one or more flowcharts from Fig. 9, Fig. 10 and Fig. 11 are shown. Therefore, the FPGA circuit arrangement 1400 can be configured and / or structured to perform some or all of the operations / functions that correspond to the machine-readable instructions of one or more flowcharts from Fig. 9, Fig. 10 and Fig. 11, effectively instantiating as dedicated logic circuits to perform the operations / functions corresponding to these software instructions in a dedicated manner analogous to an ASIC. Therefore, the FPGA circuit arrangement 1400 can perform the operations / functions corresponding to some or all of the machine-readable instructions from Fig. 9, Fig. 10 and Fig. 11, perform faster than the general-purpose microprocessor can.

[0099] In the example from Fig. 14. The FPGA 1400 circuit assembly is configured and / or structured in response to programming (or one or more reprogramming) based on a binary file. In some examples, the binary file can be compiled and / or generated based on instructions in a hardware description language (HDL), such as Lucid, Very High Speed ​​Integrated Circuits (VHSIC) Hardware Description Language (VHDL), or Verilog. For example, a user (e.g., a human user, a machine user, etc.) can write code or a program corresponding to one or more operations / functions in an HDL; the code / program can be translated into a low-level language as needed; and the code / program (e.g., the code / program in the low-level language) can be converted into the binary file (e.g., by a compiler, a software application, etc.). In some examples, the FPGA 1400 circuit assembly can be generated from Fig. 14 access and / or load the binary file to cause the FPGA circuit arrangement 1400 to exit Fig. 14 is configured and / or structured to perform one or more operations / functions. For example, the binary file can be implemented by one or a combination of a bitstream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), or machine-readable instructions to which the FPGA circuit arrangement 1400 is subject. Fig. 14 can access the FPGA circuit arrangement 1400 from Fig. 14 or to configure and / or structure one or more sections thereof.

[0100] In some examples, the binary file is compiled, generated, transformed, and / or otherwise output by a unified software platform used for programming FPGAs. For example, the unified software platform can translate first instructions (e.g., code or a program) corresponding to one or more operations / functions in a high-level language (e.g., C, C++, Python, etc.) into second instructions corresponding to the one or more operations / functions in an HDL. In some such examples, the binary file is compiled, generated, and / or otherwise output by the unified software platform based on the second instructions. In some examples, the FPGA circuitry 1400 can be made from Fig. 14 access and / or load the binary file to cause the FPGA circuit arrangement 1400 to exit Fig. 14 is configured and / or structured to perform one or more operations / functions. For example, the binary file can be implemented by one or a combination of a bitstream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), or machine-readable instructions to which the FPGA circuit arrangement 1400 is subject. Fig. 14 can access the FPGA circuit arrangement 1400 from Fig. 14 or to configure and / or structure one or more sections thereof.

[0101] The FPGA circuit arrangement 1400 from Fig. Section 14 includes an exemplary input / output (I / O) circuit arrangement 1402 for receiving and / or outputting data to / from an exemplary configuration circuit arrangement 1404 and / or external hardware 1406. For example, the configuration circuit arrangement 1404 can be implemented by an interface circuit arrangement that can receive a binary file, which may be implemented by one or more bitstream, data, or machine-readable instructions to configure the FPGA circuit arrangement 1400 or one or more parts thereof. In some such examples, the configuration circuit arrangement 1404 can receive the binary file from one or a combination of a user, a machine (e.g., a hardware circuit arrangement (e.g., a programmable or dedicated circuit arrangement) that can implement an artificial intelligence / machine learning (AI / ML) model to generate the binary file, etc.) or any combination thereof. In some examples, the external hardware 1406 can be implemented by an external hardware circuit arrangement. For example, the external hardware 1406 can be implemented by the microprocessor 1300 from . Fig. 13 will be implemented.

[0102] The FPGA circuit arrangement 1400 also includes an array of an exemplary logic gate circuit arrangement 1408, several exemplary configurable interconnects 1410, and an exemplary storage circuit arrangement 1412. The logic gate circuit arrangement 1408 and the configurable interconnects 1410 are configurable to instantiate one or more operations / functions that implement at least some of the machine-readable instructions from Fig. 9, Fig. 10 and Fig. 11 or other desired operations may correspond to the following. Fig. The logic gate assembly 1408 shown in Figure 14 is manufactured in blocks or groups. Each block contains semiconductor-based electrical structures that can be configured into logic circuits. In some examples, the electrical structures include logic gates (e.g., AND gates, OR gates, NOR gates, etc.) that provide basic building blocks for logic circuits. Electrically controllable switches (e.g., transistors) are present within each of the logic gate assemblies 1408 to allow a configuration of one or a combination of the electrical structures or logic gates to form circuits for performing desired operations / functions. The logic gate assembly 1408 may include other electrical structures, such as lookup tables (LUTs), registers (e.g., flip-flops or latches), multiplexers, etc.

[0103] The configurable intermediate connections 1410 of the illustrated example are conductive paths, conductor tracks, vias or the like, which may include electrically controllable switches (e.g. transistors) whose state can be changed by programming (e.g. using an HDL instruction language) to enable or disable one or more connections between one or more of the logic gate circuit arrangements 1408 in order to program desired logic circuits.

[0104] The storage circuit arrangement 1412 of the illustrated example is structured to store one or more results of the one or more operations performed by corresponding logic gates. The storage circuit arrangement 1412 can be implemented by registers or the like. In the illustrated example, the storage circuit arrangement 1412 is distributed among the logic gate arrangement 1408 to facilitate access and increase execution speed.

[0105] The exemplary FPGA circuit arrangement 1400 from Fig. Reference 14 also includes an exemplary dedicated operating circuit arrangement 1414. In this example, the dedicated operating circuit arrangement 1414 includes a special-purpose circuit arrangement 1416 that can be called upon to implement frequently used functions, thus avoiding the need to program these functions locally. Examples of such a special-purpose circuit arrangement 1416 include a memory control circuit arrangement (e.g., DRAM control circuit arrangement), a PCIe control circuit arrangement, a clock generator circuit arrangement, a transceiver circuit arrangement, a memory, and a multiplier-accumulator circuit arrangement. Other types of special-purpose circuit arrangements may be present. In some examples, the FPGA circuit arrangement 1400 may also include an exemplary programmable general-purpose circuit arrangement 1418, such as an exemplary CPU 1420 or an exemplary DSP 1422.Another programmable general-purpose circuit arrangement 1418 may be present in addition or alternatively, such as a GPU, an XPU, etc., which may be programmed to perform other operations.

[0106] Although Fig. 13 and Fig. 14 Two exemplary implementations of the programmable circuit arrangement 1212 from Fig. Figure 12 illustrates many other approaches. For example, an FPGA circuit arrangement can represent an on-board CPU, such as one or more of the exemplary CPU 1420 from Fig. 13, include. Therefore, the programmable circuit arrangement 1212 can consist of Fig. 12 also by combining at least the exemplary microprocessor 1300 from Fig. 13 and the exemplary FPGA circuit arrangement 1400 from Fig. 14 be implemented. In some such hybrid examples, one or more cores may be 1302 from Fig. 13. Execute a first part of the machine-readable instructions that are defined by one or more flowcharts from Fig. 9, Fig. 10 and Fig. 11 are shown to perform one or more initial operations / functions, wherein the FPGA circuit arrangement 1400 consists of Fig. 14 may be configured and / or structured to perform one or more second operations / functions corresponding to a second part of the machine-readable instructions derived from the flowcharts Fig. 9, Fig. 10 and Fig. 11 are shown, or an ASIC may be configured and / or structured to perform one or more third operations / functions corresponding to a third part of the machine-readable instructions shown in the flowcharts from Fig. 9, Fig. 10 and Fig. 11 are shown.

[0107] A part or all of the circuit arrangement made up of Fig. 2 can therefore be instantiated at the same or different times. For example, one or more identical or different parts of the 1300 microprocessor can be instantiated. Fig. 13. be programmed to execute one or more parts of machine-readable instructions at the same or different times. In some examples, one or more identical or different parts of the FPGA circuit arrangement 1400 may consist of Fig. 14. be configured and / or structured to execute operations / functions according to one or more parts of machine-readable instructions at the same or different times.

[0108] In some examples, part or all of the circuit arrangement can consist of Fig. 2. For example, they can be instantiated in one or more threads that are executed simultaneously or sequentially. For example, the 1300 microprocessor can be made from Fig. Execute 13 machine-readable instructions in one or more threads, which are executed concurrently or sequentially. In some examples, the FPGA circuit arrangement can consist of 1400 Fig. 14. It must be configured and / or structured to execute operations / functions simultaneously or sequentially. Furthermore, in some examples, part or all of the circuit arrangement may consist of Fig. 2 be implemented within one or more virtual machines or containers running on the 1300 microprocessor Fig. 13 will be executed.

[0109] In some examples, the programmable circuit arrangement 1212 can consist of Fig. 12 are located in one or more enclosures. For example, at least the 1300 microprocessor can be made of Fig. 13 and / or the FPGA circuit arrangement 1400 from Fig. 14 are located in one or more enclosures. In some examples, an XPU can be provided by the programmable circuit arrangement 1212. Fig. 12 can be implemented, which can be housed in one or more packages. The XPU can, for example, be a CPU (e.g., the 1300 microprocessor from Fig. 13, the CPU 1420 from Fig. 14 etc.) in a housing, a DSP (e.g. the DSP 1422 from Fig. 14) in another package, a GPU in another package and an FPGA (e.g. the FPGA circuit assembly 1400 from Fig. 14) in yet another housing.

[0110] A block diagram illustrating an exemplary software distribution platform 1505 for distributing software, such as the machine-readable instructions 1232 from Fig. 12, which points to other hardware devices (e.g., one or more hardware devices owned or operated by third parties other than the owner or operator of the software distribution platform), is in Fig. Figure 15 illustrates this. The exemplary software distribution platform 1505 can be implemented by any computer server, data facility, cloud service, etc., capable of storing software and transferring it to other computing devices. The third parties can be customers of the entity that owns and / or operates the software distribution platform 1505. For example, the entity that owns and / or operates the software distribution platform 1505 can be a developer, vendor, and / or licensor of software, such as the exemplary machine-readable instructions 1232 from Fig. 12. Third parties may be consumers, users, retailers, original equipment manufacturers, etc., who purchase and / or license the software for use, resale, and / or sublicensing. In the illustrated example, the software distribution platform 1505 includes one or more servers and one or more storage devices. The storage devices store the machine-readable instructions 1232, which correspond to the exemplary machine-readable instructions from Fig. 9, Fig. 10 and Fig. 11, as described above. The one or more servers of the exemplary software distribution platform 1505 communicate with an exemplary network 1510, which may correspond to one or more of the Internet or to any of the exemplary networks described above. In some examples, the one or more servers respond to requests to transfer the software as part of a commercial transaction to a requesting party. Payment for the delivery, sale, and / or licensing of the software may be processed by the one or more servers of the software distribution platform and / or by a third-party payment entity. The servers enable one or more purchasers and / or licensors to download the machine-readable instructions 1232 from the software distribution platform 1505. For example, the software, which corresponds to the exemplary machine-readable instructions from Fig. 9, Fig. 10 and Fig. 11 can be downloaded to the exemplary programmable circuit arrangement platform 1200, which is intended to execute the machine-readable instructions 1232 to implement the radar transceiver IC 200. In some examples, one or more servers of the software distribution platform 1505 regularly offer, transmit, and / or enforce updates to the software (e.g., the exemplary machine-readable instructions 1232 from Fig. 12) to ensure that improvements, patches, updates, etc., are distributed and applied to the software on end-user devices. Although previously referred to as software, the distributed “software” could alternatively be firmware.

[0111] Although an exemplary way to implement the radar transceiver IC 200 from Fig. 2 in Fig. As illustrated in point 2, one or more of the elements, processes, or devices that are in Fig. The components illustrated in Figure 2 can be combined, divided, rearranged, omitted, eliminated, or implemented in any other way. Furthermore, the exemplary chirp synthesis circuit 202 and the exemplary transmitters 2041-204 can be combined, divided, rearranged, omitted, eliminated, or implemented in any other way. N , the exemplary transmitting antennas 2061-206 N , the exemplary receiving antennas 2081-208 M , the exemplary recipients 2101-210 M , the exemplary interface circuit arrangement 212, the exemplary processor circuit 214 or more generally the exemplary radar transceiver IC 200 from Fig. 2. can be implemented by hardware alone or by hardware in combination with software and firmware. Accordingly, for example, any of the exemplary chirp synthesis circuit 202 or the exemplary transmitters 2041-204 could be used. N, the exemplary transmitting antennas 2061-206 N , the exemplary receiving antennas 2081-208 M , the exemplary recipients 2101-210 M The exemplary interface circuit arrangement 212, the exemplary processor circuit 214, or more generally the exemplary radar transceiver IC 200 can be implemented by a programmable circuit arrangement in combination with one or more machine-readable instructions (e.g., firmware or software), a processor circuit arrangement, analog circuit(s), digital circuit(s), logic circuit(s), programmable processor(s), programmable microcontroller(s), graphics processing unit(s) (GPU(s)), digital signal processor(s) (DSP(s)), ASIC(s), programmable logic device(s) (PLD(s)), and / or field-programmable logic device(s) (FPLD(s)), such as FPGAs. Furthermore, the exemplary radar transceiver IC 200 can be implemented from Fig. 2. include one or more elements, processes or devices in addition to or instead of those included in Fig. 2 are illustrated, or may include more than one or all of the illustrated elements, processes and devices.

[0112] A flowchart (flowcharts) representing exemplary machine-readable instructions that can be executed by a programmable circuit arrangement to design the radar transceiver IC 200. Fig. 2 to implement and / or instantiate, or which represents exemplary operations that can be performed by a programmable circuit arrangement to implement the radar transceiver IC 200 from Fig. 2 to implement and / or instantiate is in Fig. 9, Fig. 10 and Fig. 11 shown. The machine-readable instructions can be one or more executable programs or (a) part(s) of one or more executable programs for execution by a programmable circuit arrangement, such as the programmable circuit arrangement 1212 shown in the exemplary programmable circuit arrangement platform 1200, which is subsequently described in conjunction with Fig. 12, and can be one or more functions or part(s) of functions that are described by the exemplary programmable circuit arrangement (e.g., an FPGA) described below in conjunction with Fig. 13 or Fig. The actions described in section 14 are to be carried out. In some examples, the machine-readable instructions cause an operation, task, etc., to be performed or carried out in an automated way in the real world. As used here, "automated" means without human intervention.

[0113] The program may be implemented in instructions (e.g., software and / or firmware) stored on one or more non-transient computer-readable or machine-readable storage media, such as one or a combination of a cache memory, a magnetic storage device or disk (e.g., a floppy disk, a hard disk drive (HDD), etc.), an optical storage device or disk (e.g., a Blu-ray disc, a compact disc (CD), a digital versatile disc (DVD), etc.), a redundant array of independent disks (RAID), a register, ROM, a solid-state drive (SSD), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., random-access memory (RAM) of any type, etc.), or any other storage device or storage disk.The instructions of the non-transitory computer-readable or machine-readable medium can program or be executed by a programmable circuit arrangement located in one or more hardware devices, but the entire program or parts thereof could alternatively be executed, instantiated, or implemented in dedicated hardware by one or more hardware devices other than the programmable circuit arrangement. The machine-readable instructions can be distributed across multiple hardware devices or executed by two or more hardware devices (e.g., a server and a client hardware device). For example, the client hardware device can be an endpoint client hardware device (e.g., a hardware device associated with a human user and / or machine user) or an intermediate client hardware device gateway (e.g., a server).A wireless access network (RAN) can be implemented that enables communication between a server and an endpoint client hardware device. Similarly, the non-transitory machine-readable storage medium can include one or more media. Furthermore, although the example program refers to the [document / the] in [document / section], Fig. 9, Fig. 10 and Fig. Eleven illustrated flowchart(s) describe many alternative methods for implementing the exemplary radar transceiver IC 200. For example, the execution order of the flowchart blocks can be changed, or some of the described blocks can be modified, removed, or combined. Additionally or alternatively, any or all of the flowchart blocks can be implemented by one or more hardware circuits (e.g., processor circuitry, discrete analog circuitry, discrete digital circuitry, integrated analog circuitry, integrated digital circuitry, an FPGA, an ASIC, a comparator, an operational amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing any software or firmware.The programmable circuit arrangement can be distributed across different network locations or local to one or more hardware devices (e.g., a single-core processor (e.g., a single-core CPU), a multi-core processor (e.g., a multi-core CPU, an XPU, etc.)). As used here, a programmable circuit arrangement includes any type(s) of circuitry that can be programmed to perform a desired function, such as a CPU or a combination thereof. The programmable circuit arrangement can be any combination of one or more CPUs and one or more FPGAs located in the same package (e.g., a 4x4).A programmable circuit arrangement may include a programmable logic device (PLD), a generic array logic (GAL), a programmable array logic (PAL), a complex programmable logic device (CPLD), a simple programmable logic device (SPLD), a microcontroller unit (MCU), a programmable system-on-a-chip (PSoC), etc., or any combination thereof, in any of the contexts described above.

[0114] The machine-readable instructions described here can be stored in a compressed format, an encrypted format, a fragmented format, a compiled format, an executable format, and / or a packed format, etc. Machine-readable instructions, as described here, can be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bitstream (e.g., a computer-readable bitstream, a machine-readable bitstream, etc.) or a data structure (e.g., as part(s) of instructions, code, representations of code, etc.) that can be used to generate, construct, or produce machine-executable instructions. For example, the machine-readable instructions can be fragmented and stored on one or more storage devices, disks, or computing devices (e.g.,Machine-readable instructions may be stored on servers located in the same location or in different locations within a network or collection of networks (e.g., in the cloud, on edge devices, etc.). These instructions may require installation, modification, adaptation, updating, combination, augmentation, configuration, decryption, decompression, unpacking, distribution, remapping, and / or compilation, etc., to make them directly readable, interpretable, or executable by a computing device or other machine.For example, the machine-readable instructions can be stored in several parts, which are individually compressed, encrypted, or stored on separate computing devices, the parts, when decrypted, decompressed, or combined, forming a set of one or more computer-executable instructions or machine-executable instructions that form one or more functions or operations that together can form a program, such as the one described here.

[0115] In another example, the machine-readable instructions may be stored in a state where they can be read by a programmable circuit arrangement, but require the addition of a library (e.g., a dynamic-link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., to execute the machine-readable instructions on a specific computing device or other device. In yet another example, the machine-readable instructions may need to be configured (e.g., settings must be saved, data entered, network addresses recorded, etc.) before the machine-readable instructions or the corresponding program(s) can be executed, either fully or partially.Accordingly, machine-readable, computer-readable or machine-readable media, as used here, may contain one or a combination of instructions and (a) program(s), irrespective of the specific format or state of the machine-readable instructions or program(s).

[0116] The machine-readable instructions described here can be represented by any past, present, or future command language, scripting language, programming language, etc. For example, the machine-readable instructions can be represented using any of the following languages: C, C++, Java, C-sharp, Perl, Python, JavaScript, HyperText Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0117] As mentioned previously, the exemplary operations can be derived from Fig. 9, Fig. 10 and Fig.11. are implemented using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored on one or more non-transitory computer-readable or machine-readable media. As used herein, the terms non-transitory computer-readable medium, non-transitory computer-readable storage medium, non-transitory machine-readable medium, and non-transitory machine-readable storage medium are expressly defined to include any type of computer-readable storage device or storage disk and to exclude propagating signals and transmission media.Examples of such a non-transitory computer-readable medium, non-transitory computer-readable storage medium, non-transitory machine-readable medium, or non-transitory machine-readable storage medium include one or more optical storage devices, magnetic storage devices, a hard disk drive (HDD), flash memory, read-only memory (ROM), a CD, a DVD, a cache, RAM of any type, a register, or any other storage device or storage disk in which information is stored for any duration (e.g., for extended periods of time, permanently, for brief moments, for temporary buffering, for intermediate storage of information).As used here, the terms "non-transitory computer-readable storage device" and "non-transitory machine-readable storage device" are defined to include any physical (mechanical, magnetic, electromechanical, or electrical) hardware for preserving information for a period of time, but exclude propagating signals and transmission media. Examples of non-transitory computer-readable storage devices or non-transitory machine-readable storage devices include one or a combination of random-access memory of any type, read-only memory of any type, solid-state memory, flash memory, optical discs, magnetic disks, disk drives, or redundant array of independent disks (RAID) systems.As used here, the term "device" refers to a physical structure, such as a mechanical, electromechanical or electrical equipment, hardware or circuit arrangement, which may or may not be configured by computer-readable instructions, machine-readable instructions, etc., or may be manufactured to execute computer-readable instructions, machine-readable instructions, etc.

[0118] “Including” and “comprising” (and all forms and tenses thereof) are used here as open terms. Accordingly, whenever a claim uses any form of “include” or “comprise” (e.g., encompasses, includes, encompassing, inclusive, exhibiting, etc.) as a preamble or within any kind of claim recitation, additional elements, terms, etc., may be present without altering the scope of protection of the claim or recitation in question. As used here, when the phrase “at least” is used as the transitional expression in, for example, a claim preamble, it is an open term in the same way that the expressions “comprising” and “including” are open.As used here in the context of describing structures, components, items, objects, and things, the phrase "at least one of A and B" refers to implementations that include any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used here in the context of describing structures, components, items, objects, and things, the phrase "at least one of A or B" refers to implementations that include any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used here in the context of describing the performance or execution of processes, instructions, actions, activities, etc., the phrase "at least one of A and B" refers to implementations that include any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.Similarly, as used here in the context of describing the performance or execution of processes, instructions, actions, activities, etc., the phrase "at least one of A or B" refers to implementations that include any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0119] As used here, singular references (e.g., "a," "an," "first," "second," etc.) do not preclude a plural. The expression "a" object, as used here, refers to one or more of that object. The expressions "a" (or "an"), "one or more," and "at least one" are used interchangeably here. Furthermore, although not listed individually, multiple means, elements, or actions may be implemented by, for example, the same entity or object. Although individual features may be included in different examples or claims, they may also potentially be combined, and inclusion in different examples or claims does not imply that a combination of features is not feasible and / or advantageous.

[0120] As used here, connection references (e.g., attached, coupled, connected, joined) can include intermediate elements between the elements referenced by the connection reference and / or a relative movement between those elements, unless otherwise specified. Therefore, connection references do not imply that two elements are directly connected or in a fixed relationship to each other.

[0121] Unless specifically stated otherwise, descriptors such as "first," "second," "third," etc., are used here without implying or otherwise indicating any significance of priority, physical order, arrangement in a list, or sorting. They are used simply as labels and / or arbitrary names to distinguish elements for the ease of understanding the examples described. In some examples, the descriptor "first" may be used to refer to an element in the detailed description, while the same element in a claim may be designated by a different descriptor, such as "second" or "third." In such cases, these descriptors are used solely to distinctly identify those elements within the context of the description (e.g., within a claim), where the elements might otherwise, for example, share the same name.

[0122] As used here, the phrase “in communication”, including variations thereof, includes one or a combination of direct communication or indirect communication through one or more intermediate components and does not require direct physical (e.g., wired) communication or constant communication, but rather also includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals and / or at one-off events.

[0123] As used here, a “programmable circuit arrangement” is defined as comprising (i) one or more specialized electrical circuits (e.g., an application-specific integrated circuit (ASIC)) structured to perform a specific operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and / or (ii) one or more general-purpose semiconductor-based electrical circuits programmable with instructions to perform one or more specific functions or operations and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuit arrangements include programmable microprocessors, such as central processing units (CPUs).capable of executing the first instructions for performing one or more operations or functions, field-programmable gate arrays (FPGAs) that may be programmed with second instructions for configuring and / or structuring the FPGAs to instantiate one or more operations or functions corresponding to the first instructions, graphics processing units (GPUs) that can execute first instructions for performing one or more operations or functions, digital signal processors (DSPs) that can execute first instructions for performing one or more operations or functions, XPUs, network processing units (NPUs), one or more microcontrollers that can execute first instructions for performing one or more operations or functions, or integrated circuits,such as application-specific integrated circuits (ASICs). For example, an XPU can be implemented by a heterogeneous computing system including several types of programmable circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DPSs, etc., and any combination thereof) and an orchestration technology (e.g., application programming interface(s) (API(s)) that can assign a computational task(s) to the one or more types of programmable circuitry that are suitable and available to perform the computational task(s)).

[0124] As used here, an integrated circuit / circuit assembly is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit can be implemented as an ASIC, an FPGA, a chip, a microchip, a programmable logic assembly, a semiconductor substrate coupling multiple circuit elements, and / or a system-on-a-chip (SoC), etc.

[0125] In this description, the term "couple" can cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by a direct connection; or (b) in a second example, device A is coupled to device B via an intermediary component C, provided that the intermediary component C does not change the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

[0126] Unless specifically stated otherwise, terms such as node and interconnect may be used to mean an intermediate connection between an endpoint of a device element, a circuit element, an integrated circuit, a device or any other electronic or semiconductor component.

[0127] In the description and claims, a described "circuit arrangement" may include one or more circuits. A circuit or device described herein as including certain components may instead be configured to be coupled with these components to form the described circuit arrangement device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as one or a combination of resistors, capacitors, or inductors), or one or more sources (such as voltage and / or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a transistor, a transistor, or a power supply).a semiconductor die and / or an integrated circuit (IC) package) and can be configured to be coupled with at least some of the passive elements or sources to form the described structure either at the time of manufacture or after a period of manufacture, for example by an end user and / or a third party.

[0128] The circuits described here are reconfigurable to include the replaced components in order to provide functionality that is at least partially similar to functionality that was available before the component replacement. Although certain elements of the described examples are contained within an integrated circuit and other elements are external to the integrated circuit, other embodiments may include additional or fewer features within the integrated circuit. Furthermore, some or all of the features illustrated as external to the integrated circuit may be contained within the integrated circuit, and some features illustrated as internal to the integrated circuit may be implemented outside of the integrated circuit.As used here, the term “integrated circuit” means one or more circuits that are at least one of the following: (i) embedded in / over a semiconductor substrate; (ii) embedded in a single semiconductor package; (iii) embedded in the same module; or (iv) embedded in / on the same printed circuit board.

[0129] Any value given here is approximate, acknowledging the possible variations that occur in real-world applications. A given value may not be exact due to manufacturing tolerances and / or other real-world imperfections. Unless otherwise stated, a given value represents ±10 percent of the stated value or, if the value is zero, a reasonable range around zero.

[0130] Modifications are possible in the examples described, and other examples are possible within the scope of protection of the claims.

[0131] From the foregoing, it is clear that exemplary systems, devices, manufactured items, and procedures have been described that improve dynamic range in the presence of interference. The described systems, devices, manufactured items, and procedures improve the efficiency of using a computing device by reducing artifacts related to interference reconstruction. A reduction in artifacts related to interference reconstruction directly leads to a reduced trade-off between higher-level functions (e.g., object tracking, etc.) and reduced false target detection. Accordingly, the described systems, devices, manufactured items, and procedures involve one or more improvements to the operation of a machine, such as a computer or other electronic, electromechanical, or mechanical device.

Claims

[1] Facility comprising the following: an interface circuit arrangement for receiving digital samples representing a frame of chirps; and a programmable circuit arrangement for the following: for a distance Fourier transform (FT) representation of the frame of chirps, determining a reconstructed chirp for a chirp of the frame of chirps that contains a faulty sample; Determining a first Doppler distance representation of the frame of chirps based on the distance FT representation, where the distance FT representation includes the reconstructed chirp; and Determining a second Doppler distance representation as an element-wise minimum between the first Doppler distance representation and a third Doppler distance representation of the frame of chirps, wherein the third Doppler distance representation is based on the digital samples, the digital samples including a reconstructed sample that substitutes for the faulty sample of the chirps. [2] Device according to claim 1, comprising a receiver circuit arrangement for receiving the frame of chirps from an environment. [3] Device according to claim 1, wherein the frame of chirps is a first frame of reflected chirps from an environment and the device includes a transmitter circuit arrangement for transmitting a second frame of chirps into the environment. [4] Device according to claim 1, wherein the programmable circuit arrangement is designed as follows: based on the digital samples, determining the reconstructed sample for the faulty sample; and Determining the third Doppler distance representation based on the digital samples, where the digital samples include the chirp with the reconstructed sample. [5] Device according to claim 1, wherein the programmable circuit arrangement is designed as follows: Replacing the chirp, including the faulty sample, with a chirp with a value of zero in the digital samples; Determining the distance FT representation of the frame of chirps based on the digital samples, where the digital samples include the chirp with value zero, and where the distance FT representation has a first dimension and a second dimension; For each indice across the second dimension of the distance FT representation, determine a Doppler FT representation; for the respective Doppler FT representations: Setting to zero any value that does not meet the threshold of a peak value in the respective Doppler FT representation; and Determining an inverse distance FT representation to generate the reconstructed chirp; and Replacing the chirp, including the faulty sample, in the distance FT representation with the reconstructed chirp. [6] Device according to claim 1, wherein the programmable circuit arrangement is designed as follows: Determining the distance-FT representation of the frame of chirps, where the distance-FT representation includes the reconstructed chirp; and Determining a Doppler FT representation of the distance FT representation to determine the first Doppler distance representation. [7] Device according to claim 1, wherein the second Doppler distance representation, which is determined as the element-wise minimum between the first Doppler distance representation and the third Doppler distance representation, is intended to attenuate a first interference in one distance dimension and a second interference in one Doppler dimension. [8] Non-volatile, computer-readable medium containing instructions to cause a programmable circuit arrangement to do the following: for a distance Fourier transform (FT) representation of a frame of chirps, determining a reconstructed chirp for a chirp of the frame of chirps that contains a faulty sample, wherein the frame of chirps from an environment is received by an integrated radar circuit and is represented by digital samples; Determining a first Doppler distance representation of the frame of chirps based on the distance FT representation, where the distance FT representation includes the reconstructed chirp; and Determining a second Doppler distance representation as an element-wise minimum between the first Doppler distance representation and a third Doppler distance representation of the frame of chirps, wherein the third Doppler distance representation is based on the digital samples, the digital samples including a reconstructed sample that substitutes for the faulty sample of the chirps. [9] Non-volatile computer-readable medium according to claim 8, wherein the instructions cause the programmable circuit arrangement to do the following: based on the digital samples, determining the reconstructed sample for the faulty sample; and Determining the third Doppler distance representation based on the digital samples, where the digital samples include the chirp with the reconstructed sample. [10] Non-volatile computer-readable medium according to claim 8, wherein the instructions cause the programmable circuit arrangement to do the following: Replacing the chirp, including the faulty sample, with a chirp with a value of zero in the digital samples; Determining the distance FT representation of the frame of chirps based on the digital samples, where the digital samples include the chirp with value zero, and where the distance FT representation has a first dimension and a second dimension; For each indice across the second dimension of the distance FT representation, determine a Doppler FT representation; for the respective Doppler FT representations: Setting to zero any value that does not meet the threshold of a peak value in the respective Doppler FT representation; and Determining an inverse distance FT representation to generate the reconstructed chirp; and Replacing the chirp, including the faulty sample, in the distance FT representation with the reconstructed chirp. [11] Non-volatile computer-readable medium according to claim 8, wherein the instructions cause the programmable circuit arrangement to do the following: Determining the distance-FT representation of the frame of chirps, where the distance-FT representation includes the reconstructed chirp; and Determining a Doppler FT representation of the distance FT representation to determine the first Doppler distance representation. [12] Non-volatile computer-readable medium according to claim 8, wherein the second Doppler distance representation, which is determined as the element-wise minimum between the first Doppler distance representation and the third Doppler distance representation, is intended to attenuate a first interference in one distance dimension and a second interference in one Doppler dimension. [13] Non-volatile computer-readable medium according to claim 12, wherein attenuation of the first interference and the second interference is intended to improve the dynamic range of the integrated radar circuit. [14] Method comprising the following: Received, with an interface circuit arrangement, digital samples representing a frame of chirps; Replace, by executing a command with a programmable circuit arrangement, a chirp of the frame of chirps containing a faulty sample with a chirp with a value of zero in the digital samples; Determine, by executing an instruction with the programmable circuit arrangement, a distance Fourier Transform (FT) representation of the frame of chirps based on the digital samples, wherein the digital samples include the chirp with value zero, and wherein the distance FT representation has a first dimension and a second dimension; Determine the respective indices across the second dimension of the distance FT representation by executing an instruction with the programmable circuit arrangement, a Doppler FT representation; for the respective Doppler FT representations: Set to zero, by executing an instruction with the programmable circuit arrangement, a value that does not meet a threshold of a peak value in the respective Doppler FT representation; and Determine, by executing an instruction using the programmable circuit arrangement, an inverse distance FT representation to generate a reconstructed chirp; Replace, by executing an instruction with the programmable circuit arrangement, the chirp including the faulty sample in the distance FT representation with the reconstructed chirp; and Determine, by executing an instruction with the programmable circuit arrangement, a Doppler distance representation of the frame of chirps based on the distance FT representation, wherein the distance FT representation includes the reconstructed chirp. [15] Method according to claim 14, wherein the Doppler distance representation is a first Doppler distance representation and the method includes determining a second Doppler distance representation as an element-wise minimum between the first Doppler distance representation and a third Doppler distance representation of the frame of chirps, wherein the third Doppler distance representation is based on the digital samples, wherein the digital samples include a reconstructed sample that substitutes the faulty sample of the chirps. [16] The method of claim 15, comprising the following: based on the digital samples, determining the reconstructed sample for the faulty sample; and Determining the third Doppler distance representation based on the digital samples, where the digital samples include the chirp with the reconstructed sample. [17] Method according to claim 15, wherein the second Doppler distance representation, which is determined as the element-wise minimum between the first Doppler distance representation and the third Doppler distance representation, is intended to attenuate a first interference in one distance dimension and a second interference in one Doppler dimension. [18] Method according to claim 14, which includes receiving, with a receiver circuit arrangement, the frame of chirps from an environment. [19] Method according to claim 14, wherein the frame of chirps is a first frame of reflected chirps from an environment and the method includes transmitting, with a transmitter circuit arrangement, a second frame of chirps into the environment. [20] The method of claim 14, wherein the Doppler FT representation is a first Doppler FT representation and the method comprises: Determining the distance-FT representation of the frame of chirps, where the distance-FT representation includes the reconstructed chirp; and Determining a second Doppler FT representation of the distance FT representation to determine the Doppler distance representation.

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