SURFACE PROFILE CONTROL OF EPITACTIC AREAS IN SEMICONDUCTOR DEVICES

Abstract

A semiconductor structure and a method for fabricating the structure are disclosed. The method comprises forming a superlattice structure with a nanostructured layer and a nanostructured sacrificial layer on a base structure on a substrate, forming a polysilicon structure on the superlattice structure, and forming a S / D region within the superlattice structure. An S / D section of the S / D region extends over the nanostructured layer. The method further comprises modifying the thickness of the S / D section, depositing a dielectric layer on the modified S / D section, and replacing the polysilicon structure and the nanostructured sacrificial layer with a gate structure.

Description

CROSS-REFERENCE TO RELATED REGISTRATIONS

[0001] This application claims priority over the preliminary US patent application No. 63 / 712,667, entitled “Epitaxial Structures in Semiconductor Devices”, filed on October 28, 2024, which is incorporated by reference into the present application. BACKGROUND

[0002] Advances in semiconductor technology have led to an increasing demand for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet this demand, the semiconductor industry is continuously miniaturizing the dimensions of semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), including planar MOSFETs, fin-type field-effect transistors (finFETs), and gate-all-around field-effect transistors (GAA-FETs). This miniaturization has increased the complexity of semiconductor manufacturing processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this revelation are best understood through the following detailed description in conjunction with the accompanying drawings. Fig. Figure 1A illustrates an isometric view of a semiconductor device in accordance with some embodiments. Fig. Figures 1B-1H illustrate various cross-sectional views of a semiconductor device in accordance with some embodiments. Fig. Figure 2 is a flowchart of a process for manufacturing a semiconductor device in accordance with some embodiments. Fig. Figures 3A-14A, 3B-14B and 3C-14C illustrate isometric and cross-sectional views of a semiconductor device at various stages of its manufacturing process in accordance with some embodiments. Fig. 15 and Fig. Figure 16 illustrates cross-sectional views of another semiconductor device at various stages of its manufacturing process in accordance with some embodiments.

[0004] Illustrative embodiments are now described with reference to the accompanying drawings. In the drawings, identical reference numerals generally indicate identical, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments, or examples, for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the process for forming a first structural element over a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, such that the first and second structural elements might not be in direct contact.As used here, the formation of a first structural element on a second structural element means that the first structural element is formed in direct contact with the second structural element. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples. This repetition does not itself establish a relationship between the different embodiments and / or configurations discussed.

[0006] Spatially relative terms such as "underlying," "below," "under," "overlying," "above," and the like may be used herein to facilitate description and to describe the relationship of one element or structural element to another element(s) or structural element(s), as illustrated in the figures. These spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0007] It is noted that references in the description to "an embodiment," "any embodiment," "an example embodiment," "exemplary," etc., indicate that the described embodiment may have a particular structural element, structure, or property, but not every embodiment necessarily has that particular structural element, structure, or property. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, if a particular structural element, structure, or property is described in connection with an embodiment, it would be within the knowledge of a person skilled in the art to implement such a structural element, structure, or property in connection with other embodiments, whether explicitly described or not.

[0008] It is to be understood that the language or terminology used herein serves the purpose of description and not of limitation, so that the terminology or language used in the present description shall be interpreted by experts in a relevant field in light of the teachings presented.

[0009] In some embodiments, the terms "approximately" and "essentially" may indicate a value of a certain quantity that varies within 5-20% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±10-15%, ±15-20% of the value). These values ​​are only examples and are not intended to be limiting. The terms "approximately" and "essentially" may refer to a percentage of the value, as interpreted by those skilled in the art in the relevant field in light of the present teachings.

[0010] The GAA transistor structures can be structured by any suitable method. For example, the structures can be structured using one or more photolithography processes, including dual or multiple structuring processes. Dual or multiple structuring processes can combine photolithography and self-aligning processes, thereby producing structures with, for example, smaller pitches than would otherwise be obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacers are formed along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed and the remaining spacers can then be used to structure the GAA transistor structure.

[0011] A GAA-FET can comprise a first and second fin-shaped base structure arranged on a substrate, a first and second stack of nanostructured channel regions arranged on the first and second fin-shaped base structures, respectively, a source / drain region (S / D region) located between the first and second stack of nanostructured channel regions, and a first and second gate structure surrounding the nanostructured channel regions in the first and second stack, respectively. The S / D region is formed epitaxially along the sidewalls of the nanostructured channel regions facing the S / D region. To ensure adequate sidewall coverage of the nanostructured channel regions by the S / D region, the S / D region extends over the top surfaces of the uppermost nanostructured channel regions.As a result, the extended section of the S / D region overlaps with the adjacent gate structures along a vertical cross-sectional plane, making it more difficult to minimize parasitic capacity between the S / D region and the gate structures.

[0012] To address the aforementioned challenges, this disclosure provides exemplary GAA-FETs with reduced parasitic capacitance between a gate structure and an S / D region, and exemplary methods for fabricating these GAA-FETs. In some embodiments, the formation of the S / D region can be followed by an etching process on the S / D region to reduce the thickness of the extended S / D section without compromising the sidewall coverage of the nanostructured channel regions by the S / D region. In some embodiments, to ensure adequate sidewall coverage of the nanostructured channel regions by the S / D region, the etching process can be controlled to achieve W-shaped or concave cross-sectional profiles (also referred to as "etch profiles") along vertical cross-sectional planes (e.g., XZ and YZ planes) for the S / D cover surface.In some embodiments, for the W-shaped or concave cross-sectional profiles of the S / D cover surface extending between adjacent nanostructured channel regions, the edges of the S / D cover surface can be raised above the cover surfaces of the uppermost nanostructured channel regions, and the central section of the S / D cover surface can have a convex or concave profile. In some embodiments, during the etching process, the thickness of the extended S / D section can be reduced from a first thickness of approximately 4 nm to approximately 12 nm to a second thickness of approximately 2 nm to approximately 8 nm. Such a reduction in the thickness of the extended S / D section can lead to a reduction in the parasitic capacitance between the S / D region and the gate structures by approximately 2% to approximately 3%.In some embodiments, reducing the thickness of the extended S / D section can also facilitate the formation of gate structures with shorter heights, which makes it easier to miniaturize GAA-FETs to meet the increasing demand for small and portable semiconductor devices.

[0013] In some embodiments, the etching process can be followed by the formation of an etch control layer (e.g., a silicon nitride layer (SiN layer); also referred to as a "hard mask layer") on the S / D cover surface and on cover surfaces of an etch stop layer and an interlayer dielectric arranged on the S / D region. The etch control layer can preserve the integrity of the edge profiles of the S / D cover surface during subsequent processes on the S / D region. In some embodiments, the etch control layer can also facilitate the formation of a deep contact opening in the S / D region while preventing the etch stop layer and the interlayer dielectric from being over-etched during the formation of the contact opening.Consequently, a contact structure with a larger contact area can be formed on the S / D region, while the section of the contact structure on the etch stop layer and the interlayer dielectric can have a shallower depth than that formed without the barrier layer on the S / D region. In some embodiments, due to such a shallow contact structure depth, the parasitic capacitance between the S / D region and the section of the contact structure on the etch stop layer and the interlayer dielectric can be reduced by approximately 1% to approximately 4%. Thus, the total parasitic capacitance of the GAA-FET can be reduced by approximately 3% to approximately 7%.

[0014] Fig. Figure 1A illustrates an isometric view of a semiconductor device 100 which may represent a GAA-FET 100, according to some embodiments. Fig. 1B, Fig. 1E and Fig. 1H illustrates various cross-sectional views of GAA-FET 100 along line AA of Fig. 1A, with additional structures which, for the sake of simplicity, are in Fig. 1A are not shown, according to some embodiments. Fig. 1C and Fig. Figure 1F illustrates various cross-sectional views of GAA-FET 100 along line BB of Fig. 1A, with additional structures which, for the sake of simplicity, are in Fig. 1A and Fig. 1B are not shown, according to some embodiments. Fig. 1D and Fig. 1G illustrates various cross-sectional views of GAA-FET 100 along line CC of Fig. 1A, with additional structures which, for the sake of simplicity, are in Fig. 1A are not shown, according to some embodiments. The explanation of elements in Fig. 1A-1H with the same designations applies to the others unless explicitly stated otherwise.

[0015] With reference to Fig. In some embodiments, 1A-1H can be a substrate 102 (in GAA-FET 100 (i) Fig. 1A shown; not shown for simplicity. Fig. 1B-1H shown), (ii) STI areas 104 (in cross-sectional views of Fig. 1B, Fig. 1E and Fig. 1H not visible), arranged on substrate 102, (iii) fin-shaped base structures 106 (also referred to as “plate bases 106” or “fin bases 106”) arranged on substrate 102, (iv) stacks of nanostructured channel regions 108A-108C arranged on each of fin-shaped base structures 106A-106D (in cross-sectional views of Fig. 1C, Fig. 1D, Fig. 1F and Fig. 1G not visible), (v) Gate structures 110 (also referred to as “GAA structures 110”; in cross-sectional views of Fig. 1C, Fig. 1D, Fig. 1F and Fig. 1G not visible), surrounding nanostructured channel regions 108A-108C, (vi) outer gate spacers 112 (in cross-sectional views of Fig. 1C, Fig. 1D, Fig. 1F and Fig. 1G not visible), (vii) inner gate spacers 114 (in cross-sectional views of Fig. 1C, Fig. 1D, Fig. 1F and Fig. 1G not visible), (viii) S / D regions 116, (ix) intermediate layers 118, (x) etch stop layers (ESLs) 120A and 120B (ESL 120A, in cross-sectional views of Fig. 1B, Fig. 1E and Fig. 1H not visible), (xi) Interlayer dielectrics (ILD layers) 122A and 122B (ILD layer 122A, in cross-sectional views of Fig. 1B, Fig. 1E and Fig. 1H not visible), (xii) etch control layers 124 (also referred to as “hard mask layers 124”), (xiii) fixture isolation structures 126 (also referred to as “cut-metal gate structures (CMG structures) 126”; in cross-sectional views of Fig. 1B, Fig. 1E and Fig. (1H not visible), (xiv) contact structures 128 and (xv) dielectric layers 130. Each of the S / D regions 116 can refer to a source or a drain individually or jointly, depending on the context.

[0016] In some embodiments, substrate 102 can be a semiconductor material such as silicon (Si), germanium (Ge), silicon germanium (SiGe), a silicon-on-insulator (SOI) structure, or a combination thereof. Furthermore, substrate 102 can be doped with p-type dopants (e.g., boron, indium, aluminum, or gallium) or n-type dopants (e.g., phosphorus or arsenic). In some embodiments, STI regions 104 can be an insulating material such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon germanium oxide (SiGeO). x). In some embodiments, fin-shaped base structures 106 can contain a material similar to substrate 102. Fin-shaped base structures 106 can have elongated sides extending along an X-axis.

[0017] In some embodiments, nanostructured channel regions 108A-108C can be in the form of nanosheets, nanowires, nanorods, nanotubes, or other suitable nanostructured shapes. As used here, the term "nanostructured" defines a structure, layer, and / or region with a horizontal dimension (e.g., along an X and / or Y axis) and / or a vertical dimension (e.g., along a Z axis) smaller than approximately 100 nm, for example, approximately 90 nm, approximately 50 nm, approximately 10 nm, or other values ​​smaller than approximately 100 nm. Nanostructured channel regions 108A-108C can contain semiconductor materials similar to or different from substrate 102.In some embodiments, nanostructured channel regions 108A-108C can contain Si, silicon arsenide (SiAs), silicon phosphide (SiP), silicon carbide (SiC), silicon carbon phosphide (SiCP), silicon germanium (SiGe), silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium tin boron (SiGeSnB), a III-V semiconductor compound, or other suitable semiconductor materials. In some embodiments, each of the nanostructured channel regions 108A-108C can have a thickness of approximately 3 nm to approximately 15 nm along a Z-axis. Although three nanostructured channel regions 108A-108C are shown in each stack, GAA-FET 100 can have any number of nanostructured channel regions. Although rectangular cross-sections of nanostructured channel regions 108A-108C are shown, nanostructured channel regions 108A-108C can have cross-sections of other geometric shapes (e.g. circular, elliptical, triangular or polygonal).

[0018] Each of the gate structures 110 can be a multilayer structure and can surround nanostructured channel regions 108A-108C, the gate structures 110 being referred to as "GAA structures". Each gate structure 110 can comprise (i) an oxide interface layer (IL layer) 110A, (ii) a dielectric high-k gate layer (HK layer) 110B, and (iii) a conductive layer 110C. In some embodiments, the IL layer 110A can be arranged directly on the uppermost nanostructured channel regions 108A. In some embodiments, the IL layer 110A can be SiO2, SiGeO2. x or germanium oxide (GeO x) and can have a thickness of approximately 0.5 nm to approximately 2 nm. In some embodiments, the dielectric HK gate layer 110B can be placed directly on the IL layer 110A and can have a thickness of approximately 1 nm to approximately 3 nm. In some embodiments, the HK gate oxide layer 110B can contain a high-k dielectric material, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO2). In some embodiments, the side walls of the IL layer 110A and HK gate oxide layer 110B can be in contact with side walls of outer gate spacers 112 and inner gate spacers 114.

[0019] In some embodiments, the conductive layer 110C can be arranged on the dielectric HK gate layer 110B and can be a multilayer structure. The various layers of conductive layer 110C are not shown for simplicity. In some embodiments, conductive layer 110C can have a work function metal layer (WFM layer) arranged on the dielectric HK gate layer 110B and a gate metal filler layer arranged on the WFM layer. In some embodiments, the WFM layer may contain essentially aluminum-free (e.g., without Al) nitrides or Ti- or Ta-based alloys, such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium-gold alloy (Ti-Au), titanium-copper alloy (Ti-Cu), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum-gold alloy (Ta-Au), and tantalum-copper (Ta-Cu).In some embodiments, the WFM layer may contain titanium-aluminum (TiAl), titanium-aluminum carbide (TiAlC), tantalum-aluminum (TaAl), tantalum-aluminum carbide (TaAlC), aluminum-doped titanium, aluminum-doped TiN, aluminum-doped titanium, aluminum-doped TaN, or other suitable aluminum-based materials. In some embodiments, the gate metal fill layer may contain a suitable conductive material, such as tungsten (W), titanium (Ti), silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), aluminum, iridium (Ir), nickel (Ni), metal alloys, and a combination thereof.

[0020] Outer gate spacers 112 can electrically isolate gate structures 110 from adjacent S / D regions 116 and contact structures 128. Inner gate spacers 114 can electrically isolate gate sections between nanostructured channel regions 108A-108C from adjacent S / D regions 116. In some embodiments, each of the inner gate spacers 114 can have a thickness T1 of approximately 4 nm to approximately 6 nm. Within this thickness range, inner gate spacers 114 can adequately electrically isolate gate sections from adjacent S / D regions 116 without affecting the device size and manufacturing costs. In some embodiments, outer gate spacers 112 and inner gate spacers 114 can contain a dielectric material such as SiO2, SiN, SiON, SiCN, and SiOCN.

[0021] In some embodiments, S / D regions 116 can contain an epitaxially grown semiconductor material, such as Si, and n-type dopants, such as phosphorus and other suitable n-type dopants for n-GAA-FET 100. S / D regions 116 can contain an epitaxially grown semiconductor material, such as Si and SiGe, and p-type dopants, such as boron and other suitable p-type dopants for p-GAA-FET 100.

[0022] In some embodiments, S / D regions 116 are formed epitaxially along sidewalls of nanostructured channel regions 108A-108C, as in Fig. 1A, Fig. 1B, Fig. 1E and Fig. Figure 1H shows that to ensure adequate sidewall coverage of top nanostructured channel regions 108A by S / D regions 116 for adequate conductivity between them, S / D regions 116 are extended over the cover surfaces of top nanostructured channel regions 108A. As a result, extended S / D sections 116a overlap with adjacent conductive layers 110C of gate structures 110 along a vertical cross-sectional plane (e.g., the XZ plane), which can lead to parasitic capacitance between gate structures 110 and S / D regions 116. To prevent or minimize such parasitic capacitance between gate structures 110 and S / D regions 116, the thickness T2 of extended S / D sections 116a can be approximately 2 nm to approximately 8 nm.In some embodiments, when the thickness T2 is below approximately 2 nm, the sidewalls of the uppermost nanostructured channel regions 108A cannot be adequately covered by S / D regions 116, which degrades the performance of the GAA-FET 100. Conversely, when the thickness T2 is above approximately 8 nm, the overlapping regions between gate structures 110 and S / D regions 116 increase, and consequently, the parasitic capacitance between the gate structures 110 and S / D regions 116 increases by approximately 2% to approximately 3% or more. Furthermore, when the thickness T2 is above approximately 8 nm, forming gate structures 110 with shorter heights to miniaturize the GAA-FET 100 to meet the increasing demand for small and portable semiconductor devices becomes challenging.If the thickness T2 of extended S / D sections 116a is kept within the range of about 2 nm to about 8 nm, the heights of gate structures 110 can be reduced from a height of about 12 nm to about 16 nm to a height H1 of about 8 nm to about 12 nm, while the parasitic capacitance between gate structures 110 and S / D regions 116 is reduced by about 2% to about 3% or more.

[0023] In some embodiments, to further ensure adequate sidewall coverage of uppermost nanostructured channel regions 108A by S / D regions 116, S / D cover surfaces 116t of S / D regions 116 can be formed with W-shaped cross-sectional profiles (also referred to as “etch profiles”) along vertical cross-sectional planes (e.g., XZ and YZ planes), as shown in Fig. Figures 1A-1D and 1H show this. In some embodiments, S / D cover surfaces 116t can be formed not with W-shaped cross-sectional profiles, but with concave cross-sectional profiles along vertical cross-sectional planes (e.g., XZ and YZ planes), as shown in Fig. Figures 1E-1G show that for the W-shaped or concave cross-sectional profiles of S / D cover surfaces 116t along XZ planes, the edges of S / D cover surfaces 116t can be raised above the cover surfaces of uppermost nanostructured channel regions 108A, and the middle sections of S / D cover surfaces 116t can have convex or concave profiles.

[0024] In some embodiments, intermediate layers 118 can be arranged below S / D regions 116 and in recessed areas of fin-shaped base structures 106. In some embodiments, intermediate layers 118 can prevent the diffusion of dopants from S / D regions 116 to fin-shaped base structures 106, thereby preventing leakage current between adjacent S / D regions 116 and short-channel effects in GAA-FET 100. In some embodiments, the intermediate layer 118 can consist of multiple layers containing an undoped semiconductor layer 118A and a dielectric layer 118B. In some embodiments, the intermediate layer 118 can be an undoped semiconductor layer or a dielectric layer. The undoped semiconductor layer can be an undoped silicon or silicon-germanium layer.

[0025] In some embodiments, undoped semiconductor layers 118A can be arranged in the recessed regions of fin-shaped base structures 106. In some embodiments, undoped semiconductor layers 110A can comprise undoped silicon or another suitable undoped semiconductor material. In some embodiments, undoped semiconductor layers 118A can extend into the fin-shaped base structures 106 over a distance of about 20 nm to about 40 nm. In some embodiments, if the distance is less than about 20 nm, undoped semiconductor layers 111A cannot adequately prevent the diffusion of dopants from S / D regions 116 to the fin-shaped base structures 106. On the other hand, if the distance is greater than about 40 nm, the processing time (e.g., etching time, deposition time) for forming undoped semiconductor layers 118A increases, and consequently, the manufacturing costs of GAA-FET 100 increase.

[0026] In some embodiments, dielectric layers 118B can be arranged directly on undoped semiconductor layers 118A and along sidewalls of the lowest inner spacers 114. In some embodiments, each dielectric layer 111B can contain a nitride material such as SiN, SiO2, SiON, SiCON, SiOC, and SiCN. In some embodiments, each dielectric layer 118B can contain a silicon-rich dielectric material. In some embodiments, the silicon-rich dielectric material can be (i) silicon-rich nitride (Si x N y ) with a concentration of silicon atoms that is higher than the concentrations of nitrogen atoms, (ii) silicon-rich oxynitride (Si x O y N z ) with a concentration of silicon atoms that is higher than the concentrations of oxygen and nitrogen atoms, (iii) silicon-rich oxycarbide (Si x O y C z) with a concentration of silicon atoms that is higher than the concentrations of oxygen atoms and carbon atoms, (iv) silicon-rich oxycarbonitride (Si w O x C y N z ) with a concentration of silicon atoms that is higher than the concentrations of oxygen atoms, carbon atoms and nitrogen atoms, (v) silicon-rich boron oxynitride (Si w B x O y N z ) with a concentration of silicon atoms that is higher than the concentrations of oxygen atoms, boron atoms and nitrogen atoms, (vi) silicon-rich boron oxycarbide (Si w B x O y C z) with a concentration of silicon atoms that is higher than the concentrations of oxygen atoms, boron atoms, and carbon atoms, or (vii) other suitable silicon-rich dielectric materials based on nitride or carbide. The silicon-rich dielectric material of dielectric layer 118B can impart high etch resistance to dielectric layer 118B during its formation. In some embodiments, each dielectric layer 118B can have a thickness T3 of about 2 nm to about 8 nm. Within this thickness range, dielectric layers 118B can adequately prevent the diffusion of dopants from S / D regions 116 to semiconductor layers 111A without affecting the device size and manufacturing cost of GAA-FET 100.

[0027] In some embodiments, (i) ESLs 120A can be arranged directly on S / D regions 116 and STI regions 104, (ii) ILD layers 122A can be arranged directly on ESLs 120A, (iii) ESLs 120B can be arranged directly on etch control layers 124, gate structures 110, outer gate spacers 112, dielectric layers 130, and can surround contact structures 128, and (iv) ILD layers 122B can be arranged directly on ESLs 120B and dielectric layers 130 and can surround contact structures 128. In some embodiments, ESLs 120A and 120B can have a thickness of about 3 nm to about 6 nm. In some embodiments, ILD layers 122B can have a thickness T5 of about 10 nm to about 20 nm. In some embodiments, ESLs 120A and 120B and ILD layers 122A and 122B may contain dielectric material such as SiO2, SiN, SiON, SiCN, SiOC and SiOCN.

[0028] In some embodiments, etch control layers 124 can be arranged directly on (i) S / D cover surfaces 116t, (ii) cover surfaces of ESLs 120A, and (iii) cover surfaces of ILD layers 122A. Etch control layers can be used to control the etch profiles of contact openings 1038 (described with reference to Fig. 10A-10C) in S / D regions 116. Additionally, etch control layers 124 can be used to prevent the formation of dielectric layers 130 around sections of contact structures 128 in S / D regions 116. The presence of dielectric layers 130 around sections of contact structures 128 in S / D regions can create undesirable barriers to electron conduction between contact structures 128 and the top nanostructured channel regions 108A. Thus, the electrical conductivity between contact structures 128 and the top nanostructured channel regions 108A can be improved by using etch control layers 124. Furthermore, etch control layers 124 can be used to control the heights of sections of contact structures 128 formed on ESLs 120A and ILD layers 122A between adjacent S / D regions 116, as described in detail below.By controlling these heights, the parasitic capacitance between these sections of contact structures 128 and S / D regions 116 can be controlled. In some embodiments, by using etch control layers 124, sections of contact structures 128 on ESLs 120A and ILD layers 122A with a height H2 of about 15 nm to about 65 nm can be formed to reduce the parasitic capacitance between these sections of contact structures 128 and S / D regions 116 by about 1% to about 4%. In some embodiments, etch control layers 124 can have a thickness T4 of about 4 nm to about 14 nm.Within this thickness range T4, etch control layers 124 can adequately (i) control the etch profiles of contact orifices 1038, (ii) prevent the formation of dielectric layers 130 in S / D regions 116, and (iii) control the heights of contact structures 128 formed on ESLs 120A and ILD layers 122A without affecting the device size and manufacturing cost of GAA-FET 100. In some embodiments, etch control layers 124 can contain a dielectric material different from the dielectric materials of ESLs 120A and 120B. In some embodiments, etch control layers 124 can include SiN layers.

[0029] In some embodiments, in addition to gate spacers 112, ESLs 120A, and ILD layers 122A, gate structures 110 can be electrically isolated from one another by device isolation structures 126 to provide independently controlled gate structures. Device isolation structures 126 can be formed in a cut-metal-gate (CMG) process to cut long gate structures (e.g., along a Y-axis) into shorter gate structures, such as gate structures 110. In some embodiments, each device isolation structure 126 can have an oxide filler layer 126A and a nitride lining 126B surrounding the oxide filler layer 126A. In some embodiments, oxide filling layers 126A may contain SiO2 or SiO2-based material (e.g. silicon oxycarbide) and nitride linings 126B may contain SiN material.In some embodiments, each device isolation structure 126 can have a width W1 of about 21 nm to about 33 nm and a height H3 of about 110 nm to about 160 nm. Within these ranges of width W1 and height H3, device isolation structures 126 can provide adequate electrical isolation for gate structures 110 from each other without affecting the device size and manufacturing cost of GAA-FET 100.

[0030] In some embodiments, the contact structure 128 can be arranged on one or more S / D areas 116 of GAA-FET 100, as shown in Fig. 1A, Fig. 1B, Fig. 1C, Fig. 1E, Fig. 1F and Fig. 1H shown. Some S / D areas 116 may not have contact structures 128 arranged on them, as shown in Fig. 1D and Fig. Figure 1G shows that in some embodiments, first contact sections 128t (also referred to as "upper contact sections 128t") of contact structures 128 can extend over S / D cover surfaces 116t, and second contact sections 128b (also referred to as "bottom contact sections 128b") of contact structures 128 can extend below S / D cover surfaces 116t. In some embodiments, upper contact sections 128t can be surrounded by dielectric layers 130, and bottom contact sections 128b can be surrounded by S / D regions 116. In some embodiments, each bottom contact section 128b can have a height H4 of about 1 nm to about 45 nm and a width W2 of about 10 nm to about 16 nm along an XZ plane. Within these areas of height H4 and width W2, a large contact area can be formed between contact structures 128 and S / D areas 116 without affecting the device size and manufacturing costs of GAA-FET 100.In some embodiments, ground contact sections 128b of different contact structures 128 can have the same height H4 and width W2 as in . Fig. 1B and Fig. 1E shown. In some embodiments, ground contact sections 128b of different contact structures 128 can have different heights and widths, as shown in Fig. 1H shown. For example, ground contact sections 128b of one of the contact structures 128 can have a height H4 and width W2, and ground contact sections 128b of another of the contact structures 128 can have a height H5 and a width W3, as shown in Fig. 1H shown. In some embodiments, height H5 can be greater than height H4 and width W3 can be greater than width W2.

[0031] In some embodiments, each contact structure 128 can (i) comprise a silicide layer 128A arranged in S / D region 116, and (ii) a conductive layer 128B arranged on top of the silicide layer 128A. In some embodiments, each silicide layer 128A can (i) have a thickness T6 of about 2 nm to about 6 nm, (ii) have a U-shaped cross-sectional profile along an XZ plane (shown in Fig. 1B, Fig. 1E and Fig. 1H) and (iii) a W-shaped cross-sectional profile along a YZ plane (shown in Fig. 1C) or a concave cross-sectional profile along a YZ plane (shown in Fig. 1F). In some embodiments, silicide layers 128A in the n-GAA-FET 100 titanium silicide (Ti) can be present. x Si y ), tantalum silicide (Ta x Si y ), Molybdenum (Mo x Si y ), Zirconium silicide (Zr x Si y ), Hafnium silicide (Hf x Si y ), Scandium silicide (Sc x Siy ), Yttrium silicide (Y x Si y ), Terbium silicide (Tb x Si y ), Lutetium silicide (Lu x Si y ), erbium silicide (Er x Si y ), Ybtterbium silicide (Yb x Si y ), Europium silicide (Eu x Si y ), thorium silicide (Th x Si y ), other suitable metal silicide materials, or a combination thereof. In some embodiments, the silicide layer 124A in the p-GAA-FET 100 may contain nickel silicide (Ni). x Si y ), cobalt silicide (Co x Si y ), Manganous silicide (Mn x Si y ), tungsten silicide (W x Si y ), iron silicide (Fe x Si y ), Rhodium silicide (Rh x Si y ), palladium silicide (Pd x Si y ), ruthenium silicide (Ru x Si y ), platinum silicide (Pt x Si y ), Iridium silicide (Ir x Si y), Osmium silicide (Os x Si y ), other suitable metal silicide materials or a combination thereof. In some embodiments, conductive layers 128B may contain conductive materials such as Co, W, Ru, Al, Mo, Ir, Ni, Osmium (Os), Rhodium (Rh), other suitable conductive materials and a combination thereof.

[0032] In some embodiments, dielectric layers 130 can be arranged on S / D cover surfaces 116t and surround upper contact sections 128t. Dielectric layers 130 can (i) prevent or minimize the diffusion of oxygen atoms from ILD layers 122B into conductive layers 128B and (ii) prevent or minimize the diffusion of metal atoms from conductive layers 128B into gate structures 110. In some embodiments, dielectric layers 130 can comprise oxygen-free dielectric nitride layers (e.g., SiN layers), oxygen-free dielectric carbide layers (e.g., silicon carbide layers (SiC layers)), or oxygen-free carbonitride layers (e.g., silicon carbonitride layers (SiCN layers)).In some embodiments, dielectric layers 130 may have a thickness T7 of about 1 nm to about 3 nm to adequately prevent or minimize (i) the diffusion of oxygen atoms from ILD layers 122B into conductive layers 128B and (ii) the diffusion of metal atoms from conductive layers 128B into gate structures 110.

[0033] Fig. Figure 2 is a flowchart of an exemplary process 200 for manufacturing a GAA-FET 100, as described above with reference to Fig. 1A-1H described, according to some embodiments. For illustrative purposes, the Fig. Section 2 will describe the illustrated processes with reference to the exemplary manufacturing process for producing a GAA-FET 100, as described in Fig. 3A-14A, 3B-14B, 3C-14C, 15 and 16 illustrated. Fig. Figures 3A-14A are isometric views of GAA-FET 100 at various manufacturing stages, according to some embodiments. Fig. Figures 3B-14B, 15 and 16 are cross-sectional views of GAA-FET 100 along line AA of Fig. 1A in various manufacturing stages, according to some embodiments. Fig. 3C-14C are cross-sectional views of GAA-FET 100 along line BB of Fig. 1A in various manufacturing stages, according to some embodiments. Operations may be performed in a different sequence or not performed at all, depending on specific applications. It should be noted that Process 200 cannot produce a complete GAA-FET 100. Therefore, it is clear that additional processes may be provided before, during, and after Process 200, and that some other processes can only be briefly described here. The explanation of elements in Fig. 1A-1H, 3A-14A, 3B-14B, 3C-14C, 15 and 16 with the same designations apply to the others unless otherwise stated.

[0034] With reference to Fig. In process 205, superlattice structures are formed on fin-shaped base structures, and polysilicon structures and outer gate spacers are formed on the superlattice structures. For example, as described with reference to Fig. As described in sections 3A-3C, superlattice structures 309 (also referred to as "nanosheet stacks 309") are formed on fin-shaped base structures 106, and polysilicon structures 310 are formed on superlattice structure 309. Superlattice structures 309 and polysilicon structures 310 are shown in cross-sectional view in [reference missing]. Fig. 3C not visible. In some embodiments, hard mask layers 332 and 334 can be formed during the formation of polysilicon structures 310. Superlattice structures 309 can comprise nanostructured layers 108A-108C and nanostructured sacrificial layers 308 arranged in an alternating configuration. In some embodiments, nanostructured layers 108A-108C can contain Si and nanostructured sacrificial layers 308 can contain SiGe. In some embodiments, each of the nanostructured layers 108A-108C and nanostructured sacrificial layers 308 can have a thickness of about 3 nm to about 15 nm along a Z-axis. During subsequent processing, polysilicon structures 310 and nanostructured sacrificial layers 308 can be replaced by gate structures 110 in a gate replacement process.

[0035] With reference to Fig. In process 210, inner gate spacers and S / D regions are formed in the superlattice structures. For example, as described with reference to Fig. As described in sections 3A-3C, inner gate spacers 114 and S / D regions 116 are formed in superlattice structures 309. Inner gate spacers 114 are shown in cross-sectional view in Fig. 3C not visible. In some embodiments, S / D openings (not shown) can be formed in superlattice structures 309, followed by the formation of isolation trenches (not shown) in fin-shaped base structures 106. The formation of isolation trenches can be followed by the formation of inner gate spacers 114 along sidewalls of nanostructured sacrificial layers 308, as shown in Fig. 3A and Fig. Figure 3B shows that the formation of inner gate spacers 114 can be followed by the formation of intermediate layers 118 in the isolation trenches, whereupon the epitaxial growth of S / D regions 116 in the S / D openings can occur. In some embodiments, S / D regions 116 can extend over superlattice structures 309, and the elongated S / D sections 116a can be formed with a thickness T8 of about 4 nm to about 12 nm, as shown in Figure 3B. Fig. Figure 3B shows that the formation of S / D regions 116 can be followed by the formation of ESLs 120A and ILD layers 122A on S / D regions 116, as shown in Fig. 4A-4C shown.

[0036] With reference to Fig. In process 215, sections of the S / D regions extending over the superlattice structures are modified. For example, as described with reference to Fig. As described in Figures 5A-7A, 5B-7B, and 5C-7C, extended S / D sections 116a can be modified to reduce their thickness from thickness T8 to thickness T2. In some embodiments, the modification of extended S / D sections 116a can include successive operations to (i) perform a first etching process on the structures of Fig. 4A-4C, to remove sections of ILD layers 122A and expose sections of ESLs 120A on extended S / D sections 116a, as in Fig. 5A-5C shown, (ii) performing a second etching process on the structures of Fig. 5A-5C to remove the exposed sections of ESLs 120A and expose extended S / D sections 116a, as in Fig. 6A-6C shown, and (iii) performing a third etching process on the structures of Fig. 6A-6C, to etch extended S / D sections 116a and reduce their thicknesses from thickness T8 to thickness T2, as in Fig. Figures 7A-7C show that in some embodiments, the third etching process may comprise a dry etching process using etching gases such as tetrafluoromethane (CF4) and nitrogen trifluoride (NF3) with mixed gases such as hydrogen (H2) and argon (Ar). In some embodiments, the third etching process may comprise a wet etching process using a mixture of ammonia hydroxide (NH4OH) with H2O2 and deionized (DI) water. In some embodiments, depending on the etching parameters of the third etching process, S / D cover surfaces 116t of extended S / D sections 116a with W-shaped cross-sectional profiles may be formed, as shown in Figures 7A-7C. Fig. 7A-7C shown, or can be formed with concave cross-sectional profiles, as in Fig. 1E-1G shown.

[0037] With reference to Fig. 2. In process 220, etch control layers are formed on the modified sections of the S / D areas. As, for example, with reference to Fig. As described in Figures 8A-8C, etch control layers 124 are formed on extended S / D sections 116a that are modified. The formation of etch control layers 124 can involve successive processes for (i) depositing a dielectric nitride layer (e.g., a SiN layer, not shown) on the structures of Fig. 7A-7C and (ii) performing a chemical-mechanical polishing process (CMP process) on the dielectric nitride layer to modify the structures of Fig. 8A-8C to form. In some embodiments, after the CMP process, the cover surfaces of etch control layers 124, outer gate spacers 112 and polysilicon structures 310 can be essentially coplanar to each other.

[0038] With reference to Fig. In process 225, the polysilicon structures and nanostructured sacrificial layers of the superlattice structures are replaced by gate structures. For example, with reference to Fig. As described in 9A-9C, polysilicon structures 310 and nanostructured sacrificial layers 308 are replaced by gate structures 110 (in cross-sectional view of Fig. 9C not visible). The formation of gate structures 110 can remove polysilicon structures 310 and nanostructured sacrificial layers 308 from the structures of Fig. 8A and Fig. 8B, to form gate openings (not shown), and forming gate structures 110 in the gate openings include, as in Fig. 9A and Fig. Figure 9B shows that in some embodiments, the cover surfaces of etch control layers 124, outer gate spacers 112, and gate structures 110 can be substantially coplanar with each other. In some embodiments, the formation of gate structures 110 can be followed by the formation of device isolation structures 126, as shown in Figure 9B. Fig. 9A and Fig. 9C shown (device isolation structures 126 are shown in cross-sectional view of Fig. 9B not visible). The formation of device isolation structures 126 can be achieved by the deposition of ESLs 120B, ILD layers 122B and a hard mask layer 1036 on the structures of Fig. 9A-9C follow. In some embodiments, the hard mask layer 1036 may contain a tungsten carbide layer (WC layer).

[0039] With reference to Fig. 2. In process 230, contact structures are formed on the S / D areas. For example, with reference to Fig. As described in 10A-14A, 10B-14B and 10C-14C, contact structures 1128 are formed on S / D regions 116. The formation of contact structures 128 can involve successive processes for (i) performing an initial etching process to remove sections of hard mask layer 1036, ILD layers 122B, ESLs 120B and etch control layers 124 on S / D regions 116 to form contact openings 1038 on S / D regions 116, as described in Fig. 10A-10C shown, (ii) removal of hard mask layer 1036 (not shown), (iii) deposition of a dielectric nitride layer 1040 on cover surfaces of ILD layers 122B and on the exposed surfaces of ILD layers 122B, ESLs 120B, etch control layers 124, ILD layers 122A, ESLs 120A and S / D regions 116 in contact openings 1038, as shown in Fig. 11A-11C shown, (iv) performing a second etching process on the structures of Fig. 11A-11C to form dielectric layers 130 and to extend contact openings 1038 into S / D regions 116 by a depth D1, as shown in Fig. 12A-12C shown, (v) performing a third etching process on exposed S / D regions 116 in contact openings 1038 to increase the depth of contact openings 1038 from depth D1 to depth D2, as shown in Fig. 13A-13C shown, (vi) Formation of silicide layers 128A in contact openings 1038, as shown in Fig. 14A-14C shown, and (vii) forming conductive layers 128B on silicide layers 128A, as shown in Fig. Figures 14A-14C show that the following are included. In some embodiments, after the formation of conductive layers 128B, the cover surfaces of conductive layers 128B, ILD layers 122B and dielectric layers 130 can be substantially coplanar with each other.

[0040] In some embodiments, the second etching process may comprise a dry etching process using etching gases such as fluoromethane (CH3F), hexafluorocyclobutene (C4F6), and carbonyl sulfide (COS) with mixed gases such as H2 and nitrogen (N2), followed by a post-cleaning process using deionized water (DI water). In some embodiments, the third etching process may comprise a dry etching process using an etching gas such as CF4 and a mixed gas such as Ar, followed by a post-cleaning process using a hydrogen fluoride solution (HF solution).

[0041] In some embodiments, GAA-FET 100 can be shown with the cross-sectional view of Fig. 1H are formed using method 200, except that in process 230, (i) the third etching process may be followed by a fourth etching process on one or more S / D areas 116 to increase the depth of one or more contact openings 1038 from depth D2 to depth D3, as in Fig. 15 shown, and (ii) silicide layers 128A and conductive layers 128B in contact openings 1038 of Fig. 15 can be formed to structure the Fig. 16 to form. In some embodiments, the fourth etching process may include a dry etching process using an etching gas such as CF4 and a mixed gas such as Ar, which may be followed by a post-cleaning process using HF solution.

[0042] The present disclosure provides exemplary GAA-FETs (e.g., GAA-FET 100) with reduced parasitic capacitance between a gate structure and an S / D region and exemplary methods for fabricating these GAA-FETs. In some embodiments, the formation of the S / D region (e.g., S / D regions 116) can be followed by an etching process on the S / D region to reduce the thickness of the extended S / D section (e.g., extended S / D sections 116a) without affecting the sidewall coverage of the nanostructured channel regions (nanostructured channel regions 108A-108C) by the S / D region. In some embodiments, to ensure adequate sidewall coverage of the nanostructured channel regions by the S / D region, the etching process can be controlled to achieve W-shaped or concave cross-sectional profiles along vertical cross-sectional planes (e.g., XZ and YZ planes) for the S / D cover surface (e.g., S / D cover surfaces 116t).In some embodiments, for the W-shaped or concave cross-sectional profiles of the S / D cover surface extending between adjacent nanostructured channel regions, the edges of the S / D cover surface can be raised above the cover surfaces of the uppermost nanostructured channel regions (e.g., uppermost nanostructured channel regions 108A), and the central section of the S / D cover surface can have a convex or concave profile. In some embodiments, during the etching process, the thickness of the extended S / D section can be reduced from a first thickness (e.g., thickness T8) of approximately 4 nm to approximately 12 nm to a second thickness (e.g., thickness T2) of approximately 2 nm to approximately 8 nm. Such a reduction in the thickness of the extended S / D section can result in a reduction of the parasitic capacitance between the S / D region and the gate structures by approximately 2% to approximately 3%.In some embodiments, reducing the thickness of the extended S / D section can also facilitate the formation of gate structures with lower heights (e.g., height H1), which makes it easier to miniaturize GAA-FETs to meet the ever-increasing demand for small and portable semiconductor devices.

[0043] In some embodiments, the etching process can be followed by the formation of an etch control layer (e.g., etch control layers 124) on the S / D top surface and on top surfaces of an ESL (e.g., ESLs 120A) and ILD layer (e.g., ILD layers 122A) arranged on the S / D area. The etch control layer can preserve the integrity of the edge profiles of the S / D top surface during subsequent processes on the S / D area. In some embodiments, the etch control layer can also facilitate the formation of a deep contact opening (e.g., contact openings 1038) in the S / D area while preventing the ESL and ILD layer from being over-etched during the formation of the contact opening. As a result, a contact structure (e.g.,Contact structures 128) are formed on the S / D region with a larger contact area with the S / D region, while the section of the contact structure on the ESL and ILD layer can have a shallower depth than that formed without the barrier layer on the S / D region. In some embodiments, due to such a shallow depth of the contact structure, the parasitic capacitance between the S / D region and the section of the contact structure on the ESL and ILD layer can be reduced by about 1% to about 4%. Therefore, the total parasitic capacitance of the GAA-FET can be reduced by about 3% to about 7%.

[0044] In some embodiments, a method comprises forming a superlattice structure with a nanostructured layer and a nanostructured sacrificial layer on a base structure on a substrate, forming a polysilicon structure on the superlattice structure, and forming a S / D region within the superlattice structure. An S / D portion of the S / D region extends over the nanostructured layer. The method further comprises modifying the thickness of the S / D portion, depositing a dielectric layer on the modified S / D portion, and replacing the polysilicon structure and the nanostructured sacrificial layer with a gate structure.

[0045] In some embodiments, a method comprises forming a stack of nanostructured layer and nanostructured sacrificial layer on a base structure on a substrate, forming a polysilicon structure surrounding the stack of nanostructured layer and nanostructured sacrificial layer, epitaxially growing an S / D region adjacent to the nanostructured layer, modifying a cross-sectional profile of an S / D segment of the S / D region extending over the nanostructured layer, and replacing the polysilicon structure and the nanostructured sacrificial layer with a gate structure.

[0046] In some embodiments, a semiconductor device comprises a substrate, a nanostructured channel region arranged on the substrate, and a S / D region arranged adjacent to the nanostructured channel region. An S / D portion of the S / D region extends over the nanostructured layer, and a top surface of the S / D portion has a W-shaped or concave cross-sectional profile. The semiconductor device further comprises a first dielectric layer arranged on the side walls of the S / D region and a second dielectric layer arranged on the top surface of the S / D portion and the first dielectric layer. The materials of the first and second dielectric layers differ from each other.

[0047] The foregoing outlines features of some embodiments so that those skilled in the art will better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can already use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or obtain the same advantages as the embodiments presented herein. Those skilled in the art should also recognize that such equivalent designs do not deviate from the nature and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without deviating from the nature and scope of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 712,667

[0001] Cited non-patent literature

[0000] Epitaxial Structures in Semiconductor Devices”, submitted on October 28, 2024

[0001]

Claims

[1] Procedure, encompassing: Forming a superlattice structure with a nanostructured layer and a nanostructured sacrificial layer on a base structure on a substrate; Forming a polysilicon structure on the superlattice structure; Forming a source / drain region in the superlattice structure, wherein a source / drain section of the source / drain region extends over the nanostructured layer; Modifying the thickness of the source / drain section; Deposition of a dielectric layer on the modified source / drain section; and Replacing the polysilicon structure and the nanostructured sacrificial layer with a gate structure. [2] Method according to claim 1, wherein modifying the thickness of the source / drain section comprises performing an etching process on the source / drain section. [3] Method according to claim 1 or 2, wherein modifying the thickness of the source / drain section comprises reducing the thickness of the source / drain section. [4] Method according to any of the preceding claims, further comprising depositing an etch stop layer on the source / drain region prior to modifying the thickness of the source / drain section. [5] Method according to claim 4, wherein modifying the thickness of the source / drain section comprises etching the etch stop layer to expose the source / drain section. [6] Method according to any of the preceding claims, wherein the deposition of the dielectric layer comprises the deposition of a silicon nitride layer on the modified source / drain section. [7] Method according to any of the preceding claims, wherein modifying the thickness of the source / drain section comprises modifying a cross-sectional profile of a cover surface of the source / drain section. [8] Method according to any of the preceding claims, further comprising forming a silicide layer in the source / drain region, wherein the silicide layer comprises: a W-shaped cross-sectional profile along a first cross-sectional plane; and a U-shaped cross-sectional profile along a second cross-sectional plane. [9] Method according to any of the foregoing claims, further comprising: Performing an initial etching process on the source / drain to create a contact opening in the source / drain area; and Perform a second etching process on the source / drain to increase the depth of the contact opening in the source / drain area. [10] Method according to claim 9, further comprising: Formation of a silicide layer in the contact opening after the second etching process; and Deposition of a conductive layer on the silicide layer. [11] Procedure, encompassing: Forming a stack of a nanostructured layer and a nanostructured sacrificial layer on a base structure on a substrate; Forming a polysilicon structure that surrounds the stack of the nanostructured layer and the nanostructured sacrificial layer; epitaxial growth of a source / drain region next to the nanostructured layer; Modifying a cross-sectional profile of a source / drain segment of the source / drain region extending over the nanostructured layer; and Replacing the polysilicon structure and the nanostructured sacrificial layer with a gate structure. [12] Method according to claim 11, wherein modifying the cross-sectional profile of the source / drain section comprises converting a cover surface of the source / drain section from a convex cross-sectional profile to a W-shaped cross-sectional profile or a concave cross-sectional profile. [13] Method according to claim 11 or 12, wherein modifying the cross-sectional profile of the source / drain section comprises performing an etching process on the source / drain section. [14] Method according to any one of claims 11 to 13, further comprising: Forming a contact opening with a first opening on the source / drain area and a second opening in the source / drain area; Formation of a silicide layer in the second opening; and Deposition of a conductive layer in the first and second openings. [15] Method according to claim 14, further comprising forming a dielectric layer along side walls of the first opening prior to forming the silicide layer. [16] Method according to any one of claims 11 to 15, further comprising depositing a nitride layer on the modified cross-sectional profile of the source / drain section prior to replacing the polysilicon structure and the nanostructured sacrificial layer. [17] Semiconductor device comprising: a substrate; a nanostructured channel area arranged on the substrate; a source / drain region arranged adjacent to the nanostructured channel region, wherein a source / drain section of the source / drain region extends over the nanostructured channel region and wherein a cover surface of the source / drain section has a W-shaped or a concave cross-sectional profile; a first dielectric layer arranged on the sidewalls of the source / drain region; and a second dielectric layer arranged on the top surface of the source / drain section and the first dielectric layer, wherein the materials of the first and second dielectric layers differ from each other. [18] Semiconductor device according to claim 17, further comprising a silicide layer arranged in the source / drain region, wherein the silicide layer comprises: a W-shaped cross-sectional profile along a first cross-sectional plane; and a U-shaped cross-sectional profile along a second cross-sectional plane. [19] Semiconductor device according to claim 17 or 18, further comprising: a contact structure comprising a first contact section located in the source / drain region and a second contact section located on the source / drain region; and a third dielectric layer surrounding the second contact section. [20] Semiconductor device according to claim 19, further comprising an etch stop layer surrounding the third dielectric layer.

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