COMPARATOR WITH MODULARABLE REFERENCE AND REFERENCE OBSERVATION SUPPORT

Abstract

A comparator circuit comprises a matching capacitor in series with a first switching device and a second switching device. The first and second switching devices are connected in parallel between the matching capacitor and a reference voltage. The comparator circuit further comprises a sampling capacitor in series with a third switching device and a fourth switching device. The third switching device is connected in series between the sampling capacitor and a DAC, and the fourth switching device is connected in series between the sampling capacitor and an input voltage. The comparator circuit further comprises a comparator with an inverting input and a non-inverting input. The inverting input is capacitively coupled to the matching capacitor, and the non-inverting input is capacitively coupled to the sampling capacitor.The comparator circuit further includes a fifth switching device and a sixth switching device in series between the matching capacitor and the sampling capacitor.

Description

AREA OF INVENTION

[0001] Embodiments of the present disclosure relate generally to comparators in electronic circuits. In particular, embodiments of the present disclosure relate to a high-speed auto-zero comparator with modulatable reference and reference observability support. BACKGROUND

[0002] A comparator is a device widely used in electronic circuits. It generally compares two voltages or currents and outputs a digital signal indicating which is greater. A comparator typically incorporates a specialized, high-gain differential amplifier and is commonly used in devices that measure and digitize analog signals, such as analog-to-digital converters (ADCs) and relaxation oscillators.

[0003] In certain applications (e.g., automotive, industrial, microcontrollers, programmable system-on-a-chip (PSoC), etc.), a high-bandwidth voltage-to-pulse-width modulation (PWM) transfer function is required to support specific switching loop implementations. These applications also require a precision event detection mechanism (e.g., overvoltage or overcurrent) to achieve fast fault detection and accuracy.

[0004] To meet these requirements, a precision comparator with a modulatable reference (e.g., by means of digital-to-analog converter (DAC) controls), such as a high-speed auto-zero comparator circuit 100 with a dedicated auto-zero phase, which is in Fig. 1 is illustrated, can be used.

[0005] As in Fig. As shown in Figure 1, the comparator circuit 100 comprises a comparator 102 connected to input terminals 121-122 (e.g., inverting and non-inverting terminals) that are capacitively coupled to the matching capacitor 101 and the sampling capacitor 111 of the comparator circuit 100. The comparator 102 provides complementary output signals at the output terminal 123 by comparing input signals applied to the input terminals 121-122. The matching capacitor 101 (also called a reactive capacitor) and the sampling capacitor 111 can have the same capacitance value. As further shown in Figure 1, the comparator circuit 100 can be connected to the input terminals 121-122. Fig. As shown in Figure 1, the comparator circuit 100 further comprises switches 103-104, which are connected in series between the matching capacitor 101 and the sampling capacitor 111, with the matching capacitor 101 connecting between ground (GND) and switch 103. The input terminal 121 is also connected to a node between the matching capacitor 101 and switch 103, and the input terminal 122 is also connected to a node between switch 104 and the sampling capacitor 111. A common-mode voltage (VCM) is connected to a node between switch 103 and switch 104.

[0006] Furthermore, the comparator circuit 100 also includes a switch 105, which is connected between the input voltage VIN and the sampling capacitor 111, and switches 106-107, which are connected in series between GND and a node between switch 105 and the sampling capacitor 111. The comparator circuit 100 further includes a capacitive digital-to-analog converter (CAPDAC) 120, which is connected to a node between the sampling capacitor 111 and the input terminal 122. As shown, the CAPDAC 120 includes a capacitor (or capacitor array) 112 and an array of switches 108-110. Switch 108 is connected in series with the capacitor array 112 between GND or reference voltage high (VREFH) and the node between the sampling capacitor 111 and the input terminal 122. Switches 109-110 are connected in parallel between VREFH and a node between capacitor 112 and switch 108 to form a capacitive DAC.

[0007] During the auto-zero phase, switches 103, 104, 106, 107, and 110 are closed, and the idle state is open. During the sampling phase, switches 103, 105, and 110 are closed. During the resolution phase, switches 106 and 107 are closed, and the DAC switch array (108, 109) is configured to inject a reference voltage in the form of a charge, causing a voltage across switch 104 to be resolved by comparator 102 at its output terminal 123.

[0008] Unfortunately, in the architecture of comparator circuit 100 VREFH, an observable gain error exists due to a mismatch between the sampling capacitor 111 and the CAP DAC 120. The sampling capacitor used is increased in size to accommodate the gain error (resulting in a slower DAC transition), and a larger sampling capacitor would correspond to a lower input impedance. Furthermore, the architecture of comparator circuit 100 requires a periodic dedicated auto-zero phase, resulting in a periodic blind zone to accommodate the offset voltage of comparator 102. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the disclosure are illustrated by way of example and without limitation in the figures of the accompanying drawings, in which the same reference numerals indicate similar elements. Fig. Figure 1 is a schematic diagram of a conventional auto-zero comparator circuit with a modulatable reference using a capacitive DAC. Fig. Figure 2 is a schematic diagram of an incremental auto-zero comparator circuit according to one embodiment. Fig. Figure 3A is a schematic diagram illustrating an incremental auto-zero high-speed comparator circuit operating in a sampling phase according to one embodiment. Fig. 3B is a schematic diagram illustrating the incremental auto-zero high-speed comparator circuit of Fig. Figure 3A illustrates a dissolution phase operating according to one embodiment. Fig. 3C is a timing diagram illustrating a clock signal and comparator output signals of the comparator circuit of Fig. 3A- Fig. are assigned to 3B. Fig. Figure 4 is a schematic diagram illustrating an incremental auto-zero high-speed comparator circuit with DAC as a reference according to one embodiment. Fig. Figure 5A is a schematic diagram illustrating an incremental auto-zero high-speed comparator circuit with reference voltage observability according to one embodiment. Fig. 5B is a timing diagram illustrating signals from the comparator circuit of Fig. 5A are assigned, with a windowing phase controlling a switch for reference observability. DETAILED DESCRIPTION

[0010] Various embodiments and aspects of the inventions are described with reference to the details discussed below, and the accompanying drawings illustrate the different embodiments. The following description and drawings illustrate the invention and are not to be construed as limiting the invention. Numerous specific details are described to provide a thorough understanding of various embodiments of the present invention. However, in certain cases, well-known or conventional details are omitted to provide a concise discussion of embodiments of the present inventions.

[0011] Reference in the description to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the invention. The appearance of the phrase "in an embodiment" at various points in the description does not necessarily refer to the same embodiment.

[0012] According to one aspect, a comparator circuit can include a matching capacitor in series with a first switching device and a second switching device. The first and second switching devices can be connected in parallel between the matching capacitor and a reference voltage. The comparator circuit can further include a sampling capacitor in series with a third switching device and a fourth switching device. The third switching device can be in series between the sampling capacitor and a DAC, and the fourth switching device can be in series between the sampling capacitor and an input voltage. The comparator circuit can also include a comparator with an inverting input and a non-inverting input.The inverting input terminal can be capacitively coupled to the matching capacitor, and the non-inverting input terminal can be capacitively coupled to the sampling capacitor. The comparator circuit can further include a fifth switching device and a sixth switching device in series between the matching capacitor and the sampling capacitor.

[0013] According to another aspect, a comparator circuit can comprise a number of cascaded comparator amplifiers. The comparator circuit can further include a matching capacitor in series with a first switching device and a second switching device. The first and second switching devices can be connected in parallel between the matching capacitor and a common-mode voltage. The comparator circuit can further include a sampling capacitor in series with a third switching device and a fourth switching device. The third switching device can be connected in series between the sampling capacitor and an input voltage, and the fourth switching device can be connected in series between the sampling capacitor and a reference voltage. In one embodiment, a first comparator among the cascaded comparator amplifiers can include an inverting input terminal and a non-inverting input terminal.The inverting input terminal can be capacitively coupled to the matching capacitor, and the non-inverting input terminal can be capacitively coupled to the sampling capacitor.

[0014] According to yet another aspect, a comparator circuit can comprise a number of cascaded comparator amplifiers. The comparator circuit can further comprise a matching capacitor in series with a first switching device and a second switching device. The first and second switching devices can be connected in parallel between the matching capacitor and a common-mode voltage. The comparator circuit can further comprise a sampling capacitor in series with a third switching device and a fourth switching device. The third switching device can be connected in series between the sampling capacitor and an input voltage, and the fourth switching device can be connected in series between the sampling capacitor and a DAC. In one embodiment, a first comparator among the cascaded comparator amplifiers can comprise an inverting input and a non-inverting input.The inverting input terminal can be capacitively coupled to the matching capacitor, and the non-inverting input terminal can be capacitively coupled to the sampling capacitor.

[0015] Fig. Figure 2 is a schematic diagram of an incremental auto-zero comparator circuit according to one embodiment. With reference to Fig. 2 The comparator circuit may include, but is not limited to, 200 switches (or switching devices) 201-202, 204-205, 20-208 (e.g., metal-oxide-semiconductor (MOS) switches), an matching capacitor 203, a sampling capacitor 206, a voltage-to-digital-to-analog converter (DAC) 209, and a comparator 210 (e.g., differential amplifiers such as operational amplifiers (op-amplifiers), latch comparators, etc.).

[0016] As shown, the comparator 210 can be connected to input terminals 221-122 (e.g., inverting and non-inverting terminals), which can be capacitively coupled to the matching capacitor 203 and the sampling capacitor 206, respectively. The comparator 210 can provide complementary output signals at the output terminal 211 by comparing input signals applied to the input terminals 221-222. In some embodiments, the matching capacitor 203 and the sampling capacitor 206 can have the same capacitance value. As further shown in Fig. As shown in Figure 2, switches 204-205 can be connected in series between the matching capacitor 203 and the sampling capacitor 206. Switches 201-202 can be connected in parallel between a reference voltage (VREF) and the matching capacitor 203. Switch 207 can be connected in series with the DAC 209 and the sampling capacitor 206, with switch 207 being located between the DAC 209 and the sampling capacitor 206. Switch 208 can be connected in series with the input voltage (VIN) and the sampling capacitor 206, with switch 208 being located between the VIN and the sampling capacitor 206. In this embodiment, the VIN and the DAC 209, along with their input bits, can be interchanged to obtain a complementary comparison.In one embodiment, a circuit connected to the negative input of comparator 221 and a circuit connected to the positive input of comparator 222 can be interchanged to generate the complementary function.

[0017] In one embodiment, the input terminal 221 can also be connected to a node between the matching capacitor 203 and the switch 204, and the input terminal 222 can also be connected to a node between the switch 205 and the sampling capacitor 206. VREF can also be connected to a node between the switch 204 and the switch 205.

[0018] During operation, during the first phase of a clock cycle (e.g., sampling and auto-zero phase φ1), switches 202, 204-205, and 208 can be turned on (closed), and switches 201 and 207 can be turned off (open). During the second phase of the clock cycle (e.g., resolution phase φ2), switches 202, 204-205, and 208 can be turned off (open), and switches 201 and 207 can be turned on (closed) to connect DAC 209 to sampling capacitor 206 and VREF to matching capacitor 201. In this scenario, sampling capacitor 206 can be used to compare VIN with a DAC voltage generated by the configuration value of the DAC input bits.

[0019] In one embodiment, the comparator circuit 200 can further comprise a windowed sampling mechanism for a DAC voltage, which includes a resistor 223, a switch (or switching device) 224, and a DAC sampling capacitor 225 connected in series between the DAC 209 (and VIN) and GND 226. During the sampling phase, the switch 224 can be turned on (closed) to sample the DAC 209 using the DAC sampling capacitor 225 for DAC observability. This embodiment allows the use of a separate windowing phase (φDAC) to control the switch 224, which may have a delayed rising edge (phase delay) compared to the sampling phase when the DAC 209 is being sampled. Furthermore, a dedicated φDAC phase enables the incremental charging of the DAC sampling capacitor 225 when the DAC 209 is in a transient phase, thus avoiding overshoot / undershoot error integration.

[0020] Using the architecture of comparator 200, there is no blind zone because the incremental auto-zero of the comparator 210's offset voltage is performed at the time of signal sampling (e.g., VIN). Furthermore, the signal sampling (first phase) is followed by a voltage superposition from DAC 209 (second phase) for comparison. In this way, there is no voltage division in the sampling voltage (thus allowing the use of a smaller sampling capacitor), DAC 209 only needs to charge the small parasitic capacitance of sampling capacitor 206 (resulting in a faster transition at relatively low power), and there is no gain error due to non-capacitor mismatch. Moreover, the comparator 200's architecture allows for windowed DAC sampling for DAC observability during operation.Thus, the DAC reference is observable without transient parametric power loss, which is generally a requirement for safety-critical applications.

[0021] Fig. Figure 3A is a schematic diagram illustrating an incremental auto-zero high-speed comparator circuit operating in a sampling phase according to one embodiment. With reference to Fig. 3A includes, but is not limited to, the auto-zero high-speed comparator circuit 300 comparators 309, 314, 319, switches (or switching devices) 301-302, 304-305, 307-308, 312-313, 317-318 (e.g. MOS switches), matching capacitor 303, sampling capacitor 306 and capacitors 310-311, 315-316.

[0022] As shown, comparators (or comparator amplifiers) 309, 314, and 319 can be cascaded to provide greater gain with minimal delay. Output terminals 333–334 of comparator 309 can be capacitively coupled to input terminals 335–336 of comparator 314 via capacitors 310–311. Output terminals 337–338 of comparator 314 can be capacitively coupled to input terminals 339–340 of comparator 319 via capacitors 315–316. In some embodiments, the comparators 309 and 314 can be a preamplifier (e.g., a differential amplifier, such as an operational amplifier) ​​that amplifies the input signals applied to the input terminals 331-332, and the comparator 319 can be a latch comparator (e.g., a Strong-Arm latch) that outputs complementary output signals at the output terminal 320 by comparing the amplified input signals.In one embodiment, each of the terminals 333-340 can be an inverting or non-inverting terminal.

[0023] With further reference to Fig. In 3A, the comparator 309 can be connected to input terminals 331-332 (e.g., inverting and non-inverting terminals), which can be capacitively coupled to the matching capacitor 303 and the sampling capacitor 306, respectively. In some embodiments, the matching capacitor 303 and the sampling capacitor 306 can have the same capacitance value. The switches 304-305 can be connected in series between the matching capacitor 303 and the sampling capacitor 306. A common-mode voltage (CM) can be connected to a node between the switches 304-305. In one embodiment, the switches 301-302 can be connected in parallel between the CM and the matching capacitor 303. The switch 307 can be connected in series with the input voltage (VINP) 321 and the sampling capacitor 306, with the switch 307 being arranged between the VINP 321 and the sampling capacitor 306.The switch 308 can be connected in series with a reference voltage through the voltage DAC 322 and the sampling capacitor 306, with the switch 308 being arranged between the VREF 322 and the sampling capacitor 306.

[0024] In one embodiment, switches 312-313 can be connected in series between capacitor 310 and capacitor 311, with a VCM connected to a node between switch 312 and switch 313. Similarly, switches 317-318 can be connected in series between capacitor 315 and capacitor 316, with a VCM connected to a node between switch 317 and switch 318.

[0025] With further reference to Fig. During a sampling phase, switches 301, 304-305, 307, 312-313, and 317-318 can be switched on (closed), and switches 302 and 308 can be switched off (open) to sample the VINP 321 via the sampling capacitor 306. During the sampling phase, the voltage across the sampling capacitor 306 can be equal to (VCM - VINP). Furthermore, when the VINP is being sampled, the same sampling phase can be used for the auto-zero of comparators 309, 314, and 319. The charge lost in the auto-zero capacitors (e.g., capacitors 310, 311, 315, 318) can also be replenished, or the comparator offset can be incrementally stored in the auto-zero capacitor with each sampling cycle. This incremental automatic zeroing of the offset voltage would eliminate the need for a separate AZ phase, thus avoiding the blind zone for the comparator.

[0026] With reference to Fig. During a resolution phase, switches 301, 304-305, 307, 312-313, and 317-318 can be switched off (open), and switches 302 and 308 can be switched on (closed). During this phase, the voltages at input terminals 331-332 can be used for comparison. In some embodiments, the voltage at input terminal 331 (V) can be N ) and the voltage at the input terminal 332 (V P ) are calculated as follows: VP=(VCM−VINP+VREF) VN=VCM

[0027] Fig. 3C is a timing diagram illustrating a clock signal and comparator output signals, which are generated using a comparator circuit from Fig. 3A- Fig. 3B are associated. In Fig. For example, the clock signal 380 can be used to control switches 301-302, 304-305, 307-308, 312-313, and 317-318. As shown, the clock signal 380 can comprise a variety of sample and auto-zero phases 350A-C (e.g., during low states) and a variety of release phases 351A-C (e.g., during high states). The phase duration 370 of a sample and auto-zero phase and the phase duration 371 of a release phase can each be in the range of nanoseconds (ns), although the embodiments of the disclosure are not limited to this example. Fig. 3C can produce complementary comparator output signals 390 at output terminal 320. The output signals 390 can cover a variety of valid data ranges 360A-C.

[0028] Fig. Figure 4 is a schematic diagram illustrating an incremental auto-zero high-speed comparator circuit with a DAC as a reference according to one embodiment. Fig. 4 is the comparator circuit 400 of the comparator circuit 300 of Fig. 3B similarly. Accordingly, for the sake of brevity, the common components between comparator circuit 400 and comparator circuit 300 (e.g. comparators 309, 314, 319, switches 301-302, 304-305, 307-308, 312-313, 317-318, matching capacitor 303, sampling capacitor 306 and capacitors 310-311, 315-316) are not described again here.

[0029] As in Fig. As shown in Figure 4, an output of the DAC 410 can be used as a reference instead of the VREF 322 (for example, in Fig. (3B shown). In this embodiment, the DAC output is routed across the same (small) sampling capacitor 306 in the resolution phase. Additionally, the architecture of the comparator circuit 400 does not exhibit any voltage division with respect to the sampling capacitor 306, thus eliminating any additional gain error and allowing for a significant reduction in the sampling capacitor value. This architecture also allows the DAC 410 to be easily loaded by the parasitic capacitance of the base plate of the sampling capacitor 306, resulting in a faster DAC crossover response.

[0030] Fig. Figure 5A is a schematic diagram illustrating an incremental auto-zero high-speed comparator circuit with reference voltage observability according to one embodiment. Fig. 5A is the comparator circuit 500 of the comparator circuit 400 of Fig. 4 similarly. Accordingly, for the sake of brevity, the common components between comparator circuit 500 and comparator circuit 400 (e.g. comparators 309, 314, 319, switches 301-302, 304-305, 307-308, 312-313, 317-318, matching capacitor 303, sampling capacitor 306, capacitors 310-311, 315-316 and DAC 410) are not described again here.

[0031] As in Fig. As shown in Figure 5A, the comparator circuit 500 can, in addition to the components shown in comparator circuit 400, also include a windowed sampling mechanism 530 of a DAC voltage, comprising a resistor 512, a switch (or switching device) 514, and a DAC sampling capacitor 516 connected in series between the DAC 410 and GND 518. During the sampling phase, the switch 514 can also be turned on (closed) to sample the DAC 410 using the DAC sampling capacitor 516 for DAC observability. This embodiment allows the use of a separate windowing phase (φDAC) to control the switch 514, which may have a delayed rising edge (phase delay) compared to the sampling phase when the DAC 410 is being sampled.Furthermore, a dedicated φDAC phase enables the incremental charging of the DAC sampling capacitor 516 when the DAC 410 is in a transient phase, thus avoiding overshoot / undershoot error integration.

[0032] Fig. 5B is a timing diagram illustrating signals associated with the 500 comparator circuit. Fig. Figure 5B shows an incremental auto-zero concept, where a DAC offset is incrementally stored in an auto-zero capacitor in successive auto-zero phases, so that after a few clock cycles a significant portion of the comparator offset is cleared. As shown, a clock signal 501 can be used to control switches 301-302, 304-305, 307-308, 312-313, 317-318, and 514. The clock signal 501 can include a variety of sampling and auto-zero phases 550A-C (e.g., during low states) and a variety of resolution phases 551A-C (e.g., during high states). The phase duration 540 of a sampling and auto-zero phase and the phase duration 541 of a resolution phase can each be in the range of nanoseconds, although the embodiments of the disclosure are not limited to this example. Fig. 5B can produce complementary comparator output signals 502 at output terminal 320. The output signals 502 can cover a variety of valid data ranges 560A-C.

[0033] As further in Fig. As illustrated in Figure 5B, the sampling phase 503 and the windowing phase (φDAC) 504 can have a delayed rise time 570 to allow the DAC (e.g., DAC 410) to settle before sampling. The sampled DAC voltages are shown in the DAC voltage signal 505, and the voltage signal 590 shows the integrated (or superimposed) DAC voltage across the DAC's sampling capacitor (e.g., sampling capacitor 516).

[0034] Various units, circuits, or other components may be described or claimed to be "configured to" or "configurable to" perform a task or tasks. In such contexts, the expression "configured to" or "configurable to" is used to denote a structure by indicating that the units / circuits / components comprise a structure (e.g., a circuit) that performs the task or tasks during operation. Thus, it can be said that the unit / circuit / component is configured to perform the task, or is configurable to perform the task, even if the specified unit / circuit / component is not currently operating (e.g., is not powered on).The units / circuits / components used with the language "configured to" or "configurable to" include hardware—for example, circuits, memory that stores program instructions executable to implement operation, etc. The statement that a unit / circuit / component is "configured to" perform one or more tasks or "configurable to" perform one or more tasks is expressly not intended to apply to 35 USC 112(f) or 35 USC 112, sixth paragraph, for that unit / circuit / component.

[0035] In the foregoing description, embodiments of the invention have been described with reference to specific exemplary embodiments thereof. It is understood that various modifications can be made to these without deviating from the broader concept and scope of the invention as set forth in the following claims. Accordingly, the description and the drawings are to be considered illustrative and not limiting.

Claims

[1] A comparator circuit comprising the following: a matching capacitor in series with a first switching device and a second switching device, wherein the first and the second switching device are connected in parallel between the matching capacitor and a reference voltage; a sampling capacitor in series with a third switching device and a fourth switching device, wherein the third switching device is connected in series between the sampling capacitor and a digital-to-analog converter (DAC) and the fourth switching device is connected in series between the sampling capacitor and an input voltage; a comparator with an inverting input terminal and a non-inverting input terminal, wherein the inverting input terminal is capacitively coupled to the matching capacitor and the non-inverting input terminal is capacitively coupled to the sampling capacitor; and a fifth switching device and a sixth switching device in series between the matching capacitor and the sampling capacitor. [2] Comparator circuit according to claim 1, wherein the reference voltage is connected to a node between the fifth and the sixth switching device. [3] Comparator circuit according to claim 1, wherein during a sampling phase the second, fourth, fifth and sixth switching devices are closed and the first and third switching devices are open to automatically set an offset voltage of the comparator to zero and to sample the input voltage. [4] Comparator circuit according to claim 1, wherein during a resolution phase the second, fourth, fifth and sixth switching devices are open and the first and third switching devices are closed to charge the sampling capacitor via the DAC. [5] Comparator circuit according to claim 1, further comprising the first, second, third and fourth switching device and the DAC, wherein the first, second, third, fourth, fifth and sixth switching device are selectively open and closed in response to a phase of a clock signal. [6] A comparator circuit comprising the following: a large number of cascaded comparator amplifiers; a matching capacitor in series with a first switching device and a second switching device, wherein the first and the second switching device are connected in parallel between the matching capacitor and a common-mode voltage; and a sampling capacitor in series with a third switching device and a fourth switching device, wherein the third switching device is connected in series between the sampling capacitor and an input voltage and the fourth switching device is connected in series between the sampling capacitor and a reference voltage; wherein a first comparator among the plurality of cascaded comparator amplifiers includes an inverting input terminal and a non-inverting input terminal, wherein the inverting input terminal is capacitively coupled to the matching capacitor and the non-inverting input terminal is capacitively coupled to the sampling capacitor. [7] Comparator circuit according to claim 6, further comprising: the first, the second, the third and the fourth switching device; a fifth switching device and a sixth switching device in series between the matching capacitor and the sampling capacitor. [8] Comparator circuit according to claim 7, wherein: the comparator circuit further includes a first capacitor, a second capacitor, a third capacitor and a fourth capacitor; The output terminals of the first capacitor are capacitively coupled to the input terminals of a second capacitor under the multitude of cascaded comparator amplifiers via the first and second capacitors, respectively; The output terminals of the second capacitor are capacitively coupled to the input terminals of a third capacitor under the multitude of cascaded comparator amplifiers via the third or fourth capacitor. [9] Comparator circuit according to claim 8, further comprising: a seventh switching device and an eighth switching device in series between the first and second capacitors; and a ninth switching device and a tenth switching device in series between the third and fourth capacitors. [10] Comparator circuit according to claim 9, wherein the common-mode voltage is connected to a node between the fifth and sixth switching devices, a node between the seventh and eighth switching devices and a node between the ninth and tenth switching devices. [11] Comparator circuit according to claim 10, wherein during a first phase of a clock cycle the first, third, fifth, sixth, seventh, eighth, ninth and tenth switching devices are closed and the second and fourth switching devices are open to automatically set offset voltages of the first, second and third comparator to zero and to sample the input voltage. [12] Comparator circuit according to claim 11, wherein during a second phase of the clock cycle the first, third, fifth, sixth, seventh, eighth, ninth and tenth switching devices are open and the second and fourth switching devices are closed to charge the sampling capacitor via the reference voltage. [13] A comparator circuit comprising the following: a large number of cascaded comparator amplifiers; a matching capacitor in series with a first switching device and a second switching device, wherein the first and the second switching device are connected in parallel between the matching capacitor and a common-mode voltage; and a sampling capacitor in series with a third switching device and a fourth switching device, wherein the third switching device is connected in series between the sampling capacitor and an input voltage and the fourth switching device is connected in series between the sampling capacitor and a digital-to-analog converter (DAC); wherein a first comparator among the plurality of cascaded comparator amplifiers includes an inverting input terminal and a non-inverting input terminal, wherein the inverting input terminal is capacitively coupled to the matching capacitor and the non-inverting input terminal is capacitively coupled to the sampling capacitor. [14] Comparator circuit according to claim 13, further comprising: the first, the second, the third and the fourth switching device; a fifth switching device and a sixth switching device in series between the matching capacitor and the sampling capacitor. [15] Comparator circuit according to claim 14, wherein: the comparator circuit further includes a first capacitor, a second capacitor, a third capacitor and a fourth capacitor; The output terminals of the first capacitor are capacitively coupled to the input terminals of a second capacitor under the multitude of cascaded comparator amplifiers via the first and second capacitors, respectively; The output terminals of the second capacitor are capacitively coupled to the input terminals of a third capacitor under the multitude of cascaded comparator amplifiers via the third or fourth capacitor. [16] Comparator circuit according to claim 15, further comprising: a seventh switching device and an eighth switching device in series between the first and second capacitors; and a ninth switching device and a tenth switching device in series between the third and fourth capacitors. [17] Comparator circuit according to claim 16, wherein the common-mode voltage is connected to a node between the fifth and sixth switching devices, a node between the seventh and eighth switching devices and a node between the ninth and tenth switching devices. [18] Comparator circuit according to claim 17, further comprising: a resistor, a switching device and a DAC sampling capacitor in series between the DAC and a ground. [19] Comparator circuit according to claim 18, wherein during a sampling phase of a clock cycle the first, third, fifth, sixth, seventh, eighth, ninth and tenth switching devices are closed and the second and fourth switching devices are open to automatically set offset voltages of the first, second and third comparator to zero and to sample the input voltage. [20] Comparator circuit according to claim 19, wherein during a dedicated windowing phase of the clock cycle the switching device is closed in order to sample the DAC via the DAC sampling capacitor, wherein the dedicated windowing phase has a phase delay with respect to the sampling phase.