Semiconductor device and method for its manufacture

Abstract

A semiconductor device comprises an active region and a junction termination region, each comprising a drain electrode, a first epitaxial layer of a first conductivity type arranged on the drain electrode, and a second epitaxial layer of the first conductivity type arranged on the first epitaxial layer. The junction termination region further comprises a first junction termination region etched onto a portion of the second epitaxial layer and a second junction termination region that is not etched. A field oxide layer is arranged on a portion of the first junction termination region. A doped region of a second conductivity type is arranged to extend from below the field oxide layer to the second junction termination region.

Description

CROSS-REFERENCE TO RELATED REGISTRATION

[0001] This application claims priority pursuant to 35 USC §119(a) of Korean patent application No. 10-2024-0153615, filed on November 1, 2024, the entire disclosure of which is hereby incorporated by reference for all purposes. BACKGROUND 1. Area

[0002] The present disclosure relates to a semiconductor device which can achieve a more stable voltage resistance compared to the prior art, and to a method for its manufacture. 2. Description of the background

[0003] Power semiconductor devices such as MOSFETs (metal-oxide-semiconductor field-effect transistors) and IGBTs (insulated-gate bipolar transistors) are primarily used as semiconductor switching devices in power electronics applications. Among these power semiconductor devices, IGBTs can be divided into a horizontal structure, in which a source (or emitter) electrode, a gate (or base) electrode, and a drain (or collector) electrode are all formed on the top side of a semiconductor substrate, and a vertical structure, in which the source and gate electrodes are formed on one side of the semiconductor substrate and the drain electrode is formed on the other.

[0004] In IGBT devices, it can be desirable to reduce the electric field peaks occurring at the substrate surface in a termination region. The maximum electric field peak typically occurs within a junction termination region where an equipotential ring is present. Under extremely high current and voltage conditions, this region is significantly weakened, leading to avalanche failure due to a high leakage current density under reverse bias. To prevent this, techniques such as using a P-ring structure by forming a multitude of P-type conductive rings or increasing the area of ​​the junction termination region to reduce the electric field have been proposed.

[0005] While the P-ring structure can reduce the electric field to a certain extent, it has limitations when used in high-voltage devices. Alternatively, the electric field can be further reduced by increasing the junction termination area, but this leads to an undesirable increase in the device size and thus presents another problem.

[0006] Such IGBT semiconductor devices must be able to dissipate the electric field generated under reverse bias conditions, thereby reducing the electric field peak and ensuring a stable breakdown voltage that is related to the dielectric strength of the semiconductor device.

[0007] Therefore, various approaches have been proposed to improve the structure of semiconductor devices in order to increase their voltage resistance.

[0008] The information above serves only as background information for a better understanding of the present disclosure. No decision has been made, nor is any statement made, as to whether the information above is applicable as prior art in relation to the disclosure. CONTENT OF THE REVELATION

[0009] This summary serves to present a selection of concepts in simplified form, which are explained in more detail below. This summary is neither intended to identify essential or necessary features of the claimed subject matter, nor is it intended to assist in determining the scope of the claimed subject matter.

[0010] In general terms, a semiconductor device comprises an active region and a junction termination region, each comprising a drain electrode, a first epitaxial layer of a first conductivity type arranged on the drain electrode, and a second epitaxial layer of the first conductivity type arranged on the first epitaxial layer. The junction termination region further comprises a first junction termination region etched onto a portion of the second epitaxial layer and a second junction termination region that is not etched. A field oxide layer is arranged on a portion of the first junction termination region. A doped region of a second conductivity type is arranged to extend from below the field oxide layer to the second junction termination region.

[0011] The doped region can include a lightly doped region of the second conductivity type located in the first transition termination region and a heavily doped region of the second conductivity type located to extend from the first transition termination region to the second transition termination region.

[0012] The thickness of the heavily doped region can be greater than the thickness of the lightly doped region.

[0013] A surface of the field oxide layer can be coplanar to a surface of the second epitaxial layer that is present in the second transition closure region.

[0014] The semiconductor device can further comprise a body region of the second conductivity type formed between trench gates in the active region, wherein the body region is connected to the doped region.

[0015] The semiconductor device may further comprise a layer of a second conductivity type formed between the drain electrode and the first epitaxial layer.

[0016] The transition termination region may further comprise: a transition termination etch region arranged between the field oxide layer and the second transition termination region; a field plate insulating layer arranged on the inner top and outer top of the transition termination etch region; a field plate arranged on the field plate insulating layer; an intermediate layer insulating layer arranged on the field plate; and a source electrode and a gate electrode formed on the intermediate layer insulating layer.

[0017] In a further general aspect, a semiconductor device comprises an active region and a junction termination region, each comprising: a drain electrode; a first epitaxial layer of a first conductivity type arranged on the drain electrode; and a second epitaxial layer of the first conductivity type arranged on the first epitaxial layer. The junction termination region further comprises a first junction termination region etched onto a portion of the second epitaxial layer and a second junction termination region that is not etched. A field oxide layer is arranged on a portion of the first junction termination region. Doping regions of a second conductivity type of varying thicknesses are arranged in the first junction termination region and the second junction termination region.

[0018] The semiconductor device can further comprise a body region of the second conductivity type formed between trench gates in the active region, wherein the body region is connected to the doped region.

[0019] The doped regions can include a lightly doped region of the second conductivity type located at the first transition termination region and a heavily doped region of the second conductivity type located such that it extends from the first transition termination region to the second transition termination region and has a higher doping concentration than the lightly doped region of the second conductivity type.

[0020] The thickness of the heavily doped region can be greater than the thickness of the lightly doped region.

[0021] The doping concentration of the lightly doped region can gradually decrease towards an edge of the first transition termination region.

[0022] The semiconductor device can further comprise a source electrode that is electrically in contact with the heavily doped region, a field plate that is arranged on part of the heavily doped region and on the lightly doped region, and a gate electrode that is electrically in contact with the field plate.

[0023] The semiconductor device may further comprise a layer of a second conductivity type formed between the drain electrode and the first epitaxial layer.

[0024] In a further general aspect, a method for fabricating a semiconductor device with an active region and a junction termination region comprises the following: forming a first epitaxial layer of a first conductivity type on a first conductivity type semiconductor substrate; forming a second epitaxial layer of the first conductivity type on the first epitaxial layer; etching a top-side portion of the second epitaxial layer located in the junction termination region; performing a first ion implantation of a second conductivity type into both the etched and unetched junction termination regions to form a first ion implantation region; performing a second ion implantation of the second conductivity type after the first ion implantation into a portion of both the etched and unetched junction termination regions to form a second ion implantation region;and the formation of a field oxide layer on part of the etched transition termination area by a thermal oxidation process.

[0025] During the formation of the field oxide layer, implanted ions can be diffused to form a doping region of a second conductivity type.

[0026] A mask pattern used in the formation of the first ion implantation area can be designed such that the distances between the mask patterns gradually decrease towards a chip edge.

[0027] The concentrations of the ions of the second conductivity type, which are formed during the first ion implantation and the second ion implantation, are the same.

[0028] The process may further include: forming a transition-termination etching region after the formation of the field oxide layer; forming a field plate insulating layer in the transition-termination etching region; forming a field plate on the field plate insulating layer; forming an interlayer insulating layer on the field plate; and etching a portion of the interlayer insulating layer to form a gate electrode in contact with the field plate and a source electrode in contact with the doping region.

[0029] The process may further include: performing a grinding process on a bottom side of the semiconductor substrate; performing an ion implantation process of a second conductivity type after the grinding process to form a layer of the second conductivity type; and forming a drain electrode on a bottom side of the layer.

[0030] Further features and aspects will become apparent from the following detailed description, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a cross-sectional view to illustrate a semiconductor device according to the prior art. Fig. 2A is a doping concentration profile of the in Fig. 1 semiconductor device shown, and Fig. 2B is an electric field profile of the in Fig. 1 semiconductor device shown. Fig. Figure 3 is a cross-sectional view to illustrate another semiconductor device with a P-type bridge ring (PBR) structure according to the prior art. Fig. 4A is a doping concentration profile of the in Fig. 3 semiconductor device shown, and Fig. 4B is an electric field profile of the in Fig. 3 semiconductor device shown. Fig. 5 to Fig. Figure 10 are process diagrams illustrating a method for manufacturing a semiconductor device according to an example in the present disclosure. Fig. Figure 11 is a cross-sectional view of a semiconductor device manufactured according to the manufacturing process of the present disclosure. Fig. 12A to Fig. Figure 14 are diagrams that compare the impact ionization profile, electric field and potential of a semiconductor device according to the present disclosure with those of a conventional device. Fig. Figure 15 is a process flow diagram illustrating a method for manufacturing a semiconductor device according to an example in the present disclosure.

[0031] In the drawings and detailed description, identical reference numerals refer to identical elements unless otherwise specified. The drawings may not be to scale, and the relative size, proportions, and representation of elements in the drawings may be exaggerated for clarity, illustration, and conciseness. DETAILED DESCRIPTION

[0032] Examples of the present disclosure are described in detail below with reference to the accompanying drawings, although it should be noted that the examples are not limited thereto.

[0033] The following detailed description is intended to provide the reader with a comprehensive understanding of the methods, devices, and / or systems described herein. However, upon understanding the disclosure of this application, various changes, modifications, and equivalents of the methods, devices, and / or systems described herein will be apparent. For example, the sequences of operations described herein are merely examples and are not limited to those set forth herein, but may be modified, as will be evident upon understanding the disclosure of this application, with the exception of operations that necessarily occur in a specific sequence.Furthermore, descriptions of features that are known according to the understanding of the disclosure of this application may be omitted for the sake of clarity and conciseness, although it should be noted that the omission of features and their descriptions should also not be understood as an admission of their general knowledge.

[0034] The features described herein can be embodied in various forms and are not to be understood as limited to the examples described herein. Rather, the examples described herein have been cited merely to illustrate some of the many possible ways in which the methods, devices, and / or systems described herein can be implemented, which are apparent from an understanding of the disclosure of this application. The use of the term "may" in relation to an example or embodiment, e.g., in relation to what an example or embodiment may contain or implement, means that at least one example or embodiment exists where such a feature is contained or implemented, while not limiting all examples to such features.

[0035] If, throughout the description, an element such as a layer, area, or substrate is described as being "on" another element, "connected" to another element, or "coupled" to another element, it can be directly "on" the other element, "connected" to it, or "coupled" to it, or one or more other elements can lie between them. However, if an element is described as "directly on," "directly connected to," or "directly coupled to" another element, no other elements can lie between them.

[0036] As used here, the term “and / or” includes each individual and each combination of two or more of the associated listed elements.

[0037] Although terms such as "first," "second," and "third" may be used here to describe different elements, components, areas, layers, or sections, these elements, components, areas, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, area, layer, or section from another. Thus, a first element, component, area, layer, or section referred to in the examples described herein may also be referred to as a second element, component, area, layer, or section without deviating from the lessons of the examples.

[0038] Spatially relative terms such as "top," "upper," "bottom," and "lower" can be used here to simplify the description and describe the relationship of one element to another, as illustrated in the figures. These spatially relative terms are intended to encompass not only the orientation shown in the figures but also various orientations of the device in use or operation. For example, if the device in the figures is inverted, an element described as "top" or "upper" relative to another element will then be "bottom" or "lower" relative to that other element. Thus, the term "top" encompasses both the upper and lower orientations, depending on the spatial orientation of the device. The device may also be oriented in other ways (e.g., rotated by 90 degrees or in other orientations), and the spatially relative terms used here should be interpreted accordingly.

[0039] The terminology used here serves only to describe various examples and is not intended to limit the disclosure. The articles "a," "an," and "that" are also intended to include the plural forms unless the context clearly indicates otherwise. The terms "comprises," "contains," and "exhibits" denote the presence of the specified features, numbers, processes, members, elements, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, processes, members, elements, and / or combinations thereof.

[0040] Due to manufacturing techniques and / or tolerances, deviations from the shapes shown in the drawings may occur. Therefore, the examples described here are not limited to the specific shapes shown in the drawings, but also include shape changes that occur during manufacturing.

[0041] The features of the examples described here can be combined in various ways, as will become apparent upon understanding the disclosure of this application. Furthermore, while the examples described here exhibit a multitude of configurations, other configurations are also possible, as will become apparent upon understanding the disclosure of this application.

[0042] A detailed description follows below with reference to the attached drawings.

[0043] As is known, an IGBT semiconductor device comprises an active region responsible for conducting current and determining Rds(on), and a junction termination region that supports the breakdown voltage against the blocking voltage generated during the turn-off process.

[0044] The present disclosure provides a semiconductor device and a method for its fabrication which enable stable breakdown voltage performance by providing a lower electric field peak value and a higher breakdown voltage compared to conventional devices.

[0045] The present disclosure also provides a semiconductor device and a method for its fabrication, which enables precise focusing during a photolithography process for the active area of ​​the semiconductor device.

[0046] Fig. Figure 1 is a cross-sectional view to illustrate a semiconductor device according to the prior art. Fig. 2A is a doping concentration profile of the in Fig. 1 semiconductor device shown. Fig. 2B is an electric field profile of the in Fig. 1 semiconductor device shown.

[0047] Referring to Fig. 1 uses a prior art semiconductor device 10, a structure in which a floating field ring (FFR) 14 is formed in a junction termination region to ensure a stable breakdown voltage value (BVCES). When the floating field ring 14 is as in Fig. As shown in Figure 1, the electric field generated during reverse operation under breakdown conditions can be distributed from the active area of ​​the semiconductor device 10 to the chip edge, thereby ensuring a stable breakdown voltage value.

[0048] In the semiconductor device 10, a collector layer 11 is arranged, and a first epitaxial layer 12 is formed on the collector layer 11. A second epitaxial layer 13 is formed on the first epitaxial layer 12, and the second epitaxial layer 13 can be referred to as the drift layer.

[0049] The first and second epitaxial layers exhibit a first conductivity type, which may, for example, be an N-type dopant.

[0050] The collector layer 11 can have a second conductivity type, for example a P-type dopant.

[0051] A collector electrode may be formed below the collector layer 11.

[0052] Within the second epitaxial layer 13, several floating field rings 14 are formed.

[0053] A field oxide 15 is formed on the several suspended field rings 14.

[0054] Several floating electrodes 16, 17 are formed on the field oxide 15.

[0055] Although the structure of the levitating field ring 14 is effective for scattering the electric field, as in Fig. As shown in Figure 1, the floating field rings 14 are formed with a predetermined distance D1 between them. Consequently, the electric field in the regions between the floating field rings 14 may not be sufficiently supported. The distance D1 tends to increase towards the chip edge, and the size of the floating field rings 14 tends to decrease accordingly. Referring to the in Fig. The doping concentration profile X1 to X2 shown in Figure 2A indicates that the regions between the floating field rings 14 exhibit relatively higher electric field peaks, which leads to problems. Furthermore, due to the distance D1 between the floating field rings 14, a relatively large substrate area may be required. As shown in Fig. As shown in Figure 2B, the inability to adequately support the electric field leads to repeated increases and decreases in the electric field peak values, making it difficult to efficiently mitigate the electric field across the middle range.

[0056] To overcome these disadvantages, a second conductive or P-type expansion region has been proposed in engineering, as described in Fig. 3 shown.

[0057] Fig. Figure 3 is a cross-sectional view to illustrate another semiconductor device with a PBR structure according to the prior art. Fig. 4A is a doping concentration profile of the in Fig. 3 semiconductor device shown, and Fig. 4B is an electric field profile of the in Fig. 3 semiconductor device shown.

[0058] Referring to Fig. Figure 3 comprises a semiconductor device 20 with a PBR structure, a collector layer 21, a first epitaxial layer 22 formed on the collector layer 21, and a second epitaxial layer 23 formed on the first epitaxial layer 22. The second epitaxial layer 23 can also be referred to as a drift layer.

[0059] An extension area 24 with a second conductivity type is arranged within the second epitaxial layer 23, and a field oxide layer 25 is formed over the extension area 24 with the second conductivity type.

[0060] The field plate metals 26, 27 are arranged between the field oxide layers 25.

[0061] In Fig. 3 The structure refers to a configuration in which the floating column regions are interconnected so that they do not remain electrically floating when the extension region with the second conductivity type (or P-type extension region) 24 is in a floating state in the transition termination region. Compared to Fig. Figure 1 shows that the column areas are connected.

[0062] The P-type extension area 24 can alternatively be referred to as a variation of a lateral doping area (VLD) or as a transition termination extension (JTE) area.

[0063] Accordingly, the doping concentration of the semiconductor device 20 comprising the extension range 24 with the second conductivity type corresponds to the doping concentration line of the extension range with the second conductivity type from X1 to X2 in Fig. 3. As in Fig. As shown in Figure 4A, the doping concentration in the transition termination region decreases essentially linearly towards the edge. As shown in Fig. As shown in Figure 4B, the peak electric field value can also be reduced compared to conventional structures. Although Fig. 4A and Fig. 4B doping gradients of 0.5, 0.6, 0.7, and 0.8 show that a larger doping gradient can lead to an increased ion implantation distance during the formation of the PBR structure. Overall, the PBR structure facilitates the formation of the PBR structure compared to the structure in Fig. 1. The distribution of the electric field and the reduction of electric field peaks, thereby enabling a more stable voltage withstand capability.

[0064] Nevertheless, the in Fig. 3 Semiconductor device 20 shown with the extension structure of the second conductivity type has disadvantages, as it is difficult to adjust the position of the electric field peak and to control the stage between the active region and the transition termination region.

[0065] The present disclosure was developed to solve the problems described above, in which the semiconductor devices of the Fig. 1 and Fig. 3. Due to a low breakdown voltage and high electric field peaks, sufficient dielectric strength cannot be guaranteed, and to facilitate the adjustment of the electric field peak position. To this end, the present disclosure improves the fabrication process for the semiconductor device, in particular the process related to the junction termination region. Accordingly, the following diagrams primarily illustrate the junction termination region, and the fabrication process for the semiconductor device according to the present disclosure is described below with reference to the accompanying drawings.

[0066] Fig. 5 to Fig. Figure 10 are process diagrams illustrating a method for manufacturing a semiconductor device according to the present disclosure.

[0067] Referring to Fig. In step 5, to fabricate a semiconductor device 100, a first epitaxial layer 102 is formed on a semiconductor substrate 101, and a second epitaxial layer 103 (also called a drift layer 103) is formed on the first epitaxial layer 102 using the same dopant. In this example, the semiconductor substrate 101, the first epitaxial layer 102, and the second epitaxial layer (drift layer) 103 all have a first conductivity type, which can be, for example, an N-type dopant.

[0068] The semiconductor substrate 101 can be a silicon substrate.

[0069] In Fig. 5 the central part of the semiconductor substrate 101 corresponds to the transition termination region, wherein the left side of the transition termination region represents the active region and the right side represents the chip edge of the device.

[0070] Referring to Fig. 6. A portion of the top surface of the transition termination region is etched. In the drawing, this portion is labeled "etched area". The etch depth corresponds to the thickness of a field oxide layer that will be formed in a subsequent process to eliminate a step between the transition termination region and the active region, even after the field oxide layer has formed.

[0071] In the prior art, the termination region of a semiconductor device was not etched; instead, a field oxide layer of a predetermined thickness was formed directly over it. As a result, a step inevitably formed at the boundary between the termination region and the active region due to the field oxide layer. This step caused difficulties during focusing operations using photolithography equipment, particularly during a trench etching process to form a gate in the active region or during structuring to form a contact region. In the example of the present disclosure, etching the termination region is intended to eliminate the step between the termination region and the active region, thereby enabling precise focusing on the intended region during a photolithography process.

[0072] As in Fig. As shown in Figure 6, the etch start point S in the transition termination region can be located closer to the active area than to the chip edge. This is related to the position of an emitter region to be formed in a subsequent process. This etching process allows the transition termination region to be divided into two sub-regions: a first termination region 110 and a second termination region 120. Based on the etch start point S, the first termination region 110 is located closer to the chip edge, and the second termination region 120 is located closer to the active area. The first termination region 110 refers to the etched area, while the second termination region 120 refers to the unetched area.

[0073] Fig. Figure 7 is a diagram illustrating an ion implantation process to form a first ion implantation area of ​​a second conductivity type.

[0074] As in Fig. As shown in Figure 7, PBR masks (PM1 to PM26) can be arranged within the first termination region 110 and the second termination region 120. Multiple openings (L1 to L25) can be structured in the PBR masks (PM1 to PM26) so that ions of the second conductivity type can be implanted into the top surface of a second epitaxial layer 103 to form a doped region or PBR region.

[0075] Ions of the second conductivity type can be implanted into the openings of the PBR masks (PM1 to PM26) to form a first ion implantation layer 131, 132-1 to 132-2.

[0076] The first ion implantation layer (131, 132-1 to 132-25) can be subdivided into a first primary ion implantation layer 131 (also referred to as the “1-1 ion implantation layer”), which may be formed as a single ion-implanted area, and a plurality of first secondary ion implantation layers 132-1 to 132-25 (also referred to as the “1-2 ion implantation layers”), which may be formed as several discrete ion-implanted areas.

[0077] The first primary ion implantation layer 131 and the first secondary ion implantation layers 132-1 to 132-25 can be implanted using boron (B) or another dopant of the second conductivity type and formed as P-type regions.

[0078] The first primary ion implantation layer and the first secondary ion implantation layers can be collectively referred to as the first ion implantation area 130, which is also referred to as the PBR ion implantation area.

[0079] In particular, the first secondary ion implantation layers 132-1 to 132-25 are formed such that the width of each unit doping region narrows towards the chip edge of the device. The unit doping regions are spaced apart at predetermined intervals, and the undoped regions between the unit doping regions widen towards the chip edge.

[0080] Depending on the width of the individual openings (L1 to L25) in the PBR masks (PM1 to PM26), the widths of the respective first secondary ion implantation layers 132-1 to 132-25 can vary. The widths of the first secondary ion implantation layers can gradually increase from the chip edge towards the active region.

[0081] For example, the opening width W1 can be wider than the opening width W2.

[0082] If the concentration of the second conductivity type dopant is high in the area next to the PBR masks (PM1 to PM26) near the chip edge, the electric field can concentrate in this area, reducing the reliability of the device.

[0083] Accordingly, the width of the PBR ion implantation layer adjacent to the PBR mask can be narrower than that of other PBR ion implantation layers, thus relatively reducing the concentration of the implanted dopant and allowing the electric field to be distributed more broadly near the chip edge. In contrast, in the second PBR region 132, the width of each unit doping region is reduced towards the chip edge. The unit doping regions are arranged with a predetermined spacing, and conversely, the undoped regions between the unit doping regions become wider towards the chip edge.

[0084] This means that the mask pattern is characterized by the fact that the distance between adjacent mask openings becomes narrower towards the chip edge.

[0085] Fig. Figure 8 is a diagram illustrating the formation of a mask to create a second ion implantation area.

[0086] As in Fig. As shown in Figure 8, a PPBR mask is formed within the first termination region 110. A mask is deposited and structured over a portion of the first termination region 110 (near the etch point of the first termination region) and over the second termination region 120 to prepare for an additional ion implantation process, thereby forming the PPBR mask in the first termination region 110.

[0087] A mask can also be deposited over the active area.

[0088] Fig. Figure 9 is a diagram illustrating an ion implantation process to form a second ion implantation area.

[0089] As in Fig. As shown in Figure 9, a dopant such as boron (B) is additionally implanted into a portion of the first termination region 110 and into the second termination region 120 to form a second ion implantation region 140, which can also be referred to as the PPBR implantation region. The second ion implantation region 140 includes the etch start point S.

[0090] The concentration of the dopant during the second ion implantation can be the same as that of the previously performed first ion implantation; however, due to the additional ion implantation, the total concentration in the second ion implantation area may be higher than that in the first ion implantation area.

[0091] In other examples, the concentration of the dopant can be adjusted according to the desired breakdown voltage of the semiconductor device.

[0092] By implanting ions into the junction termination region in this way to form the first ion implantation region 130 and the second ion implantation region 140, it is possible to adjust the position of the electric field peak. In other words, the area in which ions are implanted in the semiconductor device can vary depending on the position of the electric field peak.

[0093] Fig. Figure 10 is a diagram illustrating a process for forming a field oxide layer and a P-type doped region.

[0094] Referring to Fig. In step 10, a field oxide layer 104 is formed on the etched surface of the substrate in the second termination area 120. The field oxide layer 104 is also formed in the first termination area 110, and its thickness corresponds to the previously etched depth. Accordingly, the step between the transition termination area and the active area can be eliminated.

[0095] The field oxide layer 104 acts as an insulating and passivating layer capable of withstanding high voltage. The field oxide layer 104 typically consists of silicon dioxide (SiO2), which can be deposited onto the substrate surface using various deposition methods. Common deposition methods for silicon dioxide include thermal oxidation and chemical vapor deposition (CVD). In this example, a thermal oxidation process can be used as an example, where the field oxide layer is formed by a deposition process carried out in a high-temperature furnace at approximately 1000 °C to 1200 °C.

[0096] When the field oxide layer 104 is formed on the substrate surface using the thermal oxidation process described above, a high-temperature process is employed. According to this example, the heat generated during the formation of the field oxide layer 104 can also cause thermal diffusion of a doped region 105 of the second conductivity type into the drift layer 103. The second conductivity type is P-type. That is, the doped region 105 of the P-type is formed utilizing the heat provided during the formation of the field oxide layer 104.

[0097] As described above, in this example the transition termination region is first etched to a predetermined depth, and a field oxide layer 104 is formed on the etched area. The heat supplied during the formation of the field oxide layer 104 is also used to form the doped region 105 of the p-type in the substrate. This eliminates the step between the transition termination region and the active region caused by the field oxide layer in the prior art.

[0098] The doped region 105 of the second conductivity type can exhibit a concentration difference due to the previously performed first and second ion implantation processes. A heavily doped region of the second conductivity type 105-2, located closer to the active region, can undergo both ion implantation processes, resulting in a relatively higher concentration, while a lightly doped region 105-1, which undergoes only the first ion implantation process, can exhibit a relatively lower concentration.

[0099] Fig. Figure 11 is a cross-sectional view of a semiconductor device manufactured according to the manufacturing process of the present disclosure.

[0100] Referring to Fig. The device 11 comprises a semiconductor device 100 and a semiconductor substrate 101, which is partially ground to reduce its thickness, thereby enabling the formation of a collector region of a second conductivity type in a first direction (i.e., the vertical direction). A P-type dopant is implanted to form a collector region 107 of the second conductivity type. The device further comprises a first epitaxial layer 102 and a drift layer 103 formed over the collector region 107 of the second conductivity type. A collector electrode 106 is formed on the back side of the collector region 107 of the second conductivity type.

[0101] In the case of a MOSFET, the collector electrode 106 can function as a drain electrode.

[0102] As in Fig. As shown in Figure 11, the semiconductor device 100 can be divided in a second direction (i.e. the horizontal direction) which is perpendicular to the first direction into an active region and a transition termination region.

[0103] The transition termination area comprises a first transition termination area 110, which has been etched, and a second transition termination area 120, which remains unetched. The active area and the transition termination area together comprise the collector electrode 106, the second conductivity-type collector area 107, the first epitaxial layer 102, and the second epitaxial layer (drift layer) 103.

[0104] The first transition termination region 110 comprises a field oxide layer 104 formed in a region etched to a predetermined depth into the top surface of the second epitaxial layer 103. The etch depth can be equal to the thickness of the field oxide layer 104, so that no step is formed between the transition termination region and the active region. This enables reliable execution of processes such as trenching and photolithography in the active region. Within the first transition termination region 110, a portion of the field oxide layer 104 is further etched to form a transition termination etch region 150.

[0105] Etching can be performed on both sides of the field oxide layer for the process clearance, and the etched area can be referred to as the transition termination etch area 150.

[0106] A field plate insulating layer (152) is formed on the inner and outer top surfaces of the transition termination etching area 150. A field plate 160 is formed over the field plate insulating layer with a predetermined thickness, and an intermediate layer insulating layer 170 is formed over the field plate 160 and the field oxide layer 104.

[0107] The field plate 160 is formed in a trench shape within the transition termination etching area and can be electrically connected to the doped area 105 of the second conductivity type via the field plate insulating layer. This structure helps to attenuate the electric field generated under blocking bias conditions.

[0108] An emitter electrode 180 and a gate electrode 190 are formed above the intermediate insulating layer 170. The emitter electrode 180 is larger than the gate electrode 190, and the emitter contact connected to the emitter electrode is also wider, thus ensuring a sufficient current path during the application of a reverse voltage or during breakdown.

[0109] In a MOSFET implementation, the emitter electrode 180 can serve as a source electrode.

[0110] The gate electrode 190 can be electrically connected or coupled to the field plate 160.

[0111] A doped region 105 of the second conductivity type is formed in the second epitaxial layer 103 of the first conductivity type. The doped region 105 of the second conductivity type can extend from below the field oxide layer 104 to the active region. The doped region 105 of the second conductivity type is formed by thermal diffusion during the high-temperature process used to form the field oxide layer 104 and overlaps with the first and second ion implantation regions formed in previous steps.

[0112] Depending on the concentration of the dopant, the doped region 105 of the second conductivity type can be referred to as the lightly doped region 105-1 or the heavily doped region 105-2.

[0113] The thicknesses of the lightly doped region 105-1 and the heavily doped region 105-2, located within the doped region 105 of the second conductivity type, can vary depending on the dopant concentration. The thickness t1 of the lightly doped region 105-1 is less than the thickness t2 of the heavily doped region 105-2. The reference area for measuring thickness t1 is the etched area of ​​the second epitaxial layer within the first transition termination region 110, while the reference area for measuring thickness t2 is the unetched area of ​​the second epitaxial layer within the second transition termination region 120.

[0114] The concentration of the dopant in the doped region 105-1 of the second conductivity type with low concentration can gradually decrease in the X2 direction.

[0115] A P-type body region 111 or base region is formed in the active area and can be connected to the doped region 105 of the second conductivity type.

[0116] A trench-gate region is formed between the body regions 111 of the second conductivity type. Within each body region 111 of the second conductivity type, a source region or emitter region is formed, and a body contact region of the second conductivity type is formed between adjacent source regions. A source electrode can be electrically connected to both the source regions and the body contact region of the second conductivity type.

[0117] A channel stop region 109 can be formed near the edge of the transition termination region, and a channel stop electrode 195 or an equipotential metal can be formed over the channel stop region. The channel stop region is provided to prevent the depletion layer from extending into the channel stop region when a high blocking voltage is applied.

[0118] The channel stop region can be formed from a first conductivity type or as an N-type region.

[0119] As in Fig. As shown in Figure 11, the field oxide layer 104 is formed in the etched area of ​​the transition termination region, so that the heights of the active region and the transition termination region are aligned due to the field oxide layer 104.

[0120] Fig. 12A is a simulation diagram illustrating the extent of the electric field in a conventional structure, and Fig. Figure 12B is a simulation diagram illustrating the extent of the electric field in the structure of the present disclosure.

[0121] Referring to Fig. At 12A, the electric field extends laterally, necessitating a certain minimum lateral area, which can lead to an increase in the device size. Furthermore, the presence of N-type regions positioned between the floating field rings can increase the electric field peak, making it difficult to withstand the electric field.

[0122] Referring to Fig. In the structure of the present disclosure, the formation of a doped region of the second conductivity type in 12B reduces the lateral extent of the electric field, thereby enabling a reduction in device size. Furthermore, the concentration of the electric field is reduced, making it possible to achieve a higher breakdown voltage (BVCES) compared to the conventional structure.

[0123] Referring to Fig. Figure 13 shows electric field diagrams of the present disclosure and the prior art.

[0124] In the prior art electric field diagram, an electric field peak phenomenon occurs, which requires a sufficient lateral area to withstand the electric field. However, due to the increased electric field peak, it is difficult to ensure the reliability of the device and to guarantee a stable breakdown voltage.

[0125] In contrast, the electric field diagram of the present disclosure shows a streamlined or parabolic electric field profile in which the electric field peak is stably controlled. This allows for improved reliability of the device and a stable breakdown voltage.

[0126] Fig. Figure 14 is an electric field potential diagram, which is obtained by integrating the electric field diagram of the Fig. 13 were received.

[0127] As in Fig. As shown in Figure 13, the electric field potential curve of the present disclosure rises linearly, which enables stable reverse operation. In contrast, the prior art electric field potential curve rises in an unstable, step-like manner.

[0128] The differences in the length of the P-type ring (transition termination region), the electric field peak, and the breakdown voltage (BVCES) between the conventional structure and the structure of the present disclosure are summarized in the following Table 1. Table 1: Element Herkömmliche Struktur Struktur der vorliegendenOffenbarung Länge des P-Typ-Rings Mitte-200 µm Mitte-100 µm Elektrische Feldspitze 1,85E+5 V / cm 1,61E+5 V / cm BVCES 688 V 711 V

[0129] Fig. Figure 15 is a process flow diagram illustrating a method for manufacturing a semiconductor device according to an example in the present disclosure.

[0130] Referring to Fig. 15 comprises a method for manufacturing a semiconductor device according to an example of the present disclosure comprising the following processes: forming an epitaxial layer on a semiconductor substrate (S10); etching a junction termination region of the semiconductor substrate (S20); performing a first and a second ion implantation into the junction termination region (S30); forming a field oxide layer in the junction termination region (S40); forming a p-type doped region in the substrate during the formation of the field oxide layer (S50); implanting n-type ions into the active region in the semiconductor substrate and performing a thermal annealing process (S60); etching a trench in the junction termination region and forming a gate oxide layer in the junction termination region; depositing and etching polysilicon on the gate oxide layer (S80); forming a base region and an emitter region in the semiconductor substrate (S90);Forming an interlayer insulating layer (S100); forming a metal layer over the interlayer insulating layer (S110); forming a passivation layer over the metal layer (S120); grinding and polishing a back side of the semiconductor substrate and forming a collector area (S130); and forming a collector layer on the back side of the semiconductor substrate (S140).

[0131] The processes corresponding to the improvements of the present disclosure include processes S20 to S50. Processes from S60 onwards generally follow known semiconductor manufacturing processes.

[0132] A brief explanation of the manufacturing process in Fig. 15 reads as follows.

[0133] An epitaxial layer 102 and a drift layer 103 are formed on a semiconductor substrate 101. The semiconductor substrate 101 comprises an active region and a transition termination region, and in the present disclosure, the etched part of the epitaxial layer can correspond to the transition termination region.

[0134] The transition termination area is etched to a predetermined depth. Based on an etching start point (S in Fig. 6) the unetched part can be designated as the first finishing area 110 and the etched part as the second finishing area 120.

[0135] A first ion implantation is performed in both the first closure area 110 and the second closure area 120, followed by a second ion implantation in part of the first ion-implanted area.

[0136] Subsequently, a field oxide layer 104 is formed in the second termination region, and the heat generated during the formation of the field oxide layer 104 introduces a P-type dopant into the substrate, thereby forming a P-type doping region 105. The P-type doping region 105 is formed such that it is electrically connected to the active region from below the field oxide layer 104.

[0137] An N-type ion implantation and annealing process is performed in the active area.

[0138] Subsequently, a trench 130 is etched into the active area and a gate oxide layer is formed within the trench.

[0139] Polysilicon 160 is deposited on the gate oxide layer, and the polysilicon is etched to form a gate area.

[0140] A P-type dopant is implanted to form a base region, and a thermal process is performed at a predetermined temperature. Subsequently, P + - and N + -Dopants are implanted to form an emitter region and a base contact region.

[0141] After the emitter area has been formed, an intermediate insulating layer 170 is deposited and a contact photoresist layer is formed. To then form an emitter contact, the intermediate insulating layer 170 is etched, the photoresist layer is removed, and a metal wiring for the emitter material, a gate via, and a gate bond pad are formed.

[0142] A passivation layer (e.g., an oxide layer and a nitride layer) is formed.

[0143] Once the processing of the front side of the semiconductor substrate is completed using the steps described above, the processing of the back side of the semiconductor substrate can be carried out.

[0144] Backside processing includes grinding and cleaning the back side of the semiconductor substrate, performing a P-type ion implantation process on the back side to form a collector layer of a second conductivity type, and removing a metal layer on top of it to form a collector electrode.

[0145] As described above, the present disclosure provides a method for fabricating a semiconductor device in which the semiconductor substrate is etched in the junction termination region to a depth corresponding to the thickness of the field oxide layer to be subsequently formed, prior to the formation of the field oxide layer. The formation of the field oxide layer after such etching eliminates a step difference between the active region and the junction termination region. It is evident that the semiconductor device fabricated by this process provides a lower electric field value and a higher breakdown voltage compared to conventional devices.

[0146] According to the present disclosure, a semiconductor device with stable breakdown characteristics can be provided because, compared to conventional semiconductor devices, it provides a lower electric field peak value and a higher breakdown voltage or device resistance voltage.

[0147] Since the present disclosure also enables the elimination of a step difference between the active area and the transition termination area during the manufacturing process, it enables precise focusing in a photolithography process for the active area in subsequent processing steps.

[0148] Although this disclosure includes specific examples, it is evident from an understanding of the disclosure of this application that various changes in form and detail can be made to these examples without departing from the spirit and scope of the claims and their equivalents. The examples described here are to be considered descriptive only and are not intended to be limiting. Descriptions of features or aspects in each example are to be considered applicable to similar features or aspects in other examples. Suitable results can be obtained if the described techniques are carried out in a different sequence and / or if components in a described system, architecture, device, or circuit are combined in a different way and / or replaced or supplemented by other components or their equivalents.Therefore, the scope of the disclosure is not defined by the detailed description, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents are to be interpreted as being contained in the disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] KR 10-2024-0153615

[0001]

Claims

[1] Semiconductor device comprising: an active area and a transition completion area, each comprising the following: a drain electrode; a first epitaxial layer of a first conductivity type, which is arranged on the drain electrode; and a second epitaxial layer of the first conductivity type, which is arranged on top of the first epitaxial layer, wherein the transition termination area further comprises a first transition termination area that is etched on part of the second epitaxial layer and a second transition termination area that is not etched, wherein a field oxide layer is arranged on part of the first transition termination region, and wherein a doped region of a second conductivity type is arranged such that it extends from below the field oxide layer to the second transition termination region. [2] Semiconductor device according to claim 1, wherein the doped region comprises: a lightly doped region of the second conductivity type, which is located in the first transition termination region; and a highly doped area of ​​the second conductivity type, arranged to extend from the first transition termination area to the second transition termination area. [3] Semiconductor device according to claim 2, wherein the thickness of the heavily doped region is greater than the thickness of the lightly doped region. [4] Semiconductor device according to claim 1, wherein an area of ​​the field oxide layer is coplanar to an area of ​​the second epitaxial layer which is present in the second junction termination region. [5] Semiconductor device according to claim 1, further comprising: a body region of the second conductivity type, located between trench gates in the active area, where the body region is connected to the doped region. [6] Semiconductor device according to claim 1, further comprising: a layer of a second conductivity type formed between the drain electrode and the first epitaxial layer. [7] Semiconductor device according to claim 1, wherein the transition termination region further comprises: a transition termination etching area located between the field oxide layer and the second transition termination area; a field plate insulating layer arranged on the inner top and outer top of the transition termination etching area; a field plate that is arranged on the field plate insulating layer; an intermediate insulating layer arranged on the field plate; and a source electrode and a gate electrode formed on the interlayer insulating layer. [8] Semiconductor device comprising: an active area and a transition completion area, each comprising the following: a drain electrode; a first epitaxial layer of a first conductivity type, which is arranged on the drain electrode; and a second epitaxial layer of the first conductivity type, which is arranged on top of the first epitaxial layer, wherein the transition termination area further comprises a first transition termination area that is etched on part of the second epitaxial layer and a second transition termination area that is not etched, wherein a field oxide layer is arranged on part of the first transition termination region; and wherein doping areas of a second conductivity type with different thicknesses are arranged in the first transition termination area and the second transition termination area. [9] Semiconductor device according to claim 8, further comprising: a body region of the second conductivity type, formed between trench gates in the active area, where the body region is connected to the doped region. [10] Semiconductor device according to claim 8, wherein the doped regions comprise: a lightly doped region of the second conductivity type, which is located at the first transition termination region, and a heavily doped region of the second conductivity type, arranged to extend from the first transition termination region to the second transition termination region and having a higher doping concentration than the lightly doped region of the second conductivity type. [11] Semiconductor device according to claim 10, wherein the thickness of the heavily doped region is greater than the thickness of the lightly doped region. [12] Semiconductor device according to claim 10, wherein the doping concentration of the lightly doped region gradually decreases towards an edge of the first transition termination region. [13] Semiconductor device according to claim 10, further comprising: a source electrode that is electrically in contact with the heavily doped area; a field plate arranged on part of the heavily doped region and on the lightly doped region; and a gate electrode that is electrically in contact with the field plate. [14] Semiconductor device according to claim 10, further comprising: a layer of a second conductivity type formed between the drain electrode and the first epitaxial layer. [15] Method for manufacturing a semiconductor device having an active region and a junction termination region, the method comprising: Formation of a first epitaxial layer of a first conductivity type on a first conductivity type semiconductor substrate; Formation of a second epitaxial layer of the first conductivity type on the first epitaxial layer; Etching of an upper surface section of the second epitaxial layer located in the transition closure area; Performing an initial ion implantation of a second conductivity type into both etched and non-etched transition termination areas to form an initial ion implantation area; Performing a second ion implantation of the second conductivity type after the first ion implantation into a portion of both the etched and non-etched transition termination areas to form a second ion implantation area; and Formation of a field oxide layer on part of the etched transition termination area by a thermal oxidation process. [16] Method according to claim 15, wherein implanted ions are diffused during the formation of the field oxide layer to form a doping region of a second conductivity type. [17] Method according to claim 15, wherein a mask pattern used in the formation of the first ion implantation area is formed such that the distances between the mask patterns gradually decrease towards a chip edge. [18] Method according to claim 15, wherein the concentrations of the ions of the second conductivity type formed during the first ion implantation and the second ion implantation are the same. [19] The method of claim 15, further comprising: Formation of a transition-termination etching area after the formation of the field oxide layer; Forming a field plate insulating layer in the transition termination etching area; Forming a field plate on the field plate insulating layer; Forming an intermediate insulating layer on the field plate; and Etching part of the interlayer insulating layer to form a gate electrode in contact with the field plate and a source electrode in contact with the doping area. [20] The method of claim 15, further comprising: Performing a grinding process on one underside of the semiconductor substrate; Performing a second conductivity-type ion implantation process after the grinding process to form a second conductivity-type layer; and Forming a drain electrode on one underside of the layer.

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