MULTI-CHANNEL SIGNAL AND POWER ANALYST

Abstract

A signal and power analysis instrument comprises one or more high-bandwidth input channels configured as one or more equivalence-time (RET) input channels and / or one or more radio frequency (RF) channels, one or more input channels configured as one or more low-bandwidth real-time (RT) input channels, one or more analog-to-digital converters (ADCs) with pipes, a first set of pipes connected to the one or more high-bandwidth input channels to generate high-bandwidth data, and a second set of pipes connected to the one or more low-bandwidth RT input channels to generate low-bandwidth RT data, a system clock connected to the high-bandwidth input channels and the low-bandwidth RT input channels, and a memory connected to the system clock.connected to the first set of pipes and the second set of pipes, and one or more processors for storing low-bandwidth RT data and high-bandwidth data in memory and for matching the high-bandwidth data and the low-bandwidth data.

Description

REFERENCE TO RELATED REGISTRATIONS

[0001] This disclosure is a non-preliminary filing and claims precedence over the preliminary US filing No. 63 / 718.480 entitled “MULTI-CHANNEL SIGNAL AND POWER ANALYZER”, which was filed on November 8, 2024, and the disclosure of which is incorporated herein by reference in its entirety. AREA OF TECHNOLOGY

[0002] This disclosure relates to test and measurement equipment, in particular a combined multi-channel signal and power analysis instrument. BACKGROUND

[0003] With the advancement of generative AI, data centers, electric vehicles (EVs), 5G / 6G wireless technology, and quantum computing, the need for high-channel-count devices capable of combined signal integrity (SI) and power integrity (PI) analysis is increasing. Faster wired data transmission enables generative AI and data centers to handle the increased data demands, requiring higher performance for data transmission and processing. Industry standards such as IEEE Ethernet 800G require oscilloscopes with high analog bandwidth to measure signal integrity. Power supplies, on the other hand, require oscilloscopes with much lower analog bandwidth to measure power integrity.Since there are correlations between signal integrity (SI) and power integrity (PI), a single device capable of capturing time-correlated signals for SI / PI analysis provides users with better insight into their designs. EV, 5G / 6G wireless, and quantum computing all have an unmet need for a single device to capture and analyze time-correlated time-domain signals, RF signals, and power signals.

[0004] The need for such devices stems from several areas. The advancement of generative AI has triggered a significant development of high-performance computing infrastructures, including clusters of GPUs for LLM training and large data centers for data storage, processing, and transmission. These applications demand higher performance. The global adoption of electric vehicles (EVs) is increasing the need for performance analysis instruments. Modern vehicles are equipped with fast wired and wireless data communication systems to transmit video, radar, and other sensor data. Quantum computing systems are incorporating ever-increasing numbers of qubits; hundreds and thousands of qubits in a single quantum computer require spectrum analyzers with a high channel count. 5G and 6G radio testing, with their massive multi-input multi-output (MIMO) architectures, also necessitates spectrum analyzers with a higher channel count.

[0005] Signal integrity analysis (SI analysis) is required for high-speed time-domain signals such as the 800G PAM4 Ethernet signal and for high-bandwidth RF signals such as 5G and 6G radio signals. Power integrity analysis (PI analysis) is required for power supplies and electric motors. The interaction between the power supply and the signal path necessitates SI / PI analysis. SI / PI analysis is initially performed during the system design phase using simulation. When the actual systems are manufactured, test equipment is used to verify the design and debug the system.

[0006] US Patent No. 11,789,051, entitled "Real-equivalent-time oscilloscope," granted on October 17, 2023, the contents of which are hereby incorporated in their entirety into this disclosure, describes a new class of oscilloscopes, the real-equivalent (RET) oscilloscopes. The RET oscilloscope uses only a single ADC with a lower sample rate per channel, thereby significantly reducing complexity and cost compared to a conventional real-time oscilloscope, which typically has multiple ADCs time-nested to achieve a higher sample rate. US patent application No. 2024 / 0313795 entitled “Real-Equivalent-Time oscilloscope and Wideband Real-Time Spectrum Analyzer”, filed on February 29, 2024, the contents of which are incorporated in full into this disclosure by reference, describes a new class of instruments that are equivalent to those described in US patent No. 11,789.The RET oscilloscope architecture described in U.S. Patent No. 11,789,051 and U.S. Patent Application No. 2024 / 0313795 are used to enable the device to also be operated as a real-time spectrum analyzer. Embodiments of this disclosure utilize the technology described in U.S. Patent No. 11,789,051 and U.S. Patent Application No. 2024 / 0313795. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 shows an embodiment of a signal and power analysis instrument. Fig. Figure 2 shows a block diagram of an embodiment of a signal and power analysis. Fig. Figure 3 shows a block diagram of an embodiment of a channel architecture of a signal and power analysis instrument. Fig. Figure 4 shows an example of a spectrogram of a signal resulting from a power integrity problem. DETAILED DESCRIPTION

[0007] The embodiments presented here include a new instrument referred to herein as the Signal and Power Analyzer (SPA). In general, the SPA has a higher channel count, its system clock enables synchronized signal acquisition across all channels, and each channel of the instrument can be configured as an oscilloscope channel with high analog bandwidth equivalent-time sampling, a high-bandwidth real-time spectrum analyzer channel, or a lower-bandwidth real-time oscilloscope channel. The SPA's unique architecture enables high channel density, lower costs, and reduced power consumption. A single SPA unit serves both the power market and the wired and wireless data communication market.

[0008] The SPA has many uses, but one particular application is the combined analysis of signal integrity and power integrity at the same time. As in Fig. As shown in Figure 1, the ability to perform combined signal integrity and power integrity analyses enables developers to understand the impact of power integrity issues on signals. High-speed time-domain signals, such as the 800G PAM4 Ethernet signal, and high-bandwidth RF signals, such as 5G and 6G radio frequency signals, require signal integrity analysis (SI analysis). Power supplies and electric motors that generate power signals require power integrity analysis (PI analysis). The interaction between the power supply and the signal path requires SI / PI analysis. SI / PI analysis is initially performed using simulation during the system design phase. When the actual systems are in operation, two different devices are currently required, e.g.,A higher-bandwidth real-time oscilloscope is used for signal acquisition, and a lower-bandwidth real-time oscilloscope for the current signal. Because two separate devices are used, it is difficult to obtain a precise time-correlated view on both devices.

[0009] The embodiments presented here comprise more than just a combination of two separate devices. They enable the temporal alignment of signals in the time domain and the frequency domain, allowing developers to understand the effects of performance data and data signals on each other and to develop more robust systems and troubleshoot errors.

[0010] Fig. Figure 2 shows a diagram of an embodiment of a SPA test and measurement instrument. The instrument 20 includes one or more ports such as 24, which can be any electrical or optical signal transmission media. Ports such as 24 can include receivers, transmitters, and / or transceivers. Each port 24 comprises one channel of the test and measurement instrument. The structures encompassed by Figure 22 are replicated for each channel of the instrument.

[0011] The signals from the terminals are then sent to a vertical offset 26, which can adjust the offset or output value of the received signal. In some training exercises or examples, the vertical gain / offset control 26 may also include vertical gain adjustment. If no vertical gain adjustment is present, vertical noise can be reduced, but there is also a reduction in the dynamic range. To remedy this, in some examples, an external attenuator and / or amplifier may be used to attenuate and / or amplify the signal under test. The signal is sent from the vertical gain / offset control 26 to a track-and-hold circuit 28. The track-and-hold circuit 28 samples each signal and holds it stable for a period sufficient to allow acquisition by an analog-to-digital converter (ADC) such as 30.

[0012] In the embodiments described here, the ADC 30 is part of a group of one or more ADCs. The ADCs form a "pool" of ADCs, each of which can have one or more "pipes," such as 31. In the embodiments described here, ADC pipes are treated as independent ADCs that can be connected to channels of various configurations, typically controlled by the processor 40. In an example of currently available oscilloscopes, in a 4-channel real-time oscilloscope (4-channel RT oscilloscope) with a total of 100 GS / s (gigasamples / second) ADCs, each channel receives 100 / 4 = 25 GS / s when users turn on all 4 channels. If users turn on only 2 channels, each channel receives 100 / 2 = 50 GS / s. The instrument of the embodiments contains wires and switches, such as the switch arrangement 32, which activate different channels and ADC paths.

[0013] The ADC 30 converts the analog data signal and / or the power signal from the track-and-hold circuit 28 into digital signal and power data. The digitized signal from the ADC 30 can then be stored in a capture memory 34. The ADC 30 could be a single high-resolution ADC, for example, a 12-bit analog-to-digital converter with multiple pipes. The different channels can be connected via multiple pipes, such as 31, within a single ADC or via multiple pipes across different ADCs. The embodiments do not require a specific configuration of ADCs and pipes.

[0014] One or more processors 40 can be configured to execute instructions from memory and perform all procedures and / or associated steps specified by these instructions, such as receiving the captured signals from the capture memory 34 and reconstructing the signal under test without using a hardware trigger or capturing the sample at the high sampling rate.

[0015] The memory 34, or any other memory of the test and measurement instrument 20, can be implemented as a processor cache, random access memory (RAM), read-only memory (ROM), solid-state memory, hard disk(s), or any other type of memory. The memory serves as a medium for storing data, computer program output, and other instructions.

[0016] User inputs 38 are coupled to one or more processors 40. User inputs 38 can include a keyboard, mouse, trackball, touchscreen, and / or other controls that a user can use to interact with a GUI on the display 36. The display 36 can be a digital screen, a cathode ray tube-based screen, or another type of monitor to display waveforms, measurement data, and other data to a user. While the components of the test and measurement instrument are shown as integrated into the test and measurement instrument 20, it will be clear to a person skilled in the art that each of these components may be located outside the test and measurement instrument 20 and may be coupled to the test and measurement instrument 20 in any conventional way, for example, via wired and / or wireless communication media and / or mechanisms.In some examples, for instance, the display 36 might be located away from the test and measurement instrument 20.

[0017] SPA implementations feature trainable channels. There are four different training types. The system may have one or more real-time (RT) channels. Each RT channel can comprise a high-sampling-rate / high-bandwidth channel or a low-sampling-rate / low-bandwidth channel, or any two RT channel types. High-bandwidth RT channels require a large number of ADCs. Low-bandwidth RT channels require a smaller number of ADCs. Real-time equivalent (RET) channels with high bandwidth and low sampling rates constitute a third type. A fourth channel type is a high-bandwidth, low-sampling-rate radio frequency (RF) channel. High-bandwidth RT channels typically digitize an entire waveform in a single pass using one or more ADCs with a sampling rate high enough to capture the signal in real time. RET channels have low sampling rates and high bandwidth.They typically sample the incoming signal at a sampling rate below the required Nyquist frequency value over several iterations of a repeating pattern, then perform software clock recovery and reconstruct the signal in the equivalent time domain. RF channels generally require at least two low-sampling-rate pipes to digitize the high-bandwidth incoming signal.

[0018] The SPA is configured to have one or more high-bandwidth channels, comprising at least one or more RET channels and one or more RF channels, as well as a low-bandwidth RT channel. The SPA may include one or both RET and RF channels in combination with one or more low-bandwidth RT channels. In another embodiment, the high-bandwidth channels include a high-bandwidth RT channel. The high-bandwidth channels may comprise a combination of RET and RF channel(s), RET and one high-bandwidth RT channel(s), RF and one high-bandwidth RT channel(s), or RET, RF, and high-bandwidth RT channel(s). The high-bandwidth channels, regardless of their configuration, are combined with the low-bandwidth RT channel(s).

[0019] To better understand this, consider the following example. The sampler of the high-bandwidth RT channel is connected to a set of multiple ADCs or pipes. In one example, there could be 16 pipes from either a single ADC or multiple ADCs. These 16 pipes can be time-interleaved to provide the high combined ADC sample rate for the high-bandwidth RT channel. The sampler of the RET channel is connected to a second set of pipes or ADCs, which may include one or only a few ADC pipes, and whose combined ADC sample rate is much lower than that of the high-bandwidth RT channel. The RET channel can support the high analog bandwidth of the RT channel. The instrument, according to the embodiments, provides multiple channels that can be configured as RET channels, RF channels, low-bandwidth RT channels, and high-bandwidth RT channels.For signal and power analysis, the low-bandwidth RT channels can be connected to the power signal of the device under test (DUT) or to a power supply that powers the DUT. The high-bandwidth RET, RF, and RT channels can be connected to the data signals of the DUT. Combining these two inputs enables combined power integrity and signal integrity analysis.

[0020] Fig. Figure 3 shows an embodiment of a general architecture of the multi-channel SPA instrument according to embodiments of the disclosure. Because the lower ADC sample rate supports the RET / RF channels, these require fewer hardware components and consume less power. Therefore, an SPA instrument can contain multiple channels. The SPA may have a higher channel count than an RT oscilloscope of the same size or an RT spectrum analyzer of the same size with the same analog bandwidth. The RET / RF channels are used for signal integrity (SI) analysis. Each channel, such as 50 and 52, can also be configured as a real-time (RT) channel, like a normal channel of a real-time oscilloscope. The low-bandwidth RT channels can be used for power integrity (PI) analysis. Since the system clock 54 drives all channels in the instrument, all channel acquisitions are synchronized.The system clock information is stored together with the acquired channel data in the acquisition memory 34. The time-correlated acquisition data with the system clock information 54 enables an accurate and coherent combined SI / PI analysis in real time.

[0021] For example, a device under test (DUT) 56 could be connected to a first of the channels 50, which in this example is configured as a signal integrity RET data input channel. This allows the channel to operate with high analog bandwidth and acquire the data signal. The ADC and / or ADC pipes, as described in Fig. The processors shown in Figure 2 then convert the data signal into signal data. One or more processors then reconstruct the complete data for the signal data and store it in memory. Meanwhile, the power supply 58 is connected to an input channel configured as a low-bandwidth analog RT channel to capture the current signal, which is then converted into power data to distinguish it from the signal data coming from the device under test (DUT). The power supply 58 may be located on the DUT or include an external power supply. Each channel has a set of ADCs or ADC pipes, with high-bandwidth RT channels having a higher number of ADCs than the RET and RF channels, and possibly also than the low-bandwidth RT channel. For example, the high-bandwidth RT channel requires 64 pipes, the RET channel 1 pipe, and the RF channel 2 pipes.The high-bandwidth RT channel therefore requires significantly more pipes than the RET or RF channels.

[0022] Fig.Figure 4 shows an example of a situation where the SPA would offer many design advantages. The spectrogram shows the unexpected transient responses of an oscillator that occurred before the 1.2 µs mark on the time axis (horizontal axis). The data for the spectrogram was acquired using a high-bandwidth real-time oscilloscope. It took some time for the developer to discover that the transient responses were caused by a power supply problem. The developer had to debug the power supply using a second, lower-bandwidth real-time oscilloscope. The SPA implementations described here can quickly and reliably identify the problems. The power supply problem and the oscillator's transient responses can be captured in a time-correlated manner.Triggering in the time domain or frequency domain can be used to compare signal and power data so that users can quickly detect anomalies.

[0023] The embodiments described herein disclose a new SPA instrument. The SPA offers a higher number of channels in a single instrument and enables time-correlated acquisitions, allowing for combined SI / PI analysis in real time.

[0024] Aspects of the disclosure may be executed on specially designed hardware, firmware, digital signal processors, or a specially programmed general-purpose computer, including a processor that operates according to programmed instructions. The terms "controller" or "processor" as used herein are intended to include microprocessors, microcomputers, application-specific integrated circuits (ASICs), and dedicated hardware controllers. One or more aspects of the disclosure may be embodied in computer-readable data and computer-executable instructions, for example, in one or more program modules executed by one or more computers (including monitoring modules) or other devices. In general, program modules include routines, programs, objects, components, data structures, and so on.These are instructions that perform specific tasks or implement certain abstract data types when executed by a processor in a computer or other device. The computer-executable instructions can be stored on a non-volatile, computer-readable medium, such as a hard disk, optical disk, removable storage medium, solid-state storage, or random access memory (RAM). As is known to those skilled in the art, the functionality of program modules can be combined or distributed in various ways as desired. Furthermore, the functionality can be embodied, wholly or partially, in firmware or hardware equivalents such as integrated circuits, FPGAs, and the like.Certain data structures can be used to implement one or more aspects of the disclosure more effectively, and such data structures are considered within the context of the computer-executable instructions and computer-usable data described here.

[0025] The disclosed aspects may, in some cases, be implemented in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions that are transmitted to or stored on one or more non-transitory computer-readable media and can be read and executed by one or more processors. Such instructions may be referred to as a computer program product. For the purposes of this description, computer-readable media are any media accessible to a computing device. For example, and without limitation, computer-readable media may include computer storage media and communication media.

[0026] Computer storage media are all media that can be used to store computer-readable information. For example, and without limitation, computer storage media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory or other storage technologies, compact disc read-only memory (CD-ROM), digital video disc (DVD) or other optical storage media, magnetic cartridges, magnetic tapes, magnetic disk storage or other magnetic storage devices, and any other volatile or non-volatile, removable or non-removable media implemented in any technology. Computer storage media exclude signals per se and transient forms of signal transmission.

[0027] Communication media are all media that can be used to transmit computer-readable information. Examples of communication media include coaxial cables, fiber optic cables, air, and other media suitable for transmitting electrical, optical, radio frequency (RF), infrared, acoustic, or other signals. EXAMPLES

[0028] The following are illustrative examples of the disclosed technologies. An embodiment of the technologies may include one or more of the examples described below and any combination thereof.

[0029] Example 1 is a signal and power analysis instrument comprising: one or more high-bandwidth input channels configured as at least one of one or more equivalence-time (RET) input channels or one or more radio frequency (RF) channels connected to a device under test (DUT); one or more input channels configured as one or more low-bandwidth real-time (RT) input channels; one or more analog-to-digital converters (ADCs), each ADC having one or more pipes, a first set of the one or more pipes being connected to the one or more high-bandwidth input channels to generate high-bandwidth data, and a second set of the one or more pipes being connected to the one or more low-bandwidth RT input channels to generate low-bandwidth data;a system clock connected to the one or more high-bandwidth input channels and the one or more low-bandwidth RT input channels; a memory connected to the system clock, the first set of the one or more pipes connected to the one or more high-bandwidth input channels, and the second set of the one or more pipes connected to the one or more low-bandwidth RT input channels; and one or more processors configured to execute code that causes the one or more processors to: store low-bandwidth data from the second set of pipes in memory; store high-bandwidth data from the first set of pipes in memory; and synchronize the high-bandwidth data and the low-bandwidth data using the system clock.

[0030] Example 2 is the signal and power analysis instrument from Example 1, wherein the one or more high-bandwidth input channels include one or more RET input channels and one or more RF input channels, only RET input channels, or only RF input channels.

[0031] Example 3 is the signal and power analysis instrument from Example 1 or 2, wherein the one or more high-bandwidth input channels further comprise one or more high-bandwidth RT input signal channels, and the instrument further comprises a third set of pipes connected to the one or more high-bandwidth RT input signal channels.

[0032] Example 4 is the signal and power analysis instrument from Example 3, wherein the one or more high-bandwidth input channels comprise one or more RET input channels and one or more high-bandwidth input channels, one or more RF input channels and one or more high-bandwidth RT channels, or one or more RET input channels, one or more RF input channels and one or more high-bandwidth input channels.

[0033] Example 5 is the signal and power analysis instrument from Example 3, wherein the one or more high-bandwidth input channels include one or more RET input channels, and a first set of pipes includes fewer pipes than a number of pipes in the third set of pipes.

[0034] Example 6 is the signal and power analysis instrument from one of Examples 1 to 5, wherein the one or more high-bandwidth input channels are configured to receive one or more signals from the DUT, and the high-bandwidth data comprises signal data.

[0035] Example 7 is the signal and power analysis instrument from Example 6, wherein the one or more low-bandwidth RT input channels are configured to be connected to a power supply that powers the DUT, and the low-bandwidth RT data includes power data.

[0036] Example 8 is the signal and power analysis instrument from Example 7, wherein the code that causes one or more processors to time-align the high-bandwidth data and the low-bandwidth data includes code to align the power data and the signal data using the system clock.

[0037] Example 9 is the signal and power analysis instrument from Example 6, wherein the signal data includes at least one of RET data and RF data.

[0038] Example 10 is the signal and power analysis instrument from Example 6, wherein the signal data includes at least one of high-bandwidth RET, RF and RT data.

[0039] Example 11 is a method for performing a signal integrity and power integrity analysis, comprising: receiving one or more signals from one or more input channels configured as one or more low-bandwidth RT input channels; receiving one or more signals from a device under test (DUT) from one or more high-bandwidth input channels configured as one or more input channels with an RT input channel and radio frequency (RF) channels; using a first set of one or more analog-to-digital converter (ADC) pipes connected to the one or more low-bandwidth input channels and RT input channel to generate low-bandwidth and real-time data;Using a second set of the one or more ADC pipes connected to the one or more high-bandwidth input channels to generate high-bandwidth data; storing the high-bandwidth data and the low-bandwidth RT data in an acquisition memory; and timing the low-bandwidth RT data and the high-bandwidth data using a system clock.

[0040] Example 12 is the method from Example 11, wherein receiving signals from the one or more high-bandwidth input channels includes receiving signals from the one or more RET input channels and the one or more RF input channels, receiving signals only from the one or more RET input channels, or receiving signals only from the one or more RF input channels.

[0041] Example 13 is the method from Example 11 or 12, further comprising receiving one or more signals from one or more high-bandwidth RT input channels and using a third set of ADC pipes connected to the one or more high-bandwidth RT input channels.

[0042] Example 14 is the method from Example 13, wherein receiving one or more signals from the one or more high-bandwidth channels is the receiving of one or more signals from the one or more RET input channels and the one or more high-bandwidth RT input channels, the one or more RF input channels and the one or more high-bandwidth RT channels, or the one or more RET input channels, the one or more RF input channels and the one or more high-bandwidth RT input channels.

[0043] Example 15 is the method from Example 13, wherein the one or more high-bandwidth input channels include one or more RET input channels, and the first set of pipes includes fewer pipes than a number of pipes in the third set of pipes.

[0044] Example 16 is the method from Example 13, wherein receiving one or more signals from the DUT includes receiving one or more signals from at least one of the high-bandwidth RET, RF and RT signals.

[0045] Example 17 is the method from one of Examples 11 to 16, wherein receiving one or more signals from the DUT from the one or more high-bandwidth input channels includes receiving signal data.

[0046] Example 18 is the method from Example 17, wherein receiving one or more signals from the one or more low-bandwidth RT input channels includes receiving one or more signals from a power supply that powers the DUT, and receiving the one or more signals from the one or more low-bandwidth RT channels includes receiving power data.

[0047] Example 19 is the procedure from Example 18, wherein the temporal matching of the low-bandwidth data and the high-bandwidth data includes matching the power data and the signal data.

[0048] Example 20 is the procedure from Example 19, which further includes performing a signal integrity analysis and a power integrity analysis of the time-matched power and signal data.

[0049] All features disclosed in the description, including the claims, the abstract, and the drawings, as well as all steps in each disclosed method or process, may be combined in any combination, except for combinations in which at least some of these features and / or steps are mutually exclusive. Each feature disclosed in the description, including the claims, the abstract, and the drawings, may be replaced by alternative features that serve the same, an equivalent, or a similar purpose, unless expressly stated otherwise.

[0050] Furthermore, this written description refers to certain features. It is understood that the disclosure in this specification includes all possible combinations of these certain features. For example, if a particular feature is disclosed in connection with a particular aspect, this feature may also be used, to the extent possible, in connection with other aspects.

[0051] Where this application refers to a process with two or more defined steps or operations, the defined steps or operations may be carried out in any order or simultaneously, provided that the context does not preclude such possibilities.

[0052] Although specific examples of the invention have been presented and described for illustrative purposes, it is understood that various modifications can be made without deviating from the spirit and scope of the invention. Accordingly, the invention should only be limited by the appended claims. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 718.480

[0001] US 11,789,051

[0006] US 2024 / 0313795

[0006]

Claims

[1] A signal and power analysis instrument comprising the following: one or more high-bandwidth input channels configured as at least one of one or more equivalence time (RET) input channels or one or more radio frequency (RF) channels connected to a device under test (DUT); one or more input channels configured as one or more low-bandwidth real-time (RT) input channels; one or more analog-to-digital converters (ADCs), each ADC having one or more pipes, wherein a first set of the one or more pipes is connected to the one or more high-bandwidth input channels to generate high-bandwidth data, and wherein a second set of the one or more pipes is connected to the one or more low-bandwidth RT input channels to generate low-bandwidth data; a system clock connected to one or more high-bandwidth input channels and one or more low-bandwidth RT input channels; a memory connected to the system clock, to the first set of one or more pipes connected to one or more high-bandwidth input channels, and to the second set of one or more pipes connected to one or more low-bandwidth RT input channels; and one or more processors trained to execute code that causes the one or more processors to do the following: Storing low-bandwidth data from the second set of pipes in memory; Storing high-bandwidth data from the first set of pipes into memory; and Timing synchronization of high-bandwidth and low-bandwidth data using the system clock. [2] The signal and power analysis instrument according to claim 1, wherein the one or more high bandwidth input channels comprise one or more RET input channels and one or more RF input channels, only RET input channels or only RF input channels. [3] The signal and power analysis instrument according to claim 1 or 2, wherein the one or more high-bandwidth input channels further comprise one or more high-bandwidth RT input signal channels and the instrument further comprises a third set of pipes connected to the one or more high-bandwidth RT input signal channels. [4] The signal and power analysis instrument according to claim 3, wherein the one or more high-bandwidth input channels comprise one or more RET input channels and one or more high-bandwidth RT input channels, one or more RF input channels and one or more high-bandwidth RT channels, or one or more RET input channels, one or more RF input channels and one or more high-bandwidth RT input channels. [5] The signal and power analysis instrument according to claim 3 or 4, wherein the one or more high bandwidth input channels comprise one or more RET input channels and a first set of pipes comprises fewer pipes than a number of pipes in the third set of pipes. [6] The signal and power analysis instrument according to any one of claims 1 to 5, wherein the one or more high-bandwidth input channels are configured to receive one or more signals from the DUT, and the high-bandwidth data comprise signal data. [7] The signal and power analysis instrument according to claim 6, wherein the one or more low-bandwidth RT input channels are configured to be connected to a power supply that powers the DUT, and the low-bandwidth data includes power data. [8] The signal and power analysis instrument according to claim 7, wherein the code that causes the one or more processors to time-align the high-bandwidth data and the low-bandwidth data comprises code to align the power data and the signal data using the system clock. [9] The signal and power analysis instrument according to any one of claims 6 to 8, wherein the signal data comprise at least either RET data or RF data. [10] The signal and power analysis instrument according to any one of claims 6 to 9, wherein the signal data includes at least high bandwidth RET, RF and RT data. [11] A method for performing a signal integrity analysis and a power integrity analysis, comprising the following: Receiving one or more signals from one or more input channels configured as one or more low-bandwidth real-time (RT) input channels; Receiving one or more signals from a device under test (DUT) via one or more high-bandwidth input channels configured as one or more equivalence-time (RET) input channels and radio frequency (RF) channels; Using an initial set of one or more analog-to-digital converter (ADC) pipes connected to the one or more low-bandwidth RT input channels to generate low-bandwidth RT data; Using a second set of one or more ADC pipes connected to one or more high-bandwidth input channels to generate high-bandwidth data; Storing the high-bandwidth data and the low-bandwidth real-time data in a single capture memory; and Timing synchronization of low-bandwidth RT data and high-bandwidth data using a system clock. [12] The method according to claim 11, wherein receiving signals from the one or more high-bandwidth input channels comprises one or more of the following steps: receiving signals from the one or more RET input channels and the one or more RF input channels, receiving signals only from the one or more RET input channels or only from the one or more RF input channels. [13] The method according to claim 11 or 12, further comprising receiving one or more signals from one or more high-bandwidth RT input channels and using a third set of ADC pipes connected to the one or more high-bandwidth RT input channels. [14] The method according to claim 13, wherein receiving one or more signals from the one or more high-bandwidth input channels comprises receiving one or more signals from the one or more RET input channels and the one or more high-bandwidth RT input channels, from the one or more RF input channels and the one or more high-bandwidth RT channels, or from the one or more RET input channels, from the one or more RF input channels and from the one or more high-bandwidth RT input channels. [15] The method according to claim 13 or 14, wherein the one or more high bandwidth input channels comprise one or more RET input channels and the first set of pipes comprises fewer pipes than a number of pipes in the third set of pipes. [16] The method according to any one of claims 13 to 15, wherein receiving one or more signals from the DUT comprises receiving one or more signals from at least one of the high bandwidth RET, RF and RT signals. [17] The method according to any one of claims 11 to 16, wherein receiving one or more signals from the DUT from the one or more high-bandwidth input channels comprises receiving signal data. [18] The method according to claim 17, wherein receiving one or more signals from the one or more low-bandwidth RT input channels comprises receiving one or more signals from a power supply that powers the DUT, and receiving the one or more signals from the one or more low-bandwidth RT channels comprises receiving power data. [19] The method according to claim 18, wherein the timing adjustment of the low bandwidth data and the high bandwidth data includes adjusting the power data and the signal data. [20] The method according to claim 19, which further comprises performing a signal integrity analysis and a power integrity analysis on the time-matched power data and signal data.

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