Level converter for power converters

Abstract

A level shifter for a power converter comprises: a differential detector; a first transistor with a drain electrically connected to a first node of the differential detector, a gate, and a source; a second transistor with a drain electrically connected to a second node of the differential detector, a gate, and a source; and a circuit configured to simultaneously apply an equal voltage to the source of the first and second transistors based on a digital signal input to the level shifter. The circuit is also configured to apply a different gate voltage, depending on the input digital signal, to select which side of the level shifter will draw current to the differential detector.The differential detector is configured to convert the digital signal into a different voltage level based on a differential current between the first and second transistors.

Description

[0001] Power converters, such as half-bridge and full-bridge converters, typically employ a bootstrap technique that includes a bootstrap capacitor to create a floating voltage range to drive one or more of the converter's high-side power switches. In a typical DC-DC buck converter application, there is a dead time between when the high-side power switch is active and when the low-side power switch is active, during which all power switches are off. During this dead time, the output inductor forces current to flow, and as a result, the switching node of the power converter is forced to a negative value. When silicon transistors are used to implement the power switches, the low-side power switch incorporates a parasitic / body diode, and the negative voltage across the switching node is approximately -0.7 V.When one or more GaN transistors (or high-electron-mobility gallium nitride transistors, or GaN HEMTs) are used to implement the low-side power switch, the low-side power switch lacks a body diode and can conduct current when the voltage between the drain and gate creates a channel. In this case, the switching node of the power converter is forced to a more negative voltage, such as in the range of -2 V to -5 V. Due to the presence of the bootstrap capacitor, the bootstrap node, which is the positive supply voltage of the high-side driver, follows the switching node of the power converter and drops to a level close to ground.To exit dead-time mode, the input control of the high-side driver switches, sends a signal from the low-voltage input section to the high-side section through a level shifter, and finally switches the driver for the high-side power switch. Since the switching node of the power converter and the low-voltage input section are both close to 0 V in this case, there is insufficient headroom for standard level shifter architectures to propagate the current signal.

[0002] Therefore, there is a need for a level converter design with improved voltage reserve for power converter applications.

[0003] The object of the present invention is to provide level converters and a power converter with improved properties.

[0004] This problem is solved by a level converter according to claim 1, a level converter according to claim 11 and a power converter according to claim 15.

[0005] According to one embodiment of a level converter, the level converter has the following features: a differential detector; a first transistor with a drain electrically connected to a first node of the differential detector, a gate and a source; a second transistor with a drain electrically connected to a second node of the differential detector, a gate and a source; and a circuit configured to simultaneously apply an equal voltage to the source of the first and second transistors based on a digital signal input to the level converter, wherein the differential detector is configured to convert the digital signal into a different voltage level based on a differential current between the first and second transistors.

[0006] According to another embodiment of a level converter, the level converter has the following features: a differential detector; a first transistor with a drain electrically connected to a first node of the differential detector, a gate, and a source; a second transistor with a drain electrically connected to a second node of the differential detector, a gate, and a source; a common capacitor with a first terminal and a second terminal; a first switching device electrically connected between a first DC supply voltage or a local ground reference and the first terminal of the common capacitor; a second switching device electrically connected between the first terminal of the common capacitor and ground or a bootstrap node;and a third switching device electrically connected between the second terminal of the common capacitor and ground or the bootstrap node, wherein the second terminal of the common capacitor is electrically connected to the source of the first and second transistors.

[0007] According to one embodiment of a power converter, the power converter has the following features: a high-side power switching device; a gate driver configured to drive a gate of the high-side power switching device; and a level shifter.The level shifter has the following features: a differential detector; a first transistor with a drain electrically connected to a first node of the differential detector, a gate and a source; a second transistor with a drain electrically connected to a second node of the differential detector, a gate and a source; and a circuit configured to simultaneously apply an equal voltage to the source of the first and second transistors based on a digital signal input to the level shifter, the differential detector being configured to convert the digital signal into a voltage range of the gate driver based on a differential current between the first and second transistors.

[0008] Experts will recognize additional features and benefits upon reading the following detailed description and examining the accompanying drawings.

[0009] The elements in the drawings are not necessarily to scale relative to each other. The same reference numerals denote corresponding similar parts. The features of the various illustrated embodiments can be combined, provided they are not mutually exclusive.

[0010] Preferred embodiments of the present invention are discussed in more detail below with reference to the accompanying drawings, in which: Fig. Figure 1A illustrates a circuit diagram of a level-up converter according to an exemplary embodiment. Fig. Figure 1B illustrates the on / off states of various switching devices included in the level-up converter and the gate-source voltage (Vgs) of the high-voltage transistors included in the level-up converter during operation of the level-up converter. Fig. 2 illustrates a circuit diagram of a level-up converter according to another embodiment. Fig. Figure 3 illustrates a circuit diagram of a level-up converter according to another embodiment. Fig. Figure 4 illustrates a circuit diagram of a level-step converter according to an exemplary embodiment. Fig. Figure 5 illustrates a circuit diagram of a common switching network contained in the level-up converter according to an exemplary embodiment. Fig. Six different signal waveforms are illustrated, which correspond to the operation of the level-up converter of Fig. 5 are assigned. Fig. Figure 7 illustrates a circuit diagram of a common switching network contained in the level-step converter according to an exemplary embodiment. Fig. Figure 8 illustrates a circuit diagram of a switching device contained in a gate potential switching network of the level converter, according to an exemplary embodiment. Fig. Figure 9 illustrates an embodiment of a power converter which includes the level-up or level-down converter described herein.

[0011] The embodiments described herein provide a level shifter with improved voltage margin. The level shifter can be used in power converter applications such as half-bridge and full-bridge converters. The level shifter uses high-voltage transistors and a differential circuit to transmit digital information from a low-side region to a high-side region. The high-voltage transistors are driven at their source terminals, not their gate terminals. The gate terminals of the high-voltage transistors are connected to ground or to a DC voltage, e.g., near ground. The same voltage is simultaneously applied to the source of the high-voltage transistors, with the applied source voltage corresponding to the low or high level of the input digital signal.The gates of the high-voltage transistors are controlled separately to set different Vgs (gate-source voltage) for both high-voltage devices.

[0012] For example, a common capacitor and a common switching network can be used to simultaneously apply the same voltage to the source of high-voltage transistors. In response to a transition in the digital signal, the common switching network can connect the common capacitor to the source of the high-voltage transistors, thus simultaneously applying a negative voltage to the source of the transistors. After a transition in the digital signal, the common switching network can then pre-charge the common capacitor for the next transition in the digital signal. In another example, a common diode can be part of the circuit that simultaneously applies the same voltage to the source of the high-voltage transistors. The use of common components, such as...Using a common capacitor and a common switching network and / or a common diode to simultaneously apply the same voltage to the source of the high-voltage transistors reduces the number and size of the components, shares the high-voltage insulation, and eliminates the need for an additional high-voltage device.

[0013] Next, exemplary embodiments of the level converter and the power converters using the level converter are described with reference to the figures.

[0014] Fig. Figure 1A illustrates a circuit diagram of a level shifter 100 according to an exemplary embodiment. The level shifter 100 comprises a differential detector 102, a first (high-voltage) transistor M1a with a drain D1a electrically connected to a first node nda of the differential detector 102, and a second (high-voltage) transistor M1b with a drain D1b electrically connected to a second node ndb of the differential detector 102. The gate G1a of the first transistor M1a is electrically connected to ground or a fixed DC voltage vb. The gate G1b of the second transistor M1b is also electrically connected to ground or a fixed DC voltage vb. The fixed DC voltage vb can be the same or different for the first and second transistors M1a and M1b.

[0015] The level shifter 100 also includes a circuit 104 that simultaneously applies the same voltage vdd_Iv to the sources S1a and S1b of the first and second transistors M1a and M1b, based on a digital signal pwm_i input to the level shifter 100. The differential detector 102 converts the digital input signal pwm_i into a different voltage level pwm_o based on a differential current between the first transistor M1a and the second transistor M1b. The first and second transistors M1a and M1b exhibit short pull-down current pulses. The differential detector 102 detects the difference and generates a pulse that is buffered so that the pulse remains active until the next cycle. This allows for rapid turn-off of the first transistor M1a (or the second transistor M1b), thereby reducing power losses and relaxing reliability requirements for these transistors.

[0016] In Fig. Circuit 104 comprises a common capacitor c1 and a common switching network s1-s3. The capacitor c1 and the switching network s1-s3 are "common" in that the same capacitor c1 and the same switching network are used to apply a voltage vdd_lv to the source S1a, S1b of the first and second transistors M1a, M1b. The in Fig. The common capacitor / switching network circuit configuration shown in Figure 1A allows the same voltage vdd_lv to be applied simultaneously to the sources S1a and S1b of the first and second transistors M1a and M1b, based on the digital signal pwm_i input to the level shifter 100. Accordingly, separate capacitors and switching networks are not required to properly bias the sources S1a and S1b of the first and second transistors M1a and M1b. Furthermore, the switching devices s4a, s5a, s4b, and s5b determine which high-voltage transistor M1a and M1b will maintain Vgs equal to OV and which high-voltage transistor M1a and M1b will maintain a high Vgs to transmit a signal.

[0017] In response to a transition in the digital signal pwm_i input to the level shifter 100, the common switching network s1-s3 connects the common capacitor c1 to the source of the first and second transistors, simultaneously applying a negative voltage to the source S1a, S1b of the first and second transistors M1a, M1b. Furthermore, the common switching network s1-s3 simultaneously selects the gate G1a, G1b of one of the first and second transistors M1a, M1b to be short-circuited to the common source (node ​​ns), while the other gate G1b, G1a is held grounded, so that one of the high-voltage transistors M1a, M1b has Vgs = 0V and the other high-voltage transistor M1b, M1a has Vgs = 3V. After the transition in the digital input signal pwm_i, the common switching network s1-s3 precharges the common capacitor c1 for the next transition in the digital input signal pwm_i.

[0018] In Fig. 1A comprises the common switching network s1-s3, a first switching device s1, which is electrically connected between a first DC supply voltage or a local ground reference vdd_lv and a first terminal 106 of the common capacitor c1, a second switching device s2, which is electrically connected between the first terminal 106 of the common capacitor c1 and ground or a bootstrap node HB, and a third switching device s3, which is electrically connected between a second terminal 108 of the common capacitor c1 and ground or the bootstrap node HB. The second terminal 108 of the common capacitor c1 is electrically connected to the sources S1a, S1b of the first and second transistors M1a, M1b.

[0019] The second switching device s2 turns on in response to a transition in the digital signal pwm_i input to the level shifter 100. The first switching device s1 and the third switching device s3 are both off when the second switching device s2 is on. In this (first) state, the voltage across the common capacitor c1 is simultaneously applied to the sources S1a, S1b of the first and second transistors M1a, M1b. The second switching device s2 turns off after a predefined time from the transition in the digital input signal pwm_i. The first switching device s1 and the third switching device s3 are both on when the second switching device s2 is off. In this (second) state, the common capacitor c1 charges to vdd_Iv in preparation for the next transition in the digital input signal pwm_i.

[0020] In Fig. In this case, level converter 100 is an upward-level converter, meaning that it converts the digital signal pwm_i input to it into a higher voltage level. In this upward-level converter configuration, differential detector 102 is connected between a bootstrap node HB and the first and second transistors M1a and M1b. These transistors are NMOS (n-channel metal-oxide-semiconductor) devices connected between differential detector 102 and ground. Differential detector 102 converts the digital input signal pwm_i into a higher voltage level based on the differential current between transistor M1a and transistor M1b.

[0021] The level converter 100 in Fig. 1A is differential, with the operation of the left and right sides being complementary. The switching devices s1, s2, s3 of the common switching network s1-s3 are used to control the node ns, which controls the current of both the first transistor M1a and the second transistor M1b. Therefore, the same switching network s1-s3 controls the current in both sides of the level shifter 100.

[0022] In a non-switching state condition, the third switching device s3 is switched on, ensuring that node ns is connected to GND and transistors M1a and M1b are switched off. During this state, the first switching device s1 is also switched on, charging the common capacitor c1 with the voltage difference between vdd_Iv and GND. To allow the charging of the common capacitor c1, the second switching device s2 is kept switched off. Since transistors M1a and M1b are both switched off in this state, the differential detector 102 is buffered to the last state level.

[0023] The left side of the level shifter 100 is used to temporarily store the differential detector 102 in a first position. The right side of the level shifter 100 is used to temporarily store the differential detector 102 in a second position. Since the same voltage is simultaneously applied to the sources S1a and S1b of the first and second transistors M1a and M1b via the common capacitor c1 and the common switching network s1-s3 in Fig. When current 1A is applied, the level converter 100 also includes a first switching network 110, which controls the electrical potential at the gate G1a of the first transistor M1a, and a second switching network 112, which controls the electrical potential at the gate G1b of the second transistor M1b. The separate gate-potential switching networks 110 and 112 allow the differential detector 102 to be temporarily stored in both positions.

[0024] The first gate potential switching network 110 comprises a first switching device s4a, which is electrically connected between ground and the gate G1a of the first transistor M1a at node nga. The first gate potential switching network 110 also comprises a second switching device s5a, which is electrically connected between the gate G1a and the source S1a of the first transistor M1a. The second gate potential switching network 112 similarly comprises a third switching device s4b, which is electrically connected between ground and the gate G1b of the second transistor M1b at node ngb, and a fourth switching device s5b, which is electrically connected between the gate G1b and the source S1b of the second transistor M1b.

[0025] The first gate potential switching network 110 can be used to connect the gate G1a of the first transistor M1a to ground or close to ground potential by closing switching device s4a and opening switching device s5a, so that a voltage difference exists between the gate-source voltage (VGS) and the drain-source voltage (VDS) of the first transistor M1a, which draws current in the first (left) node nda of the differential detector 102. The second gate potential switching network 112 can be used to disconnect the gate G1b of the second transistor M1b from ground by opening switching device s4b and closing switching device s5b, so that there is little or no voltage difference between the gate-source voltage and the drain-source voltage of the second transistor M1b, and therefore no current is drawn in the second (right) node ndb of the differential detector 102. Fig. Figure 1B illustrates the on / off states of the switching devices s1, s2, s3 of the common switching network s1-s3 and the switching devices s4a, s5a, s4b, s5b of the gate potential switching networks 110, 112 and the Vgs of the first and second high voltage transistors M1a, M1b during the operation of the level shifter 100.

[0026] The differential detector 102 detects that current is flowing in the left side (from transistor M1a) and no current is flowing in the right side (from transistor M1b), and in response switches the output pwm_o of the level shifter 100 from low to high (or high to low). The current flowing in the first transistor M1a is supplied by the common capacitor c1, which can be switched on for only a few nanoseconds, for example (the switch-on time must be slightly longer than the propagation delay of the level shifter 100). After a predefined time, the first gate potential switching network 110 disconnects the gate G1a of the first transistor M1a from ground by opening the switching devices s4a and s5a. Since there is no current difference between the first and second transistors M1a and M1b in this state, the output of the differential detector 102 is temporarily stored.

[0027] To temporarily store the differential detector 102 in the opposite position, the second gate potential switching network 112 can be used to connect the gate G1b of the second transistor M1b to ground or near ground potential by closing the switching device s4b and opening the switching device s5b, so that there is a voltage difference between the gate-source voltage and the drain-source voltage of the second transistor M1b, which draws current into the second (right) node ndb of the differential detector 102.The first gate potential switching network 110 can be used to disconnect the gate G1a of the first transistor M1a from ground by opening the switching device s4a and closing the switching device s5a, so that there is little or no voltage difference between the gate-source voltage and the drain-source voltage of the first transistor M1a and therefore no current is drawn in the first (left) node nda of the differential detector 102.

[0028] The differential detector 102 detects that current is flowing in the right-hand side (from transistor M1b) and no current is flowing in the left-hand side (from transistor M1a), and in response switches the output pwm_o of the level shifter 100 from high to low (or low to high). The current flowing in the second transistor M1b is supplied by the common capacitor c1, which, as explained above, can only be switched on for a few nanoseconds (the turn-on time must be slightly longer than the propagation delay of the level shifter 100). After a predefined time, the second gate potential switching network 112 disconnects the gate G1b of the second transistor M1b from ground by opening the switching devices s4b and s5b. Since there is no current difference between the second and the first transistors M1b and M1a in this state, the output of the differential detector 102 is buffered again.The size of the common capacitor c1 should be designed to ensure a small discharge during the time when the respective high-voltage transistors M1a, M1b are switched on.

[0029] Fig. Figure 2 illustrates a circuit diagram of the level converter 100 according to another embodiment. The level converter 100 in Fig. 2 is similar to the level converter 100 in Fig. 1A. In Fig. 2. The level shifter 100 further comprises a first additional switching device M2a, which is electrically connected between the source S1a of the first transistor M1a and the common capacitor c1, and a second additional switching device M2b, which is electrically connected between the source S1b of the second transistor M1b and the common capacitor c1. In this embodiment, the additional switching devices M2a, M2b are NMOS devices and can have a lower rated voltage than the first and the second (main) transistors M1a, M1b. Furthermore, the second switching device s5a of the first gate potential switching network 110 and the second switching device s5b of the second gate potential switching network 112 are combined as a pair of cross-coupled NMOS devices M3a, M3b in Fig. 2 implemented. The drain D2a of the first additional switching device M2a is electrically connected to the source S1a of the first transistor M1a, the source S2a of the first additional switching device M2a is electrically connected to the common node ns of circuit 104, and the gate G2a of the first additional switching device M2a is electrically connected to the node nga of the first gate potential switching network 110. The drain D2b of the second additional switching device M2b is electrically connected to the source S1b of the second transistor M1b, the source S2b of the second additional switching device M2b is electrically connected to the common node ns of circuit 104, and the gate G2b of the second additional switching device M2b is electrically connected to the node ngb of the second gate potential switching network 112.

[0030] Fig. Figure 3 illustrates a diode-based embodiment of the level converter 100. Fig. Figure 3 comprises the circuit 104 of the level converter 100 with the common capacitor c1 and a common diode d1, and the common switching network s1-s3 is omitted. The anode of the common diode d1 is electrically connected to the source S2a, S2b of the first and the second additional switching device M2a, M2b. The cathode of the common diode d1 is electrically connected to ground. The common capacitor c1 has a first terminal 106 to which a negative pulse signal “npulse” is applied, derived from the digital input signal pwm_i by a pulse generator 114. The second terminal 108 of the common capacitor c1 is electrically connected to the source S2a, S2b of the first and the second additional switching device M2a, M2b and to the anode of the common diode d1.

[0031] Fig. Figure 4 illustrates a circuit diagram of the level converter 100 according to another embodiment. The one in Fig. The embodiment shown in 4 is similar to the one in Fig. 1A and Fig. 2. Example shown. In Fig. In section 4, the level converter 100 is a step-down level converter, meaning that it converts the digital signal pwm_i input to the level converter 100 into a lower voltage level. In this step-down level converter configuration, the differential detector 102 is connected between ground and the first and second transistors M1a and M1b. The first and second transistors M1a and M1b are PMOS devices (p-channel metal-oxide-semiconductor devices) connected between the differential detector 102 and the bootstrap node HB. The additional switching devices M2a and M2b of the gate potential switching networks 110 and 112 are also PMOS devices. The first switching device s1 of the common switching network s1-s3 is electrically connected between a first local ground reference vss_local and the first terminal 106 of the common capacitor c1.The second switching device s2 of the common switching network s1-s3 is electrically connected between the first terminal 106 of the common capacitor c1 and the bootstrap node HB. The third switching device s3 of the common network s1-s3 is electrically connected between the second terminal 108 of the common capacitor c1 and the bootstrap node HB. The differential detector 102 converts the digital input signal pwm_i into a lower voltage level based on the differential current between the first transistor M1a and the second transistor M1b.

[0032] Fig. Figure 5 illustrates an embodiment of the common switching network s1-s3 for the embodiment of the step-up level converter. Fig. 5 The first switching device s1 of the common switching network s1-s3 comprises a first PMOS transistor M12 with a positive pulse gate input G12 via an inverter INV2, which is electrically connected to the first terminal 106 of the common capacitor c1, a drain D12, which is electrically connected to the DC supply voltage vdd_Iv, and a source S12. The first switching device s1 in Fig. Section 5 also includes a first inverter 200, which is formed by a second PMOS transistor M14 and a first NMOS transistor M15. The first inverter 200 has a positive pulse input via inverter INV3, which is applied to the gate G14 of the second PMOS transistor M14 and to the gate G15 of the first NMOS transistor M15. The drain D14 of the second PMOS transistor M14 is electrically coupled to the source S12 of the first PMOS transistor M12. The source S15 of the first NMOS transistor M15 is grounded.

[0033] The second switching device s2 of the common switching network s1-s3 in Fig. 5 comprises a second NMOS transistor M10 with a grounded gate input G10, a source S10 electrically connected to the source S1 of the first transistor M1a and the second terminal 108 of the common capacitor c1, and a drain D10. The second switching device s2 in Fig. 5 also includes a third PMOS transistor M13 with a grounded gate input G13, a source S13 electrically connected to the output of the first inverter 200, and a drain D13 electrically connected to the drain D10 of the second NMOS transistor M10.

[0034] The third switching device s3 of the common switching network s1-s3 in Fig. 5 comprises a third NMOS transistor M11 with a gate G11 electrically connected to the drain D13 of the third PMOS transistor P13 and the drain D10 of the second NMOS transistor M10, a source S11 electrically connected to the source S1 of the first transistor M1, and a drain D11 electrically connected to ground.

[0035] Fig. Figure 6 illustrates various signal waveforms that correspond to the operation of the in Fig. The implementation of the level-up converter shown in Figure 5 is assigned to the pulse generator 114, which generates the negative pulse output npulse based on the digital signal pwm_i input to the level converter 100. In the stable state, the negative pulse output of the pulse generator 114 is set to a logic 1 level, and node n11 is connected to the DC supply voltage vdd_Iv to charge the common capacitor c1. Ground is provided to the common node ns by the third NMOS transistor M11 of the third switching device s3. The gate G11 of the third NMOS transistor M11 is coupled to node n13, which is connected to the DC supply voltage vdd_Iv supplied by node n12 through the third PMOS transistor M13 of the second switching device s2.The potential of node n12 is defined by the potential of node n10 and node n11, which is detected by inverter INV2, which controls node n14.

[0036] When a negative edge appears at the output of pulse generator 114, node n10 moves upwards, causing node n12 to immediately move downwards, which in turn moves node n13 downwards to approximately a threshold voltage Vt above ground (until transistor M13 allows it). This causes the third NMOS transistor M11 of the third switching device s3 to be almost completely switched off. At this point, node n13 becomes high-impedance, and the common node ns is not driven and is defined only by the charge state of the common capacitor c1 with respect to node n11. Switching off transistor M11 before the movement of the common node ns prevents the common capacitor c1 from being unintentionally discharged by transistor M11 while node ns moves below ground potential.

[0037] The upward movement of node n10 also causes node n11 to slowly move downwards due to the inrush current at the first transistor M1a. The common capacitor c1 forces the common node ns to follow the movement of node n11, but node ns moves downwards from ground potential to a negative value. Once node ns reaches a threshold voltage Vt below ground, the second NMOS transistor M10 of the second switching device s2 begins to conduct and connects nodes ns1 and n13, forcing the third NMOS transistor M11 of the third switching device s3 to remain off throughout the transition.

[0038] In this state, the common capacitor c1 supplies charge to the source S1a of the first transistor M1a of node n11, which is held at ground potential by inverter INV1. The charge on the common capacitor c1 decreases, causing the common node ns to slowly move upwards towards ground potential. The charge supplied by the common capacitor c1 is sufficient to be detected at the bootstrap node HB domain. Sufficient time is provided to the bootstrap node HB domain to reliably detect the pulse, while simultaneously reducing the pulse width as much as possible to minimize power consumption.

[0039] When the digital signal pwm_i, input to the level shifter 100, begins a rising edge, the pulse output npulse of the pulse generator 114 terminates the negative pulse. Node n10 then moves downwards, causing node n11 to begin moving upwards. Node ns follows node n11 upwards, while the third NMOS transistor M11 of the third switching device s3 is held off (transistor M10 keeps node n13 connected to node ns1). When node n11 moves high enough, inverter INV2 detects this condition and moves node n14 downwards, causing node n12 to rise. Node n13 begins to follow node n12 once the voltage at node n12 exceeds the threshold voltage Vt of the third PMOS transistor M13 of the second switching device s2.This activates transistor M11, which provides a path for the common capacitor c1 to recharge via inverter INV1 and transistor M11. The process returns to its initial state and is then ready to be repeated.

[0040] Fig. Figure 7 illustrates the same circuit as Fig. 5, but implemented as a level-down converter. In Fig. 7. The pulse generator 114 generates a positive pulse output “ppulse” based on the digital signal pwm_i, which is input to the level converter 100. Furthermore, the first switching device s1 of the common switching network s1-s3 comprises a first NMOS transistor M21 with a negative pulse gate input G21 via an inverter INV21, which is electrically connected to the first terminal 106 of the common capacitor c1, a source S21, which is electrically connected to a first local ground reference vssf, and a drain D21. The first switching device s1 also includes a first inverter 500, which is formed by a second NMOS transistor M25 and a first PMOS transistor M26. The first inverter 500 has a negative pulse input via the inverter INV23, which is applied to the gate G25 of the second NMOS transistor M25 and to the gate G25 of the first PMOS transistor M26.The source S25 of the second NMOS transistor M25 is electrically coupled to the drain D21 of the first NMOS transistor M21. The drain D26 of the first PMOS transistor M26 is electrically connected to the bootstrap node HB.

[0041] The second switching device s2 of the common switching network s1-s3 in Fig. 5 comprises a second PMOS transistor M24 with a gate G24 electrically connected to the bootstrap node HB, a source S24 electrically connected to the second terminal 108 of the common capacitor c1, and a drain D24. The second switching device s2 in Fig. 5 also includes a third NMOS transistor M22 with a gate G22 electrically connected to the bootstrap node HB, a source S22 electrically connected to the output of the first inverter 500, and a drain D22 electrically connected to the drain D24 of the second PMOS transistor M24.

[0042] The third switching device s3 of the common switching network s1-s3 in Fig. 5 comprises a third PMOS transistor M23 with a gate G23 electrically connected to the drain D22 of the third NMOS transistor M22 and the drain D24 of the second PMOS transistor M24, a source S23 electrically connected to the second terminal 108 of the common capacitor c1, and a drain D23 electrically connected to the bootstrap node HB.

[0043] Fig. Figure 8 illustrates an embodiment of the first switching device s4a, 24b, which is included in both gate potential switching networks 110, 112 of the level converter 100. Fig. 8 comprises the first switching device s4a, 24b of each gate-potential switching network 110, 112, comprising a first NMOS transistor M8 with a body diode BD8, a grounded gate G8, a drain D8 electrically connected to the corresponding gate node nga / ngb, and a source S8. Both first switching devices s4a, 24b also comprise a second NMOS transistor M7 with a body diode BD7, a gate G7 electrically connected to the source S8 of the first NMOS transistor M8 at node n1, a drain D8 electrically connected to the corresponding gate node nga / ngb, and a grounded source S7.Both first switching devices s4a, 24b further comprise a first PMOS transistor M6 with a body diode M6, a grounded gate G6, a drain D6 electrically connected to a control input ctrl_i, and a source S6 electrically connected to the source S8 of the first NMOS transistor M8 and the gate G7 of the second NMOS transistor M7 at node n1. The control input ctrl_i determines whether the first switching device s4a, 24b is switched on or off. The control input ctrl_i for the first switching devices s4a, 24b is complementary, such that either the left side or the right side of the level shifter 100 is active at any given time, as previously explained herein in connection with the intermediate storage functionality of the differential detector 102.

[0044] Fig. Figure 9 illustrates an embodiment of a power converter 300, e.g., a half-bridge converter, a full-bridge converter, etc., which includes the level shifter 100 described herein. The power converter 300 also includes a high-side power switching device MPHS and a (floating) gate driver 302 for driving a gate G_MPHS of the high-side power switching device MPHS. The level shifter 100 converts a digital signal HI, which is input to the level shifter 100, into a voltage range dr_hs of the high-side gate driver 302.

[0045] As explained herein, the level converter 100 comprises the following: a differential detector 102; a first transistor M1a with a drain D1a electrically connected to a first node nda of the differential detector 102, a gate G1a, and a source S1a; a second transistor M1b with a drain D1b electrically connected to a second node ndb of the differential detector 102, a gate G1b, and a source S1b; and a circuit 104 configured to simultaneously apply an equal voltage to the sources S1a and S1b of the first and second transistors M1a and M1b based on a digital signal pwm_i input to the level converter 100. The circuit 104, which simultaneously applies the same voltage to the sources S1a and S1b of the first and second transistors M1a and M1b of the level converter 100, comprises, for example,A common capacitor c1 with a first terminal 106 and a second terminal 108, a first switching device s1 electrically connected between a first DC supply voltage vdd_lv or a local ground reference and the first terminal 106 of the common capacitor c1, a second switching device s2 electrically connected between the first terminal 106 of the common capacitor c1 and ground (boost-level converter housing) or a bootstrap node HB (step-down-level converter housing), and a third switching device s3 electrically connected between the second terminal 108 of the common capacitor c1 and ground (boost-level converter housing) or the bootstrap node HB (step-down-level converter housing). The second terminal 108 of the common capacitor c1 is electrically connected to the sources S1a, S1b of the first and second transistors M1a, M1b of the level converter 100.The differential detector 102 converts the digital signal pwm_i into a voltage range of the high-side gate driver 302 on the basis of the differential current between the first transistor M1a and the second transistor M1b of the level converter 100.

[0046] In Fig. 9. The power converter 300 has a buck converter topology. However, the power converter 300 can have a different type of power converter topology, e.g., boost converter, buck-boost converter, etc. In the case of a buck converter, the power converter 300 also includes a low-side power switching device MPLS, which is electrically connected to the high-side power switching device MPHS in a half-bridge configuration. In particular, the drain D_MPLS of the low-side power switching device MPLS is electrically connected to the source S_MPHS of the high-side power switching device MPHS at a switching node SW, wherein the source S_MPLS of the low-side power switching device MPLS is electrically connected to a reference potential VSS, e.g., ground, and the drain S_MPHS of the high-side power switching device MPHS is electrically connected to a voltage source VIN.A gate driver 304 is provided for controlling the gate G_MPLS of the low-side power switching device MPLS. In one embodiment, the drivers 302 and 304 are GaN (gallium nitride) drivers.

[0047] An inductor L1 is electrically connected to the switching node SW between the low-side power switching device MPLS and the high-side power switching device MPHS. A bootstrap capacitor Cboot is electrically connected between the switching node SW and the bootstrap node HB, providing a supply voltage for the gate driver 302 for the high-side power switching device MPHS. The load supplied with power by the power converter 300 is in Fig. Figure 9 illustrates a resistor Rload, where a capacitor Cout stabilizes the voltage Vout applied to the load Rload. A switching device “bootsw” recharges the bootstrap capacitor Cboot via a voltage source VCC for the high-side gate driver 302.

[0048] In the case of the step-up level converter, the differential detector 102 is connected between the bootstrap node HB and the first and second transistors M1a, M1b of the step-up level converter 100, the first and second transistors M1a, M1b of the step-up level converter 100 are connected between the differential detector 102 and ground, and the differential detector 102 converts the digital input signal HI into a higher voltage level based on the differential current between the first transistor M1a and the second transistor M1b of the step-up level converter 100.

[0049] In the case of the step-down level converter, the differential detector 102 is connected between ground and the first and second transistors M1a, M1b of the step-down level converter 100, the first and second transistors M1a, M1b of the step-down level converter 100 are connected between the differential detector 102 and the bootstrap node HB, and the differential detector 102 converts the digital input signal HI into a lower voltage level based on the differential current between the first transistor M1a and the second transistor M1b of the step-down level converter 100.

[0050] As in Fig.As shown in Figure 1A, the circuit 104, which simultaneously applies the same voltage to the sources S1a and S1b of the first and second transistors M1a and M1b of the level shifter 100, can include a common capacitor c1 and a common switching network s1-s3. In response to a first transition in the digital input signal HI for the high-side gate driver 302, the first gate potential switching network 110 of the level shifter activates the left side of the level shifter 100, which includes the first transistor M1a. Since the common switching network s1-s3 and the common capacitor c1 simultaneously apply the same voltage to the sources S1a and S1b of the first and second transistors M1a and M1b, a negative voltage is applied to the source S1a of the first transistor M1a.After the first transition in the digital input signal HI for the high-side gate driver 302, the common switching network s1-s3 precharges the common capacitor c1 for the next (second) transition in the digital input signal HI.

[0051] In response to the second transition in the digital input signal HI for the high-side gate driver 302, which is opposite to the first transition, the second gate potential switching network 112 of the level shifter activates the right side of the level shifter 100, which includes the second transistor M1b. As explained above, the common switching network s1-s3 and the common capacitor c1 simultaneously apply the same voltage to the sources S1a, S1b of the first and second transistors M1a, M1b. Thus, in response to the second transition in the digital input signal HI for the high-side gate driver 302, a negative voltage is applied to the source S1b of the second transistor M1b. After the second transition in the digital input signal HI for the high-side gate driver 302, the common switching network s1-s3 pre-charges the common capacitor c1 for the next (first) transition in the digital input signal HI.This allows the differential detector 102 to convert the digital input signal HI for the high-side gate driver 302 into a differential voltage level (pwm_o) based on the differential current between the first transistor M1a and the second transistor M1b of the level shifter 100. For step-down level shifting, the level shifter 100 can be used for high-side control and for level shifting from the VIN range to the low side. That is, the level shifter 100 can be connected to the input of the low-side gate driver 304.

[0052] Although the present revelation is not limited to this, the following numbered examples illustrate one or more aspects of the revelation.

[0053] Example 1. A level shifter comprising: a differential detector; a first transistor with a drain electrically connected to a first node of the differential detector, a gate and a source; a second transistor with a drain electrically connected to a second node of the differential detector, a gate and a source; and a circuit configured to simultaneously apply an equal voltage to the source of the first and second transistors based on a digital signal input to the level shifter, the differential detector being configured to convert the digital signal to a different voltage level based on a differential current between the first and second transistors.

[0054] Example 2. The level shifter according to Example 1, wherein the circuit has a common capacitor and a common switching network, wherein in response to a transition in the digital signal the common switching network is configured to connect the common capacitor to the source of the first and second transistors, so that a negative voltage is simultaneously applied to the source of the first and second transistors, wherein after the transition in the digital signal the common switching network is configured to precharge the common capacitor for a next transition in the digital signal.

[0055] Example 3. The level shifter according to Example 2, wherein the common switching network has the following features: a first switching device electrically connected between a first DC supply voltage or a local ground reference and a first terminal of the common capacitor; a second switching device electrically connected between the first terminal of the common capacitor and ground or a bootstrap node; and a third switching device electrically connected between a second terminal of the common capacitor and ground or the bootstrap node, wherein the second terminal of the common capacitor is electrically connected to the source of the first and second transistors.

[0056] Example 4. The level shifter according to Example 3, wherein the second switching device is configured to turn on in response to the transition in the digital signal, and the first switching device and the third switching device are both configured to be off when the second switching device is on, wherein the second switching device is configured to turn off after a predefined time from the transition in the digital signal, and the first switching device and the third switching device are both configured to be on when the second switching device is off.

[0057] Example 5. The level converter according to one of Examples 1 to 4, wherein the differential detector is connected between a bootstrap node and the first and second transistors, wherein the first and second transistors are connected between the differential detector and ground, and wherein the differential detector is configured to convert the digital signal to a higher voltage level based on the differential current between the first and second transistors.

[0058] Example 6. The level shifter according to one of Examples 1 to 4, wherein the differential detector is connected between ground and the first and second transistors, wherein the first and second transistors are connected between the differential detector and a bootstrap node, and wherein the differential detector is configured to convert the digital signal to a lower voltage level based on the differential current between the first and second transistors.

[0059] Example 7. The level shifter according to any of Examples 1 to 6, further comprising: a first switching network configured to control an electrical potential at the gate of the first transistor; and a second switching network configured to control an electrical potential at the gate of the second transistor.

[0060] Example 8. The level shifter according to Example 7, wherein the first switching network comprises a first switching device electrically connected between ground and the gate of the first transistor, and a second switching device electrically connected between the gate and the source of the first transistor, and wherein the second switching network comprises a third switching device electrically connected between ground and the gate of the second transistor, and a fourth switching device electrically connected between the gate and the source of the second transistor.

[0061] Example 9. The level shifter according to any one of Examples 1 to 8, further comprising: a first switching device electrically connected between the source of the first transistor and a common capacitor of the circuit; a second switching device electrically connected between the source of the second transistor and the common capacitor; a first switching network configured to control an electrical potential at a gate of the first switching device; and a second switching network configured to control an electrical potential at a gate of the second switching device.

[0062] Example 10. The level shifter according to Example 9, wherein a common diode of the circuit has an anode electrically connected to a source of the first and second switching devices and a cathode electrically connected to ground, wherein the common capacitor has a first terminal to which a pulse signal derived from the digital signal is applied and a second terminal electrically connected to the source of the first and second switching devices and the anode of the common diode.

[0063] Example 11. A level shifter comprising the following features: a differential detector; a first transistor with a drain electrically connected to a first node of the differential detector, a gate, and a source; a second transistor with a drain electrically connected to a second node of the differential detector, a gate, and a source; a common capacitor with a first terminal and a second terminal; a first switching device electrically connected between a first DC supply voltage or a local ground reference and the first terminal of the common capacitor; a second switching device electrically connected between the first terminal of the common capacitor and ground or a bootstrap node;and a third switching device electrically connected between the second terminal of the common capacitor and ground or the bootstrap node, wherein the second terminal of the common capacitor is electrically connected to the source of the first and second transistors.

[0064] Example 12. The level shifter according to Example 11, wherein the first switching device has the following features: a first PMOS transistor having a positive pulse gate input electrically connected to the first terminal of the common capacitor, a drain electrically connected to the first DC supply voltage, and a source; and a first inverter formed by a second PMOS transistor and a first NMOS transistor, wherein the first inverter has a positive pulse input, a drain of the second PMOS transistor is electrically coupled to the source of the first PMOS transistor, and a source of the first NMOS transistor is grounded, wherein the second switching device has the following features: a second NMOS transistor with a grounded gate input, a source electrically connected to the source of the first transistor and the second terminal of the common capacitor, and a drain;and a third PMOS transistor with a grounded gate input, a source electrically connected to an output of the first inverter, and a drain electrically connected to the drain of the second NMOS transistor, wherein the third switching device has the following features: a third NMOS transistor with a gate electrically connected to the drain of the third PMOS transistor and the drain of the second NMOS transistor, a source electrically connected to the source of the first transistor, and a drain electrically connected to ground.

[0065] Example 13. The level shifter according to Example 11, wherein the first switching device has the following features: a first NMOS transistor with a negative pulse gate input electrically connected to the first terminal of the common capacitor, a source electrically connected to a local ground reference, and a drain;and a first inverter formed by a second NMOS transistor and a first PMOS transistor, wherein the first inverter has a negative pulse input, a source of the second NMOS transistor is electrically coupled to the drain of the first NMOS transistor, a drain of the first PMOS transistor is electrically connected to a bootstrap node, wherein the second switching device has the following features: a second PMOS transistor with a gate electrically connected to the bootstrap node, a source electrically connected to the second terminal of the common capacitor, and a drain;and a third NMOS transistor with a gate electrically connected to the bootstrap node, a source electrically connected to an output of the first inverter, and a drain electrically connected to the drain of the second PMOS transistor, wherein the third switching device has the following features: a third PMOS transistor with a gate electrically connected to the drain of the third NMOS transistor and the drain of the second PMOS transistor, a source electrically connected to the second terminal of the common capacitor, and a drain electrically connected to the bootstrap node.;

[0066] Example 14. The level shifter according to one of Examples 11 to 13, further comprising: a first switching network configured to control an electrical potential at the gate of the first transistor; and a second switching network configured to control an electrical potential at the gate of the second transistor.

[0067] Example 15. A power converter having the following features: a high-side power switching device; a gate driver configured to drive a gate of the high-side power switching device; and a level shifter, wherein the level shifter has the following features: a differential detector; a first transistor having a drain electrically connected to a first node of the differential detector, a gate, and a source; a second transistor having a drain electrically connected to a second node of the differential detector, a gate, and a source;and a circuit configured to simultaneously apply an equal voltage to the source of the first and second transistors based on a digital signal input to the level shifter, wherein the differential detector is configured to convert the digital signal into a voltage range of the gate driver based on a differential current between the first and second transistors.

[0068] Example 16. The power converter according to Example 15, further comprising: a low-side power switching device electrically connected to the high-side power switching device in a half-bridge configuration; an inductor electrically connected to a switching node between the low-side power switching device and the high-side power switching device; and a capacitor electrically connected between the switching nodes and a bootstrap node providing a supply voltage for the gate driver of the high-side power switching device.

[0069] Example 17. The power converter according to Example 16, wherein the differential detector is connected between the bootstrap nodes and the first and second transistors of the level shifter, wherein the first and second transistors of the level shifter are connected between the differential detector and ground, and wherein the differential detector is configured to convert the digital signal to a higher voltage level based on the differential current between the first transistor and the second transistor of the level shifter.

[0070] Example 18. The power converter according to Example 16, wherein the differential detector is connected between ground and the first and second transistors of the level shifter, wherein the first and second transistors of the level shifter are connected between the differential detector and the bootstrap node, and wherein the differential detector is configured to convert the digital signal to a lower voltage level based on the differential current between the first transistor and the second transistor of the level shifter.

[0071] Example 19. The power converter according to one of Examples 15 to 18, wherein the level converter circuit has a common capacitor and a common switching network, wherein, in response to a transition in the digital signal, the common switching network is configured to connect the common capacitor to the source of the first and second transistors, such that a negative voltage is simultaneously applied to the source of the first and second transistors, wherein, after the transition in the digital signal, the common switching network is configured to precharge the common capacitor for a next transition in the digital signal.

[0072] Example 20. The power converter according to Example 19, wherein the common switching network of the level shifter has the following features: a first switching device electrically connected between a first DC supply voltage or a local ground reference and a first terminal of the common capacitor; a second switching device electrically connected between the first terminal of the common capacitor and ground or a bootstrap node; and a third switching device electrically connected between a second terminal of the common capacitor and ground or the bootstrap node, wherein the second terminal of the common capacitor is electrically connected to the source of the first and second transistors.

[0073] Terms like "first," "second," and the like are used to describe different elements, regions, sections, etc., and are not intended to be restrictive. The same terms refer to the same elements throughout the description.

[0074] As used herein, the terms "have," "contain," "include," and the like are open-ended terms that indicate the presence of the specified elements or features but do not exclude additional elements or features. The articles "a" and "the" are intended to include both the plural and the singular unless the context clearly indicates otherwise.

[0075] The expression "and / or" should be interpreted to encompass all possible conjunctive and disjunctive combinations unless explicitly stated otherwise. For example, the expression "A and / or B" should be interpreted to mean only A, only B, or both A and B. The expression "at least one of" should be interpreted in the same way as "and / or" unless explicitly stated otherwise. For example, the expression "at least one of A and B" should be interpreted to mean only A, only B, or both A and B.

[0076] It is understood that the features of the various embodiments described herein can be combined with one another, unless expressly stated otherwise.

[0077] Although specific embodiments have been illustrated and described herein, it is obvious to those skilled in the art that a multitude of alternative and / or equivalent implementations can replace the specific embodiments shown and described without altering the scope of protection of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention is limited only by the claims and their equivalents.

Claims

[1] Level converter (100) which has the following features: a differential detector (102); a first transistor (M1a) with a drain that is electrically connected to a first node of the differential detector (102), a gate and a source; a second transistor (M1b) with a drain electrically connected to a second node of the differential detector (102), a gate and a source; and a circuit (104) configured to simultaneously apply an equal voltage to the source of the first and second transistors (M1a, M1b) based on a digital signal input into the level converter (100), wherein the differential detector (102) is configured to convert the digital signal into a different voltage level based on a differential current between the first and second transistors (M1a, M1b). [2] Level converter (100) according to claim 1, wherein the circuit (104) has a common capacitor (c1) and a common switching network (s1-s3), wherein, in response to a transition in the digital signal, the common switching network (s1-s3) is configured to connect the common capacitor (c1) to the source of the first and second transistors (M1a, M1b), so that a negative voltage is simultaneously applied to the source of the first and second transistors (M1a, M1b), where, after the transition in the digital signal, the common switching network (s1-s3) is configured to precharge the common capacitor (c1) for a next transition in the digital signal. [3] Level converter (100) according to claim 2, the common switching network (s1-s3) has the following features: a first switching device which is electrically connected between a first DC supply voltage or a local ground reference and a first terminal (106) of the common capacitor (c1); a second switching device that is electrically connected between the first terminal (106) of the common capacitor (c1) and ground or a bootstrap node; and a third switching device which is electrically connected between a second terminal (108) of the common capacitor (c1) and ground or the bootstrap node, wherein the second terminal (108) of the common capacitor (c1) is electrically connected to the source of the first and second transistors (M1a, M1b). [4] Level converter (100) according to claim 3, wherein the second switching device is configured to turn on in response to the transition in the digital signal, and the first switching device and the third switching device are both configured to be off when the second switching device is turned on, wherein the second switching device is configured to turn off after a predefined time from the transition in the digital signal, and the first switching device and the third switching device are both configured to be turned on when the second switching device is turned off. [5] Level converter (100) according to any one of claims 1 to 4, wherein the differential detector (102) is connected between a bootstrap node (HB) and the first and second transistors (M1a, M1b), wherein the first and second transistors (M1a, M1b) are connected between the differential detector (102) and ground, and wherein the differential detector (102) is configured to convert the digital signal into a higher voltage level based on the differential current between the first and second transistors (M1a, M1b). [6] Level converter (100) according to any one of claims 1 to 4, wherein the differential detector (102) is connected between ground and the first and second transistors (M1a, M1b), wherein the first and second transistors (M1a, M1b) are connected between the differential detector (102) and a bootstrap node (HB), and wherein the differential detector (102) is configured to convert the digital signal to a lower voltage level based on the differential current between the first and second transistors (M1a, M1b). [7] Level converter (100) according to any one of claims 1 to 6, further comprising the following features: a first switching network configured to control an electrical potential at the gate of the first transistor (M1a); and a second switching network configured to control an electrical potential at the gate of the second transistor (M1b). [8] Level converter (100) according to claim 7, wherein the first switching network comprises a first switching device which is electrically connected between the ground and the gate of the first transistor (M1a), and a second switching device which is electrically connected between the gate and the source of the first transistor (M1a), and wherein the second switching network comprises a third switching device which is electrically connected between the ground and the gate of the second transistor (M1b), and a fourth switching device which is electrically connected between the gate and the source of the second transistor (M1b). [9] Level converter (100) according to any one of claims 1 to 8, further comprising the following features: a first switching device which is electrically connected between the source of the first transistor (M1a) and a common capacitor (c1) of the circuit (104); a second switching device that is electrically connected between the source of the second transistor (M1b) and the common capacitor (c1); a first switching network configured to control an electrical potential at a gate of the first switching device; and a second switching network configured to control an electrical potential at a gate of the second switching device. [10] Level converter (100) according to claim 9, wherein a common diode (d1) of the circuit (104) has an anode electrically connected to a source of the first and the second switching device and a cathode electrically connected to ground, wherein the common capacitor (c1) has a first terminal (106) to which a pulse signal derived from the digital signal is applied, and a second terminal (108) which is electrically connected to the source of the first and second switching devices and the anode of the common diode (d1). [11] Level converter (100) which has the following features: a differential detector (102); a first transistor (M1a) with a drain that is electrically connected to a first node of the differential detector (102), a gate and a source; a second transistor (M1b) with a drain that is electrically connected to a second node of the differential detector (102), a gate and a source; a common capacitor (c1) with a first terminal (106) and a second terminal (108); a first switching device which is electrically connected between a first DC supply voltage or a local ground reference and the first terminal (106) of the common capacitor (c1); a second switching device that is electrically connected between the first terminal (106) of the common capacitor (c1) and ground or a bootstrap node; and a third switching device which is electrically connected between the second terminal (108) of the common capacitor (c1) and ground or the bootstrap node, wherein the second terminal (108) of the common capacitor (c1) is electrically connected to the source of the first and second transistors (M1a, M1b). [12] Level converter (100) according to claim 11, the first switching device has the following features: a first PMOS transistor with a positive pulse gate input electrically connected to the first terminal (106) of the common capacitor (c1), a drain electrically connected to the first DC supply voltage, and a source; and a first inverter formed by a second PMOS transistor and a first NMOS transistor, wherein the first inverter has a positive pulse input, a drain of the second PMOS transistor is electrically coupled to the source of the first PMOS transistor, and a source of the first NMOS transistor is grounded, the second switching device has the following features: a second NMOS transistor with a grounded gate input, a source electrically connected to the source of the first transistor (M1a) and the second terminal (108) of the common capacitor (c1), and a drain; and a third PMOS transistor with a grounded gate input, a source electrically connected to an output of the first inverter, and a drain electrically connected to the drain of the second NMOS transistor, the third switching device has the following features: a third NMOS transistor with a gate electrically connected to the drain of the third PMOS transistor and the drain of the second NMOS transistor, a source electrically connected to the source of the first transistor (M1a), and a drain electrically connected to ground. [13] Level converter (100) according to one of claims 11 or 12, the first switching device has the following features: a first NMOS transistor with a negative pulse gate input electrically connected to the first terminal (106) of the common capacitor (c1), a source electrically connected to a local ground reference, and a drain; and a first inverter formed by a second NMOS transistor and a first PMOS transistor, wherein the first inverter has a negative pulse input, a source of the second NMOS transistor is electrically coupled to the drain of the first NMOS transistor, and a drain of the first PMOS transistor is electrically connected to a bootstrap node (HB). the second switching device has the following features: a second PMOS transistor with a gate electrically connected to the bootstrap node (HB), a source electrically connected to the second terminal (108) of the common capacitor (c1), and a drain; and a third NMOS transistor with a gate electrically connected to the bootstrap node (HB), a source electrically connected to an output of the first inverter, and a drain electrically connected to the drain of the second PMOS transistor, the third switching device has the following features: a third PMOS transistor with a gate electrically connected to the drain of the third NMOS transistor and the drain of the second PMOS transistor, a source electrically connected to the second terminal (108) of the common capacitor (c1), and a drain electrically connected to the bootstrap node (HB). [14] Level converter (100) according to one of claims 11 to 13, which further comprises the following features: a first switching network configured to control an electrical potential at the gate of the first transistor (M1a); and a second switching network configured to control an electrical potential at the gate of the second transistor (M1b). [15] Power converter which has the following features: a high-side power switching device (MPHS); a gate driver configured to drive a gate of the high-side power switching device (MPHS); and a level converter (100), wherein the level converter (100) has the following features: a differential detector (102); a first transistor (M1a) with a drain that is electrically connected to a first node of the differential detector (102), a gate and a source; a second transistor (M1b) with a drain electrically connected to a second node of the differential detector (102), a gate and a source; and a circuit (104) configured to simultaneously apply an equal voltage to the source of the first and second transistors (M1a, M1b) based on a digital signal input into the level converter (100), wherein the differential detector (102) is configured to convert the digital signal on the basis of a differential current between the first transistor (M1a) and the second transistor (M1b) into a voltage range of the gate driver. [16] Power converter according to claim 15, which further comprises the following features: a low-side power switching device (MPLS) electrically connected to the high-side power switching device (MPHS) in a half-bridge configuration; an inductor electrically connected to a switching node (SW) between the low-side power switching device (MPLS) and the high-side power switching device (MPHS); and a capacitor that is electrically connected between the switching node (SW) and a bootstrap node (HB) that provides a supply voltage for the gate driver for the high-side power switching device (MPHS). [17] Power converter according to claim 16, wherein the differential detector (102) is connected between the bootstrap nodes (HB) and the first and second transistors (M1a, M1b) of the level converter (100), wherein the first and second transistors (M1a, M1b) of the level converter (100) are connected between the differential detector (102) and ground, and wherein the differential detector (102) is configured to convert the digital signal into a higher voltage level based on the differential current between the first transistor (M1a) and the second transistor (M1b) of the level converter (100). [18] Power converter according to claim 16, wherein the differential detector (102) is connected between ground and the first and second transistors (M1a, M1b) of the level converter (100), wherein the first and second transistors (M1a, M1b) of the level converter (100) are connected between the differential detector (102) and the bootstrap nodes (HB), and wherein the differential detector (102) is configured to convert the digital signal to a lower voltage level based on the differential current between the first transistor (M1a) and the second transistor (M1b) of the level converter (100). [19] Power converter according to any one of claims 15 to 18, wherein the circuit (104) of the level converter (100) has a common capacitor (c1) and a common switching network (s1-s3), wherein, in response to a transition in the digital signal, the common switching network (s1-s3) is configured to connect the common capacitor (c1) to the source of the first and second transistors (M1a, M1b), so that a negative voltage is simultaneously applied to the source of the first and second transistors (M1a, M1b), where, after the transition in the digital signal, the common switching network (s1-s3) is configured to precharge the common capacitor (c1) for a next transition in the digital signal. [20] Power converter according to claim 19, wherein the common switching network (s1-s3) of the level converter (100) has the following features: a first switching device which is electrically connected between a first DC supply voltage or a local ground reference and a first terminal (106) of the common capacitor (c1); a second switching device that is electrically connected between the first terminal (106) of the common capacitor (c1) and ground or a bootstrap node; and a third switching device which is electrically connected between a second terminal (108) of the common capacitor (c1) and ground or the bootstrap node, wherein the second terminal (108) of the common capacitor (c1) is electrically connected to the source of the first and second transistors (M1a, M1b).

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