Power semiconductor device

Abstract

A backward-conducting power semiconductor device comprising a wafer (10) containing layers with different conductivity types, wherein the layers are arranged between an emitter electrode (2) on an emitter side (11) and a collector electrode (25) on a collector side (15) opposite the emitter side (11), and comprising the following: - a drift layer (3) of a first conductivity type, arranged between the emitter side (11) and the collector side (15), - a first layer (8) comprising a first region (81) of the first conductivity type with a higher doping concentration than the drift layer (3) and a second region (85) of a second conductivity type arranged adjacent to the first region (81), wherein the first layer (8) is arranged between the drift layer (3) and the collector electrode (25), - several base layers (4) of the second conductivity type arranged between the drift layer (3) and the emitter electrode (2), wherein the base layers (4) are in direct electrical contact with the emitter electrode (2), - several source regions (6) of the first conductivity type, arranged on the emitter side (11), embedded in one of the base layers (4) and contacting the emitter electrode (2), wherein the source regions (6) have a higher doping concentration than the drift layer (3), - several gate electrodes, each of which is electrically insulated from the base layers (4), the source regions (6) and the drift layer (3) by an insulating layer (78), wherein the emitter electrode (2) contains several base layer contact areas (22) at which the emitter electrode (2) contacts the base layers (4) and the source areas (6), wherein in the wafer (10) an IGBT semiconductor cell (18) is formed, which contains layers or parts of layers which lie in an orthogonal projection with respect to the emitter side (11) of one of the base layer contact areas (22) with which one of the source areas (6) is in contact, this source area (6) and such part of one of the base layers (4) in which an electrically conductive channel may be formed, wherein a cluster is formed by several such IGBT cells, in particular by at least 10 IGBT cells, wherein the IGBT cells are arranged directly adjacent to one another in one direction on the emitter side (11) and IGBT cells are arranged at a cell distance, wherein the device further comprises a trough (5) of the second conductivity type, which is arranged in a plane parallel to the emitter side (11), wherein the base layers (4) are arranged in this plane, wherein the tray (5) is arranged in a different direction than the direction in which the multiple IGBT cells are arranged, wherein the well (5) has a surface area and wherein the well (5) is arranged outside the IGBT cells (18) and is electrically connected to the emitter electrode (2) directly at a well contact area which is at most 10% of the maximum area of ​​the well (5) or via at least one of the base layers (4), wherein each of the at least one base layer (4) has a base layer surface area, and the at least one base layer (4) is in contact with the well (5) in a contact area which is less than 1% of the base layer surface area.

Description

Field of invention

[0001] The invention relates to the field of power semiconductor devices. It relates to a backward-conducting power semiconductor device with layers of different conductivity types, in particular a drift layer, a first layer, and several base layers according to claim 1. Background of the invention

[0002] A state-of-the-art reverse-conducting insulated-gate bipolar transistor (RC-IGBT) is in Fig. Figure 1 shows a bipolar transistor with an insulated gate and an integrated freewheeling diode mounted on a wafer 10. Such a reverse-conducting semiconductor device 150 comprises an n-drift layer 3 with a first main face, which is the emitter face 11 of the integrated IGBT, and a second main face, which is the collector face 15 of the IGBT and is located opposite the emitter face 11. A p-doped base layer 4 is arranged on the emitter face 11. On the base layer 4, n-doped source regions 6 with a higher doping concentration than those of the drift layer 3 are arranged.

[0003] On the emitter side 11, an electrically insulating layer 78 is arranged, covering the base layer 4 and the drift layer 3 and partially covering the source regions. An electrically conductive planar gate electrode 7 is completely embedded in the insulating layer 78. Above the central part of the base layer 4, there is no source region and no electrically insulating layer.

[0004] An emitter electrode 2 is arranged on this central section of the base layer 4, which also covers the insulating layer 78. The emitter electrode 2 is in direct electrical contact with the source region 6 and with the base layer 4 in a contact area 22, but it is electrically insulated from the planar gate electrode 7 by a further insulating layer 782.

[0005] On the collector side 15, a buffer layer 9 is arranged on the drift layer 3. On the side of the buffer layer 9 opposite the drift layer 3, a first layer 8 is arranged with alternating first n-regions 81 and p-doped second regions 85. The first regions 81 and the buffer layer 9 have a higher doping concentration than the drift layer 3.

[0006] A collector electrode 25 is arranged on the collector side 15, which covers the first and second areas 81, 85 and is in direct electrical contact with them.

[0007] In such a backward-conducting semiconductor device 150 of the prior art, a freewheeling diode is formed between the collector electrode 25, a part of which forms a cathode electrode in the diode, the first n regions 81, which form a cathode region in the diode, the drift layer 3, a part of which forms the diode drift layer, the p-base layer 4, a part of which forms an anode region in the diode, and the emitter electrode 2, which forms an anode in the diode.

[0008] A bipolar transistor (IGBT) with an insulated gate is formed between the collector electrode 25, part of which forms the IGBT collector electrode, the second p-regions 85, which form a collector layer in the IGBT, the drift layer 3, part of which forms the IGBT drift layer, the base layer 4, part of which forms a p-base layer in the IGBT, the source region 3, which forms an n-IGBT source region, and the emitter electrode 2. In the switching state of the IGBT, an electrically conductive channel is formed between the emitter electrode 2, the source region 6, and the p-base layer 4 in the direction of the n-drift layer 3.

[0009] In such a prior art reverse-conducting IGBT device (RC-IGBT device), a p-base layer 4 of the IGBT cell is used as an anode of the internal diode when the device is in diode mode. However, the p-base layer 4 is short-circuited to the n-source region 6, which may be connected to the drift layer 3 via the MOS channel. If the channel is open, the electron current flows through the channel and shorts the pn junction between the p-base layer 4 and the drift layer 3. As a result, the pn junction between the p-base layer 4 and the drift layer 3 is not biased, thus preventing hole injection. The current is sustained by the unipolar electron current flowing through the channel. Injection may begin when the potential difference reaches the intended voltage of the junction; however, the voltage across the contacts could be much higher.When hole injection begins, the conductivity of drift layer 3 is modulated, reducing the voltage drop. Therefore, the diode exhibits a characteristic MOS-controlled negative resistance region (voltage dropout) in its IV characteristics, depending on the gate voltage. The dropout voltage is greatest when the gate voltage is above the threshold, while below the threshold or negative, the channel is closed, and the dropout voltage is completely absent.

[0010] Furthermore, the MOS channel controls the plasma concentration below the p-base layer 4 during the conduction state of the internal diode. Applying a gate voltage above the threshold extracts the plasma through the induced channel, thereby reducing the plasma below the p-base layer 4 and resulting in higher switching losses compared to situations where the gate-emitter voltage is below the threshold or negative.

[0011] In various applications, gate control during diode operation cannot be chosen arbitrarily, so the device should be able to provide good performance when positive gate voltages are applied.

[0012] US 5 702 961 A shows an IGBT that alternatively comprises base layers and p-doped anode layers, and on the collector side, strictly aligned n-layers in projection onto the anode layers and n-doped layers in projection onto the base layers. However, this alternative arrangement negatively affects the IGBT performance.

[0013] US 2005 / 0 073 004 A1 describes a prior art MOSFET device having a heavily p-doped protective ring termination at the periphery of the device.

[0014] US 2005 / 0045960A1 describes a reverse-conducting IGBT with trench-gate electrodes. Two trench gates form an active IGBT cell. An anode layer, less p-doped and shallower than the base layer, is positioned between two such active cells. This design also suffers from the disadvantage that the p-layers are oriented in the same direction as the base layers (in line with the base layers) and that the contact area between the anode layer and the emitter electrode is large, resulting in high IGBT conduction losses.

[0015] US 2007 / 0108468A1 describes another reverse-conducting IGBT in which active IGBT cells alternate with regions containing p-doped layers, the p-doped layers having grooves arranged at an emitter potential. The p-doped layers are in extensive contact with the emitter electrode. Therefore, this device has the same disadvantages as mentioned above.

[0016] US 2004 / 0183138A1 discloses a high-switching-capability semiconductor device comprising a plurality of stripe trench lines arranged in parallel in each of the adjacent cell regions of a semiconductor layer and extending from one cell region to the other, a gate insulating film formed in each of the trench lines, and a gate electrode embedded in each of the trench lines, with the gate insulating film positioned between each. Description of the invention

[0017] It is an object of the invention to create a backward-conducting power semiconductor device with improved performance of the device in diode mode.

[0018] This problem is solved by the semiconductor device with the features of claim 1. The power semiconductor device according to the invention comprises layers of different conductivity types in a wafer, wherein the layers are arranged between an emitter electrode on an emitter side and a collector electrode on a collector side that is arranged opposite the emitter side.

[0019] The device comprises the following layers: - a drift layer of a first conductivity type, arranged between the emitter side and the collector side, - a first layer containing a first region of the first conductivity type and a higher doping concentration than the drift layer, wherein the first layer is arranged between the drift layer and the collector electrode, - a base layer of a second conductivity type, arranged between the drift layer and the emitter electrode, wherein the base layer is in direct electrical contact with the emitter electrode, - a source region of the first conductivity type, which is located on the emitter side, embedded in the base layer and in contact with the emitter electrode, wherein the source region has a higher doping concentration than the drift layer, - a gate electrode that is electrically isolated from the base layer, the source region and the drift layer by an insulating layer.

[0020] The emitter electrode comprises a contact region where it is in contact with the base layer and the source region. Within the wafer, an active semiconductor cell is formed, containing layers or portions of layers that are orthogonally projected with respect to the emitter side of the contact region of the emitter electrode, the source region, and that part of the base layer where an electrically conductive channel can be formed. The active region therefore contains the orthogonal projection of these layers / regions, or a portion thereof, to the collector electrode and is located between them; that is, the active region also includes a portion of the drift layer and the first layer.

[0021] The device further comprises a well of the second conductivity type, arranged in the same plane as the base layer, wherein the plane is parallel to the emitter side, wherein the well is arranged outside the active cell and is electrically connected to the emitter electrode either directly at a well contact area which is at most 10% of the maximum area of ​​the well, or via at least one of the base layers, wherein each of the at least one base layer has a base layer surface area, and the at least one base layer is in contact with the well in a contact area which is less than 1% of the base layer surface area.

[0022] The well improves diode operation because the influence of the MOS channel during forward conduction of the diode is reduced, and the voltage drop at low currents when the gate-emitter voltage above the threshold is applied to the gate is also reduced. The influence of the gate control on the diode is reduced by the arrangement according to the invention.

[0023] The introduction of the well creates an additional diode-emitter region that is decoupled from the MOS channel. The well is located outside the active cell, such that it is not situated between the cells in the PIN diode region. Therefore, it does not adversely affect the device's performance in IGBT operation and does not influence the cell design parameters (e.g., step size, i.e., the distance between two cells). Consequently, the well does not provide MOS control. The well or well zones can have different doping levels, depths, and lifetime termination schemes compared to those of the base layer. Depending on the desired optimal injection of the additional p-well region, the well can be designed to be partially floating (by contacting the well with the emitter electrode via the base layer) or non-floating (by having the well in direct contact with the emitter diode).

[0024] By using a single well or well zones with a small area compared to the device area in a plane parallel to the emitter side, the performance of the IGBT operation is less affected. In this way, the diode performance can be optimized independently of the IGBT and the fallback and switching plasma concentration, which are controlled for optimal diode operating mode losses and SOA.

[0025] Further advantages of the present invention will become apparent from the dependent claims. Brief description of the drawings

[0026] The subject matter of the invention is explained in more detail in the following text with reference to the accompanying drawings; these show: Fig. 1 an RC-IGBT with a planar gate electrode according to the state of the art; Fig. 2 a top view of a first exemplary arrangement of p-base layers and a p-tub in a plane along the line DD in Fig. 3; Fig. 3 a sectional view of an RC-IGBT according to the invention with planar gate electrodes along section AA in Fig. 2; Fig. 4 a sectional view of the embodiment of an RC-IGBT according to the invention along section BB in Fig. 2; Fig. 5 and Fig. 6 Variations of a sectional view of the embodiment of an RC-IGBT according to the invention with planar gate electrodes along section BB or AA in Fig. 2, wherein the tray is connected to the emitter electrode via the base layer; Fig. 7 a sectional view of the embodiment of an RC-IGBT according to the invention with planar gate electrodes along section CC in Fig. 6; Fig. 8 a modification of a sectional view of the embodiment of an RC-IGBT according to the invention with planar gate electrodes along section AA in Fig. 2, wherein the tray is directly connected to the emitter electrode; Fig. 9 a sectional view of the embodiment of the RC-IGBT according to the invention with planar gate electrodes along section C'-C' in Fig. 8; Fig. 10-14 Top views of variations of exemplary arrangements of p-base layers and a p-trough for an RC-IGBT according to the invention in a plane along the line DD in Fig. 3; Fig. 15 a sectional view of a further embodiment of an RC-IGBT according to the invention with trench-gate electrodes along section AA in Fig. 2; Fig. 16 a modification of a sectional view of the embodiment of an RC-IGBT according to the invention with trench-gate electrodes and an enrichment layer along section AA in Fig. 2; Fig. 17 a sectional view of a further embodiment of a MOSFET according to the invention with trench-gate electrodes along section AA in Fig. 2; Fig. 18-22 Top views of different exemplary arrangements of the layers in one plane along the line DD in Fig. 3; Fig. 23 p-wells located at the base layer, with varying distances to the MOS channel in the active cell; and Fig. 24 the current against the bias voltage for the embodiments of Fig. 23.

[0027] The reference numerals used in the figures, as well as their meanings, are summarized in the list of reference numerals. Generally, similar or similarly functioning parts have the same reference numerals. The described embodiments are intended as examples and are not meant to limit the invention. Detailed description of preferred embodiments

[0028] Fig. Figure 3 shows a semiconductor device according to the invention in the form of a backward-conducting power semiconductor device with a wafer 10. The device comprises layers of different conductivity types between an emitter electrode 2 on an emitter side 11 and a collector electrode 25 on a collector side 15, which is arranged opposite the emitter side 11.

[0029] The device includes: - an (n-)doped drift layer 3, which is arranged between the emitter side 11 and the collector side 15, - a first layer 8, which contains at least one n-doped first region 81 with a higher doping concentration than that of the drift layer 3 and at least one p-doped second region 85; wherein the first layer 8 is arranged between the drift layer 3 and the collector electrode 25, - several p-doped base layers 4 arranged between the drift layer 3 and the emitter electrode 2, wherein the base layers 4 are in direct electrical contact with the emitter electrode 2, - several n-doped source regions 6 arranged on the emitter side 11 and embedded in the base layer 4 and in contact with the emitter electrode 2, wherein the source regions 6 have a higher doping concentration than the drift layer 3, - several gate electrodes 7, each of which is electrically insulated from the base layers 4, the source regions 6 and the drift layer 3 by an insulating layer 78.

[0030] The emitter electrode 2 contains several base layer contact areas 22, where the emitter electrode 2 is in contact with the base layers 4 and the source areas 6.

[0031] For a backward-conducting power semiconductor device as in Fig. As shown in Figure 3, the first layer 8 further comprises a second p-doped region 85, which is arranged near the first region 81. The device can also comprise more than one first and / or one second region, which are arranged alternately and are adjacent to one another. In an exemplary embodiment, the device comprises several second regions 85 as well as one or more large second pilot regions.

[0032] In Fig. The device comprises a design with a planar gate electrode. The planar gate electrode 7 is arranged on the top side of the emitter face 11 and is electrically insulated from the base layer 4, the source region 6, and the drift layer 3 by an insulating layer 78. Typically, a further insulating layer 782 is arranged between the planar gate electrode 7 and the emitter electrode 2.

[0033] In the wafer 10, an active semiconductor cell 18 is formed and comprises such layers or parts of such layers that lie in an orthogonal projection with respect to the emitter face 11 of one of the base layer contact areas 22 of the emitter electrode, with which one of the source areas is in contact, the source area 6, and a part of one of the base layers 4, in which an electrically conductive channel may be formed. The channels are indicated in the figures by the arrow labeled "electrons". In the sectional view of Fig. Only active cells are shown (the same applies to the Fig. 15-17).

[0034] A cluster is formed by several such active cells, in particular by at least 10 active cells. The expression "the cells belonging to a cluster are directly adjacent to each other in one direction on the emitter side (11) and active cells are arranged in one cell spacing direction" includes a straight direction as in Fig. 2 shown (from A to A), a circular direction, as in Fig. Figure 13 shows, but any other direction in a plane parallel to the emitter side, where the cells are directly adjacent, such as a sinusoidal direction, is also possible. A cell spacing is the repetition distance between two adjacent cells.

[0035] The semiconductor device can comprise a p-doped well 5 in the form of a single well 51, or alternatively, the device can comprise multiple well zones 52, i.e., two or more well zones 52. Unless otherwise specified in the description, even if only a single well is shown in a figure, the device can also comprise multiple such wells in a continuation of the structure shown in the figure. The well has a surface region that is the region of the well in the plane of the emitter side.

[0036] The well should not be mixed with p-doped layers located at the edge / periphery of the device or the emitter electrode in a terminal area, e.g., as a guard ring. Such heavily p-doped, but not electrically controllable, layers are present at the edge of the semiconductor device. The one or more wells should be located in the active region of the device, where clusters of IGBT cells and one or more wells are present and alternate / surround each other. The presence of clusters of active IGBT cells ensures good IGBT performance of the device, while the introduction of the weakly contacting wells between such clusters achieves low switching losses and maintains a high SOA.

[0037] The p-doped well 5 is arranged in the same plane as the base layers 4, with this plane being parallel to the emitter side 11. The well 5 is located outside the active cells 18 and is electrically connected to the emitter electrode 2. This connection can be achieved directly using a portion of the well's surface area on the emitter side 11 or via the base layer 4; alternatively, both connections are implemented in the same device. The contact between the well 5 and the emitter electrode 2 is achieved with a well contact area that comprises at most 10% of the maximum surface area of ​​the well 5.

[0038] Well 5 is oriented in a different direction than the direction in which the multiple active cells are arranged. For example, well 5 is oriented perpendicular to the direction in which the active cells are arranged (but still in the same plane parallel to the emitter side).

[0039] Fig. Figure 2 shows an arrangement of several base layers 4 and a trough 5 in the form of trough zones 52 according to a first embodiment of the invention. The base layers 4 are arranged in Fig. 2 shown as an example of an active cell. The basal layers 4 in Fig. 2 are arranged in one direction, i.e., in two (or more) rows (line AA). Of course, it is also possible to arrange the base layers in only one row. The cells are arranged as clusters, for example, in a row of at least 10 cells. The base layers 4 can be designed as strips, with the base layers 4 arranged in a row parallel to the longer sides of the strips ( Fig. 2) The strips are to be understood as layers that have a longer extent in one direction than in the other directions (hereinafter referred to as end sections). The end sections of these strips, which are arranged in a row and which are set on the same side, are in contact with a trough 5 which is arranged along the end sections of the base layers 4, i.e. perpendicular to the longer sides of the base layers 4. In Fig. 2 the end sections of the base layers on the opposite side of the stripes are also in contact with another trough zone 52.

[0040] Fig. 3 is a section through line AA of Fig. 2, while Fig. 4 is a section through line BB, which is perpendicular to line AA. In Fig. Figure 4 shows that the base layer 4 and the well 5 can be in contact with each other, thereby creating a contact between the well 5 and the emitter electrode 2 via the base layer 4. Furthermore, this figure shows another electrical contact between the well 5 and the emitter electrode 2 as a direct contact. This contact is made not over the entire surface area of ​​the well 5, as shown in Figure 4. Fig. As shown in Figure 4, or through the base layer 4, the injection from the well 5 can be adjusted to lower values. Furthermore, this does not significantly disrupt the design of the IGBT front and creates more options for designing optimal IGBT performance.

[0041] Fig. Figure 5 shows another embodiment according to the invention, which has a trough zone 52 on the right side of the figure that is not directly in contact with the emitter electrode 2, but the trough zone 52 is in contact with the base layer 4, which is in contact with the emitter electrode 2, i.e. the contact is partially suspended.

[0042] The trough zone 52 on the left side of the figure is covered by an insulating layer to achieve weak contact with the emitter electrode 2 (semi-floating).

[0043] In another exemplary embodiment, no conductive channel is formed on a surface of the well layer 5. For a design with a planar gate electrode, this can be achieved, for example, by the insulating layer 78 having a sufficiently large thickness, or by the well 5 having a sufficiently high doping concentration, or by a combination of both, so that no electrical channel is formed.

[0044] Alternatively, the planar gate electrode 7 can be terminated at the edge of the active cell 18 (as e.g. in Fig. 8 is shown), alternatively, where the channel can be formed, there may be no source area ( Fig. 6), or there is no emitter electrode 2 present (right side of Fig. 5).

[0045] Fig. Figure 6 shows an embodiment of the invention in which the base layer 4 and the well 5 are arranged in mutual contact and abut each other, but the well 5 is insulated from the emitter electrode 2 by an insulating layer 78. The active cell 18 in this figure is limited to the area of ​​the wafer 10 that lies in an orthogonal projection with respect to the emitter side 11 of the contact area 22 of the emitter electrode, with which the source area 6 is in contact, the source area 6 and the base layer 4 or a part of the base layer 4 in which an electrically conductive channel can be formed. This means for the in Fig. In the device shown in Figure 6, cell 18 ends at the right boundary of contact area 22 because the contact area 22 of the emitter electrode 2 on the right side of the device is not in contact with a source area, therefore no channel to the trough zone 52 on the right side is formed. The boundary of the active cells 18 in Fig. 6 is indicated by a dashed line.

[0046] In Fig. The active cell 18 comprises the base layer 4, the source region 6, and parts of the first region 81, the second region 85, and the drift layer 3. The well 5 and the base layer 4 therefore differ at least by the arrangement of the p-doped layer either inside or outside the active cell 18. This means that a p-doped layer on the emitter side 11 can be uniquely classified as a well 5 or a base layer 4 by its position either inside the active cell 18, i.e., by defining a base layer 4, or outside the active IGBT cell 18, i.e., by defining a well 5.

[0047] In Fig. Figure 6 shows a device in which the vat 5 has a transition to the drift layer 3 that extends deeper into the wafer 10 than a transition between the base layer 4 and the drift layer 3. Alternatively, the vat 5 can also have a transition of the same depth or even a shallower transition between the base layer 4 and the drift layer 3. Furthermore, the doping concentration of the vat 5 can be higher, equal to, or lower than the doping concentration of the base layer 4. Any combination of higher / equal to / lower doping concentration with higher / equal to or shallower transition depth is, of course, possible.

[0048] Fig. 7 is a section along line CC of Fig. 6. The basin 5 shown in this figure projects towards the side of the base layer 4 to which it adjoins; however, the basin 5 may also be the same length or shorter than the adjacent side of the base layer 4.

[0049] Fig. Figure 8 shows a further device according to the invention with a direct electrical contact between the tray 5 and the emitter electrode 2 in a limited part of the surface area of ​​the tray, which forms a tray contact area with the emitter electrode 2. The tray contact area can be arranged in any suitable part of the tray surface, for example in a central part (in Fig. 8 shown) or at the edge / corner of the tub ( Fig. 5), however, this invention should of course also cover any other position of the tub contact area.

[0050] Fig. Figure 9 again shows a section along the line C'-C' of Fig. 8. The area where the tray 5 is in contact with the emitter electrode 2 is indicated by a hatched area in grey. Fig. 9. This area differs from the base layer contact area 22 and is easily distinguishable because no source area 6 is in contact with this gray, hatched area where the well 5 is in contact with the emitter electrode 2. Therefore, no channel is formed and this area does not contribute to the active cell 18. By contacting the well layer 5 directly with the emitter electrode 2, a high injection from the well 5 is ensured. Additional flexibility can be achieved by adjusting the contact area between the emitter electrode 2 and the well layer 5.

[0051] Fig. Figure 10 shows a further embodiment of the semiconductor device according to the invention in a section in a plane that corresponds to the line DD in Fig. 3 corresponds where the device contains several such trough zones 52 which are electrically separated from one another by the drift layer 4. In the Fig. In the case shown in Figure 10, each basin zone 52 is in contact with several base layers 4 (in Fig. 10 with the end sections on one side of the base layers, which are formed as strips), i.e., an electrical contact between the well zones 52 and the emitter electrode 2 is established via the base layers 4. This arrangement has the advantage of creating good contact between the emitter electrode 2 and the well layer 5 without significant modification of the IGBT design.

[0052] In Fig. The trough zones 52 are arranged in rows perpendicular to the rows in which the cells (specified by the base layers 4) are arranged. The trough zones are spaced at a distance corresponding to the trough spacing. The trough spacing is, for example, at least three or even four times greater than the cell spacing. An exemplary value for the trough spacing is at least 500 µm.

[0053] Fig. Figure 11 shows a device in which the trough zones 52 are separated from the base layers 4 by the drift layer 3. In this case, an electrical contact between the trough 52 and the emitter electrode 2 is directly established (as, for example, in Fig. 8 is shown).

[0054] Another alternative, which is in Fig. As shown in Figure 12, each base layer 4 is in contact with two well zones 52 arranged on opposite sides of the end sections of the base layers 4; that is, the base layers 4 are arranged between two well zones 52. Such well zones 52 can also be connected to each other via a p-doped connecting well zone 55, which is another p-doped layer oriented in the same direction as the base layers but is not embedded in a source region, i.e., it is not part of an active cell. If the well 5 includes connecting well zones 55, the electrical contact of the well 5 with the emitter electrode 2 can be established by the well zones 52 or by the well connecting zones 55 with the emitter electrode 2.For example, the connection basin zones 55 can also be connected to the emitter electrode 2 via the basin zones 52 (where the basin zones 52 can then be connected to the emitter electrode 2 either directly or via the base layers 4).

[0055] The Fig. 13 and Fig. Figure 14 shows variations in which the base layers 4 are arranged in a circular direction as strips distributed around a single circular trough 51 or trough zone 52. In addition to this arrangement, Figure 14 shows Fig. 14, that such strips can in turn be surrounded by a further trough zone 52 in the form of a ring, so that the base layers 4 in the form of strips can be connected to the inner circular trough zone 52 as well as to the outer annular trough zone 52. For these embodiments, the cell spacing is to be understood as the minimum distance between two directly adjacent active IGBT cells, i.e., the distance between the cells in the inner trough zone 52.

[0056] The multiple base layers 4 share the same base layer surface area. The base layer surface area is the area of ​​the entire surface of base layer 4.

[0057] If a well 5 is electrically connected to the emitter electrode 2 via a base layer 4, the connection is provided in a connection area. This connection area is the area where the well 5 (or the well zone 52) borders the base layer 4. In another exemplary embodiment, the base layers 4 are in contact with the well / well zones 51, 52 in a connection area that comprises less than 1% of the base layer surface area. If the base layer 4 is in contact with more than one, typically two, well zones 52, each connection area is, in an exemplary embodiment, less than 1%. If a well layer 5 is electrically connected to the emitter electrode 2 directly by placing the emitter electrode 2 on the well layer 5, the connection area can be adjusted.The emitter electrode 2 can be in contact with the trough 5 in the area which represents less than 1% of the trough layer surface area.

[0058] As an alternative to the designs with a planar gate electrode, the device can be used for trench cell designs as in Fig. Figure 15 shows a trench-gate electrode 75 electrically isolated from the base layer 4, the source region 6, and the drift layer 3 by an insulating layer 78. The trench-gate electrode 75 is located in the same plane (this plane being parallel to the emitter side 11) and laterally to the base layer 4, and extends deeper into the drift layer 3 than the base layer 4. Typically, another insulating layer 782 is arranged between the gate electrode 7 and the emitter electrode 2.

[0059] Fig. Figure 16 shows a further exemplary embodiment in which the device according to the invention further comprises an n-doped enrichment layer 95, which has a higher doping concentration than the drift layer 3. The enrichment layer 95 is arranged between the drift layer 3 and the base layer 4, thereby separating them. The enrichment layer 95 could also be arranged between the trough 5 and the drift layer 3. Naturally, the enrichment layers 95 can be applied to any type of device, e.g., to designs with a trench gate or a planar gate.

[0060] Each trough / trough zone 51, 52 has a trough / trough zone area, while the drift layer 3 has a drift layer area in a plane parallel to the emitter side 11. The total maximum trough area (i.e., the area of ​​all trough zones in the plane) can be in the range of 0.1 to 10% of the drift layer area in the plane (which typically also corresponds to the maximum device area).

[0061] In another exemplary embodiment, the trough layer 5 has a transition depth in the range of 1 to 15 µm, and the doping density is higher than 1 × 10 16 atoms / cm² 3 .

[0062] The Fig. 18, Fig. 19, Fig. 20, Fig. 21 to Fig. Figures 22 show variations of the arrangement of a single tub 51 or of tub zones 52 in a section that follows the plane along line CC of Fig. 3 corresponds to. In Fig. The source regions 6 and the base layers 4 surround the contact area 22 of the emitter electrode 2 on two opposite sides in a plane parallel to the emitter side 11. Perpendicular to these sides in the same plane, the trough zones 52 are arranged as continuous strips extending along several active cells 18. The base layer 4 and the base layer contact area 22 can extend to the trough zones 52, thus creating a larger contact area between the trough layer 5 and the emitter electrode 2.

[0063] Alternatively, the bathing zones 52 can be used, as in Fig. As shown in Figure 19, the trough zones are arranged at the boundary of the active cell, but are limited to the size of the active cell 18 or even smaller than the size of this active cell 18, i.e., they are located at the boundary of the active cell 18. In many applications, it is advantageous to distribute the trough zones uniformly in the device, but still with minimal interaction of the trough zones with the active cells during the switching state of the device. This is the case if the distance between the trough zones is greater than the coefficient of ambipolar diffusion, which usually has values ​​in the range of 100 to 2000 µm. Therefore, good performance is achieved if the trough zones 52 are spaced 100 to 2000 µm apart. A dimension of the individual trough 51 can then be in the range of 1 to 200 µm.The dimension shall be measured in a plane parallel to the emitter side 11 and perpendicular to the direction of the cluster as the maximum extent of the individual trough 51 in this plane.

[0064] The Fig. 20 and Fig. Figure 21 shows variations in which the base layers 4 and the trough zones 52 are arranged in a similar way to those in Fig. The arrangement shown in Figure 6 is as follows. The cells 18 have source regions 6 and p-base layers 4, which are arranged on two opposite sides of the cells, while the trough zones 52 are arranged in the same plane perpendicular to the source regions 6 and the base layers 4. The trough zones 52 can connect several such cells, which are arranged along the length of the trough zones 52 ( Fig. 20).

[0065] In Fig. 22 is a base layer 4 in the shape of a cross surrounded by a trough zone 52 in the shape of a ring. The base layers 4 and the source areas 6 show the same cross design.

[0066] In Fig. Figure 23 shows another device according to the invention, in which the tub 5 is connected to the base layer 4. Fig. Figure 23A shows a prior art device without a trough. The closer the trough 5 is arranged to the emitter electrode 2 ( Fig. 23B to 23E), the less influence the channel has on the diode properties. Fig. Figure 24A shows that the device without p-well 5 has a strong drop-back effect. The drop-back disappears when the distance between well 5 and emitter electrode 2 decreases ( Fig. 24B to E).

[0067] The structure according to the invention with trough 5 outside the active cell 18 can be applied to MOSFETs. For such MOSFETs ( Fig.17) The first layer 8 consists only of the first region 81 in the form of an uninterrupted, homogeneous layer over the entire plane of the wafer 10. There is no p-doped second region in the plane between the drift layer and the collector electrode 25.

[0068] In another embodiment, the conductivity types are reversed, i.e., all layers of the first conductivity type are of the p-type (e.g., the drift layer 3, the source region 6), while all layers of the second conductivity type are of the n-type (e.g., the base layer 4, the collector layer 85).

[0069] It should be noted that the indefinite article "ein" or "eine" does not exclude the plural. Furthermore, elements that have been described in relation to different embodiments can be combined. Reference symbol list 1 reverse-conducting power semiconductor device 10 wafers 11 Emitter side 15 Collector side 18 active cells 100 MOSFET 150 backward conducting power semiconductor device of the state of the art 2 emitter electrode 22 Contact area 25 Collector electrode 3 Drift layer 4 Base layer 5 tubs 51 individual tubs 52 Bathtub area 55 Connection tray zone 6 Source area 7 planar gate electrode 75 Trench-Gate Electrode 78 insulating layer 781 first insulating layer 782 second insulating layer 8 first shift 81 first area 85 second area 9 Buffer layer 95 Enrichment layer

Claims

[1] A backward conducting power semiconductor device comprising a wafer (10) containing layers with different conductivity types, wherein the layers are arranged between an emitter electrode (2) on an emitter side (11) and a collector electrode (25) on a collector side (15) opposite the emitter side (11), and comprising the following: - a drift layer (3) of a first conductivity type, arranged between the emitter side (11) and the collector side (15), - a first layer (8) comprising a first region (81) of the first conductivity type with a higher doping concentration than the drift layer (3) and a second region (85) of a second conductivity type arranged adjacent to the first region (81), wherein the first layer (8) is arranged between the drift layer (3) and the collector electrode (25), - several base layers (4) of the second conductivity type arranged between the drift layer (3) and the emitter electrode (2), wherein the base layers (4) are in direct electrical contact with the emitter electrode (2), - several source regions (6) of the first conductivity type, arranged on the emitter side (11), embedded in one of the base layers (4) and contacting the emitter electrode (2), wherein the source regions (6) have a higher doping concentration than the drift layer (3), - several gate electrodes, each of which is electrically insulated from the base layers (4), the source regions (6) and the drift layer (3) by an insulating layer (78), wherein the emitter electrode (2) contains several base layer contact areas (22) at which the emitter electrode (2) contacts the base layers (4) and the source areas (6), wherein in the wafer (10) an IGBT semiconductor cell (18) is formed, which contains layers or parts of layers which lie in an orthogonal projection with respect to the emitter side (11) of one of the base layer contact areas (22) with which one of the source areas (6) is in contact, this source area (6) and such part of one of the base layers (4) in which an electrically conductive channel may be formed, wherein a cluster is formed by several such IGBT cells, in particular by at least 10 IGBT cells, wherein the IGBT cells are arranged directly adjacent to one another in one direction on the emitter side (11) and IGBT cells are arranged at a cell distance, wherein the device further comprises a trough (5) of the second conductivity type, which is arranged in a plane parallel to the emitter side (11), wherein the base layers (4) are arranged in this plane, wherein the tray (5) is arranged in a different direction than the direction in which the multiple IGBT cells are arranged, wherein the well (5) has a surface area and wherein the well (5) is arranged outside the IGBT cells (18) and is electrically connected to the emitter electrode (2) directly at a well contact area which is at most 10% of the maximum area of ​​the well (5) or via at least one of the base layers (4), wherein each of the at least one base layer (4) has a base layer surface area, and the at least one base layer (4) is in contact with the well (5) in a contact area which is less than 1% of the base layer surface area. [2] Device according to claim 1, characterized by, that the trough (5) has at least one transition to the drift layer (3) which extends deeper into the wafer (10) than the transition of the base layer (4) to the drift layer (3), or has a doping concentration that is higher than that of the base layer (4). [3] Device according to one of claims 1 or 2, characterized by that the tub (5) is designed as a single tub (51) or that the tub (5) is designed in the form of several tub zones (52). [4] Device according to claim 3, characterized by , that at least some or all of the tub zones (52) are connected to each other or that the tub zones (52) are separated from each other. [5] Device according to claim 3, characterized by , that the multiple base layers (4) are connected to the single trough (51) or to at least one of the trough zones (52). [6] Device according to any one of claims 1 to 5, characterized by, that the basin zones (52) are arranged with a basin spacing that is at least three times, in particular four times, larger than the cell spacing of the IGBT cells. [7] Device according to any one of claims 1 to 6, characterized by , that the tray (5) is arranged perpendicular to the direction in which the multiple IGBT cells (18) are arranged. [8] Device according to claim 3, characterized by , that a maximum trough area of ​​the individual trough (51) or of the at least one trough zone (52) in a plane parallel to the emitter side (11) is in the range of 0.1% to 20% of a drift layer area in that plane. [9] Device according to claim 3, characterized by , that the trough zones (52) are arranged at a trough distance from each other of at least 500 µm, in particular at most 2000 µm. [10] Device according to claim 3, characterized by, that a dimension of the individual trough (51) in a plane parallel to the emitter side (11) lies in the range of 1 to 200 µm. [11] Device according to any one of claims 1 to 9, characterized by , that the device comprises several planar gate electrodes (7) extending to a region above the well (5), and that no conductive channel is formed in the well (5) by the insulating layer (78) having a sufficiently large thickness and / or by the well (5) having a sufficiently high doping concentration. [12] Device according to any one of claims 1 to 11, characterized by , that the base layers (4) are separated from the drift layer (3) by an enrichment layer (95) of the first conductivity type, which has a higher doping concentration than the drift layer (3). [13] Device according to any one of claims 1 to 12, characterized by, that the cell spacing of the IGBT cells is at most 150 µm, in particular at most 120 µm and in particular at most 50 µm.

Images