ELECTRONIC COMPONENTS AND METHOD OF MAKING AN ELECTRONIC COMPONENT

Abstract

Electronic component (30) comprising: a semiconductor layer (12) having a first conductivity type and having a first surface; a primary junction in the semiconductor layer (12) at the first surface thereof; a lightly doped region (36) adjacent to the primary junction and having a second conductivity type opposite to the first conductivity type; and a junction termination structure (39) in the lightly doped region (36), the junction termination structure (39) having, when viewed in a plane of the first surface, an upper boundary (39A), a lateral boundary (39B), and a corner region (40) between the upper boundary (39A) and the lateral boundary (39B); wherein the lightly doped region (36) extends in a first direction away from the primary junction outside the junction termination structure (39) and extends normal to a point on the upper boundary (39A) by a first distance (44) which is less than a second distance (46) by which the lightly doped region (36) extends in a second direction away from the primary junction and normal to a point (39D) on the corner region (40), and wherein the electronic component (30) additionally comprises at least one potential-free guard ring segment (50) between a corner of the junction termination structure (39) and a corner of the component (30), the corner of the junction termination structure (39) being between the potential-free guard ring segment (50) and the primary junction, characterized in that the potential-free guard ring segment (50) has an implanted region in the semiconductor layer (12) which is insulated from the junction termination structure (39).

Description

AREA

[0001] The present invention relates to electronic components and methods of forming an electronic component. BACKGROUND

[0002] High-voltage silicon carbide (SiC) devices can handle high voltages and can handle up to approximately 100 amperes or more of electrical current, depending on the size of their active area. High-voltage SiC devices have a number of important applications, particularly in power conditioning, distribution, and control.

[0003] A conventional power device structure includes an n-type SiC substrate on which an n-type epitaxial layer serving as a drift region is formed. The device typically includes a PN and / or Schottky junction on the n-type layer, which acts as a main junction for blocking reverse bias voltage and providing forward current flow. A p-type junction termination extension (JTE) region (planar lateral junction edge), typically formed by ion implantation, may surround the main junction. The implants used to form the JTE region may be aluminum, boron, or any other suitable p-type dopant.The purpose of the JTE region is to reduce or avoid the electric field crowding the edges and to reduce or prevent the space charge region from interacting with the device surface. Surface effects can cause the space charge region to spread unevenly, which can adversely affect the breakdown voltage of the device. Other termination techniques include guard rings and floating field rings, which can be more heavily influenced by surface effects. A channel stop region can also be formed by implanting n-type dopants, such as nitrogen or phosphorus, to prevent or reduce extension of the space charge region to the device edge.

[0004] Additional conventional terminations of SiC Schottky diodes are described in "Planar Terminations in 4H-SiC Schottky Diodes With Low Leakage and High Yields" by Singh et al., ISPSD '97, pp. 157-160. A p-type epitaxially grown guard-ring termination for a SiC Schottky barrier diode is discussed in "The Guard-Ring Termination for High-Voltage SiC Schottky Barrier Diodes" by Ueno et al., IEEE Electron Device Letters, Vol. 16, No. 7, July, 1995, pp. 331-332. In addition, other termination techniques are described in WO 1997 / 008754 A2.

[0005] In addition to junction termination extension (JTE), multiple floating guard rings (MFGR) and field plates (FP) are commonly used termination designs in high-voltage silicon carbide devices. Another common edge termination technique is a mesa edge termination.

[0006] Field plate termination is also a common technique for edge termination of a device and can be cost-effective. In conventional field plate devices, high fields are favored by the oxide layer beneath the metal field plate. This technique works well for silicon devices, where the peak field in the semiconductor is relatively small. In SiC devices, the electric fields in the off-state can be very large (~2 MV / cm), which is multiplied by a factor of 2.5 at the oxide-semiconductor interface. This results in very high oxide fields and can cause long-term reliability problems. Thus, field plate terminations may be unsuitable for use in SiC devices.

[0007] The use of multiple floating guard rings in addition to the JTE has been proposed as a technique for reducing the sensitivity of the JTE to implanted dosage variation. See Kinoshita et al., "Guard Ring Assisted RESURF: A New Termination Structure Providing Stable And High Breakdown Voltage for SiC Power Devices," Tech. Digest of ISPSD '02, pp. 253-256. Kinoshita et al. reported that such techniques reduced the sensitivity to implanted dosage variation. However, the area used for termination was increased to nearly three times the area of ​​the JTE alone because the guard rings are added to both the inner edge of the JTE and the outer edge of the JTE.

[0008] A conventional JTE-terminated PIN diode is Fig. 1. As shown therein, a PIN diode 100 includes an n-type drift layer 112 between a p+ layer 116 and an n+ substrate 114. Fig. Figure 1 illustrates one half of a PIN structure; the structure may include mirror-image regions (not shown). An anode contact 123 is located on the p+ layer 116, and a cathode contact 125 is located on the n+ substrate 114. A junction termination extension (JTE) region 120 including a plurality of JTE zones 120A, 120B, 120C is provided in the n- drift layer 112 adjacent to the p+ layer 116. The JTE zones 120A, 120B, 120C are p-type regions that may have levels of charge that decrease outwardly in a stepwise manner with the distance from the PN junction between the p+ layer 116 and the n- drift layer 112. Although three JTE zones 120A, 120B, 120C are illustrated, more or fewer JTE zones may be provided.

[0009] The JTE zones 120A, 120B, 120C may be formed by successively implanting ions into the n-drift layer 112. However, such implantation may require multiple masking and implantation steps, increasing complexity and production costs. This may be exacerbated by increasing the number of JTE zones. Furthermore, the stepwise doping gradient provided by such an approach may not provide ideal termination.

[0010] Additional conventional terminations of SiC Schottky diodes are described in "Planar Terminations in 4H-SiC Schottky Diodes With Low Leakage and High Yields" by Singh et al, ISPSD '97, pp. 157-160. A p-type epitaxially grown guard-ring termination for a SiC Schottky barrier diode is described in "The Guard-Ring Termination for High-Voltage SiC Schottky Barrier Diodes" by Ueno et al, IEEE Electron Device Letters, Vol. 16, No. 7, July, 1995, pp. 331-332. In addition, other termination techniques are described in WO 1997 / 008 754 A2.

[0011] Another type of transition closure is disclosed in US 7 026 650 B2, assigned to the assignee of the present invention, the disclosure of which is incorporated herein by reference as if fully set forth.

[0012] DE 102 11 688 A1 describes an electronic component having a semiconductor layer of a first conductivity type, a primary junction in the semiconductor layer at a first surface thereof, a lightly doped region adjacent to the primary junction and of a second conductivity type opposite to the first conductivity type, and a junction termination structure in the lightly doped region, the junction termination structure having, when viewed in a plane of the first surface, an upper boundary, a lateral boundary, and a corner region between the upper boundary and the lateral boundary.In addition, the lightly doped region extends in a first direction away from the primary junction outside the junction termination structure normal to a point on the upper boundary by a first distance which is less than a second distance by which the lightly doped region extends in a second direction away from the primary junction and normal to a point on the corner region.

[0013] Furthermore, US 2006 / 0 065 899 A1, US 2010 / 0 059 818 A1 and US 2010 / 0 200 936 A1 also disclose electronic components. SUMMARY

[0014] The present invention provides an electronic component having the features of claim 1, an electronic component having the features of claim 2, an electronic component having the features of claim 3, an electronic component having the features of claim 13, an electronic component having the features of claim 16, a method of forming an electronic component having the features of claim 17, a method of forming an electronic component having the features of claim 18, a method of forming an electronic component having the features of claim 19 and a method of forming an electronic component having the features of claim 20.

[0015] The junction termination structure may include a guard ring adjacent to and spaced from the primary junction, the guard ring having the second conductivity type and a doping concentration higher than a doping concentration of the lightly doped region.

[0016] The semiconductor layer may comprise silicon carbide.

[0017] The upper boundary of the junction termination structure may be aligned in a <11-20> crystallographic direction of the silicon carbide semiconductor layer, and the lateral boundary of the junction termination structure may be aligned in a <10-10> crystallographic direction of the silicon carbide semiconductor layer.

[0018] The corner of the junction termination structure may be in an upper left corner of the electronic device if the upper boundary of the junction termination structure is positioned above the primary junction and the lateral boundary of the junction termination structure is positioned to the left of the primary junction.

[0019] The lightly doped region may extend in the first direction away from the primary junction and normal to the point at the upper boundary by a distance of about 10 micrometers and may extend in the second direction away from the primary junction and normal to the point at the corner by a distance of at least about 20 micrometers.

[0020] The first conductivity type may be one of the n-type or the p-type, and the second conductivity type may be one of the p-type or the n-type.

[0021] The electronic component may have four corner regions, and the lightly doped region extends into each of the four corner regions.

[0022] The potential-free guard ring segment may have a radius of curvature that is approximately the same as a radius of curvature of the corner of the transition termination structure.

[0023] The corner of the lightly doped region may have a first radius of curvature which may be smaller than a second radius of curvature of the corner of the junction termination structure. DESCRIPTION OF THE DRAWINGS Fig. Figure 1 illustrates a SiC PIN diode with a conventional junction termination extension (JTE). Fig. Figure 2 is a schematic diagram of a hexagonal structure of the crystal unit cell. Fig. Figure 3 is a schematic view of a SiC wafer processed to have primary and secondary orientation flats. Fig. Figure 4 is a top view of a PIN diode having an unused corner area. Fig. 5 is a cross-sectional view of the device of Fig. 4. Fig. Figure 6 is a detailed plan view of a portion of the device of Fig. 4. Fig. 7, Fig. 8 and Fig. 9 are detailed plan views of portions of electronic components in accordance with some embodiments. Fig. 10 is a cross-sectional view of a Schottky diode in accordance with some embodiments. DETAILED DESCRIPTION

[0024] Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are illustrated. This invention may, however, take many different forms and should not be considered limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numerals refer to like elements throughout.

[0025] As described in detail below, embodiments of the present invention may provide improved edge termination of semiconductor devices, such as PN, Schottky, PIN, or other such semiconductor devices. Certain embodiments of the present invention provide edge termination for silicon carbide (SiC) devices. For example, embodiments of the present invention may be used as edge termination for SiC Schottky diodes, junction barrier Schottky (JBS) diodes, PIN diodes, thyristors, transistors, or other such SiC devices.

[0026] Semiconductor power devices are designed to block (in the off-state) or pass (in the on-state) large levels of voltage and / or electrical current. For example, in the off-state, a semiconductor power device may be designed to withstand hundreds to thousands of volts of electrical potential.

[0027] However, at high blocking voltages, a semiconductor power device may begin to leak some electrical current through the device. Such electrical current, referred to as "leakage current," can be highly undesirable. Leakage current may begin to flow if the blocking voltage is increased beyond the device's rated voltage, which is usually a function of the doping and drift layer thickness. Leakage current may also begin to flow if the device's edge termination fails.

[0028] A guard ring edge termination of a power semiconductor device may begin to collapse, allowing leakage current to flow at a voltage lower than the device's rated voltage. It has been found that such leakage current may begin to flow near a specific region of the edge termination. Specifically, when a high reverse bias voltage is applied to a silicon carbide-based semiconductor device, leakage current may begin to flow in a region near the upper left corner of a guard ring formed on a wafer having a specific crystallographic orientation.

[0029] Fig. Figure 2 illustrates a hexagonal unit cell of a hypothetical crystal. The unit cell 10 has a pair of opposing hexagonal faces 11A, 11B. The hexagonal faces are normal to the c-axis, which is along the <0001> The direction is defined by the Miller-Bravais indexing system for designating directions in a hexagonal crystal. Consequently, the hexagonal faces are sometimes called the c-faces, which define the c-planes or basal planes of the crystal. Planes perpendicular to the c-plane are called prismatic planes.

[0030] Fig. Figure 3 illustrates a single wafer of single crystal silicon carbide substrate 20 on which a device is to be fabricated. The wafer 20 has a generally circular perimeter. A pair of flats 22, 24 (which for clarity are Fig. 3 are exaggerated) was milled into the wafer 20 to assist in the orientation of the wafer. In particular, the wafer 20 has a primary flat 22 and a secondary flat 24. The primary flat 22 is in the {10-10} plane and runs along the <11-20> crystallographic direction, while the secondary flat 24 is in the {11-20} plane and runs along the <10-10> crystallographic direction. Viewed from the carbon surface of the wafer, the primary flat 22 is on the bottom side of the wafer and the secondary flat 24 is on the right side of the wafer.

[0031] The surface 26 of the wafer generally corresponds to the c-face of the silicon carbide crystal (except that the wafer may be sliced ​​at an angle to the α axis toward the <11-20> direction to accommodate epitaxial growth).

[0032] A PIN diode 30 with a guard ring termination is in Fig. 4-6. In particular, Fig. 4 is a plan view of a semiconductor power device 30, such as a silicon carbide PIN diode, Fig. 5 is a cross section along the line AA of Fig. 4, and Fig. 6 is a detailed view of an upper corner region 30A of the component 30.

[0033] The device 30 may be formed within a surface of a silicon carbide substrate 26 defined by a plurality of sawing lines 32 at which the substrate will be sawn to separate the fabricated devices from one another.

[0034] The device 30 includes a silicon carbide substrate 14. The substrate may be doped with dopants having a first conductivity type and may have a polytype of 2H, 4H, 6H, 3C, and / or 15R.

[0035] The device 30 includes a lightly doped drift layer 12 of the first conductivity type and a region 42 having a second conductivity type opposite to the first conductivity type and forming a PN junction with the drift layer 12. Assuming the first conductivity type is n-type and the second conductivity type is p-type, an anode contact 34 is on the p-type region 42, and a cathode contact is on the n-type substrate 14.

[0036] A guard ring structure is provided on the surface of the drift layer 12 adjacent the PN junction between the region 42 and the drift layer 12. The guard ring structure includes a plurality of guard rings 38 of the second conductivity type forming concentric rings around the active region of the device (i.e., the region including the main PN junction). The guard rings 38 may be formed, for example, by ion implantation. Formation of the guard ring is described in detail in US 7 026 650 B2 and US 2006 / 0 118 792 A1, which are assigned to the assignee of the present invention and are incorporated herein by reference.

[0037] Also included in the structure is a lightly doped region 36 of the second conductivity type, provided between the guard rings 38 at the surface of the drift layer 12. The lightly doped region 36 may extend outside the outermost guard ring 38 and may be formed to a depth in the drift layer 12 that is less than the depth to which the guard rings extend. In some embodiments, the lightly doped region 36 may provide a surface charge compensation region, as discussed, for example, in US 7 026 650 B2 and US 2006 / 0 118 792 A1. In some other embodiments, the lightly doped region may provide a reduced surface field (RESURF) region at the surface of the drift layer, as discussed, for example, in US 7 026 650 B2 and US 2006 / 0 118 792 A1.The lightly doped region 36 may extend completely or incompletely between adjacent guard rings 38. Furthermore, the lightly doped region 36 may extend deeper or narrower into the drift layer 12 than the guard rings 38.

[0038] Referring to Fig. 4 and Fig. 6, when viewed from above, the guard rings 38 may be rounded at the corners of the device to help reduce leakage current, which may otherwise occur if the guard rings are designed to have sharp corners where voltage may peak. However, rounding the corners of the guard rings 38 may result in a loss of potentially useful area of ​​the die. That is, rounding the corners 38 creates a corner region 40 of unused space between the corners of the area defined by the saw streets 32 and the rounded corner 38A of the outermost guard ring 38. Some embodiments exploit this "lost" space by forming structures and / or features therein that may reduce leakage current, particularly at the most vulnerable corners of the device.

[0039] As in Fig. As illustrated in Figure 4, the device 30 may be oriented on a wafer 20 such that the saw streets 32 are parallel to specified orthogonal directions from the substrate. For example, two of the saw streets 32 may be parallel to the <11-20> direction, while two of the saw streets 32 may be parallel to the <10-10> direction.

[0040] Referring to Fig. 7, in some embodiments, the lightly doped region 36 may extend into one or more of the corner regions 40 between the corners of the saw streets 32 and the outermost guard ring 39. The lightly doped region 36 may thus be configured to have a smaller radius of curvature than the outermost guard ring 39 in the corner region 40. In some embodiments, the lightly doped region 36 may extend into all corner regions. In other embodiments, the lightly doped region 36 may extend into fewer than all corner regions; for example, the lightly doped region 36 may extend into only one corner region.

[0041] In one aspect, the lightly doped region 36 may extend in a first direction away from the primary junction and normal to a point 39D at the corner of the outermost guard ring 39 by a distance that is greater than a distance by which the lightly doped region 36 extends in a direction away from the primary junction and normal to a point 39C at a boundary 39A, 39B of the outermost guard ring 39.In other words, the lightly doped region 36 may extend outside the outermost guard ring 39 in a first direction away from the primary junction by a first distance 44 in a first region from the lightly doped region adjacent the corner region 40, and may extend outside the outermost guard ring 39 in a second direction away from the primary junction in a second region from the lightly doped region adjacent a boundary 39A of the outermost guard ring 39 by a second distance 46 which is greater than the first distance 44.

[0042] In some embodiments, the lightly doped region 36 may extend in a direction away from the primary junction and normal to a point 39C at a boundary 39A, 39B of the outermost guard ring 39 by about 10 micrometers, and may extend in a direction away from the primary junction and normal to a point 39D at the corner of the outermost guard ring 39 by at least about 20 micrometers.

[0043] Extending the lightly doped region 36 as discussed above can help reduce and / or spread the electric field in an area prone to electrical breakdown at high reverse bias voltages. This can reduce the leakage current from the device, potentially leading to improved yields and / or a reduction in chip size for similar breakdown voltages. Extending the lightly doped region 36 can be accomplished without increasing the overall size of the chip, as the lightly doped region can be extended into previously unused space between the corner of the outermost guard ring and the outer corner of the device.

[0044] Further embodiments are in Fig. 8 and Fig. 9. As shown therein, one or more supplemental guard ring segments 50 may be provided as isolated implanted regions of the second conductivity type in one or more of the corner regions 40 between a corner of the outermost guard ring and an outer corner of the device. The guard ring segments 50 may have a radius of curvature that is the same as or similar to the radius of the guard rings 38 in the corner region 40 in some embodiments.

[0045] In some embodiments, the guard ring segments 50 may be provided in all corner regions. In other embodiments, the guard ring segments 50 may be provided in fewer than all corner regions; for example, the guard ring segments 50 may be provided in only one corner region.

[0046] In some embodiments, the guard ring segments 50 may be provided inside the extension from the lightly doped regions 36 into the corner region 40, as in Fig. 8. In other embodiments, as shown in Fig. 9, the guard ring segments 50 can be provided without extending the lightly doped regions 36 into the corner region 40. Although the guard ring segments 50 need not extend completely around the main junction of the device in the manner of guard rings 38, they can still help to distribute the electric field in the vulnerable corner region 40, thus increasing the breakdown voltage of the device.

[0047] Although embodiments of the invention have been described with respect to PIN diode devices, embodiments of the invention may be used in conjunction with other types of devices, and / or devices having other types of junctions. For example, Fig. 10 is a cross-sectional view of a structure of a Schottky diode 31 in accordance with some embodiments, having a Schottky contact 35 forming a rectifying Schottky junction with the underlying drift layer 12.

[0048] It should be understood that although the terms first, second, etc. may be used herein to describe different elements, these elements are not intended to be limited by these terms. These terms are used merely to distinguish one element from another. For example, a first element could be called a second element, and similarly, a second element could be called a first element, without departing from the scope of the present invention. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0049] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It is also to be understood that the terms "comprises," "having," "comprises," and / or "comprising," when used in this specification, specify the presence of the stated features, integers, steps, acts, elements, and / or components, but do not preclude the presence or addition of one or more features, integers, steps, acts, elements, components, and / or groups thereof.

[0050] Unless otherwise specified, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It is also understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the related art, and will not be interpreted in an idealized or overly formal sense unless expressly stated so herein.

[0051] It is to be understood that when an element, such as a layer, region, or substrate, is referred to herein as being "on" or extending "onto" another element, then it may be directly on or extend directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, then no intervening elements are present. It is also to be understood that when an element is referred to as being "connected" or "coupled" to another element, then it may be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, then no intervening elements are present.

[0052] Relative terms such as "below," "above," "upper," "lower," "horizontal," "lateral," "vertical," "beneath," "above," etc., may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the figures. It is understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0053] Embodiments of the invention have been described herein with reference to cross-sectional illustrations, which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. In addition, variations from the shapes of the illustrations can be expected as a result of, for example, manufacturing processes and / or tolerances. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein, but are intended to encompass variations in the shapes resulting, for example, from manufacturing.For example, an implanted region illustrated as a rectangle will typically have rounded or curved features and / or a gradient of implanted concentration at its edges, rather than a discrete transition from the implanted to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of any region of a device and are not intended to limit the scope of the invention.

[0054] Some embodiments of the invention have been described with reference to semiconductor layers and / or regions characterized as having a conductivity type, such as n-type or p-type, which relates to the majority charge carrier concentration in the layer and / or region. Thus, n-type material has a majority equilibrium concentration of negatively charged electrons, while p-type material has a majority equilibrium concentration of positively charged holes. Some material may be labeled with a "+" or "-" (as in n+, n-, p+, p-, n++, n--, p++, p--, or the like) to indicate a relatively larger ("+") or smaller ("-") concentration of majority charge carriers compared to another layer or region.However, such a designation does not imply the existence of a particular concentration of majority or minority charge carriers in a layer or region.

[0055] Many different embodiments have been disclosed herein, in conjunction with the above description and drawings. It should be understood that it would be excessively monotonous and confusing to describe and illustrate literally every combination and subcombination of these embodiments. Accordingly, all embodiments may be combined in any manner and / or combination, and this specification, including the drawings, is intended to provide a complete written description of all combinations and subcombinations of the embodiments described herein, and of the manner and process of making and using them.

Claims

[1] Electronic component (30), comprising: a semiconductor layer (12) having a first conductivity type and having a first surface; a primary junction in the semiconductor layer (12) at the first surface thereof; a lightly doped region (36) adjacent to the primary junction and having a second conductivity type opposite to the first conductivity type; and a junction termination structure (39) in the lightly doped region (36), the junction termination structure (39) having, when viewed in a plane of the first surface, an upper boundary (39A), a lateral boundary (39B), and a corner region (40) between the upper boundary (39A) and the lateral boundary (39B); wherein the lightly doped region (36) extends in a first direction away from the primary junction outside the junction termination structure (39) and extends normal to a point on the upper boundary (39A) by a first distance (44) which is less than a second distance (46) by which the lightly doped region (36) extends in a second direction away from the primary junction and normal to a point (39D) on the corner region (40), and wherein the electronic component (30) additionally comprises at least one potential-free guard ring segment (50) between a corner of the junction termination structure (39) and a corner of the component (30), the corner of the junction termination structure (39) being between the potential-free guard ring segment (50) and the primary junction, characterized by , that the potential-free guard ring segment (50) has an implanted region in the semiconductor layer (12) which is insulated from the junction termination structure (39). [2] Electronic component (30) comprising: a semiconductor layer (12) having a first conductivity type and having a first surface; a primary junction in the semiconductor layer (12) at the first surface thereof; a lightly doped region (36) adjacent to the primary junction and having a second conductivity type opposite to the first conductivity type; and a junction termination structure (39) in the lightly doped region (36), the junction termination structure (39) having, when viewed in a plane of the first surface, an upper boundary (39A), a lateral boundary (39B), and a corner region (40) between the upper boundary (39A) and the lateral boundary (39B); wherein the lightly doped region (36) extends in a first direction away from the primary junction outside the junction termination structure (39) and extends normal to a point on the upper boundary (39A) by a first distance (44) which is less than a second distance (46) by which the lightly doped region (36) extends in a second direction away from the primary junction and normal to a point (39D) on the corner region (40), and wherein the electronic component (30) additionally comprises at least one potential-free guard ring segment (50) between a corner of the junction termination structure (39) and a corner of the component (30), the corner of the junction termination structure (39) being between the potential-free guard ring segment (50) and the primary junction, characterized by , that the electronic component (30) has a plurality of mutually isolated potential-free guard ring segments (50) between the corner of the junction termination structure (39) and the corner of the component (30). [3] Electronic component (30) comprising: a semiconductor layer (12) having a first conductivity type and having a first surface; a primary junction in the semiconductor layer (12) at the first surface thereof; a lightly doped region (36) adjacent to the primary junction and having a second conductivity type opposite to the first conductivity type; and a junction termination structure (39) in the lightly doped region (36), the junction termination structure (39) having, when viewed in a plane of the first surface, an upper boundary (39A), a lateral boundary (39B), and a corner region (40) between the upper boundary (39A) and the lateral boundary (39B); wherein the lightly doped region (36) extends in a first direction away from the primary junction outside the junction termination structure (39) and extends normal to a point on the upper boundary (39A) by a first distance (44) which is less than a second distance (46) by which the lightly doped region (36) extends in a second direction away from the primary junction and normal to a point (39D) on the corner region (40), and wherein the electronic component (30) additionally comprises at least one potential-free guard ring segment (50) between a corner of the junction termination structure (39) and a corner of the component (30), the corner of the junction termination structure (39) being between the potential-free guard ring segment (50) and the primary junction, characterized by , that the potential-free guard ring segment (50) does not extend completely around the primary transition. [4] The electronic component (30) of claim 1, 2 or 3, wherein the junction termination structure (39) comprises a guard ring (39) adjacent to and spaced from the primary junction, the guard ring (39) having the second conductivity type and having a doping concentration higher than a doping concentration of the lightly doped region (36). [5] Electronic component (30) according to claim 1, 2 or 3, wherein the semiconductor layer (12) comprises silicon carbide. [6] The electronic component (30) of claim 5, wherein the upper boundary (39A) of the junction termination structure (39) is oriented in a <11-20> crystallographic direction from the silicon carbide semiconductor layer (12) and the lateral boundary (39B) of the junction termination structure (39) is oriented in a <10-10> crystallographic direction from the silicon carbide semiconductor layer (12). [7] The electronic component (30) of claim 1, 2 or 3, wherein the corner of the junction termination structure (39) is in an upper left corner of the electronic component (30) when the upper boundary (39A) of the junction termination structure (39) is positioned above the primary junction, and the lateral boundary (39B) of the junction termination structure (39) is positioned to the left of the primary junction. [8] The electronic component (30) of claim 1, 2 or 3, wherein the lightly doped region (36) extends in the first direction away from the primary junction outside the junction termination structure (39) and extends normal to the point at the upper boundary (39A) by a first distance (44) of approximately 10 micrometers and extends in the second direction away from the primary junction and normal to the point (39D) at the corner by a second distance (46) of at least approximately 20 micrometers. [9] The electronic component (30) of claim 1, 2 or 3, wherein the first conductivity type is one of the n-type or p-type, and the second conductivity type is one of the p-type or n-type. [10] The electronic component (30) of claim 1, 2 or 3, wherein the electronic component (30) has four corner regions (40), and wherein the lightly doped region (36) extends into each of the four corner regions (40). [11] The electronic component (30) of claim 1, 2 or 3, wherein the floating guard ring segment (50) has a radius of curvature that is approximately the same as a radius of curvature of the corner of the junction termination structure (39). [12] The electronic component (30) of claim 1, 2 or 3, wherein the corner of the lightly doped region (36) has a first radius of curvature which is smaller than a second radius of curvature of the corner of the junction termination structure (39). [13] Electronic component (30) comprising: a semiconductor layer (12) having a first conductivity type and having a first surface; a primary junction in the semiconductor layer (12) at the first surface thereof; a transition closure structure (39) adjacent to the primary transition; at least one potential-free guard ring segment (50) in the semiconductor layer (12) outside the junction termination structure (39), the potential-free guard ring segment (50) having a second conductivity type opposite to the first conductivity type; and wherein the potential-free guard ring segment (50) does not extend completely around the primary transition. [14] The electronic component (30) of claim 13, wherein the floating guard ring segment (50) has a radius of curvature that is approximately the same as a radius of curvature of the corner of the junction termination structure (39). [15] The electronic component (30) of claim 13, wherein the junction termination structure (39) comprises a guard ring (39) doped with dopants of the second conductivity type. [16] Electronic component (30) comprising: a semiconductor layer (12) having a first conductivity type and having a first surface; a primary junction in the semiconductor layer (12) at the first surface thereof; a lightly doped region (36) having a second conductivity type opposite to the first conductivity type at the surface of the semiconductor layer (12) and adjacent to the primary junction; and a structure (39) for the transition termination within the lightly doped region (36); wherein the junction termination structure (39), when viewed in a plane of the first surface, has an upper boundary (39A), a lateral boundary (39B), and a corner between the upper boundary (39A) and the lateral boundary (39B), and the lightly doped region (36), when viewed in a plane of the first surface, has an upper boundary, a lateral boundary, and a corner between the upper boundary and the lateral boundary; and wherein the corner of the lightly doped region (36) has a first radius of curvature which is less than a second radius of curvature of the corner of the junction termination structure (39); and wherein the lightly doped region (36) extends into a first depth of the semiconductor layer (12) which is less than a second depth into which the junction termination structure (39) extends. [17] A method of forming an electronic component (30), comprising: Providing a semiconductor layer (12) having a first conductivity type and having a first surface; Providing a primary junction in the semiconductor layer (12) at the first surface thereof; and Providing a lightly doped region (36) adjacent to the primary junction at the surface of the semiconductor layer and having a second conductivity type opposite to the first conductivity type; and Providing a junction termination structure (39) in the lightly doped region (36); wherein the junction termination structure (39), when viewed in a plane of the first surface, has an upper boundary (39A), a lateral boundary (39B), and a corner between the upper boundary (39A) and the lateral boundary (39B); wherein the lightly doped region (36) extends in a first direction away from the primary junction outside the junction termination structure (39) and extends normal to a point at the upper boundary (39A) by a first distance (44) which is less than a second distance (46) by which the lightly doped region (36) extends in a second direction away from the primary junction and normal to a point (39D) at the corner, and wherein the electronic component (30) is additionally formed with at least one potential-free guard ring segment (50) between a corner of the junction termination structure (39) and a corner of the component (30), the corner of the junction termination structure (39) being between the potential-free guard ring segment (50) and the primary junction, characterized by , that the potential-free guard ring segment (50) has an implanted region in the semiconductor layer (12) which is insulated from the junction termination structure (39). [18] A method of forming an electronic component (30), comprising: Providing a semiconductor layer (12) having a first conductivity type and having a first surface; Providing a primary junction in the semiconductor layer (12) at the first surface thereof; and Providing a lightly doped region (36) adjacent to the primary junction at the surface of the semiconductor layer and having a second conductivity type opposite to the first conductivity type; and Providing a junction termination structure (39) in the lightly doped region (36); wherein the junction termination structure (39), when viewed in a plane of the first surface, has an upper boundary (39A), a lateral boundary (39B), and a corner between the upper boundary (39A) and the lateral boundary (39B); wherein the lightly doped region (36) extends in a first direction away from the primary junction outside the junction termination structure (39) and extends normal to a point at the upper boundary (39A) by a first distance (44) which is less than a second distance (46) by which the lightly doped region (36) extends in a second direction away from the primary junction and normal to a point (39D) at the corner, and wherein the electronic component (30) is additionally formed with at least one potential-free guard ring segment (50) between a corner of the junction termination structure (39) and a corner of the component (30), the corner of the junction termination structure (39) being between the potential-free guard ring segment (50) and the primary junction, characterized by , that the electronic component (30) is formed with a plurality of mutually insulated potential-free guard ring segments (50) between the corner of the junction termination structure (39) and the corner of the component (30). [19] A method of forming an electronic component (30), comprising: Providing a semiconductor layer (12) having a first conductivity type and having a first surface; Providing a primary junction in the semiconductor layer (12) at the first surface thereof; and Providing a lightly doped region (36) adjacent to the primary junction at the surface of the semiconductor layer and having a second conductivity type opposite to the first conductivity type; and Providing a junction termination structure (39) in the lightly doped region (36); wherein the junction termination structure (39), when viewed in a plane of the first surface, has an upper boundary (39A), a lateral boundary (39B), and a corner between the upper boundary (39A) and the lateral boundary (39B); wherein the lightly doped region (36) extends in a first direction away from the primary junction outside the junction termination structure (39) and extends normal to a point at the upper boundary (39A) by a first distance (44) which is less than a second distance (46) by which the lightly doped region (36) extends in a second direction away from the primary junction and normal to a point (39D) at the corner, and wherein the electronic component (30) is additionally formed with at least one potential-free guard ring segment (50) between a corner of the junction termination structure (39) and a corner of the component (30), the corner of the junction termination structure (39) being between the potential-free guard ring segment (50) and the primary junction, characterized by , that the potential-free guard ring segment (50) does not extend completely around the primary transition. [20] A method of forming an electronic component (30), comprising: Providing a semiconductor layer (12) having a first conductivity type and having a first surface; Providing a primary junction in the semiconductor layer (12) at the first surface thereof; Providing a junction termination structure (39) having a guard ring (39) on the first surface of the semiconductor layer (12) surrounding the primary junction, the junction termination structure (39) having, when viewed in a plane of the first surface, an upper boundary (39A), a lateral boundary (39B), and a corner between the upper boundary (39A) and the lateral boundary (39B); and Providing at least one potential-free guard ring segment (50) in the semiconductor layer (12) outside the corner of the junction termination structure (39), the potential-free guard ring segment (50) being doped with dopants of the second conductivity type; wherein the potential-free guard ring segment (50) does not extend completely around the primary transition.

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