III-V semiconductor structures with reduced pit defects and methods for forming them

Abstract

Methods for forming a semiconductor structure, comprising: Formation of a III-V semiconductor layer on a substrate; Forming an indium III-V semiconductor layer with a reduced V-pit density on a growth surface of the III-V semiconductor layer with an indium solid-phase concentration above an indium saturation region by combining at least one indium precursor, a group III element precursor different from the indium precursor, and a group V element precursor in a processing chamber equipped with an indium supersaturation region comprising a chamber temperature lower than a chamber temperature corresponding to the indium saturation region; Increasing the concentration of indium in the V-Pit sidewalls, where the growth surface is a {0001} plane and the growth surface of the V-Pit sidewalls is {10-11} planes.

Description

AREA

[0001] Embodiments of the present invention generally relate to III-V semiconductor structures and methods for forming III-V semiconductor structures. BACKGROUND

[0002] III-V semiconductor materials, such as III arsenides (e.g., indium gallium arsenide (InGaAs)), III phosphides (e.g., indium gallium phosphide (InGaP)), and III nitrides (e.g., indium gallium nitride (InGaN)), can be used in a wide variety of electronic device structures. Some examples of electronic devices include switching structures (e.g., transistors, etc.), light-emitting structures (e.g., laser diodes, LEDs, etc.), light-receiving structures (e.g., waveguides, subunits, mixers, photodiodes, solar cells, solar subunits, etc.), and / or microelectromechanical system structures (e.g., accelerometers, pressure sensors, etc.). Such electronic device structures containing III-V semiconductor materials can be used in a wide variety of applications. For example, such device structures are often used to transmit radiation (e.g.,visible light) of one or more different wavelengths. The light emitted by such structures can be used not only for illumination purposes, but also, for example, in media storage and retrieval applications, communication applications, printing applications, spectroscopy applications, the detection of biological substances, and image projection applications.

[0003] In more detail, the GaN layer can initially grow “pseudomorphically” on the underlying substrate, so that (for example, enhanced by atomic forces) a lattice parameter of the GaN layer essentially matches the lattice parameter of the underlying substrate on which it grows.

[0004] The lattice mismatch between the GaN layer and the underlying substrate (e.g., GaN) can induce stresses in the crystal lattice of the GaN layer. This induced stress can generate a strain energy that increases with the thickness of the GaN layer. As the thickness of the InGaN layer increases, the strain energy in the InGaN layer can increase until, at a thickness generally referred to as the "critical thickness," the InGaN layer can no longer grow pseudomorphically and experiences stress release. Such stress release in the InGaN layer can impair its quality. For example, this type of crystal quality impairment in the InGaN layer can lead to the formation of crystalline defects (e.g.,Dislocations), roughening of an InGaN layer surface, and / or the formation of areas with an inhomogeneous material composition. Methods for forming an InGaN layer are described in Miraglia PQ et al.: “Helical-type surface defects in InGaN thin films epitaxially grown on GaN templates at reduced temperatures,” Thin Solid Films, vol. 437, no. 1-2, August 2003, pages 140-149, and Kimura A. et al.: <Supersaturation-dependent step-behavior of InGaN grown by metal organic vapor phase epitaxy=, Journal of Crystal Growth, vol. 229, no. 1-4, 1 Juli 2001, Seiten 53-57, Bord O. V. et al.: <Indium incorporation and droplet formation during InGaN molecular beam epitaxy=, 3rd International Conference on Nitride Semiconductors 1999, vol. 176, no. 1, November 1999, Seiten 297-300, Shiojiri M. et al.: <Structure and formation mechanism of V defects in multiple InGaN / GaN quantum well layers=, Journal of Applied Physics, vol. 99, no. 7, April 2006, Seiten 73505-073505, gezeigt.

[0005] In some cases, these defects can render the device ineffective. For example, the defects may be significant enough to cause a short circuit across a PN connection of light-emitting diodes (LEDs) or laser diodes, preventing the light-emitting device from generating the desired electromagnetic energy.

[0006] There is a need for III-V semiconductor structures and methods for forming such III-V semiconductor structures with reduced defect densities to improve the quality of devices formed with them. In particular, there is a need for III-V semiconductor structures and a method for fabricating them containing indium alloyed with other materials to form an indium-containing layer with reduced defect densities that is relatively thick, has a relatively high indium concentration, or a combination thereof. QUICK OVERVIEW

[0007] This need is met by the method according to claim 1 and the semiconductor structure according to claim 11.

[0008] The different embodiments of the present invention generally relate to III-V semiconductor structures and methods for forming such structures. In some embodiments, the present invention includes, for example, indium gallium nitride (InGaN) structures and methods for forming InGaN structures.

[0009] This overview serves to present a selection of concepts in a simplified form, which are explained in more detail in the following detailed description of some exemplary embodiments of the invention. This overview is neither intended to define key features or essential features of the claimed subject matter, nor is it intended to use them to limit the scope of the claimed subject matter.

[0010] In further embodiments, the present invention comprises a method for growing an indium gallium nitride (InGaN) layer. A group III element precursor at a group III partial pressure is introduced into a processing chamber comprising a substrate with a III-V semiconductor layer formed thereon. A group V element precursor at a group V partial pressure is introduced into the processing chamber, and an indium precursor at an indium partial pressure is introduced into the processing chamber. An indium III-V semiconductor layer with a reduced V-pit density and a thickness greater than a critical thickness is formed by developing an indium supersaturation region in the processing chamber, in which a chamber temperature prevails that is lower than a corresponding chamber temperature for an indium saturation region.

[0011] In further embodiments, the present invention comprises methods for determining processing parameters for an InGaN layer. An indium saturation range is determined for the InGaN layer over a range of indium partial pressures with respect to a combined Group III element pressure and a substantially constant temperature and pressure for a processing chamber. An indium supersaturation range is determined which has a growth surface temperature lower than that of a growth surface temperature for the indium saturation range, wherein the indium supersaturation range is sufficient to develop a reduced V-pit density at a higher indium solid-phase concentration.

[0012] Further aspects, details and alternative combinations of the elements of embodiments of the invention will become clear from the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The present invention will be more fully understood with reference to the following detailed description of exemplary embodiments of the present invention, which are illustrated in the accompanying drawings. Fig. Figure 1 is a simplified cross-sectional drawing of a semiconductor structure with a substrate, a III-V semiconductor layer and an In-III-V semiconductor layer formed on it, and represents the dislocations and V-pits formed therein; Fig. Figure 2 is a simplified isometric drawing representing a V-pit in an In-III-V semiconductor layer; Fig. Figure 3 is a simplified cross-sectional drawing of a substrate with a III-V semiconductor layer and an In-III-V semiconductor layer formed thereon, and represents a reduced density of V-pits formed therein according to at least one embodiment of the invention; Fig. Figure 4 is a graph of an indium solid-phase concentration versus an indium gas-phase concentration to represent an indium saturation range over certain gas-phase indium concentrations; Fig. Figure 5 is a graph of an indium solid-phase concentration versus an indium partial pressure, representing the saturation region. Fig. 4 and shows a supersaturation range according to at least one embodiment of the invention; and Fig. 6A-6C are graphenes exhibiting an indium solid phase concentration, a V-pit density or a V-pit width, all in relation to an indium partial pressure according to at least one embodiment of the invention. DETAILED DESCRIPTION OF FORMATIONS OF THE INVENTION

[0014] The illustrations shown here are not intended to be actual views of a specific material, device or process, but are merely idealized representations used to describe embodiments of the present invention.

[0015] It is understood that any reference to an element using a designation such as "first," "second," and so on, does not restrict the set or order of those elements unless explicitly stated otherwise. Rather, these designations may be used here as a suitable method for distinguishing between two or more elements or examples of an element. Thus, a reference to first and second elements does not mean that only two elements may be used there, or that the first element must precede the second element in some particular way. Moreover, unless otherwise indicated, a set of elements may include at least one element.

[0016] The elements described here may include multiple examples of the same element. These elements may be generally identified by a reference symbol (e.g., 110) and specifically by a letter identifier (e.g., 110A) or a numerical symbol preceded by a hyphen (e.g., 110-1). For the sake of simplicity, reference symbols generally begin with the number of the drawing in which the elements are introduced or most extensively explained. Thus, for example, the reference symbols in a Fig. 1 mostly in the numeric format 1xx and the elements in a Fig. 4 in the numerical format 4xx.

[0017] The following description provides specific details, such as material types and processing conditions, to give a comprehensive explanation of embodiments of the present disclosure and their application. However, the person skilled in the art will understand that the embodiments of the present disclosure can be implemented in practice without using these specific details and in conjunction with conventional manufacturing techniques. Furthermore, the present description does not provide a complete process flow for the manufacture of a semiconductor device or semiconductor system. Only those process steps and structures necessary to understand the embodiments of the present invention are described here in detail.The materials described here can be formed (e.g., deposited or grown) using any suitable technique, but are not limited to, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD, or physical vapor deposition (PVD). Although the materials described and illustrated here can be formed as layers, they are not limited to layers and can be formed in other three-dimensional configurations.

[0018] The terms "horizontal" and "vertical," as used here, define relative positions of elements or structures with respect to a principal face or surface of a semiconductor structure (e.g., wafer, die, substrate, etc.), independent of the orientation of the semiconductor structure, and are orthogonal dimensions translated with respect to the orientation of the described structure. The term "vertical" as used here denotes and encompasses a dimension that is essentially perpendicular to the principal face of a semiconductor structure, and the term "horizontal" denotes a dimension that is essentially parallel to the principal face of the semiconductor structure.

[0019] The term "semiconductor structure" as used here refers to and encompasses any structure used in the fabrication of a semiconductor device. Semiconductor structures include, for example, dies and wafers (e.g., support substrates and device substrates), as well as arrays or composite structures comprising at least two dies and / or wafers that are three-dimensionally integrated. Semiconductor structures also include fully fabricated semiconductor devices as well as intermediate structures formed during the fabrication of semiconductor devices. Semiconductor structures can include conductive materials, semiconductor materials, non-conductive materials (e.g., electrical insulators), and combinations thereof.

[0020] The term "modified semiconductor structure" as used here denotes and encompasses any semiconductor structure that includes at least a partially completed device structure. Modified semiconductor structures are a subset of semiconductor structures, and all modified semiconductor structures are semiconductor structures.

[0021] The term “III-V semiconductor” used here refers to and encompasses any semiconductor material that consists at least predominantly of at least one of the elements from group IIIA of the periodic table (e.g. B, Al, Ga, In and Ti) and at least one of the elements from group VA of the periodic table (e.g. N, P, As, Sb and Bi).

[0022] The terms "indium gallium nitride" and "InGaN" used here refer to alloys of indium nitride (InN) and gallium nitride (GaN) that have a composition of InxGa1-xN, where 0 <x≤1 ist.

[0023] The term “critical thickness” used here refers to the average total thickness of a layer of a semiconductor material at which and above which pseudomorphic growth is interrupted and the layer experiences stress relief.

[0024] The term "growth surface" used here refers to any area of ​​a semiconductor substrate or semiconductor layer on which additional growth of the semiconductor substrate or semiconductor layer can be carried out.

[0025] The term "dislocation" used here refers to an area of ​​a semiconductor material in which there is an inadequate crystal structure for the semiconductor material, which can be characterized by properties such as missing elements within the crystal structure and broken bonds in the crystal structure.

[0026] The term “essentially” used here refers to a result that is complete except for any shortcomings that would be expected according to the state of the art.

[0027] Embodiments of the invention can be applied to a wide range of III-V semiconductor materials. The methods and structures of the embodiments of the invention can be applied to III nitrides, III arsenides, III phosphides, and III antimonides in dual, triple, quadruple, and quintuple forms. Specific applications relate to the growth of group III nitride semiconductors containing indium, such as indium gallium nitride (InGaN). Therefore, for the sake of conciseness and simplicity, and not for the sake of limitation, the following description and drawings reflect common properties of the III nitrides and may focus particularly on InGaN.

[0028] Experiments in III nitride material systems show that InGaN layers deposited heteroepitaxially to thicknesses exceeding a critical threshold can undergo stress relief to mitigate stress in the crystal lattice resulting from crystal misalignment. However, the use of stress relief in the InGaN layers can lead to an increased indium content, resulting in a non-uniform indium concentration profile across the layer thickness. For example, an InGaN layer might exhibit a higher percentage of indium near a growth surface. Such a non-uniform indium composition within the InGaN layer may be undesirable for at least some applications.

[0029] Experiments also show that stress relief in the InGaN layer can lead to roughening of the growth surface. Such surface roughening can be detrimental to the fabrication of semiconductor devices using InGaN layers. Furthermore, experiments have shown that stress relief in the InGaN layer can lead to an increase in the density of defects in the crystalline material. Such defects can include, for example, dislocations and regions of inhomogeneous composition (i.e., phase-separated regions).

[0030] As a non-restrictive example, in the case of InGaN (a III nitride material), InGaN layers can be heteroepitaxially deposited on an underlying substrate that may have a crystal lattice that does not match that of the InGaN layer above. For example, InGaN layers can be deposited on a semiconductor substrate containing gallium nitride (GaN). The GaN may have a relaxed (i.e., essentially stress-free) in-plane lattice parameter of about 0.3189 nm (3.189 Å), and the InGaN layers may have a relaxed in-plane lattice parameter, depending on the corresponding percentage of indium, of about 0.321 nm (3.21 Å) (for 7% indium, i.e., In 0,07 Ga 0,93 N), approximately 0.324 nm (3.24 Å) (for 15% indium, i.e., In 0,15 Ga 0,85 N) and about 0.326 nm (3.26 Å) (for 25% indium, i.e. In 0,25 Ga 0,75 N) have.

[0031] Fig. Figure 1 is a simplified cross-sectional drawing of a semiconductor structure 100 comprising a layer of semiconductor material 130 and an indium III-V semiconductor layer 140 formed on it, and shows dislocations (132 and 142) and V-pits 150 formed therein. The semiconductor structure 100 can be fabricated or otherwise provided such that it comprises a substrate 110. The substrate 110 can comprise a semiconductor material that can be used as a seed layer in the formation of at least one additional layer of semiconductor material on it as part of the fabrication of the semiconductor material layer 130 and the indium III-V semiconductor layer 140, as described in more detail below.

[0032] The layer of semiconductor material 130 can be attached to and supported by the substrate 110. In some embodiments, however, the layer of semiconductor material 130 can comprise a separate main mass layer of a semiconductor material that is not deposited on and supported by a substrate or any other material.

[0033] In some embodiments, the semiconductor material layer 130 can comprise an epitaxial layer of a semiconductor material. By way of example, and without limitation, the semiconductor material layer 130 can comprise an epitaxial layer of III-V semiconductor material. As a non-limiting example, the III-V semiconductor layer 130 can be an epitaxial layer of GaN.

[0034] The substrate 110 can be a material such as aluminum oxide (Al2O3) (e.g. sapphire), zinc oxide (ZnO), silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), lithium gallate (LiGaO2), lithium aluminate (LiAlO2), yttrium aluminum oxide (Y3Al5O12) or magnesium oxide (MgO).

[0035] Optionally, at least one intermediate layer of material (not shown), such as another layer of semiconductor material, or at least one layer of dielectric material, can be arranged between the semiconductor material layer (130) and the substrate (110). Such intermediate layers of material can be used, for example, as a seed layer for forming the semiconductor material layer (130) on it, or as an adhesion layer to ensure that the semiconductor material layer (130) adheres to the substrate (110), as might be the case, for instance, if it is difficult or impossible to form the semiconductor material layer (130) directly on the substrate (110). Furthermore, adhesion of the semiconductor material layer (130) to the substrate (110) may be desirable if the semiconductor material (130) comprises polar crystal orientations.In such embodiments, the adhesion process can be used to change the polarity of the polar semiconductor material.

[0036] The drawings shown here are not to scale, and in fact the III-V semiconductor layer 130 may be relatively thin compared to the substrate 110.

[0037] Dislocations (132B and 132D) can form when the III-V semiconductor layer 130 is formed. As in Fig. As shown in Figure 1, these dislocations can be screw dislocations that continue as the layer is formed with increasing thickness.

[0038] In other words, once a dislocation occurs, it may tend to continue as the layer forms, and would thus appear on a final surface of the III-V semiconductor layer 130 after its formation is complete.

[0039] Any different method known in the art can be used to reduce the dislocation density in the III-V semiconductor layer 130. Such methods include, for example, epitaxial lateral overgrowth (ELO), pseudoepitaxy, in-situ masking techniques, and the like. The semiconductor material 130 layer can be deposited, for example, using a method such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hybrid vapor phase epitaxy (HVPE).

[0040] Fig. Figure 1 also shows an additional III-V semiconductor material 140 above the III-V semiconductor layer 130. As a non-restrictive example, the additional III-V semiconductor material 140 can comprise an InGaN layer 140 or indium in combination with another type of III-V semiconductor material, such as gallium phosphide (GaP) and gallium arsenide (GaAs). An indium semiconductor layer in combination with a III-V semiconductor material can be referred to here as an indium III-V semiconductor material or an indium III-V semiconductor layer 140.

[0041] InGaN alloy layers grow with lattice mismatch on GaN templates (e.g., GaN 130 on sapphire 110). The more indium is present in the InGaN layer 140, the greater the lattice mismatch between the InGaN layer 140 and the GaN template. In general, growth with lattice mismatch (i.e., mismatch between the InGaN layer 140 and the GaN template) is accompanied by stress release if the stress energy stored in the InGaN layer 140 is greater than the stress energy required to cause dislocation nucleation. This growth with lattice mismatch occurs for a lattice arranged in cubic systems but is more complex for materials with a hexagonal lattice structure, such as GaN, InGaN, or AlGaN.

[0042] In hexagonal layers, a plane for easy dislocation sliding may not be present, and thus a much higher strain energy can be stored in the InGaN layer 140 before dislocation nucleation. Upon reaching relaxation, plastic relaxation occurs through a modification of the growth surface. If the growth surface (0001) is hexagonal, pit defects 150 may occur. These pit defects appear as inverted pyramids with an apex near a dislocation (in many cases a screw dislocation) of the GaN subsurface and are often referred to as V-pits 150. As the InGaN layer 140 grows, the inverted pyramid also grows. In thick InGaN layers, the V-pits 150 can become very large.

[0043] In general, thinner InGaN layers 140 can grow with few or no V-pits 150. A thin layer might not reach a thickness (i.e., the critical thickness) at which stress relief would occur because the stress energy in the InGaN layer 140 increases with layer thickness. However, in some applications, thick InGaN layers may be desirable. Consequently, with conventional machining, V-pits 150 are present in the thicker InGaN layers 140, with the V-pits 150 becoming deeper and wider as the InGaN layer 140 becomes thicker.

[0044] In addition to thinner InGaN layers, it is generally possible to form a relatively V-pit-free InGaN layer if the indium concentration is kept relatively low compared to the gallium concentration. However, many applications require thick InGaN layers, high indium concentrations in the InGaN layers, or a combination thereof, all of which can lead to deep and wide V-pits.

[0045] As mentioned, in many cases the V-pits originate from a dislocation, such as screw dislocations, shown by 132B and 132D in the III-V semiconductor layer 130 and by 142A and 142E in the indium III-V semiconductor layer 140. From these dislocations 132, the V-pits (150A, 150B, 150D, and 150E) can form and grow larger than the indium III-V semiconductor layer 140. The V-pits can also originate from a single dislocation, as shown by V-pit 150C.

[0046] These deep V-pits 150 can lead to holes after further processing for layer transfer, i.e., via smart-cut and adhesion processes. The V-pits 150 can also locally alter the iron implantation depth and may lead to splitting defects. Furthermore, re-growth after layer transfer on the pitted InGaN layers results in very deep pits, which are detrimental to the LED device. For example, if a V-pit 150 occurs across the entire InGaN layer 140, it can short-circuit the diode section of the LED device, rendering the device unable to perform its intended function.

[0047] Fig. Figure 2 is a simplified isometric representation showing a non-restrictive example of a V-pit 150 in a non-restrictive exemplary InIII-V semiconductor layer 140. The hexagonal shape of the opening on a growth surface 148 results from the crystal structure growth of InGaN. Furthermore, the V-pit sidewalls 152 extend upwards from a vertex 155, where the V-pit 150 began to form as a result of crystal structure growth, such that the V-pit 150 essentially has a fixed section of width 156 to depth 154. Thus, the depth 154 of the V-pit 150 can be accurately estimated based on the width 156 of the V-pit.

[0048] Embodiments of the present invention can reduce the number and size, or a combination thereof, of the V-pits 150 that are formed when an indium III semiconductor layer 130 is formed on a III-V semiconductor layer 130. This reduction of V-pits 150 is also referred to herein as "reduced V-pit density" and "reduced density of V-pits". Thus, a reduced V-pit density can refer to fewer V-pits in a given surface area, smaller V-pits in a given surface area, or a combination of fewer V-pits and smaller V-pits in a given surface area.

[0049] Although this is not considered a specific theory for V-pit formation, Shiojiri (M. Shiojiri, CCJT Hsu, JR Yang, H. Saijo, J. Appl. Phys. 99, 073505 (2006)) suggests that the growth rate on {10-11} levels, which are the V-pit sidewalls 152, is different compared to the {0001} basal level of the growth surface 148. Furthermore, the {10-11} levels of the V-pit sidewalls 152 may have a higher adhesion coefficient for indium than the {0001} basal level of the growth surface 148.Accordingly, according to the present invention, the V-pit density can be reduced by increasing a percentage of indium in the gas phase during processing, thereby saturating the indium concentration on the {0001} basal plane of the growth surface 148 of the formed solid material, while allowing a higher concentration of indium on the {10-11} planes of the V-pit sidewalls 152 to support the growth of InGaN on the V-pit sidewalls.

[0050] Fig. Figure 3 is a simplified cross-sectional drawing of a semiconductor substrate 110 with a layer of semiconductor material 130 and an indium III-V semiconductor layer 140 formed thereon, and shows a reduced density of V-pits formed therein, according to at least one embodiment of the present invention. As in Fig. 1. The semiconductor structure 100 can be manufactured or otherwise provided such that it comprises a substrate 110. The substrate 110, the layer of semiconductor material 130, and the indium III-V semiconductor layer 140 are similar to those described in Fig. 1 are described.

[0051] Fig. Figure 3, however, shows conventional V-pits 152A, 152B and 152C (i.e., V-pits that can form when conventional machining is applied). Fig. Figure 3 also shows smaller V-pits (158A, 158B, and 158C) that produce a reduced density of V-pits, according to at least one embodiment of the invention. The reduced V-pits 158A and 158C show that the V-pits originating from the screw dislocations 132B and 132C, respectively, grew at a slower rate compared to the V-pits 152A and 152C that form during conventional machining. The reduced V-pit 158B shows a smaller V-pit compared to the V-pit 152B that can form directly from a dislocation during conventional machining.

[0052] Fig. Figure 4 is a graph of the indium solid-phase concentration versus the indium gas-phase concentration to show an indium saturation range over certain gas-phase indium concentrations. Fig. Method 4 can be developed from an experiment in a processing chamber with a relatively constant temperature, pressure, total gas flow, and wafer rotation rate. At a specific gallium flow rate, an indium flow rate can be varied to change the percentage of indium in the gas phase, as shown on the x-axis. The percentage of indium in the solid phase, which forms in the InGaN layer, is shown on the y-axis as a function of the percentage of indium in the gas phase.

[0053] In some embodiments, an indium precursor for the formation of the InGaN layer may, for example, contain trimethylindium (TMI), triethylindium (TEI), or a combination thereof. In some embodiments, a gallium precursor for the formation of the InGaN layer may, for example, contain triethylgallium (TEG) or another suitable material. In some embodiments, a nitrogen precursor for the formation of the InGaN layer may, for example, contain ammonia (NH3) or another suitable material.

[0054] Thus, for one embodiment: % Indium in the gas phase = 100*(TMI current / (TMI current+TEG current))

[0055] Initially, as the percentage of indium in the gas phase increases, the percentage of indium in the solid phase increases proportionally, as shown by segment 410A. However, an inflection point 410B is reached where a further increase in the percentage of indium in the gas phase does not lead to an increase in the percentage of indium in the solid phase, as shown by segment 410C. This range of indium concentration in the gas phase, where there is no proportional increase in the indium concentration in the solid phase, is referred to here as an indium saturation region.

[0056] Fig. Figure 5 is a graph of an indium solid-phase concentration versus an indium partial pressure, representing the saturation region of Fig. 4 and supersaturation ranges according to at least one embodiment of the invention.

[0057] As the expert will recognize, the gas flow rate in a machining chamber refers to a partial pressure resulting from the different gases present in the machining chamber. Accordingly, the indium concentration in the gas phase can also be represented as follows: % Indium in the gas phase = 100*(PTMI(PTMI+PTEG))

[0058] In other words, one can easily establish a relationship between an indium partial pressure (P TMI ) with respect to an entire group III partial pressure (P TMI + P TEG ) determine which is a combination of the indium partial pressure and a gallium partial pressure. For clarity of explanation, most of the description refers to partial pressures; however, the person skilled in the art will understand that the descriptions can also be applied to the related flow rates.

[0059] Of course, other inert gases (e.g., nitrogen) and other reactants, such as dopants, can be present in the reaction chamber. As non-restrictive examples, an N-doper can contain a silicon-containing vapor, such as silane (SiH4), and a P-doper can contain a magnesium-containing vapor, such as bis(cyclopentadienyl)magnesium (Cp2Mg).

[0060] In Fig. Figure 5 shows the y-axis as a percentage of indium in the solid phase (also referred to here as indium concentration in the solid phase) as a function of the x-axis, which shows an indium partial pressure (also referred to here as indium concentration in the gas phase).

[0061] Segments 510A and 510C show the proportional increase (510A) of the indium concentration in the solid phase with respect to the indium concentration in the gas phase, followed by the saturation region, where the indium concentration remains relatively constant with increasing indium concentration in the gas phase (510B).

[0062] Line 520 represents an indium supersaturation region, where a higher concentration of indium can be obtained in the solid-state layer compared to the saturation region. Thus, the term "indium supersaturation region" used here refers to a state in the processing chamber that is configured to develop a higher concentration of indium in the formed solid-state semiconductor layer compared to what would be formed in the solid-state semiconductor layer using the saturation region described above.

[0063] As a non-restrictive example, a saturation region can be defined as a given chamber pressure, growth surface temperature, III-element precursor partial pressure, V-element precursor partial pressure, and indium precursor partial pressure. A higher concentration or partial pressure of the indium precursor compared to the saturation region can develop a supersaturation region, resulting in a higher concentration of indium in the produced semiconductor layer.

[0064] As another non-restrictive example, in a saturation region defined by a given growth surface temperature, chamber pressure, wafer spin rate, and partial pressure combination of an indium precursor, a group III element precursor, and a group V element precursor, a decrease in the growth surface temperature can create a supersaturation region. This leads to a solid-state growth condition that develops a higher indium percentage in the resulting semiconductor layer compared to what would be achieved in the saturation region. Similarly, an increase in chamber pressure or a change in wafer spin rate while maintaining the temperature at the saturation region temperature can develop an indium supersaturation region.

[0065] On line 520, chamber parameters such as chamber pressure and wafer rotation rate can be kept relatively constant, and the temperature reduced to develop the indium supersaturation region. The temperature can be defined as either the chamber temperature or the growth surface temperature. As a non-restrictive example, the chamber temperature for segments 510A and 510B is approximately 839°C, and the chamber temperature for line 520 is approximately 811°C. Furthermore, the relative concentration between group III precursors (e.g., an indium precursor combined with a gallium precursor) and a group III precursor is kept relatively constant at a ratio of V / III = 3560.In other words, in one embodiment, as line 520 moves from left to right, the partial pressure for TEG can remain relatively constant, and as the partial pressure for TMI increases, the partial pressure for ammonia increases proportionally to maintain the V / III ratio at approximately 3560.

[0066] Line 530 can be developed as a non-restrictive example with a chamber temperature of about 811°C and a group V partial pressure (e.g., a partial pressure of ammonia) that is kept essentially constant with respect to the group III partial pressure and the changing indium partial pressure. In other words, in one embodiment, as line 530 moves from left to right, the partial pressures for TEG and ammonia can remain relatively constant, while the partial pressure for TMI increases.

[0067] More detailed and with reference to Fig. 3 and Fig. 5. The current of the indium precursor to the InGaN layer 140 can influence the incoming flux of indium species available for interaction on the growth surface 148 and the V-pit sidewalls 152. The indium can be highly volatile. At the surface, TMI decomposes and releases the metal (e.g., indium), which can penetrate the solid layer or volatilize as vapor. The higher the temperature, the greater the probability that the metal will volatilize rather than penetrate.

[0068] Therefore, there is a trade-off between the penetration of indium into the InGaN layer 140 and the desorption (also referred to here as desorption flux) of indium from the InGaN layer 140. Lowering the temperature or increasing the pressure can promote penetration to increase the solid-phase concentration of indium in the InGaN layer 140. While a saturation range can be reached for the growth surface 148, the V-pit sidewalls 152, with their different growth facet, may be more accessible for higher growth rates than the growth surface 148, potentially leading to a reduced V-pit density.

[0069] Fig. 6A-6C are graphenes exhibiting an indium solid phase concentration, a V-pit density or a V-pit width, all relative to an indium partial pressure, according to at least one embodiment of the invention.

[0070] As demonstrated by line 610 in Fig. As can be seen in Figure 6A, as the indium concentration in the gas phase increases, the indium concentration in the solid phase also increases up to an indium concentration of approximately 94%. At this point, increases in the gas phase concentration lead to lower solid phase concentrations.

[0071] As demonstrated by line 620 in Fig. As can be seen in Figure 6b, the V-pit density also increases with increasing indium concentration in the gas phase, up to an indium concentration of approximately 94%. At this point, increases in gas phase concentration lead to lower solid phase concentrations.

[0072] What's happening with line 630 in Fig. As shown in Figure 6C, however, the V-pit width decreases with increasing indium concentration in the gas phase. The points in Fig.Figure 6C shows an average V-pit width, while the upper bars 632 and the lower bars 634 show the three-sigma distribution points for the V-pit width. Consequently, with an increase in the indium partial pressure, a decreased V-pit density can be observed either by a lower number of V-pits per given area, smaller V-pits, or a combination of the number of V-pits per given area and the size of these V-pits.

[0073] Pit width is a preferred method for measuring V-pits using atomic force microscopy (AFM), as the AFM tip might not be sharp enough to penetrate the entire depth of the V-pit to accurately measure the depth. Pit depth can be calculated from the pit width using crystallographic considerations (e.g., the angle between the (10-11) and (0001) planes) (J.E. Northrup, LT. Romano, J. Neugebauer, Appl. Phys. Lett. 74(6), 2319 (1999).

[0074] It is also noted that very thin InGaN layers may have V-pits, but these cannot be detected because their widths may be below the resolution of the AFM.

[0075] As previously mentioned, numerous applications require thick InGaN layers, high indium concentrations within the InGaN layers, or a combination thereof, all of which can lead to deep, wide V-pits. Some embodiments of the present invention can produce reduced V-pit densities for solid-state indium concentrations in the range of approximately 6% to 9%. Furthermore, in some embodiments, the reduced V-pit densities can be achieved for relatively thick InGaN layers of approximately 150 nanometers and possibly up to approximately 200 nanometers.

Claims

[1] Method for forming a semiconductor structure, comprising: Formation of a III-V semiconductor layer on a substrate; Forming an indium III-V semiconductor layer with a reduced V-pit density on a growth surface of the III-V semiconductor layer with an indium solid-phase concentration above an indium saturation region by combining at least one indium precursor, a group III element precursor different from the indium precursor, and a group V element precursor in a processing chamber equipped with an indium supersaturation region comprising a chamber temperature lower than a chamber temperature corresponding to the indium saturation region; Increasing the concentration of indium in the V-Pit sidewalls, where the growth surface is a {0001} plane and the growth surface of the V-Pit sidewalls is {10-11} planes. [2] The method of claim 1, further comprising forming the indium III-V semiconductor layer with a thickness greater than a critical thickness. [3] Method according to claim 1, wherein the formation of the indium III V semiconductor layer further comprises reducing a desorption flux of indium from V-pit sidewalls of the indium III V semiconductor layer relative to a desorption flux of indium from the growth area of ​​the indium III V semiconductor layer, wherein reducing a desorption flux of indium from V-pit sidewalls of the indium III V semiconductor layer comprises reducing the chamber temperature. [4] Method according to claim 1, wherein the formation of the indium III V semiconductor layer further comprises increasing the uptake of indium in V-pit sidewalls relative to the uptake of indium in the growth surface of the indium III V semiconductor layer, wherein increasing the uptake of indium in the V-pit sidewalls comprises decreasing the chamber temperature and / or increasing the chamber pressure and / or increasing the indium partial pressure. [5] Method according to claim 1, wherein the formation of the indium III V semiconductor layer further comprises increasing an indium partial pressure in the processing chamber relative to an overall group III partial pressure. [6] Method according to claim 1, wherein the formation of the indium III V semiconductor layer comprises the formation of an indium gallium nitride (InGaN) layer. [7] The method of claim 1, further comprising selecting the group V element precursor such that it contains ammonia. [8] The method of claim 1, further comprising selecting the indium precursor such that it contains trimethylindium. [9] The method of claim 1, further comprising selecting the group III element precursor such that it contains triethylgallium. [10] Method according to claim 1, wherein the formation of the indium III-V semiconductor layer further comprises increasing the indium partial pressure in the processing chamber relative to an overall group III partial pressure. [11] Semiconductor structure obtained by the method according to any of the preceding claims, wherein the structure comprises: a substrate; a III-V semiconductor layer with a reduced V-pit density formed on the substrate; an InGaN layer with an indium solid-phase concentration that is greater than an indium solid-phase concentration from an indium saturation region; V-pits with sidewalls whose growth surfaces are {10-11} planes, where the growth surface of the InGaN layer is a {0001} basal plane. [12] Semiconductor structure according to claim 11, wherein the InGaN layer further has a thickness greater than a critical thickness.

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