Amplifier with programmable gain with common-mode sampling and method for controlling a chopper amplifier

Abstract

Amplifier with programmable gain (“PGA”) (100), comprising: a differential amplifier (A1) with one input pair (102, 104) and one output pair (106, 108), a pair of input capacitors (C IN , C IP ) with output terminals, each connected to inputs (102, 104) of the differential amplifier (A1), a pair of feedback capacitors (C FN , C FP ), which are each connected between the outputs of the differential amplifier (A1) and corresponding inputs of the differential amplifier (A1), a first chopper circuit (110) which is configured to connect the input capacitors (C IN , C IP ) to connect to the corresponding input terminals of the PGA (100), a second chopper circuit (120) configured to connect the output terminals (106, 108) of the differential amplifier (A1) to corresponding output terminals (VON, VOP) of the PGA (100), a first voltage source (V ICM ), which is configured to be connected to input terminals (102, 104) of the differential amplifier (A1) via corresponding sample switches, the corresponding sample switches being configured to close in response to a first control signal (CO) and the first voltage source (V ICM ) has a voltage that is set to a common-mode voltage of the differential amplifier (A1), and wherein the amplifier (A1) provides a second voltage source (V CMA ) which is configured with input terminals of the input capacitors (C IN , C IP) to be connected via appropriate scanning switches, the appropriate scanning switches being configured to close in response to a second control signal (COB) and the second voltage source (V CMA ) has a voltage that is set to a common-mode signal of signals to be input into the PGA (100).

Description

CROSS-REFERENCE TO A RELATED REGISTRATION

[0001] This application claims priority, granted by the preliminary application with serial number 61 / 642.223, filed on 3 May 2012 entitled “Capacitive PGA”. BACKGROUND

[0002] The present invention relates to programmable gain amplifiers (“PGAs”) and a method for controlling a chopper amplifier. Low-noise, energy-efficient, and high-precision PGAs can be implemented using a chopper differential amplifier with capacitors as feedback elements. This type of PGA is described in US Patent US 7,795,960 B2, which is attributed to Analog Devices, Inc., the applicant of the present invention. Capacitors do not transmit DC voltage signals; therefore, an input chopper circuit converts an input DC voltage signal into a square wave. The square wave is amplified by the amplifier with capacitive feedback. An output chopper circuit then demodulates the amplified square wave back into an amplified DC voltage signal.Low noise can be achieved because capacitors are noise-free, making the differential amplifier the only noise source in the PGA. The gain is precisely defined by the ratio of the capacitors, which is stable and can be well controlled in integrated circuit (IC) manufacturing processes. Programmable gain can be achieved by changing the capacitor values, for example, by adding or removing capacitors from a capacitor bank into the amplifier circuit.

[0003] US 7,795,960 B2 relates to a low-power, low-noise amplifier system comprising at least one amplifier with a first and a second differential input terminal, a first and a second differential output terminal providing a differential output; a first and a second input capacitor connected to the first and second differential input terminals of the amplifier; a first and a second feedback circuit providing a first and second differential output, respectively.a second feedback capacitor connected to the differential input and output terminals of the amplifier; an input chopper circuit for receiving a low-frequency differential input and selectively, alternately swapping these low-frequency differential inputs through the input capacitors to the differential input terminals of the amplifier; an output chopper switch for receiving and selectively, alternately swapping the amplifier differential outputs synchronously with the input chopper circuit; and a low-pass filter responding to the swapped differential outputs to provide low-noise, low-power amplification of the low-frequency differential inputs.

[0004] However, capacitive PGAs do not typically define the common-mode voltage applied to the inputs of the differential amplifier, which should be matched to the common-mode of the amplifier itself. Setting this voltage necessitates additional circuitry, which usually involves very large resistors and is therefore inherently slow. Accordingly, the inventor sees a need in the field of the invention for a PGA architecture that defines a common-mode voltage at a differential amplifier with a faster response than previous attempts. In light of this prior art, the object of the present invention is to provide an amplifier with programmable gain and a method for controlling a chopper amplifier, each of which is suitable for enriching the prior art.

[0005] The problem is solved by the features of the independent claims. The dependent claims each contain optional further developments of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 represents a PGA according to an embodiment of the present invention. Fig. 2 is a timing diagram that shows the operation of the PGAs from Fig. 1, Fig. 8 and Fig. 9 according to an embodiment of the present invention. Fig. Figure 3 represents a PGA according to another embodiment of the present invention. Fig. 4 is a timing diagram that shows the operation of the PGA from Fig. 3 according to an embodiment of the present invention. Fig. Figure 5 represents a PGA according to a further embodiment of the present invention. Fig. 6 is a timing diagram that shows the operation of the PGA from Fig. 5 according to an embodiment of the present invention. Fig. 7 is a timing diagram that shows the operation of the PGA from Fig. 5 according to another embodiment of the present invention. Fig. Figure 8 represents a PGA according to another embodiment of the present invention. Fig. Figure 9 represents a PGA according to a further embodiment of the present invention. Fig. Figure 10 represents a PGA according to another embodiment of the present invention. Fig. 11 is a timing diagram that describes the operation of the PGA. Fig. 10 and Fig. 14 according to an embodiment of the present invention. Fig. Figure 12 represents a PGA according to a further embodiment of the present invention. Fig. 13 is a timing diagram that describes the operation of the PGA. Fig. 12 according to an embodiment of the present invention. Fig. Figure 14 represents a PGA according to another embodiment of the present invention. DETAILED DESCRIPTION

[0006] Embodiments of the present invention provide PGA architectures with the features of claims 1 and 7. Figs. 1 and 2

[0007] Fig. Figure 1 represents a PGA 100 according to an embodiment of the present invention. The PGA can include a differential amplifier A1, a pair of variable input capacitors C IN , C IP , a pair of variable feedback capacitors C FN , C FP and comprise two chopper circuits 110, 120. A first chopper circuit 110 can be provided at an input of the PGA 100 and a second chopper circuit 120 can be provided at an output of the PGA 100.

[0008] The first chopper circuit 110 can have a pair of differential input terminals V IN , V IP of the PGA 100 to the first terminals of the input capacitors C IN , C IP (for simplicity, called "input terminals"). Output terminals of the input capacitors C IN , C IP The (output terminals) can be connected to input terminals 102 and 104 of amplifier A1. The feedback capacitors C FN , C FPThe outputs 106 and 108 of amplifier A1 can each be coupled in a feedback configuration with the corresponding inputs 102 and 104 of amplifier A1. The amplifier outputs 106 and 108 can be coupled with inputs of the second chopper circuit 120. Outputs of the second chopper circuit 120 can be coupled with output terminals VON and VOP of the PGA 100 and, if desired, with load devices and / or filter devices (shown as "LOAD").

[0009] The chopper circuits 110 and 120 can configure the direction of the signal flow around amplifier A1. Each chopper circuit 110 and 120 can comprise an array of switches that selectively connects the inputs of the respective circuits to their outputs. In particular, the first chopper circuit 110 can comprise two pairs of switches, each controlled by a control signal CI and CIB, respectively. One of the CI switches can connect an input terminal of C. IP -capacitor with the V IP -connect the other CI switch and the other CI switch can have an input port of C IN with the V IN Connect the -terminal. One of the CIB switches can be the input terminal of the C. IP -capacitor with the V IN -connect the other CIB switch and the input port of C can be connected. IN with the V IPConnect the CI and CIB control signals. The CI and CIB control signals can operate in a complementary manner during the chopper phases of the PGA 100's operation (described below).

[0010] Similarly, the second chopper circuit 120 can comprise two pairs of switches, each controlled by a control signal CO and COB, respectively. One of the CO switches can connect an output terminal 106 of amplifier A1 to the VON terminal, and the other CO switch can connect an output terminal 108 of amplifier A1 to the VOP terminal. One of the COB switches can connect output terminal 106 to the VOP terminal, and the other COB switch can connect output terminal 108 to the VON terminal. The CO and COB control signals can operate in a complementary manner during the chopper phases of operation of the PGA 100 (described below).

[0011] The capacitors C IP , C IN , C FN and C FPcan be variable capacitors. That means that each capacitor C IP , C IN , C FN and C FP This may include an arrangement of switching capacitor devices (not shown). During operation, the input capacitors C IP , C IN be set so that they have the same capacitance and the feedback capacitors C FN , C FP They can be configured to have the same capacity. A ratio of capacities between the C IP - / C IN -Input capacitors and the C FN - / C FP However, the feedback capacitors can be controlled by control signals (not shown) to provide programmable gain for the PGA System 100.

[0012] The PGA 100 can handle a voltage source pair V ICM , V CMA , which are connected to the input capacitors C IN , C IPare coupled via corresponding scanning switches. The voltage V ICM can be set to a common-mode voltage of differential signals, which in the PGA 100 via the V IP -, V IN -Connections are entered. The V ICM -The voltage source can be connected to the input terminals of the input capacitors b C IN , C IP They are coupled via a pair of switches that close in response to an initial control signal SMPL. The voltage V CMA can be set to a common-mode voltage of amplifier A1. The V CMA The voltage source can be connected to the input terminals 102, 104 of amplifier A1 (also to the output terminals of the input capacitors C). IP , C IN ), be coupled via second switches that close in response to a second control signal SMP.

[0013] The PGA 100 can include a control unit 150 that generates control signals SMP, SMPL, CI, CIB, CO and COB for the PGA 100 in response to an external time signal, such as a clock signal CLK.

[0014] Fig. Figure 2 is a timing diagram of the operation of the PGA 100 according to an embodiment of the present invention. As shown, the operation of the PGA 100 can proceed over several phases, called "CMS", "CHP1", "CHP2", and an optional phase called "DCMS". During the CMS phase, a common-mode sampling phase, the PGA 100 can measure the common-mode voltages V ICM and V CMA capture. The SMP and SMPL switches can be closed, thereby limiting the input terminals of the input capacitors C. IN , C IP with V ICM and the output terminals of capacitors C IP , C IN with V CMAcan be connected. The switches of the chopper circuits 110, 120 can be kept open during the CMS phase, which protects the capacitors C. IN , C IP , C FN and C FP effectively isolates from other components of the PGA 100. Thus, each capacitor C IN , C IP to store a voltage that represents a difference between the common-mode voltage of the two domains (V CIN =V CIP =V ICM -V CMA ). The sampling process can define the amplifier input common mode for amplifier A1 and keep the common-mode voltage constant at amplifier inputs 102, 104 during other operating phases.

[0015] During the first chopper phase (CHP1), the chopper circuits 110 and 120 can be activated and the sampling switches SMP and SMPL can be opened. The common-mode voltage sources V ICM , V CMA can be from the input capacitors C IN , CIP The sensor switches SMP and SMPL are separated. The CI control signal can cause its associated switches to close, thus preventing the input signal from reaching V. IP -Input with the input capacitor C IP and the input signal at V IN -Input with the input capacitor C IN is connected. The CO control signal can also cause the switches assigned to it to be closed, thereby closing the feedback capacitor C. FN with the output terminal VON and the feedback capacitor C FP can be connected to the output terminal VOP. Configured in this way, the PGA 100 can receive a differential input signal, which can be used as input voltages V. IP , V IN is based on a ratio of the input capacitors C IP / C IN to the amplifier feedback capacitors C FN / C FP strengthen.

[0016] The ones at the V IP -, VIN Differential signals input to terminals can be adjusted around the common-mode voltage V ICM of the upstream circuit of the PGA (not shown). The application of the differential signals to the input capacitors C IP , C IN This can cause the application of reverse voltages to inputs 102 and 104 of amplifier A1, but with a common-mode voltage V CMA of amplifier A1 due to the input capacitors C IP , C IN Sampled voltages during the CMS phase.

[0017] During the second chopper phase (CHP2), the configuration of the chopper circuits 110, 120 can be inverted. The sampling switches SMP, SMPL can remain open, thus limiting the common-mode voltage sources V ICM , V CMA from the input capacitors C IN , C IPThey remain disconnected. The CIB control signal can cause the switches assigned to it to be closed, thus preventing the signal from reaching input V. IP to the input capacitor C IN and the signal at input V IN to the input capacitor C IP is connected. In this way, the chopper circuit 110 inverts the distribution of the PGA input signals to the input terminals 102, 104 of the amplifier A1 when the PGA 100 transitions from the CHP1 phase to the CHP2 phase and inverts the distribution again when the PGA 100 transitions from the CHP2 phase to the CHP1 phase.

[0018] The COB control signal can also cause its associated switches to close, allowing amplifier output terminal 106 to be connected to output terminal VOP and amplifier output terminal 108 to output terminal VON. Similar to the first chopper circuit 110, the second chopper circuit 120 can invert the voltage distributions from output terminals 106 and 108 of amplifier A1 to output terminals VON and VOP when PGA 100 transitions from the CHP1 phase to the CHP2 phase, and invert them again when PGA 100 transitions from the CHP2 phase to the CHP1 phase. Nevertheless, PGA 100 amplifies a differential input signal, which is represented as input voltages V. IP , V IN is based on a ratio of the input capacitors C IP / C IN to the amplifier feedback capacitors C FN / C FP .

[0019] As in the CHP1 phase, the input voltages V can be changed during the CHP2 phase. IP , V IN to the common-mode voltage V ICM of the upstream circuit of the PGA (not shown) vary. The application of V IP , V IN Input voltages to the input capacitors C IN , C IP This can cause opposing voltages to be applied to the inputs of amplifier A1, but shifted relative to the common-mode voltage V. CMA of amplifier A1 due to the voltages applied to the input capacitors C IN , C IP during the CMS phase. Thus, the PGA 100 can perform a sampling operation during the CMS phase, which defines a common-mode signal for input signals applied to amplifier A1 during operating phases CHP1 and CHP2, which is adapted to the common-mode signal of the amplifier.

[0020] In one embodiment, the control signals CO and COB for the second chopper circuit 120 can have a shorter duration than the control signals CI and CIB input to the first chopper circuit 110. This can cause the output terminals VON, VOP to be disconnected from the output terminals of amplifier A1, since the chopper circuit switches between the CHP1 and CHP2 phases, thereby reducing any interference signals that might otherwise occur if the amplifier outputs were connected to the output terminals VON, VOP for the entire duration of the CI, CIB signals.

[0021] In some cases, the CHP2 phase can immediately follow the CHP1 phase. However, if necessary, a "Probe Common Mode Sample" (DCMS) phase can be inserted between successive chopper phases. The DCMS phase can provide symmetry in the amplifier output signals during operation. During the DCMS phase, the SMPL signal can cause the input-side plates of the input capacitors C IP and C IN with V ICM be connected. Closing the SMPL switches can cause the amplifier output to go close to zero (neglecting the A1 offset), which can result in the output voltages at the beginning of the CHP2 phase having the same input conditions as at the beginning of the CHP1 phase. As in Fig. As illustrated in point 2, the SMP signal can keep its associated switches open, those connected to V. CMAare connected. Under such circumstances, no sampling activity occurs in the DCMS phase, and therefore no additional kT / C noise is introduced into the PGA. At the end of phase CHP2, a new CMS phase can follow, and the entire timing sequence can be repeated.

[0022] In another embodiment, a single CMS sampling phase can be followed by several chopper phases (CHP1, CHP2). Common-mode sampling phases (DCMS) can be inserted between successive chopper phases CHP2, CHP1 for improved symmetry in the output signal. However, the common-mode response of circuit 100 is fastest when the common-mode signal is re-sampled after the first CHP2 phase. Furthermore, kT / C noise acquired during the CMS phase is upconverted to the chopper frequency, which can be filtered out by post-processing circuitry (not shown). Figs. 3 and 4

[0023] Fig. Figure 3 illustrates a PGA 300 according to another embodiment of the present invention. This embodiment avoids the use of a common-mode input voltage source (V1). ICM ) as in Fig. 1. In this embodiment, the PGA 300 can include a differential amplifier A1, a pair of variable input capacitors C IN , C IP , a pair of variable feedback capacitors C FN , C FP and comprise two chopper circuits 310, 320. A first chopper circuit 310 can be provided at an input to the PGA 300 and a second chopper circuit 320 can be provided at an output of the PGA 300.

[0024] The capacitors C IP , C IN , C FN and C FP can be variable capacitors. That is, each capacitor C IP , C IN , C FN and C FPThe PGA 300 may include an arrangement of capacitor devices with connecting switches (not shown) that selectively include or exclude capacitors from the arrangement. During operation, the input capacitors C IP , C IN so that they have the same capacitance, and the feedback capacitors C FN , C FP They can be set so that they have the same capacitance. A ratio of capacitances between the input capacitors C IP / C IN and the feedback capacitors C FN / C FP can be controlled to obtain the programmable gain of the PGA system 300.

[0025] The PGA 300 can supply a voltage source V CMA include those connected to the input terminals 302, 304 of amplifier A1 and, via corresponding sampling switches, also to the input capacitors C IN , C IPis coupled. The voltage V CMA can be set to a common-mode voltage of amplifier A1. The sampling switches can close in response to a control signal SMP.

[0026] In the illustrated embodiment, the input capacitors C IN , C IP as pairs of subcapacitors C IN0 , C IN1 , C IP0 and C IP1 be provided. The first chopper circuit 310 can include four pairs of switches to control the input terminals V IN , V IP with the input terminals of the C IN0 -, C IN1 -, C IP0 -and C IP1 -to connect subcapacitors. Within a first input capacitor C IP Can an input connection of subcapacitor C IP0 with the V IP -, V INThe terminals are connected via a corresponding pair of switches, each controlled by complementary control signals CI0 and CIB0. One input terminal of the counterpart subcapacitor C IP1 within C IP can with the V IP -, V IN The output terminals are connected via a second pair of switches, each controlled by a second set of complementary control signals CI1 and CIB1. Output terminals of the C IP0 -, C IP1 Subcapacitors can be coupled to an inverting input 302 of amplifier A1. Within the second input capacitor C IN can an input terminal of the subcapacitor C IN0 with the V IN -, V IP The terminals are connected via a corresponding pair of switches, each controlled by the control signals CI0 and CIB0. One input terminal of the counterpart subcapacitor C IN1 within C IN can with the VIN -, V IP -terminals are connected via a second pair of switches, which are controlled by a second set of complementary control signals C11, CIB1. Output terminals of C IN0 -, C IN1 -Subcapacitors can be coupled to a non-inverting input 304 of amplifier A1.

[0027] The feedback capacitors C FN , C FP Each of the outputs 306 and 308 of amplifier A1 can be coupled in a feedback configuration to its inputs 302 and 304. Amplifier outputs 306 and 308 can be coupled to inputs of the second chopper circuit 320. The outputs of the second chopper circuit 320 can be coupled to the output terminals VON and VOP of PGA 300 and, optionally, to load devices and / or filter devices (LOAD).

[0028] The second chopper circuit 320 can have two pairs of switches controlled by complementary control signals CO and COB. Switches controlled by the CO signal can connect a first output 306 of amplifier A1 to output terminal VON and a second output 308 of amplifier A1 to output terminal VOP. Switches controlled by the COB signal can connect the first output 306 of amplifier A1 to output terminal VOP and the second output 308 of amplifier A1 to output terminal VON.

[0029] The PGA 300 can include a control unit 350 that generates control signals SMP, CI0, CIB0, CI1, CIB1, CO and COB for the PGA 300 in response to an external time signal, such as a clock signal CLK.

[0030] Fig. Figure 4 is a timing diagram illustrating the operation of the PGA 300 according to an embodiment of the present invention. As shown, the operation of the PGA 300 can extend over several operating phases: CMS, CHP1, CHP2, and the optional DCMS phase. During the CMS phase, the SMP, CI0, and CIB1 signals of the PGA 300 can cause their corresponding switches to close. The SMP switches cause the output terminals of the C IP - and C IN -capacitors (including subcapacitors C) IP0 , C IP1 , C IN0 and C IN1 ) with the amplifier common-mode voltage V CMA be connected. The CI0 switches can cause the input terminals of the C to be connected. IP0 - and C IN0 -Subcapacitors with V IP or V IN be connected. The CIB1 switches can cause the C IP1 - and C IN1 -capacitors with V IN or V IPcan be connected. Thus, the C IP0 - and C IN1 -Subcapacitors a voltage V IP -V CMA capture during the CMS phase; and the C IP1 - and C IN0 -Subcapacitors can impede a voltage V IN -V CMA during the CMS phase. The CO and COB control signals can cause the switches in the second chopper circuit to remain open during the CMS phase.

[0031] Thus, the PGA 300 can perform a sampling operation during the CMS phase, which defines a common-mode signal for input signals applied to amplifier A1 during the operating phases CHP1, CHP2, which is adapted to the common-mode signal of the amplifier.

[0032] During the first chopper phase (CHP1), the CI0 and CI1 signals can cause their associated switches to close. The CIB0 and CIB1 signals can cause the switches to open. These control signals cause the input terminals of the C IP -capacitor (including both subcapacitors C) IP0 , C IP1 ) with the V IP -Input port and the input ports of C IN -capacitor (including both subcapacitors C) IN0 , C IN1 ) with the V IN -terminal connected. From a common-mode point of view, the charge redistribution between the C IP -Subcapacitors C IP0 , C IP1 cause a voltage to build up at C IP -capacitor as ½ (V IP -V IN )-V CMA developed, which V ICM -V CMA This corresponds to... Similarly, a charge redistribution between the C IN-Subcapacitors C IN0 , C IN1 cause a voltage to build up at C IN -capacitor as V ICM -V CMA developed. Thus, during the CHP1 phase, an input signal can be present at amplifier A1, which represents a difference between the V IP - and V IN -signals, but to the common-mode voltage V CMA is shifted towards the amplifier.

[0033] During the CHP1 phase, the CO signal can cause its associated switches to close, connecting amplifier output terminal 306 to the VON terminal and amplifier output terminal 308 to the VOP terminal. The PGA 300 can therefore generate a differential output voltage across the capacitances between the C IP - / C IN -capacitors and the C FN - / C FP -capacitors is defined.

[0034] During the second chopper phase (CHP2), the CIB1 and CIB0 signals can cause their associated switches to be closed. The CI0 and CI1 signals can cause their associated switches to remain open. These control signals can cause the input terminals of the C IP -capacitor (including both subcapacitors C) IP0 , C IP1 ) with the V IN -Input port and the input ports of C IN -capacitor (including both subcapacitors C) IN0 , C IN1 ) with the V IP -terminal is connected. From a common-mode point of view, as in the CHP1 phase, the charge redistribution between the C IP -Subcapacitors C IP0 , C IP1 cause a voltage to build up at C IP -capacitor as ½ (V IP -V IN )-V CMA developed, which V ICM -V CMAThis corresponds to... Similarly, a charge redistribution between the C IN -Subcapacitors C IN0 , C IN1 cause a voltage to build up at C IN -capacitor as V ICM -V CMA developed. Thus, during the CHP2 phase, an input signal can be present at amplifier A1 that represents a difference between the V IP - and V IN -signals, but to the common-mode voltage V CMA is shifted towards the amplifier.

[0035] During the CHP2 phase, the COB signal can cause its associated switches to close, connecting amplifier output terminal 306 to the VOP terminal and amplifier output terminal 308 to the VON terminal. The PGA 300 can generate a differential output voltage across the capacitances between the capacitors. IP - / C IN -capacitors and the C FN - / C FP -capacitors is defined.

[0036] In one embodiment, the control signals CO and COB for the second chopper circuit 320 can have a shorter duration than the control signals CI and CIB input to the first chopper circuit 310. This can cause the output terminals VON, VOP to be disconnected from the output terminals of amplifier A1, since the chopper circuit switches between the CHP1 and CHP2 phases, thereby reducing any interference signals that might otherwise occur if the amplifier outputs were connected to the output terminals VON, VOP for the entire duration of the CI, CIB signals.

[0037] In some cases, the CHP2 phase can immediately follow the CHP1 phase. Optionally, a probe common-mode sampling (DCMS) phase can be inserted between successive chopper phases. The DCMS phase can provide symmetry in the amplifier output signals during operation. During the DCMS phase, the CIB0 and CIB1 signals can cause their associated switches to be closed, while the CI0 and CIB1 signals can cause their switches to be open. The CIB0 switches can cause the input terminals of the C IP0 - and C IN0 -Subcapacitors with V IN or V IP be connected. The CIB1 switches can cause the input terminals of the C to be connected. IP1 - and C IN1 -Subcapacitors with V IP or V INThey are connected. However, during the DCMS phase, the SMP switches and the switches of the chopper circuit 320 are open. Under such circumstances, no sampling activity occurs during the DCMS phase, and therefore no additional kT / C noise is introduced into the PGA.

[0038] As in previous embodiments, a single CMS phase can also be followed by several CHP1, CHP2 and, if necessary, DCMS phases.

[0039] As indicated, the capacitors C IP , C IN , C FN and C FP variable capacitors and a ratio of capacitances between the C IP - / C IN -capacitors and the C FN - / C FP The gain provided by the PGA 300 can be determined by the capacitors. Each capacitor C IP , C IN , C FN and C FPcan be provided as an arrangement of capacitor devices with connecting switches (not shown) that selectively include or exclude capacitors from the arrangement in the PGA 300. During the CMS phase, the C IP0 -, C IP1 -, C IN0 - and C IN1 The capacitances must be adjusted so that they are equal to each other. Thus, if capacitors are made from C IP - and C IN Capacitor arrays are selected to adjust the PGA gain; half of the selected capacitors are provided to adjust the C IP1 - and C IN1 -to form subcapacitors, and the other half of the selected capacitors can be the C IP0 - and C IN0 -Form subcapacitors. Figs. 5-7

[0040] Fig. Figure 5 illustrates a PGA 500 according to another embodiment of the present invention. This embodiment also avoids the use of a voltage source V. ICM ( Fig. 1) to provide a common-mode input voltage for the PGA 500. In this embodiment, the PGA 500 can have a differential amplifier A1, a pair of variable input capacitors C IN , C IP , a pair of variable feedback capacitors C FN , C FP and comprise two chopper circuits 510 and 520. A first chopper circuit 510 can be provided at an input of the PGA 500, and a second chopper circuit 520 can be provided at an output of the PGA 500. The PGA 500 can also include a switch connected between the input terminals of the two input capacitors C. IN , C IP is connected and activated by a control signal marked SHRT.

[0041] The chopper circuits 510 and 520 can each comprise an arrangement of switches that selectively connect the inputs of the respective circuits to their outputs. In particular, the chopper circuit 510 can comprise two pairs of switches, each controlled by a control signal CI and CIB, respectively. The CI switches can connect an input terminal of the C IP -capacitor with V IP connect and can connect an input port of the C IN -capacitor with the V IN Connect the CIB switch to the input terminal. The CIB switches can connect to the input terminal of the C. IP -capacitor with V IN connect and can access the input port of the C IN -capacitor with V IP connect.

[0042] Similarly, the chopper circuit 520 can comprise two pairs of switches, each controlled by a control signal CO and COB, respectively. The CO switches can connect a first output terminal 506 of amplifier A1 to the PGA output terminal VON and can connect a second output terminal 508 of amplifier A1 to the output terminal VOP. The COB switches can connect the first output terminal 506 to the output terminal VOP and can connect the second output terminal 508 to the output terminal VON.

[0043] The capacitors C IP , C IN , C FN and C FP can be variable capacitors. That is, each capacitor C IP , C IN , C FN and C FPThe circuit may include an arrangement of capacitor devices with connecting switches (not shown) that selectively include capacitors from the arrangement into or out of the PGA 500. During operation, the input capacitors C IP , C IN , so that they have the same capacitance and the feedback capacitors C FN , C FP They can be configured to have the same capacity. A ratio of capacities between the C IP - / C IN -Input capacitors and the C FN - / C FP However, the feedback capacitors can be controlled (not shown) to provide programmable gain for the PGA System 500.

[0044] The PGA 500 can supply a voltage source V CMAinclude those connected to the input terminals 502, 504 of amplifier A1 and, via corresponding sampling switches, also to the output terminals of the input capacitors C IN , C IP is coupled. The voltage V CMA can be set to a common-mode voltage of amplifier A1. The sampling switches can close in response to a control signal SMP.

[0045] The PGA 500 can include a control unit 550 that generates control signals SMP, SHRT, CI, CIB, CO and COB for the PGA 500 in response to an external timer, such as a clock signal CLK.

[0046] Fig. Figure 6 is a timing diagram illustrating the operation of the PGA 500 according to an embodiment of the present invention. As shown, the operation of the PGA 500 can extend over several operating phases: CMS, CHP1, CHP2, and the optional DCMS phase. In this embodiment, the operation of the CMS phase can proceed in a partial phase pair. During a first partial phase 610 of the CMS phase, the SMP and CIB signals can cause their respective switches to close. The SMP switches cause the output terminals of the C IP - and C IN -Capacitors with the amplifier common-mode voltage V CMA be connected. The CIB switches can cause the input terminal of the C to be connected. IP -capacitor with V IN is connected, and the input terminal of C IN -capacitor with V IP is connected. Thus, the C IP -Capacitor during the first sub-phase 610 a voltage V IN -VCMA capture and the C IN -The capacitor can supply a voltage V during the first sub-phase of CMS IP -V CMA capture.

[0047] During the second sub-phase 620, both the CIB and SHRT signals can undergo a transition. The CIB transition can cause its associated switches to be open, thereby opening the input terminals of the C IP - and C IN -capacitors from the V IN - and V IP -connections are disconnected. The transition of the SHRT signal can cause the input connections of the C to be disconnected. IP - and C IN Capacitors are connected together. A charge redistribution can occur between the capacitors. IP - and C IN -capacitors occur, which can cause voltages across each capacitor to be ½ (V IP -V IN )-V CMA develop what V ICM -V CMAThis corresponds to the PGA 500 performing a sampling operation during the CMS phase, which can define a common-mode signal for input signals applied to amplifier A1 during the chopper phases CHP1 and CHP2, to which the amplifier's common-mode signal is adapted.

[0048] During the first chopper phase (CHP1), both the SMP and SHRT signals can undergo a transition. The SHRT signal's transition can cause its switch to open, which opens the input terminals of the C IP - and C IN -capacitors separate from each other. The charge on the C IP - and C IN -Capacitors may be trapped. The transition of the SMP signal may affect the output terminals of the C IP - and C IN -capacitors and the amplifier inputs from the amplifier common-mode voltage source V CMA separate.

[0049] The CI signal can cause its associated switches to be closed, and the CIB signal can cause its switches to be open. These control signals can cause the input terminals of the C IP -capacitor with the V IP -Input terminals are connected and the input terminals of C IN -capacitor with the V IN -connected. Differential voltages that occur at the V IP - and V IN -connections can be present at the inputs of amplifier A1, but relative to a common-mode level of the input signals (V ICM ) to the common-mode level of amplifier A1 (V CMA ) may be shifted. Amplifier A1 can generate differential voltages at amplifier output terminals 506 and 508, based on the ratio of the capacitances between the C IP - / C IN -capacitors and the C FN - / C FP -Capacitors.

[0050] During the CHP1 phase, the CO signal can cause the switches associated with it to be closed, connecting amplifier output terminal 506 to the VON terminal and amplifier output terminal 508 to the VOP terminal.

[0051] During the second chopper phase (CHP2), the CI and CO signals can cause their associated switches to be open. The CIB signal can cause its associated switches to be closed, which can cause the input terminal of C to be closed. IP -capacitor with the V IN -Input port is connected and the input port of C IN -capacitor with the V IP -connection is connected. Again, the V IP - and V IN -differential voltages present at the inputs of amplifier A1 at the terminals, but relative to a common-mode level of the input signals (V ICM) to the common-mode level of amplifier A1 (V CMA ) in an orientation that is inverted with respect to the orientation of the CHP1 phase. Amplifier A1 can generate differential voltages at amplifier output terminals 506, 508, based on the ratio of the capacitances between the C IP - / C IN -capacitors and the C FN - / C FP -Capacitors.

[0052] During the CHP2 phase, the orientation of the second chopper circuit 520 can be inverted with respect to its orientation during the CHP1 phase. Specifically, the COB phase can cause its switches to be closed, and the CO phase can cause its switches to be open. The amplifier output terminal 506 can be connected to the VOP terminal, and the amplifier output terminal 508 can be connected to the VON terminal.

[0053] As in previous embodiments, in some cases the CHP2 phase can immediately follow the CHP1 phase. However, if necessary, a "Probe Common Mode Sampling" (DCMS) phase can be inserted between successive chopper phases. The DCMS phase can provide symmetry in the amplifier output signals during operation. In the embodiment of Fig. 5 and Fig. 6. The DCMS phase can have two sub-phases, 630 and 640. During the first sub-phase, 630, the CIB signal can cause its associated switches to be open, but the CI signal can cause its switches to be closed. The CI switches can cause the input terminal of C to be closed. IP -capacitor with V IP is connected and the input terminal of C IN -capacitor with V INis connected. However, the SMP sampling signal can cause the switches associated with it to be open. Accordingly, although the input terminals of C IP and C IN the voltages present at the input terminals V IN and V IP When present, exposed to, the voltages across the input capacitors C change. IP or C IN not.

[0054] During the second subphase 640, both the CI and SHRT signals can undergo a transition. The transition of the CI signal can cause its associated switches to be open, which opens the input terminals of the C. IP - and C IN -capacitors from the V IP - and V IN -connections disconnected. The transition of the SHRT signal can cause the input connections of the C to disconnect. IP - and C IN -capacitors are connected together. Since the SMP switch is not closed, there is no charge redistribution between CIP and C IN . Closing the SHRT switch forces the voltages at the input to equal V ICM to become (and the differential voltage at the terminals of C) IP and C IN to be equal to zero). But the charge of C IP and C IN is applied to the feedback capacitor C FP and C FN Such operations can be performed during operation using the input terminals of C. IP and C IN an V ICM Provide symmetry, with the output of amplifier A1 going to the output common-mode voltage, so that the voltage at nodes 508 and 506 should be equal to the output common-mode voltage. This should mimic what happens during the CMS phase. Again, the SMP should be kept low during the DCMS phase, thus preventing sampling and therefore not adding any additional kT / C noise to the PGA output.

[0055] As in previous embodiments, the capacitors C IP , C IN , C FN and C FP variable capacitors and a ratio of capacitances between the C IP - / C IN -capacitors and the C FN - / C FP The gain provided by the PGA 500 can be determined by the capacitors. Each capacitor C IP , C IN , C FN and C FP can be provided as an arrangement of capacitor devices with connecting switches (not shown) that selectively include capacitors from the arrangement into or out of the PGA 500. During the CMS phase, the capacitances of C IP0 , C IP1 , C IN0 and C IN1 They should be adjusted so that they are equal. Thus, if the capacitors of C IP - and C IN-Capacitor arrays are selected to adjust the PGA gain; half of the selected capacitors are provided to adjust the C IP1 - and C IN1 -to form subcapacitors, and the other half of the selected capacitors can be the C IP0 - and C IN0 -Form subcapacitors.

[0056] Fig. Figure 7 is a timing diagram illustrating the operation of the PGA 500 according to another embodiment of the present invention. As in the preceding embodiments, the operation of the PGA 500 can occur over several operating phases: CMS, CHP1, CHP2, and the optional DCMS phase. Here, the operation of the CMS phase can proceed in a sub-phase pair 710, 720. During a first sub-phase 710 of the CMS phase, the SMP and CIB signals can cause their respective switches to be closed. The SMP switches can cause the output terminals of the C IP - and C IN-Capacitors with the amplifier common-mode voltage V CMA are connected. The CIB switches can cause the input terminal of the C to be disconnected. IP -capacitor with V IN is connected and the input terminal of C IN -capacitor with V IP is connected. Thus, the C IP -capacitor a voltage V IN -V CMA during the first sub-phase 710 capture and the C IN -Capacitor can hold a voltage V IP -V CMA capture during the first sub-phase of CMS.

[0057] The SMP and CIB signals can undergo a transition towards the end of the first sub-phase 710 to open their associated switches. In this embodiment, the falling edge of the SMP signal can precede the falling edge of the CIB signal (the time difference is in the Fig. (Scale 7 shown is not perceptible). Since the CIB signal switch, which is connected to the input signal (terminals V)IP , V IN ) are connected, controls, input signal-dependent charge injection errors can be caused by the input capacitors C IP and C IN The system can be detected when the SMP switches are open at the same time as the CIB switches are open. Because the falling edge of the SMP signal precedes the edge of the CIB signal, the embodiment can be configured to... Fig. 7. Avoid detecting such charge injection errors at the completion of the first sub-phase 710.

[0058] During the second sub-phase 720 of CMS, the SMP and SHRT signals can cause their associated switches to be closed. The control signals CI and CIB for the first chopper switch 510 can cause the input capacitors C IP , C IN from the input ports C IP , C IN can be separated. A charge redistribution can occur between the C IP - and C IN-capacitors occur, which can cause voltages to appear across each capacitor as ½ (V IP -V IN )-V CMA develop what V ICM -V CMA corresponds.

[0059] The SMP and SHRT signals can undergo a transition towards the end of the second subphase 720, with the falling edge of the SMP signal slightly preceding the falling edge of the SHRT signal (again, the time difference in the Fig. (scale shown in 7 is not perceptible). Because the falling flank of SMP precedes the falling flank of SHRT, the embodiment in Fig. 7. Avoid charge injection errors, which would otherwise be caused by the V ICM -V CMA -Voltages across the input capacitors C IP , C IN would be present, depend on, and be recorded.

[0060] During the first chopper phase (CHP1), both the CI and CO signals can undergo a transition. The CI signal can cause its associated switches to be closed, and the CIB signal can cause its switches to be open. These control signals can cause the input terminals of the C IP -capacitor with the V IP -Input terminals are connected and input terminals of C IN -capacitor with the V IN are connected to the V IP - and V IN Differential voltages present at the terminals can be present at the inputs of amplifier A1, but relative to a common-mode level of the input signals (V ICM ) be shifted to the common-mode level of amplifier A1. Amplifier A1 can generate differential voltages at amplifier output terminals 506 and 508, based on the ratio of the capacitances between the C IP - / C IN -capacitors and the CFN - / C FP -Capacitors.

[0061] During the CHP1 phase, the CO signal can cause the switches associated with it to be closed, connecting amplifier output terminal 506 to the VON terminal and amplifier output terminal 508 to the VOP terminal.

[0062] During the second chopper phase (CHP2), the CI and CO signals can cause their associated switches to be open. The CIB signal can cause its associated switches to be closed. The input terminal of C IP -capacitor can be connected to the V IN -connection be connected and the input terminal of the C IN -capacitor can be connected to the V IP -connection. Again, those connected to the V IP - and V IN -differential voltages present at the inputs of amplifier A1 at the terminals, but relative to a common-mode level of the input signals (V ICM) are shifted to the common-mode level of amplifier A1 in an orientation that is inverted with respect to the orientation of the CHP1 phase. Amplifier A1 can generate differential voltages at terminals 506 and 508, based on the ratio of the capacitances between the C IP - / C IN -capacitors and the C FN -C FP -Capacitors.

[0063] During the CHP2 phase, the orientation of the second chopper circuit 520 can be inverted with respect to its orientation during the CHP1 phase. Specifically, the COB phase can cause its switches to be closed, and the CO phase can cause its switches to be open. The amplifier output terminal 506 can be connected to the VOP terminal, and the amplifier output terminal 508 can be connected to the VON terminal.

[0064] As in the preceding embodiments, in some cases the CHP2 phase can immediately follow the CHP1 phase. However, if necessary, a probe common-mode sampling phase (DCMS) can be inserted between successive chopper phases. The DCMS phase can provide symmetry in the amplifier output signals during operation. In the embodiment in Fig. 5 and Fig. 7. The DCMS phase can have two sub-phases, 730 and 740. During the first sub-phase, 730, the CIB signal can cause its associated switches to be open, but the CI signal can cause its switches to be closed. The CI switches can cause the input terminal of C to be closed. IP -capacitor with V IP is connected and the input terminal of C IN -capacitor with V INis connected. However, the SMP sampling signal can cause the switches associated with it to be open. Accordingly, although the input terminals of C IP and C IN the voltages present at the input terminals V IN and V IP When present, exposed to, the voltages across the input capacitors C change. IP or C IN not.

[0065] During the second sub-phase 740, both the CI and SHRT signals can undergo a transition. The transition of the CI signal can cause its associated switches to be open, which opens the input terminals of the C. IP - and C IN -capacitors from the V IP - and V IN -connections disconnected. The transition of the SHRT signal can cause the input connections of the C to disconnect. IP - and C IN -capacitors are connected together. Short-circuiting the input terminals of C. IP and C INsets the voltage of the input terminals of C IP and C IN on V ICM and the differential voltage at the input terminals of C IP and C IN to zero. As in the previous embodiments, the DCMS phase can provide signal symmetry without adding kT / C noise.

[0066] As in previous embodiments, the capacitors C IP , C IN , C FN and C FP variable capacitors and a ratio of capacitances between the C IP - / C IN -capacitors and the C FN - / C FP The gain that the PGA 500 will provide can be determined by the capacitors. Each capacitor C IP , C IN , C FN and C FPcan be provided as an arrangement of capacitor devices with connecting switches (not shown) that selectively include capacitors from the arrangement into or out of the PGA 500. During the CMS phase, the capacitances of C IP0 , C IP1 , C IN0 and C IN1 They should be adjusted so that they are equal. Thus, if the capacitors of C IP - and C IN -Capacitor arrays are selected to adjust the PGA gain; half of the selected capacitors are provided to adjust the C IP1 - and C IN1 -to form subcapacitors, and the other half of the selected capacitors can be the C IP0 - and C IN0 -Form subcapacitors. Fig. 8

[0067] Fig. Figure 8 illustrates a PGA 800 according to another embodiment of the present invention. The PGA 800 can include a differential amplifier A1, a pair of variable input capacitors C IN , C IP , a pair of variable feedback capacitors C FN , C FP and comprise two chopper circuits 810, 820. In the embodiment in Fig. 8. The differential amplifier A1 can be provided as an operational transconductance amplifier (“OTA”). A first chopper circuit 810 can be provided at an input of the PGA 800, and a second chopper circuit 820 can be provided at an output of the PGA 800. The first chopper circuit 810 can have a pair of differential input terminals V. IN , V IP of the PGA 800, each with the input terminals of the input capacitors C IN , C IP connect. Output terminals of the input capacitors C IN , C IPcan be connected to the input terminals of amplifier A1. The feedback capacitors C FN , C FP The outputs 806 and 808 of amplifier A1 can each be coupled in a feedback configuration with the corresponding amplifier inputs. The amplifier outputs 806 and 808 can be coupled with inputs of the second chopper circuit 820. Outputs of the second chopper circuit 820 can be coupled with output terminals of the PGA 800 and, optionally, with load devices and / or filter devices (LOAD).

[0068] The chopper circuits 810 and 820 can configure the direction of the signal flow around amplifier A1. Each chopper circuit 810 and 820 can comprise an arrangement of switches that selectively connects the inputs of the respective circuit to its outputs. In particular, the first chopper circuit 810 can comprise two pairs of switches, each controlled by a control signal CI and CIB, respectively. One of the CI switches can connect an input terminal of C. IP -capacitor with the V IP -connection and the other CI switch can be an input port of the C IN with the V IN Connect the -terminal. One of the CIB switches can be the input terminal of the C. IP -capacitor with the V IN -connect the other CI switch and the input port of C can be connected. IN with the V IPConnect the CI and CIB control signals during the chopper phases of PGA 800 operation. These signals can operate in a complementary manner (described below).

[0069] Similarly, the second chopper circuit 820 can comprise two pairs of switches, each controlled by a control signal CO and COB, respectively. One of the CO switches can connect an output terminal 806 of amplifier A1 to the VON terminal, and the other CO switch can connect an output terminal 808 of amplifier A1 to the VOP terminal. One of the COB switches can connect output terminal 806 to the VOP terminal, and the other COB switch can connect output terminal 808 to the VON terminal. The CO and COB control signals can operate in a complementary manner during the chopper phases of operation of the PGA 800 (described below).

[0070] The capacitors C IP , C IN , C FN and C FPcan be variable capacitors. That means any capacitor C IP , C IN , C FN and C FP may include an arrangement of switched capacitor devices (not shown). During operation, the capacitors C IP , C IN be set so that their capacitances are equal, and the capacitors C FN , C FP They can be configured so that their capacities are equal. A ratio of capacities between the C IP - / C IN -capacitors and the C FN / C FP However, the capacitors can be controlled by control signals (not shown) to provide programmable gain for the PGA System 800.

[0071] The PGA 800 can handle a voltage source pair V ICM , V CMA include those connected to the input capacitors C via corresponding sampling switches. IN C IP are coupled. The voltage VICM can be applied to a common-mode voltage of differential input signals connected to the input terminals V IP , V IN The PGA 800 should be present and set. The voltage V CMA can be set to a common-mode voltage of amplifier A1. The first voltage source V ICM can be connected to the input terminals of the input capacitors C IN , C IP They are coupled via a pair of switches that close in response to an initial control signal, SMPL. The second voltage source, V CMA can be connected to the output terminals of the input capacitors C IP , C IN They may be coupled via second switches that close in response to a second control signal SMP.

[0072] The PGA 800 can also include a switch that connects the output terminals 806 and 808 of amplifier A1. The switch can be controlled by the same SMPL control signal that controls the switches that control the V ICM-voltage source coupled to the amplifier inputs, controls.

[0073] The PGA 800 can include a control unit 850 that generates the control signals SMP, SMPL, Cl, CIB, CO and COB for the PGA 800 in response to an external timer, such as a clock signal CLK.

[0074] In one embodiment, the operation of the PGA 800 can be carried out using the timing diagram in Fig. 2. During the CMS phase, the SMPL control signal can cause the V ICM -Voltage source with the output terminals of the input capacitors C IN , C IP is connected. The SMPL signal can also cause amplifier outputs 806 and 808 to be short-circuited together. Thus, the embodiment in Fig. 8 also any voltage offsets that may be induced by the operation of amplifier A1.

[0075] When differential amplifiers are implemented in integrated circuits, their inputs typically include an offset voltage component, which introduces an error into the operation of the PGA 800. The bypass switch provided between amplifier output terminals 806 and 808 can counteract this amplifier offset by shorting these terminals together during the CMS sampling phase.

[0076] It is assumed that C IN =C IP and C FP =C FN If the SMP signal causes the switches associated with it to be open, an offset of amplifier A1 can cause a voltage error, which is expressed as V ERR =V OFF (1 +C IN / C FN ) appears at amplifier outputs 806, 808. The operation of the chopper circuits 810, 820 can compensate for the error at the PGA outputs VON, VOP, as long as the amplifier sweep does not exceed the voltage error V. ERRand can receive the amplified input signal. If the deviation from the target frequency is significant, the error V may occur. ERR This can be reduced by adjusting the amplifier offset.

[0077] Alternatively, the offset voltage V can be used OFF The amplifier's imperfections can be reduced by automatically zeroing it out during the common-mode sampling phase. Several methods are available for automatically zeroing an amplifier, including those described in C. Enz et al., Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling and Chopper Stabilization, Proc. IEEE, Vol. 84, No. 11 (Nov. 1996). Typically, automatically zeroing an amplifier involves shorting the amplifier input, which is performed during the common-mode sampling phases (CMS) of the embodiments discussed herein.

[0078] Fig. Figure 8 illustrates an output short-circuit switch – the switch that bridges amplifier output terminals 806 and 808 – applied to the PGA architecture in Fig. 1. The principles of the present invention can be applied to the short-circuit switch on other PGA architectures, for example those in Fig. 3 and Fig. Apply the 5 PGA architectures shown. Fig. 9

[0079] Fig. Figure 9 illustrates a PGA 900 according to an embodiment of the present invention. The PGA 900 can include a differential amplifier A1, a pair of variable input capacitors C IN , C IP , a pair of variable feedback capacitors C FN , C FPand comprise two chopper circuits 910 and 920. A first chopper circuit 910 can be provided at an input of the PGA 900, and a second chopper circuit 920 can be provided at an output of the PGA 900. The first chopper circuit 910 can have a pair of differential input terminals V IN , V IP of the PGA 900, each with the input terminals of the input capacitors C IN or C IP connect. Output terminals of the input capacitors C IN , C IP can be connected to the input terminals of amplifier A1. The feedback capacitors C FN , C FPThe respective amplifier outputs 906 and 908 of amplifier A1 can each be coupled in a feedback configuration to the amplifier inputs. Amplifier outputs 906 and 908 can be coupled to the inputs of the second chopper circuit 920. Outputs of the second chopper circuit 920 can be coupled to output terminals VON and VOP of the PGA 900 and, optionally, to load devices and / or filter devices (LOAD).

[0080] The chopper circuits 910 and 920 can configure the direction of the signal flow around amplifier A1. Each chopper circuit 910 and 920 can include a switch arrangement that selectively connects the inputs of the respective circuits to their outputs. In particular, the first chopper circuit 910 can include two pairs of switches, each controlled by a control signal Cl and CIB, respectively. One of the Cl switches can connect an input terminal of C IP-capacitor with the V IP Connect one terminal and the other CL switch can be an input terminal of C IN with the V IN Connect the -terminal. One of the CIB switches can be the input terminal of the C. IP -capacitor with the V IN -connect the other CIB switch and the input port of C can be connected. IN with the V IP Connect the -terminal. The Cl and CIB control signals can operate in a complementary manner during the chopper phases of the PGA 900's operation (described below).

[0081] Similarly, the second chopper circuit 920 can comprise two pairs of switches, each controlled by a control signal CO and COB, respectively. One of the CO switches can connect an output terminal 906 of amplifier A1 to the VON terminal, and the other CO switch can connect an output terminal 908 of amplifier A1 to the VOP terminal. The CO and COB control signals can operate in a complementary manner during the chopper phases of operation of the PGA 900 (described below).

[0082] The capacitors C IP , C IN , C FN and C FP can be variable capacitors. That means that each capacitor C IP , C IN , C FN and C FP This may include an arrangement of switching capacitor devices (not shown). During operation, the input capacitors C IP , C INbe set so that they have the same capacitance and the feedback capacitors C FN , C FP They can be configured to have the same capacity. A ratio of capacities between the C IP - / C IN -capacitors and the C FN - / C FP However, the capacitors can be controlled by control signals (not shown) to provide programmable gain for the PGA System 900.

[0083] The PGA 900 can have a pair of short-circuit switches made up of the feedback capacitors C FN , C FP The provided components include those that can be controlled via a common control signal SMP.

[0084] The PGA 900 can supply a voltage source V ICM include those connected to the input capacitors C via corresponding sampling switches. IN C IP is coupled. The voltage V ICMcan be applied to a common-mode voltage of differential input signals connected to the input terminals V IP , V IN The voltage of the PGA 900 must be set. The voltage source V ICM can be connected to the input terminals of the input capacitors C IN , C IP They are coupled via a pair of switches that close in response to an initial control signal SMPL.

[0085] The PGA 900 can include a control unit 950 that generates control signals SMP, SMPL, Cl, CIB, CO and COB for the PGA 900 in response to an external timer, such as a clock signal CLK.

[0086] The PGA 900 can be controlled using the [function / tool / etc.] in [the following text / code]. Fig. The timing diagram shown in section 2 is shown. During the CMS phase, the SMP and SMPL signals can cause their associated switches to close. In response, the input terminals of the input capacitors C can be closed. IP , C INwith the input common-mode voltage V ICM The SMP switches can short-circuit the amplifier input terminals 902 and 904 with the corresponding amplifier output terminals 906 and 908.

[0087] As in previous embodiments, automatic zeroing can occur during the CMS phase. However, amplifier A1 can be configured with feedback on one during automatic zeroing. From a common-mode point of view, the amplifier configuration can cause the common-mode output of the amplifier (V CMO ) is driven at input terminals 902 and 904 of amplifier A1. Therefore, when the SMP goes LOW, the input capacitors C IP and C IN a common-mode voltage V ICM -V CMO scanning. In this respect, PGA operation is similar to the implementation in Fig. 1 with V CMA = V CMO .

[0088] From a differential point of view, amplifier A1 can drive a voltage at its inputs during the CMS phase that is close to the amplifier offset V. OFF This is the case. Therefore, when the SMP goes LOW, the input capacitors C are tested. IP and C IN a differential voltage close to V OFF from which the input voltage is subsequently subtracted during the chopper phases CHP1 and CHP2. In practice, the amplifier output terminals 906 and 908 have a constant, small voltage error close to V during the chopper phases CHP1 and CHP2. OFF , which can be removed at the PGA outputs VON, VOP by chopping.

[0089] In the circuit diagram of Fig. 9. The common-mode voltages at the input terminals 902, 904 and at the output terminals 906, 908 of amplifier A1 can be driven to the same voltage. However, this is not strictly necessary. In another embodiment, the feedback capacitors C could FP and C FN are disconnected from the amplifier during the CMS phase and pre-charged to a desired common-mode level shift voltage, as in Fig. 10 shown. Figs. 10-11

[0090] Fig. Figure 10 illustrates a PGA 1000 according to another embodiment of the present invention. The PGA 1000 can include a differential amplifier A1, a pair of variable input capacitors C IN , C IP , a pair of variable feedback capacitors C FN , C FPand comprise two chopper circuits 1010 and 1020. A first chopper circuit 1010 can be provided at an input of the PGA 1000, and a second chopper circuit 1020 can be provided at an output of the PGA 1000. The first chopper circuit 1010 can be a differential input terminal pair V. IN , V IP of the PGA 1000, each with the input terminals of the input capacitors C IN , C IP connect. Output terminals of the input capacitors C IN , C IP can be connected to the input terminals of amplifier A1. The feedback capacitors C FN , C FPThe corresponding outputs 1006 and 1008 of amplifier A1 can each be coupled in a feedback configuration to the amplifier inputs. Amplifier outputs 1006 and 1008 can be coupled to inputs of the second chopper circuit 1020. Outputs of the second chopper circuit 1020 can be coupled to output terminals VON and VOP of the PGA 1000 and, optionally, to load devices and / or filter devices (LOAD).

[0091] The chopper circuits 1010 and 1020 can configure the direction of the signal flow around amplifier A1. Each chopper circuit 1010 and 1020 can comprise an array of switches that selectively connects the inputs of the respective circuit to its outputs. In particular, the first chopper circuit 1010 can comprise two pairs of switches, each controlled by a control signal Cl and CIB, respectively. One of the Cl switches can connect an input terminal of CIP -capacitor with the V IP Connect the -terminal and the other Cl switch can be an input terminal of the C IN with the V IN Connect the -terminal. One of the CIB switches can be the input terminal of the C. IP -capacitor with the V IN -connect the other CIB switch and the input port of C can be connected. IN to the V IP Connect the -terminal. The Cl and CIB control signals can operate in a complementary manner during the chopper phases of the PGA 1000's operation (described below).

[0092] Similarly, the second chopper circuit 1020 can comprise two pairs of switches, each controlled by a control signal CO and COB, respectively. One of the CO switches can connect an output terminal 1006 of amplifier A1 to the VON terminal, and the other CO switch can connect an output terminal 1008 of amplifier A1 to the VOP terminal. The CO and COB control signals can operate in a complementary manner during the chopper phases of the PGA 1000's operation (described below).

[0093] The capacitors C IP , C IN , C FN and C FP can be variable capacitors. That means that each capacitor C IP , C IN , C FN and C FP This may include an arrangement of switching capacitor devices (not shown). During operation, the capacitors C IP , C IN be set so that they have the same capacitance and the capacitors CFN , C FP They can be configured to have the same capacity. A ratio of capacities between the C IP - / C IN -capacitors and the C FN - / C FP However, the capacitors can be controlled by control signals (not shown) to provide programmable gain for the PGA 1000.

[0094] In the embodiment in Fig. 10. A pair of switches, which can be controlled by an SMP signal, can couple the amplifier input terminals 1002, 1004 with corresponding output terminals 1006, 1008. The feedback capacitors C FN , C FP Each can be coupled to corresponding amplifier input terminals 1002 and 1004 via a second pair of switches controlled by an SMPB signal. The feedback capacitors C FN , C FPEach can be coupled via a third pair of switches, which is also controlled by the SMPB signal, to a corresponding amplifier output connection 1006, 1008.

[0095] The PGA 1000 can be a voltage source V ICM include those connected to the input capacitors C via corresponding sampling switches. IN , C IP is coupled. The voltage V ICM can be set to a common-mode voltage of differential input signals connected to the input terminals V IP , V IN of the PGA 1000. The voltage source V ICM can be connected to the input terminals of the input capacitors C IN , C IP be coupled via a pair of switches that close in response to an initial control signal SMPL.

[0096] The PGA 1000 can include a pair of amplifier common-mode voltage sources, designated as V CMA or V CMO be shown. The V CMAThe voltage source can be set to the desired common-mode input voltage of amplifier A1. The V CMO The voltage source can represent the desired common-mode output of amplifier A1 when the PGA 1000 is configured in gain mode or amplifying mode. The V CMA The voltage source can be connected to an input terminal of amplifier A1, which sets the amplifier's common-mode output voltage (labeled "OCM") via a switch controlled by the SMP signal. CMO The voltage source can be connected to the OCM input of amplifier A1 via a switch controlled by the SMPB signal.

[0097] The PGA 1000 can include a control unit 1050 that generates control signals SMP, SMPB, SMPL, Cl, CIB, CO and COB for the PGA 1000 in response to an external timer, such as a clock signal CLK.

[0098] Fig. Figure 11 is a timing diagram illustrating the operation of the PGA 1000 according to an embodiment of the present invention. During the CMS phase, the SMPL switches may be closed, which connects the input terminals of the input capacitors C IN , C IP with V ICM The SMP switches can also be closed, which can cause the input terminals 1002 and 1004 of amplifier A1 to be connected to the amplifier output terminals 1006 and 1008 of amplifier A1. Amplifier A1 can therefore have its offset voltage applied to its input terminals 1002 and 1004. An SMP switch can also connect the OCM terminal of amplifier A1 to the V CMA Connect to a power source.

[0099] The SMP signal can also cause the first terminals 1032, 1034 of the feedback capacitors C to FN , C FP with the V CMA-voltage are connected and second terminals 1036, 1038 with the V CMO -voltage are connected. The SMPB signal can cause the switches associated with it to be open, which can ensure that the feedback capacitors C FP , C FN from the input and output terminals 1002, 1004, 1006 and 1008 of amplifier A1. Thus, the input capacitor C IN a voltage V during the CMS phase ICM - V CMA - V OFF / 2 sample and the input capacitor C IP can V ICM - V CMA + V OFF / 2 sample. The sampling operation can define the amplifier input common mode for amplifier A1 with room for amplifier offset and maintain the constant common-mode voltage at the amplifier inputs during other operating phases.

[0100] The switches of the chopper circuits 1010, 1020 can be kept open during the CMS phase, thus allowing the capacitors C IN , C IP , C FN and C FP effectively separated from other components of the PGA 1000.

[0101] During the first chopper phase (CHP1), chopper circuits 1010 and 1020 can be activated, the SMP and SMPL switches can be open, and the SMPB switches can be closed. The common-mode voltage source V ICM can be measured from the input capacitors C IN , C IP be separated by the SMPL sampling switches. The feedback capacitors C FP , C FN Amplifier terminals 1002, 1004, 1006, and 1008 can be connected via the SMPB switches. When SMPB goes HIGH, the common-mode output of amplifier A1 can be set to V CMO be adjusted. Since the feedback capacitors C FP , C FNon voltages that correspond to the common-mode voltage difference V CMO -V CMA corresponding, pre-charged, the feedback capacitors C FP , C FN the PGA output common-mode voltage to V CMO In this embodiment, the feedback capacitors C shift FP , C FN the common-mode voltage effectively, while the voltage across the input capacitors C IN , C IP The stored voltage offset ensures that the PGA outputs 1000 V at zero input voltage. OFF generated at outputs 1006 and 1008, and not an amplified version of the offset voltage.

[0102] Even during the CHP1 phase, the Cl control signal can cause the switches assigned to it to be closed, thus limiting the input signal at V IP Input with the input capacitor C IP is connected and the input signal at V IN Input with the input capacitor C INis connected. The CO control signal can also cause the switches assigned to it to be closed, which in turn closes the feedback capacitor C. FN with the output terminal VON and the feedback capacitor C FP can be connected to the output terminal VOP. Configured in this way, the PGA 1000 can accept input voltages V. IP , V IN applied differential input signal based on a ratio of the input capacitors C IP / C IN to the amplifier feedback capacitors C FN / C FP strengthen.

[0103] The difference signals that determine the V IP -, V IN -connections can be entered to measure the common-mode voltage V ICM of the upstream circuit of the PGA (not shown). The application of the differential signals to the input capacitors C IP , C INcan cause the application of reverse voltages to inputs 1002, 1004 of amplifier A1, but in a common-mode voltage V CMA of amplifier A1, due to the voltages present at the input capacitors C during the CMS phase IP , C IN were scanned.

[0104] During the second chopper phase (CHP2), the configuration of the chopper circuits 1010 and 1020 can be inverted. The sampling switches SMP and SMPL can remain open, thus limiting the common-mode voltage sources V. ICM , V CMA from the input capacitors C IN , C IP remain separate. The feedback capacitors C FP , C FN The amplifier terminals 1002, 1004, 1006, and 1008 can remain connected via the SMPB switches. The CIB control signal can cause its associated switches to close, thus limiting the signal at input V. IP with the input capacitor C INis connected and the signal at input V IN with the input capacitor C IP is connected. In this way, the chopper circuit 1010 inverts the distribution of the PGA input signals to the amplifier input terminals 1002, 1004 of amplifier A1 while the PGA 1000 transitions from the CHP1 phase to the CHP2 phase and inverts the distribution again when the PGA 1000 transitions from the CHP2 phase to the CHP1 phase.

[0105] The COB control signal can cause the switches assigned to it to close, connecting amplifier output terminal 1006 to output terminal VOP and amplifier output terminal 1008 to output terminal VON. Similar to the first chopper circuit 1010, the second chopper circuit 1020 can invert the distribution of voltages from output terminals 1006 and 1008 of amplifier A1 to output terminals VON and VOP when the PGA 1000 transitions from the CHP1 phase to the CHP2 phase, and invert the distribution again when the PGA 1000 transitions from the CHP2 phase to the CHP1 phase. Nevertheless, the PGA 1000 amplifies a differential input signal, which is represented as input voltages V. IP , V IN is based on a ratio of the input capacitors C IP / C IN to the amplifier feedback capacitors C FN / C FP .

[0106] As in the CHP1 phase, the input voltages V IP , V IN during the CHP2 phase around the common-mode voltage V ICM of the upstream circuit of the PGA (not shown) vary. The application of V IP , V IN Input voltages to the input capacitors C IN , C IP This can cause the application of reverse voltages to the inputs of amplifier A1, but shifted to the common-mode voltage V. CMA of amplifier A1 due to the voltages applied to the input capacitors C IN , C IP during the CMS phase. Thus, the PGA 1000 can perform a sampling operation during the CMS phase, which can define a common-mode signal for input signals applied to amplifier A1 during operating phases CHP1 and CHP2, which is adapted to the common-mode signal of the amplifier. Figs. 12-13

[0107] Fig. Figure 12 illustrates a PGA 1200 according to another embodiment of the present invention. The PGA 1200 can include a differential amplifier A1, a pair of variable input capacitors C IN , C IP , a pair of variable feedback capacitors C FN , C FP , a pair of C-capacitors CN , C CP and comprise two chopper circuits 1210 and 1220. A first chopper circuit 1210 can be provided at an input to the PGA 1200, and a second chopper circuit 1220 can be provided at an output of the PGA 1200. The first chopper circuit 1210 can have a pair of differential input terminals V IN , V IP of the PGA 1200, each with the input terminals of the input capacitors C IN , C IP connect. Output terminals of the input capacitors C IN , C IPcan be connected to input terminals 1202 and 1204 of amplifier A1. The feedback capacitors C FN , C FP The corresponding amplifier outputs 1206 and 1208 of amplifier A1 can each be coupled in a feedback configuration to the amplifier input terminals 1202 and 1204. The amplifier outputs 1206 and 1208 can be coupled to the inputs of the second chopper circuit 1220. Outputs of the second chopper circuit 1220 can be coupled to output terminals VON and VOP of the PGA 1200 and, optionally, to load devices and / or filter devices (LOAD).

[0108] The chopper circuits 1210 and 1220 can configure the direction of the signal flow around amplifier A1. Each chopper circuit 1210 and 1220 can comprise an array of switches that selectively connects the inputs of the respective circuits to their outputs. In particular, the first chopper circuit 1210 can comprise two pairs of switches, each controlled by a control signal Cl and CIB, respectively. One of the Cl switches can connect an input terminal of C IP -capacitor with the V IP Connect the -terminal and the other Cl switch can be an input terminal of the C IN -capacitor with the V IN Connect the -terminal. One of the CIB switches can be the input terminal of the C. IP -capacitor with the V IN -connect the other CIB switch and the input terminal of the C IN -capacitor with the V IPConnect the -terminal. The Cl and CIB control signals can operate in a complementary manner during the chopping phases of the PGA 1200's operation (described below).

[0109] Similarly, the second chopper circuit 1220 can comprise two pairs of switches, each controlled by a control signal CO and COB, respectively. One of the CO switches can connect an output terminal 1206 of amplifier A1 to the VON terminal, and the other CO switch can connect an output terminal 1208 of amplifier A1 to the VOP terminal. The CO and COB control signals can operate in a complementary manner during the chopper phases of operation of the PGA 1200 (described below).

[0110] The capacitors C IP , C IN , C FN and C FP can be variable capacitors. That means that each capacitor C IP , C IN , C FN and C FPThis may include an arrangement of switching capacitor devices (not shown). During operation, the capacitors C IP , C IN be set so that they have the same capacitance and the capacitors C FN , C FP They can be configured to have the same capacity. A ratio of capacities between the C IP - / C IN -capacitors and the C FN - / C FP However, the capacitors can be controlled by control signals (not shown) to provide programmable gain for the PGA 1200.

[0111] In the embodiment of Fig. 12. A pair of switches can connect the amplifier input terminals 1202, 1204 to the corresponding output terminals 1206, 1208, which can be controlled by an SMP signal. The feedback capacitors C FN , C FP can be used with their associated charging capacitors C CN , CCP be provided. The feedback capacitors C FN , C FP can be connected between the corresponding amplifier input terminals 1202, 1204 and output terminals 1206, 1208. The charging capacitors C CN , C CP can be connected to the feedback capacitors C at nodes 1242, 1244, 1246, 1248 via switches controlled by an SMPC signal. FN , C FP be coupled. The charging capacitors C CN , C CP can with the V CMA - and V CMO -Voltage sources as in the embodiment in Fig. 10 are coupled via a second set of switches controlled by an SMPCB signal.

[0112] The PGA 1200 can supply a voltage source V ICM include those connected to the input capacitors C IN , C IP is coupled via corresponding scanning switches. The voltage V ICMcan be applied to a common-mode voltage of differential input signals connected to the input terminals V IP , V IN The voltage source V of the PGA 1200 must be set. ICM can be connected to the input terminals of the input capacitors C IN , C IP be coupled via a pair of switches that close in response to an initial control signal SMPL.

[0113] As in previous embodiments, the PGA 1200 can be a pair of amplifier common-mode voltage sources, as V CMA or V CMO shown, include. The V CMA The voltage source can be set to a desired common-mode input voltage of amplifier A1. The V CMO The voltage source can represent the desired common-mode output of amplifier A1 when the PGA 1200 is configured in gain mode. CMAThe voltage source can be connected to an input terminal OCM of amplifier A1, which sets the output common-mode voltage of amplifier A1 via a switch controlled by the SMP signal. The V CMO The voltage source can be connected to the OCM input of amplifier A1 via a switch controlled by the SMPB signal.

[0114] The V CMA The voltage source can be connected to the first terminals 1232, 1234 of the feedback capacitors C. FN , C FP They can be connected via appropriate switches that can be controlled by the SMPCB signal. The V CMO -The voltage source can be connected to the second terminals 1236, 1238 of the charging capacitors C CN , C CP They are connected via appropriate switches, which can also be controlled by the SMPCB signal.

[0115] The PGA 1200 can include a control unit 1250 that generates control signals SMP, SMPL, SMPC, SMPCB, Cl, CIB, CO and COB for the PGA 1200 in response to an external timer, such as a clock signal CLK.

[0116] Fig. Figure 13 is a timing diagram illustrating the operation of the PGA 1200 according to an embodiment of the present invention. During the CMS phase, the SMPL switches may be closed, which limits the input terminals of the input capacitors C. IN , C IP with V ICM The SMP switches can also be closed, which can cause the input terminals 1202 and 1204 of amplifier A1 to be connected to the output terminals 1206 and 1208 of amplifier A1. Amplifier A1 can therefore cause its offset voltage to be present at its input terminals 1202 and 1204. Additionally, voltages can be present at the feedback capacitors C. FN and C FPCapacitors are set to zero. An SMP switch can also connect the OCM terminal of amplifier A1 to the V CMA Connect to a power source.

[0117] The SMPC signal can cause the switches assigned to it to close, which in turn closes the charging capacitors C CN , C CP with the feedback capacitors C FN , C FP This allows for the connection of voltages across the charging capacitors C. CN , C CP be set to zero. The SMPCB signal can cause its associated switches to be open, which can ensure that the feedback capacitors C FP , C FN from the V CMA - and V CMO -voltage sources are disconnected. The switches of the chopper circuits 1210, 1220 can be kept open during the CMS phase, thus protecting the capacitors C IN , C IP , C FN and C FPIt can be effectively isolated from other components of the PGA 1200. Thus, the input capacitor C can be disconnected during the CMS phase. IN a voltage V ICM -V CMA -V OFF / 2 sample and the input capacitors C IP can V ICM -V CMA +V OFF / 2 sample. The sampling process can define the amplifier input common mode for amplifier A1 with room for amplifier offset and maintain the constant common-mode voltage at the amplifier inputs during other operating phases.

[0118] During the first chopper phase (CHP1), the chopper circuits 1210 and 1220 can be activated, the SMP, SMPL, and SMPC switches can be open, and the SMPCB switches can be closed. The common-mode voltage source V ICM can be measured from the input capacitors C IN , C IP be separated by the SMPL scanning switches. The charging capacitors C CN , C CPcan be from the feedback capacitors C FN , C FP be separated and can instead be connected to the V via the SMPCB switches CMA - and V CMO -connected to voltage sources.

[0119] Also during the CHP1 phase, the Cl control signal can cause the switches assigned to it to be closed, thereby reducing the input signal at V IP Input with the input capacitor C IP and the input signal at V IN Input with the input capacitor C IN is connected. The CO control signal can also cause the switches assigned to it to close, which in turn closes the feedback capacitor C. FN with the output terminal VON and the feedback capacitor C FP can be connected to the output terminal VOP. Configured in this way, the PGA 1200 can amplify a differential input signal, which can be used as input voltages V. IP , V INis based on a ratio of the input capacitors C IP / C IN to the amplifier feedback capacitors C FN / C FP .

[0120] The difference signals that represent the V IP -, V IN -connections can be used to adjust the common-mode voltage V ICM of the upstream circuit of the PGA (not shown). The application of the differential signals to the input capacitors C IP , C IN This can cause reverse voltages to be applied to inputs 1202 and 1204 of amplifier A1, but with a common-mode voltage V CMA of amplifier A1, due to the voltages applied to the input capacitors C IP , C IN were sampled during the CMS phase.

[0121] During the second chopper phase (CHP2), the configuration of the chopper circuits 1210 and 1220 can be inverted. The sampling switches SMP and SMPL can remain open, thus maintaining the common-mode voltage source. The charging capacitors C CN , C CP can be used via the SMPCB switches instead of the feedback capacitors C FN , C FP with the V CMA - and V CMO -voltage sources. The CIB control signal can cause the switches associated with it to close, thus reducing the signal at input V. IP with the input capacitor C IN and the signal at input V IN with the input capacitor C IPis connected. In this way, the chopper circuit 1210 inverts the distribution of the PGA input signals to the input terminals 1202, 1204 of the amplifier A1 when the PGA 1200 transitions from the CHP1 phase to the CHP2 phase and inverts the distribution again when the PGA 1200 transitions from the CHP2 phase to the CHP1 phase.

[0122] The COB control signal can cause its associated switches to also close, connecting amplifier output terminal 1206 to output terminal VOP and amplifier output terminal 1208 to output terminal VON. Similar to the first chopper circuit 1210, the second chopper circuit 1220 can invert the voltage distribution from amplifier A1's output terminals 1206 and 1208 to output terminals VON and VOP when the PGA 1200 transitions from the CHP1 phase to the CHP2 phase, and invert the distribution again when the PGA 1200 transitions from the CHP2 phase to the CHP1 phase. Nevertheless, the PGA 1200 amplifies a differential input signal, which is represented as input voltages V. IP , V IN is based on a ratio of the input capacitors C IP / C IN to the amplifier feedback capacitors C FN / C FP .

[0123] As in the CHP1 phase, the input voltages V can be changed during the CHP2 phase. IP , V IN to the common-mode voltage V ICM of the upstream circuit of the PGA (not shown) vary. The application of V IP , V IN Input voltages to the input capacitors C IN , C IP This can cause opposing voltages to be applied to the inputs of amplifier A1, but to the common-mode voltage V CMA of amplifier A1 due to the voltages applied to the input capacitors C IN , C IP The sampling times during the CMS phase are shifted. Therefore, the PGA 1200 can perform a sampling operation during the CMS phase, which defines a common-mode signal for input signals applied to amplifier A1 during operating phases CHP1 and CHP2, and which is adapted to the common-mode signal of the amplifier.

[0124] In one embodiment, the control signals CO and COB for the second chopper circuit 1220 can have a shorter duration than the control signals Cl and CIB input to the first chopper circuit 1210. This can cause the output terminals VON, VOP to be disconnected from the output terminals of amplifier A1, since the chopper circuit switches between the CHP1 and CHP2 phases, thereby reducing any interference signals that might otherwise occur if the amplifier outputs were connected to the output terminals VON, VOP for the entire duration of the Cl, CIB signals.

[0125] In some cases, the CHP2 phase can immediately follow the CHP1 phase. However, if necessary, a "probe common-mode sampling" (DCMS) phase can be inserted between successive chopper phases. Two types of probe common-mode sampling phases are described in the embodiment shown in Fig. Figure 13 shows the DCMS1 and DCMS2 phases. During the DCMS1 phase, the SMPL signal can undergo a transition, which causes the input terminals of capacitors C to IP and C IN with V ICM They can be connected. Closing the SMPL switches can cause the amplifier output to go to zero, which can result in output voltages at the beginning of the next chopper phase (CHP2) having the same initial conditions as at the beginning of the previous chopper phase (CHP1).

[0126] During the DCMS2 phases, the SMPL and SMPC signals can cause their associated switches to be closed, while the SMPCB signals can cause their associated switches to be open. During this phase, the input terminals of capacitors C IN , C IP with V ICM be connected. The charging capacitors C CN , C CP can each be connected to the feedback capacitors CFP , C FN be connected. The charging capacitors C CN , C CP were charged to a voltage that created a difference between V CMA and V CMO represents, and injects a charge representing this voltage into the PGA 1200. In this way, the PGA architecture can perform a common-mode level shift between the inputs of amplifier A1 and its outputs.

[0127] Over the course of several DCMS phases, the charging capacitors can supply a common-mode charge to the feedback capacitors C. FP and C FN emitting voltages that gradually increase the common-mode voltage across the feedback capacitors C FP and C FN increased. C CN and C CP can be affected by a common-mode level shift voltage V CMO -V CMA can be charged and can apply common-mode charging at C FP and C FNduring the DCMS phase. To reduce kT / C noise, which can be introduced when C CN and C CP To be sampled and suppressed, a CHP1 phase and a CHP2 phase can follow before C CN and C CP be sampled again. Is that due to C? CN and C CP Since the introduced kT / C noise is negligible, it could be sampled in every DCMS phase. Furthermore, C CN and C CP Remain idling during the CMS phase, since C FP and C FN short-circuited via the switches controlled by SMP. Fig. 14

[0128] Fig. Figure 14 illustrates a PGA 1400 according to another embodiment of the present invention. The PGA 1400 can include a differential amplifier A1, a pair of variable input capacitors C IN , C IP , a pair of variable feedback capacitors C FN , C FPand comprise two chopper circuits 1410 and 1420. A first chopper circuit 1410 can be provided at an input of the PGA 1400, and a second chopper circuit 1420 can be provided at an output of the PGA 1400. The first chopper circuit 1410 can have a pair of differential input terminals V IN , V IP of the PGA 1400, each with the input terminals of the input capacitors C IN , C IP connect. Output terminals of the input capacitors C IN , C IP can be connected to input terminals 1402 and 1404 of the differential amplifier A1. The feedback capacitors C FN , C FPThe outputs 1406 and 1408 of the differential amplifier A1 can each be connected in a feedback configuration to the corresponding amplifier input terminals 1402 and 1404. The amplifier outputs 1406 and 1408 can be coupled to inputs of the second chopper circuit 1420. Outputs of the second chopper circuit 1420 can be coupled to output terminals VON and VOP of the PGA 1400 and, optionally, to load devices and / or filter devices (LOAD).

[0129] The chopper circuits 1410 and 1420 can configure the direction of the signal flow around amplifier A1. Each chopper circuit 1410 and 1420 can comprise an array of switches that selectively connects the inputs of the respective circuits to their outputs. In particular, the first chopper circuit 1410 can comprise two pairs of switches, each controlled by a control signal Cl and CIB, respectively. One of the Cl switches can connect an input terminal of C IP -capacitor with the V IP Connect the -terminal and the other Cl switch can be an input terminal of the C IP -capacitor with the V IN Connect the -terminal. One of the CIB switches can be the input terminal of the C. IP -capacitor with the V IN Connect the -connector and the other CI switch can connect the input port of the C IN -capacitor with the V IPConnect the -terminal. The Cl and CIB control signals can operate in a complementary manner during the chopper phases of the PGA 1400's operation (described below).

[0130] Similarly, the second chopper circuit 1420 can comprise two pairs of switches, each controlled by a control signal CO or COB, respectively. One of the CO switches can connect an output terminal 1406 of amplifier A1 to the VON terminal, and the other Cl switch can connect an output terminal 1408 of amplifier A1 to the VOP terminal. The CO and COB control signals can operate in a complementary manner during the chopper phases of operation of the PGA 1400 (described below).

[0131] The capacitors C IP , C IN , C FN and C FP can be variable capacitors. That means that each capacitor C IP , C IN , C FN and C FPThis may include an arrangement of switching capacitor devices (not shown). During operation, the capacitors C IP , C IN be set so that they have the same capacitance and the capacitors C FN , C FP They can be configured to have the same capacity. A ratio of capacities between the C IP - / C IN -capacitors and the C FN - / C FP However, the capacitors can be controlled by control signals (not shown) to provide programmable gain for the PGA system 1400.

[0132] In the embodiment in Fig. 14. A pair of switches can couple the amplifier input terminals 1402, 1404 with corresponding output terminals 1406, 1408, which can be controlled by an SMP signal. The terminals 1436, 1438 of the feedback capacitors C FN , C FPThe output terminals 1406 and 1408 of amplifier A1 can be coupled via corresponding switches controlled by an SMPB signal. The terminals 1436 and 1438 of the feedback capacitors C FN , C FP can also be used with a V CMO The voltage source can be coupled via appropriate switches that can be controlled by the SMP signal. Again, the V CMO -The voltage source represents the desired common-mode output voltage of amplifier A1 when the PGA 1400 is configured in gain mode or amplifying mode.

[0133] As in the previous embodiments, the PGA 1400 can include a pair of amplifier common-mode voltage sources, designated as V CMA or V CMO be shown. The V CMA The voltage source can be set to the desired common-mode input voltage of amplifier A1. The V CMOThe voltage source can represent the desired common-mode output of amplifier A1 when the PGA 1400 is configured in gain mode or amplifying mode. The V CMA The voltage source can be connected to an input terminal OCM of amplifier A1, which sets the output common-mode voltage of amplifier A1 via a switch controlled by the SMP signal. The V CMO The voltage source can be connected to the OCM input of amplifier A1 via a switch controlled by the SMP signal.

[0134] The PGA 1400 can include a control unit 1450 that generates control signals SMP, SMPB, SMPL, Cl, CIB, CO and COB for the PGA 1400 in response to an external timer, such as a clock signal CLK.

[0135] In one embodiment, the operation of the PGA 1400 can be controlled using the timing diagram in Fig. 11. During the CMS phase, the SMPL signal can cause the switches associated with it to close, which causes the input terminals of the input capacitors C to close. IP , C IN with the common-mode voltage V ICM The SMP signal can cause its associated switches to close, short-circuiting the input terminals 1402 and 1404 of amplifier A1 with their corresponding output terminals 1406 and 1408. Additionally, the terminals 1436 and 1438 of the feedback capacitors can be connected to the V CMO -voltage source. The SMPB signal can cause the switches associated with it to be open, which connects terminals 1436 and 1438 of the feedback capacitors C. FN , C FP from the output terminals 1406, 1408 of amplifier A1. An SMP switch can connect the OCM terminal of amplifier A1 to the V CMA Connect to a power source.

[0136] The PGA 1400 from Fig. 14 offers better offset cancellation than the PGA architectures in Fig. 9, Fig. 10 or Fig. 12. In previous embodiments, a PGA zero input signal, namely V IP =V IN , to an offset voltage at the output of A1 of approximately V OFF lead, whereby V OFF The input-related offset of amplifier A1 is shown in the PGA 1400. Fig. However, 14 can be a zero input signal (V IP =V IN ) to a voltage of zero at the output terminals 1406, 1408 of amplifier A1.

[0137] As shown in the circuit diagram in Fig. 9 is recognizable, the PGA 1400 is out Fig. 14 the input common-mode voltage at input terminals 1402, 1404 of amplifier A1 (V CMA ) automatically switches to the output common-mode V CMO of amplifier A1. If a V CMA -Voltage different from V CMOIf desired, the output common-mode voltage of amplifier A1 could be set to the desired V during the CMS phase. CMA be hired.

[0138] The preceding description has presented various architectures for common-mode input voltages ( Fig. 1, Fig. 3 and Fig. 5) and amplifier common-mode voltages ( Fig. 8-10, 12, 14) to be sampled in a PGA. Although the Fig. 8-10, 12, 14 PGAs illustrate the V ICM Sampling methods from Fig. 1. The principles of the present invention also allow the V ICM Sampling methods from Fig. 3 and Fig. 5 on the PGA architectures of Fig. 8-10, 12, 14.

[0139] Several embodiments of the present invention are specifically illustrated and / or described herein. However, it is understood that modifications and variations of the invention are covered by the above teachings and within the scope of the following patent claims, without deviating from the essence and scope of protection of the invention.

Claims

[1] Programmable Gain Amplifier (“PGA”) (100) comprising: a differential amplifier (A1) with one input pair (102, 104) and one output pair (106, 108), a pair of input capacitors (C IN , C IP ) with output terminals, each connected to inputs (102, 104) of the differential amplifier (A1), a pair of feedback capacitors (C FN , C FP ), which are each connected between the outputs of the differential amplifier (A1) and corresponding inputs of the differential amplifier (A1), a first chopper circuit (110) which is configured to connect the input capacitors (C IN , C IP ) to connect to the corresponding input terminals of the PGA (100), a second chopper circuit (120) configured to connect the output terminals (106, 108) of the differential amplifier (A1) to corresponding output terminals (VON, VOP) of the PGA (100), a first voltage source (V ICM ), which is configured to be connected to input terminals (102, 104) of the differential amplifier (A1) via corresponding sample switches, the corresponding sample switches being configured to close in response to a first control signal (CO) and the first voltage source (V ICM ) has a voltage that is set to a common-mode voltage of the differential amplifier (A1), and wherein the amplifier (A1) provides a second voltage source (V CMA ) which is configured with input terminals of the input capacitors (C IN , C IP) to be connected via appropriate scanning switches, the appropriate scanning switches being configured to close in response to a second control signal (COB) and the second voltage source (V CMA ) has a voltage that is set to a common-mode signal of signals to be input into the PGA (100). [2] PGA (100) according to claim 1, wherein the PGA (100) further comprises a short-circuit switch coupled between output terminals (106, 108) of the differential amplifier (A1). [3] PGA (100) according to claim 1, wherein the PGA (100) further comprises a control unit (150) to manage the switching configurations of the PGA (100), wherein the control unit (150) guides the PGA (100) through several operating phases: a common-mode sampling phase, during which the input capacitors (C IN , C IP) Sample voltages that represent a difference between a common-mode voltage of input signals for the PGA (100) and the common-mode voltage of the differential amplifier (A1), a first chopper phase, during which the first and second chopper circuits (110, 120) configure the propagation of the input signals around the differential amplifier (A1) in a first alignment, and a second chopper phase, during which the first and second chopper circuits (10, 120) configure the propagation of the input signals around the differential amplifier (A1) in a second orientation that is inverted to the first orientation. [4] PGA (100) according to claim 3, wherein the included control unit (150) manages the switching configurations for another operating phase in which the input capacitors (C) are connected IN , C IP) a common-mode voltage of the input signals, but not the common-mode voltage of the differential amplifier (A1). [5] PGA (100) according to claim 1, wherein the differential amplifier (A1) is an automatically zeroing amplifier. [6] PGA (100) according to claim 1, wherein the differential amplifier (A1) is a limited amplifier. [7] Programmable Gain Amplifier (“PGA”) (900), comprising, a differential amplifier (A1) with one input pair and one output pair, a pair of input capacitors (C IP , C IN ) with output terminals, each of which is connected to inputs of the differential amplifier (A1), a pair of feedback capacitors (C FN , C FP ), which are each connected between the outputs of the differential amplifier (A1) and the corresponding inputs of the differential amplifier (A1), a first chopper circuit (910) which is configured to connect the input capacitors (C IP , C IN ) to connect to the corresponding input terminals of the PGA (900). a second chopper circuit (920) configured to connect the output terminals of the differential amplifier (A1) to corresponding output terminals of the PGA (900), and a voltage source (V CMA ), which is configured with input terminals of the input capacitor (C IP , C IN) to be connected via appropriate sampling switches, wherein the appropriate sampling switches are configured to close in response to a control signal (CI1, CIB1) and the voltage source has a voltage set to a common-mode voltage of an input signal to be applied to the (900) PGA, and wherein the (900) PGA also includes a pair of short-circuit switches, each switch being connected between an appropriate output terminal of the differential amplifier (A1) and an appropriate input terminal of the differential amplifier (A1). [8] PGA (900) according to claim 7, which further comprises: Connecting switches that couple the feedback capacitors to the input and output terminals of the differential amplifier (A1), wherein the connecting switches are controlled inversely to the short-circuit switches, and a pair of reference voltages corresponding to an input common-mode voltage of the differential amplifier (A1) and an output common-mode voltage of the differential amplifier (A1), respectively, and connected via corresponding switches to corresponding terminals of the feedback capacitors (C) FN , C FP are coupled. [9] PGA (900) according to claim 7, which further comprises: a pair of charging capacitors (C CN , C CP ), which are in accordance with the feedback capacitors (C FN , C FP ) are provided, Switches to connect the charging capacitors (C CN , C CP ) with corresponding connections of the feedback capacitors (C FN , C FP ) to connect, with the connecting switches being controlled inversely to the short-circuit switches, and a pair of reference voltages corresponding to an input common-mode voltage of the differential amplifier or an output common-mode voltage of the differential amplifier (A1) and connected via corresponding switches to corresponding terminals of the charging capacitors (C CN , C CP are coupled. [10] PGA (900) according to claim 7, which further comprises: Connecting switches that connect the feedback capacitors (C FN , C FP ) each to output terminals of the differential amplifier (A1), whereby the connecting switches are controlled inversely to the short-circuit switches, and a reference voltage, which corresponds to a common-mode output voltage of the differential amplifier (A1) and is connected to a terminal of the feedback capacitors (C) via appropriate switches. FN , C FP ) is coupled. [11] PGA (900) according to claim 7, wherein the differential amplifier (A1) is an automatically zeroing amplifier. [12] PGA (900) according to claim 7, wherein the differential amplifier (A1) is a limited amplifier. [13] Method for controlling a chopper amplifier (100, 900) with programmable gain of the capacitor type, the method comprising: During a common-mode sampling phase of operation, a voltage is sampled across input capacitors (C). IP , C IN ) of the PGA (100, 900), which corresponds to a difference between a common-mode voltage of the input signals to be fed into the PGA (100, 900) and a common-mode voltage of a differential amplifier (A1) within the PGA (100, 900), in a first chopper phase of operation, controlling chopper circuits (110, 910) within the PGA (100, 900) to propagate a differential input signal from input terminals of the PGA (100, 900) to output terminals of the PGA (100, 900), wherein the input signal has a first alignment with respect to the differential amplifier (A1), in a second chopper phase of operation, controlling the chopper circuits (120, 920) within the PGA (100, 900) to propagate the differential input signal from the input terminals of the PGA (100, 900) to the output terminals of the PGA (100, 900), wherein the input signal has a second orientation with respect to the differential amplifier (A1) inversely to the first orientation, where the sampling is terminated at one end of the first phase. [14] Method according to claim 13, wherein the method further comprises repeating the first and second chopper phases without using a further common-mode sampling phase. [15] Method according to claim 13, wherein the method furthermore, in a probe sampling phase occurring between the first and the second chopper phase, the application of an input common-mode signal to the input capacitors (C IP , C IN ) includes. [16] Method according to claim 15, wherein the common-mode sampling phase and the probe sampling phase have the same duration.

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