Use of removable gate cover to form transistors and split-gate charge-trapping memory cells

Abstract

A method of manufacturing a semiconductor device (400) having first, second and third regions on a substrate (402), comprising: Disposing a first gate layer (408) over a first dielectric (404) on the substrate (402); Arranging a cap layer (410) over the first gate layer (408); Forming a plurality of memory cells (422) in the first region, each comprising: Etching through the cap layer (410) and the first gate layer (408) in the first region to define at least one selection gate (414) disposed over the first dielectric (404); Disposing a second dielectric (412) over the at least one selection gate (414) and the substrate (402) in at least the first region; Disposing a second gate layer (416) over the second dielectric (412); Etching the second gate layer (416) to define at least one memory gate (418) disposed over the second dielectric (412), each of the at least one memory gate (418) being disposed adjacent to a corresponding sidewall of one of the at least one selection gate (414); Forming a first doped region in the substrate (402) adjacent to one side of the at least one selection gate (414) and a second doped region in the substrate (402) adjacent to an opposite side of the memory gate (418) adjacent to the at least one selection gate (414); and wherein disposing the cap layer (410) includes disposing a silicon nitride layer; Etching through the cap layer (410) and the first gate layer (408) in the second region to define a first transistor gate (420) having an initial thickness substantially equal to a thickness of the cap layer (410) and the first gate layer (408); Forming a third doped region in the substrate (402) adjacent to the first transistor gate (420); Removing the cover layer (410); Etching through the first gate layer (408) in the third region to define a second transistor gate (424) having a thickness substantially equal to the thickness of the first gate layer (408); and Forming a fourth doped region in the substrate (402) adjacent to the second transistor gate (424), wherein the third doped region extends deeper into the substrate (402) than the fourth doped region, and wherein a final thickness of the first transistor gate (420) is substantially equal to the thickness of the second transistor gate (424).

Description

BACKGROUND area

[0001] The present application relates to the fabrication of split-gate charge-trapping memory cells and other field-effect transistors formed in the same substrate. General state of the art

[0002] Non-volatile memory, such as flash memory, retains stored data even when the memory's power supply is removed. A non-volatile memory cell stores data, for example, by storing electrical charge in an electrically isolated floating gate or in a charge-trapping layer underlying a control gate of a field-effect transistor (FET). The stored electrical charge controls the threshold of the FET, thereby controlling the cell's memory state.

[0003] For example, a non-volatile memory cell is programmed using hot carrier injection to place charge into a storage layer. To facilitate the programming process, high drain and gate voltages are used, and the memory cell conducts a relatively high current during programming, which may be undesirable in low-voltage or low-power applications.

[0004] A split-gate memory cell is a type of non-volatile memory cell in which a select gate is placed next to a storage gate. During programming of a split-gate memory cell, the select gate is biased at a relatively low voltage, and only the storage gate is biased at a high voltage to provide the vertical electric field necessary for hot carrier injection. Since carrier acceleration occurs primarily in the channel region beneath the select gate, the relatively low voltage across the select gate results in more efficient carrier acceleration in the horizontal direction compared to a conventional flash memory cell. This makes hot carrier injection more efficient with lower current and lower power consumption during the programming process.A split-gate memory cell can be programmed using techniques other than hot carrier injection, and depending on the technique, any advantages over the conventional flash memory cell during the programming process may vary.

[0005] Another advantage of a split-gate memory cell is fast read time. Because the select gate is in series with the memory gate, the erased state of the memory gate can be near or in depletion mode (i.e., threshold voltage, Vt, less than zero volts). Even when the erased memory gate is in such depletion mode, the select gate in the off state prevents the channel from conducting significant current. When the threshold voltage of the erased state is near or equal to zero, the threshold voltage of the programmed state does not need to be very high while still providing a reasonable read difference between the erased and programmed states. Accordingly, the voltages applied to both the select gate and the memory gate during the read operation can be less than or equal to the supply voltage.Because the supply voltage does not have to be raised to a higher level, the reading process becomes faster.

[0006] It is common to monolithically incorporate multiple types of field-effect devices on the same substrate as the memory cells. These non-memory devices perform, for example, decoding, charge pumping, and other functions related to memory operations. The substrate may also include non-memory devices to provide functions unrelated to memory operations. Such non-memory devices, incorporated on the same substrate as the memory cells, may include transistors tailored for high-speed operations, while other transistors are tailored to handle high operating voltages. Integrating memory cell processing, such as a split-gate memory cell, with the processing of one or more types of non-memory transistors on the same substrate is challenging because each requires different manufacturing parameters.Accordingly, there is a need for a device and methods for integrating different types of devices on the same substrate to enable improved cost, performance, reliability, or manufacturability. Furthermore, the disclosure of the following documents may be helpful for understanding the present invention: US 2007 / 0 155 103 A1, US 5 834 352 A, US 6 420 222 B1, US 2007 / 0 040 208 A1, and US 2010 / 0 105 199 A1.

[0007] US 2007 / 0 155 103 A1 discloses a manufacturing method for an IC device, which comprises forming the first conductive film over a memory cell formation region and over a peripheral circuit formation region of a semiconductor substrate, patterning the first conductive film overlying the memory cell formation region to form a first conductive pattern serving as a first or control gate electrode of a memory cell, and leaving the first conductive film over the peripheral circuit formation region.The method further comprises forming a second conductive film over both the memory cell forming region and the first conductive film in the peripheral circuit forming region, etching the second conductive film to form a second or memory gate electrode of the memory cell on at least one sidewall of the first conductive pattern, and forming a gate electrode of a transistor of the peripheral circuit by etching the first conductive film in the peripheral circuit forming region.

[0008] US 5,834,352 A relates to methods for fabricating integrated circuits containing high- and low-voltage insulated-gate field-effect transistors (IGFETs). The methods comprise the steps of forming first and second insulating layers of unequal thickness at first and second locations, respectively, on a surface of a semiconductor substrate, and subsequently forming first and second gate electrodes on the first and second insulating layers, respectively. Formation of the source and drain regions of a high-voltage IGFET is then initiated by implanting first dopants of a first conductivity type through the first insulating layer and into the first location, using the first gate electrode as an implantation mask. Formation of the source and drain regions (e.g.The breakdown voltage (LDD) of the low-voltage IGFET is then initiated by implanting second dopants of the first conductivity type into the first and second insulating layers. However, the energy level of the implanted second dopants is set relatively low, so that the average projection area of ​​the implanted second dopants is larger than the thickness of the second insulating layer, but smaller than the thickness of the first insulating layer. In this way, negligible amounts of second dopants are implanted into the already partially formed source and drain regions of the high-voltage IGFET. This means that the dose of the implanted first dopants can be preselected to achieve the desired breakdown voltage characteristics of the high-voltage IGFET without contamination by the dopants used for subsequent dopants.

[0009] US Pat. No. 6,420,222 B1 describes a semiconductor manufacturing process for a semiconductor device comprising two layers of polycrystalline silicon and a double diffused drain (DDD) transistor. The number of heat treatment processes is minimized to prevent deterioration of the quality of a gate oxide film, such as a tunnel oxide film in an EEPROM. After forming a gate electrode of a DDD transistor and a bottom electrode of a capacitor, for example, from a first polycrystalline silicon layer, a DDD impurity diffusion region is formed by a heat treatment process in combination with a thermal oxide growth process to produce an oxide dielectric for the capacitor and a gate oxide of a peripheral transistor.A second polycrystalline silicon layer is then formed as the gate electrode of the peripheral transistor and the top electrode of the capacitor, thereby reducing the number of process steps and improving the quality of the gate oxide film and a tunnel oxide film by reducing the length of the heat treatment processes.

[0010] US 2007 / 0 040 208 A1 relates to a non-volatile semiconductor memory device with good write / erase characteristics. A select gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film consisting of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the select gate via the laminated layer. In the regions on both sides of the select gate and the memory gate, n-type impurity diffusion layers are formed in the p-type well, serving as source and drain. The select gate-controlled region and the memory gate-controlled region, located in the channel region between the impurity diffusion layers, have different impurity charge densities.

[0011] Finally, US 2010 / 0 105 199 A1 discloses a method for manufacturing a non-volatile semiconductor memory device that solves a problem of implanted ion penetration due to the difference in the optimal gate height during the simultaneous formation of a self-aligned split-gate memory cell using a sidewall structure and a scaled MOS transistor. A selected gate electrode forming a sidewall in a memory region is formed higher than the gate electrode in a logic region, so that the height of the sidewall gate electrode of the self-aligned split-gate memory cell is greater than that of the gate electrode in the logic region. The height reduction for the gate electrode is performed in the logic region before the gate electrode is formed. OVERVIEW

[0012] It is desirable to eliminate or mitigate at least one of the problems identified here or elsewhere, or to provide an alternative to existing apparatus or methods. In this sense, the present invention relates to a method of fabricating a semiconductor device having a first, second, and third region on a substrate according to claim 1. Advantageous embodiments may include features of dependent claims.

[0013] Further features and advantages of the present invention, as well as the structure and use of various embodiments of the present invention, are described in detail below with reference to the accompanying drawings. It should be noted that the present invention is not limited to the specific embodiments described herein. Such embodiments are presented here for illustrative purposes only. BRIEF DESCRIPTION OF THE DRAWINGS / FIGURES

[0014] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the present invention and to enable any person skilled in the relevant art(s) to make and use the present invention. Fig. 1 illustrates a cross-section of a split-gate memory cell according to various embodiments. Fig. 2 illustrates connections made to a split-gate memory cell according to various embodiments. Fig. 3 illustrates field effect devices formed in different regions of a substrate according to various embodiments. Fig. 4A-4H illustrate various cross-sectional views of a semiconductor device manufacturing process according to embodiments. Fig. 5 illustrates a cross-sectional view of field effect devices with different characteristics according to one embodiment. Fig. 6A-6F illustrate various cross-sectional views of a semiconductor device manufacturing process according to embodiments.

[0015] The features and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference numerals identify corresponding elements throughout. In the drawings, like reference numerals generally indicate identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost numeral(s) in the corresponding reference numeral. DETAILED DESCRIPTION

[0016] This specification discloses one or more embodiments incorporating the features of this invention. The disclosed embodiment(s) merely exemplify the present invention. The present invention is defined by the claims appended hereto.

[0017] The described embodiment(s) and references in the specification to "one embodiment," "an exemplary embodiment," etc., indicate that the described embodiment(s) may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Furthermore, such terms do not necessarily refer to the same embodiment. Furthermore, it is understood that if a particular feature, structure, or characteristic is described in connection with one embodiment, it is within the skill of one of ordinary skill in the art to effect such feature, structure, or characteristic in connection with other embodiments, whether expressly described or not.

[0018] Before describing the various embodiments in more detail, further explanation will be given with regard to certain terms that may be used throughout the descriptions.

[0019] The term "etch" or "etching" is used herein to generally describe a manufacturing process of patterning a material such that at least a portion of the material remains after the etching process is complete. For example, it should be understood that the process of etching silicon involves the step of patterning a masking layer (e.g., photoresist or a hard mask) over the silicon and then removing the areas of silicon that are no longer protected by the masking layer. In this way, the areas of silicon that were protected by the mask would remain after the etching process is complete. As another example, etching can also refer to a process that does not use a mask but still leaves at least a portion of the material behind after the etching process is complete.

[0020] The above description serves to distinguish the term "etching" from the term "removal." When a material is etched, at least some of the material remains after the process is complete. When a material is removed, however, substantially all of the material is removed in the process. However, in some embodiments, "removal" is considered a general term that may include etching.

[0021] Throughout the descriptions herein, various regions of the substrate on which the field-effect devices are fabricated are mentioned. It should be understood that these regions may exist anywhere on the substrate and, furthermore, the regions may not be mutually exclusive. That is, in some embodiments, portions of one or more regions may overlap. Although up to three different regions are described herein, it should be understood that any number of regions may exist on the substrate and may denote areas with certain types of devices or materials. In general, the regions are used to conveniently describe areas of the substrate that include similar devices and should not limit the scope of the described embodiments.

[0022] The terms "deposit" or "deposit" are used herein to describe the process of applying a layer of material to the substrate. Such terms are intended to describe any possible layer-forming technique, including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxy, electroplating, etc.

[0023] The term "substrate" used throughout the descriptions is usually understood to be silicon. However, the substrate may also be any of a wide group of semiconductor materials, such as germanium, gallium arsenide, indium phosphide, etc. In other embodiments, the substrate may be electrically non-conductive, such as a glass or sapphire wafer.

[0024] Before describing such embodiments in more detail, it is instructive to present an exemplary memory cell and environment in which the present embodiments may be implemented.

[0025] Fig. 1 illustrates an example of a non-volatile split-gate memory cell 100. The memory cell 100 is formed on a substrate 102, such as silicon. The substrate 102 is typically p-type or a p-type well, whereas a first doped source / drain region 104 and a second doped source / drain region 106 are n-type. However, it is also possible for the substrate 102 to be n-type, while the regions 104 and 106 are p-type.

[0026] The memory cell 100 includes two gates, a select gate (SG) 108 and a store gate (MG) 110. Each gate may be a doped polysilicon layer formed by well-known techniques, for example, deposition and etching techniques, to define the gate structure. The select gate 108 is disposed over a dielectric layer 112. The store gate 110 is disposed over a charge-trapping dielectric 114 comprising one or more dielectric layers. In one example, the charge-trapping dielectric 114 comprises a charge-trapping silicon nitride layer sandwiched between two silicon dioxide layers to create a three-layer stack, collectively and commonly referred to as "ONO." Other charge-trapping dielectrics may include, but are not limited to, a silicon-rich nitride film or any film comprising silicon, oxygen, and nitrogen in various stoichiometries.For electrical isolation between the two gates, a vertical dielectric 116 is also disposed between the select gate 108 and the storage gate 110. In some examples, the vertical dielectric 116 and the charge-trapping dielectric 114 are the same dielectric, while other examples form one dielectric before the other (e.g., they may have different dielectric properties). As such, the vertical dielectric 116 need not comprise the same film structure as the charge-trapping dielectric 114. Regions 104 and 106 are created by implanting dopants, for example, using an ion implantation technique. Regions 104 and 106 form the source or drain of the split-gate transistor depending on the applied potential.In split-gate transistors, for convenience, region 104 is commonly referred to as the drain, while region 106 is commonly referred to as the source, regardless of the relative bias voltages. It should be understood that this description is intended to provide a general overview of a typical split-gate architecture, and that in actual practice, many more detailed steps and layers are provided to form the final memory cell 100.

[0027] An exemplary write, read, and erase operation will now be described with respect to memory cell 100. To write a bit to memory cell 100, a positive voltage on the order of, for example, 5 volts is applied to region 106 while region 104 and substrate 102 are grounded. A low positive voltage on the order of, for example, 1.5 volts is applied to select gate 108, while a higher positive voltage on the order of, for example, 8 volts is applied to memory gate 110. As electrons are accelerated within a channel region between the source and drain, some of them acquire sufficient energy to be injected upward and trapped in charge-trapping dielectric 114. This is known as hot electron injection.In one example of a charge-trapping dielectric 114, the electrons are trapped within a nitride layer of the charge-trapping dielectric 114. This nitride layer is also commonly referred to as the charge-trapping layer. The trapped charges within the charge-trapping dielectric 114 store the "high" bit within the memory cell 100, even after the various supply voltages have been removed.

[0028] To "erase" the stored charge in memory cell 100 and return the state of memory cell 100 to a "low" bit, a positive voltage on the order of, for example, 5 volts is applied to region 106 while region 104 is floating or at some bias, and select gate 108 and substrate 102 are typically grounded. A high negative voltage on the order of, for example, -8 volts is applied to memory gate 110. The bias conditions between memory gate 110 and region 106 create holes through band-to-band tunneling. The created holes are sufficiently energized by the strong electric field beneath memory gate 110 and injected upward into charge-trapping dielectric 114. The injected holes effectively erase memory cell 100 to the "low" bit state.

[0029] To "read" the stored bit of memory cell 100, a low voltage ranging, for example, between zero and 3 volts is applied to each of the select gate, the storage gate, and region 104, while region 106 and substrate 102 are typically grounded. The low voltage applied to the storage gate is selected to be substantially equidistant between the threshold voltage necessary to turn on the transistor when a "high" bit is stored and the threshold voltage necessary to turn on the transistor when a "low" bit is stored, in order to clearly distinguish between the two states.For example, if the application of the low voltage during the "read" operation causes a significant current to flow between regions 104 and 106, the memory cell holds a "low" bit, and if the application of the low voltage during the "read" operation does not cause a significant current to flow between regions 104 and 106, the memory cell holds a "high" bit.

[0030] Fig. 2 illustrates an exemplary circuit diagram 200 of the memory cell 100, including connections to various metal layers in a semiconductor device. Only a single memory cell 100 is illustrated, but as indicated by the ellipses in both the X and Y directions, a group of memory cells may be connected by the various lines running in both the X and Y directions. In this way, one or more memory cells 100 may be selected for reading, writing, and erasing bits based on the bit line (BL) and source line (SL) used.

[0031] An exemplary source line (SL) runs along the X-direction and is formed in a first metal layer (M1). The source line (SL) can be used to establish an electrical connection to the doped region 106 of each memory cell 100 along a row extending in the X-direction.

[0032] An exemplary bit line (BL) runs along the Y-direction and is formed in a second metal layer (M2). The bit line (BL) can be used to establish an electrical connection to the doped region 104 of each memory cell 100 along a column extending in the Y-direction.

[0033] It is understood that the Fig. 2 are merely exemplary, and the various connections could be formed in metal layers other than those illustrated. Furthermore, although not shown, memory cells 100 may be grouped in the Z-direction and formed within multiple stacked layers.

[0034] Fig. 3 illustrates an exemplary semiconductor device 300 that includes both memory circuitry and peripheral circuitry in the same substrate. In this example, the substrate 102 includes a core region 302 and a peripheral region 304. The core region 302 includes a plurality of memory cells 100 that may operate similarly to those previously described. It should be understood that the cross-section of Fig. 3 is merely exemplary, and that the core region 302 and the peripheral region 304 may be located in any area of ​​the substrate 102 and may be composed of various different regions. Furthermore, the core region 302 and the peripheral region 304 may exist in the same general area of ​​the substrate 102.

[0035] The peripheral region 304 may include integrated circuit components such as resistors, capacitors, inductors, etc., as well as transistors. In the illustrated embodiment, the peripheral region 304 includes a plurality of high-voltage transistors 306 and low-voltage transistors 308. In one example, the high-voltage transistors 306 exist in a separate region of the substrate 102 from the low-voltage transistors 308. The high-voltage transistors 306 are capable of handling voltages as high as, for example, 20 volts, while the low-voltage transistors 308 operate at a faster speed but cannot operate at the same high voltages as the high-voltage transistors 306. In one embodiment, the low-voltage transistors 308 are designed to have a shorter gate length than the high-voltage transistors 306.The high voltage transistors 306 are typically characterized as having a thicker gate dielectric 310 than the gate dielectric of the low voltage transistors 308.

[0036] Fig. 4A-4H illustrate a manufacturing process flow for a semiconductor device including memory cells and other field-effect devices, according to one embodiment. It should be understood that the various layers are not necessarily drawn to scale, and that other processing steps may be performed between the illustrated steps, as one of ordinary skill in the art will understand based on the description herein.

[0037] Fig. 4A illustrates a cross-section of a semiconductor device 400 comprising a substrate 402 with a dielectric layer 404 disposed thereon, according to one embodiment. In one example, the dielectric layer 404 includes a thicker region 406. The thicker region 406 may be used as a gate dielectric for transistors operating at high voltage levels. Also disposed above the dielectric layer 404 is a first gate layer 408, followed by a cap layer 410.

[0038] In one embodiment, the gate layer 408 is a layer of polycrystalline silicon ("poly"). In other examples, the gate layer 408 may be any electrically conductive material, such as various metals or metal alloys. The cap layer 410 may similarly comprise any number of different materials or layers, such as silicon dioxide or silicon nitride. It is preferred, but not required, that the cap layer 410 be a material that can be selectively removed.

[0039] Fig. 4B illustrates another cross-section of the semiconductor device 400 after performing an etch process followed by deposition of a second dielectric layer 412, according to one embodiment. The etch process is performed through both the cap layer 410 and the gate layer 408 down to the first dielectric 404. The etch may use a dry technique such as, for example, reactive ion etching (RIE), or the etch may use a wet technique such as, for example, hot acid baths.

[0040] The etching is performed to define a select gate 414 according to one embodiment. In this example, the select gate 414 may eventually serve as the select gate for a memory cell, as described above with respect to Fig. 1. In this way, the Fig. 4B may be located in a memory cell region (e.g., core region) on the substrate 402. In this non-limiting example, the select gates for two memory cells are illustrated.

[0041] After the etching is performed, the second dielectric layer 412 is deposited over the substrate 402 in at least one memory cell region where the select gate 414 is formed. In one embodiment, the second dielectric layer 412 acts as a charge-trapping dielectric and includes a specific charge-trapping layer. There are many possible layering structures for the charge-trapping dielectric. In a common example, the charge-trapping dielectric is formed by depositing a layer of silicon oxide, followed by deposition of silicon nitride, followed again by deposition of silicon oxide. This procedure creates what is commonly referred to as an "ONO" stack, where the silicon nitride layer sandwiched between the two oxide layers acts as the charge-trapping layer.This charge trapping layer exists beneath the memory gate and traps charge to set the memory bit as either a '0' or a '1'.

[0042] Note that the second dielectric layer 412 is shown deposited over the first dielectric layer 404 in regions between select gates 414. However, in another embodiment, the first dielectric layer 404 may first be etched away in the exposed regions between the select gates 414 before depositing the second dielectric layer 412. Such a procedure may form a better quality charge-trapping dielectric under the memory gate.

[0043] Fig. 4C illustrates another cross-section of the semiconductor device 400 after disposing a second gate layer 416 across at least the memory cell region in which the select gate 414 is formed. In one embodiment, the second gate layer 416 is a polysilicon layer.

[0044] Fig. 4D illustrates the formation of a plurality of memory gates 418 according to one embodiment. The memory gates 418 may be formed via an "etch-back" process in which a blanket etch is performed across the substrate on the second gate layer 416. This etch removes the second gate layer 416 in all areas except those adjacent to the previously defined select gates 414. Thus, the memory gates 418 are self-aligned directly adjacent to both sidewalls of each select gate 414, and they are also formed directly above the second dielectric layer 412. It should also be noted that in this example, the memory gates 418 are taller (e.g., thicker) than the select gates 414. This is due to the presence of the cap layer 410 over the select gates 414 during the formation of the memory gates 418.

[0045] Fig. 4E illustrates another cross-section of semiconductor device 400 with some of the previously patterned memory gates 418 removed. Each memory cell requires only a single select gate and a single memory gate, according to one embodiment. The removal of unnecessary gates (e.g., as illustrated by arrows 415) creates free space on substrate 402 in the memory cell region and also enables the implantation of a doped region in substrate 402, aligned adjacent to select gate 414.

[0046] Although not shown in the figure, according to one embodiment, the doped source and drain regions are formed in the substrate for each memory cell. As mentioned above, the drain region is formed adjacent to the select gate 414 in the substrate 402, while the source region is formed adjacent to the memory gate 418 in the substrate 402. In one embodiment, the two illustrated memory cells may share the same drain region between the two select gates 414.

[0047] Fig. 4F illustrates another cross-section of the semiconductor device 400 according to one embodiment. A first transistor gate 420 is patterned via an etch process that may be similar to the previous etch process used to define the select gates 414. The first transistor gate 420 is patterned over the thicker region 406 of the first dielectric 404. In one embodiment, the first transistor gate 420 is the gate for a high-voltage transistor designed to handle high-intensity voltages. Such voltage intensities may be up to 20 volts. The first transistor gate 420 may be formed in a region on the substrate 402 that includes other high-voltage capable devices. It should be understood that the single illustrated first transistor gate 420 may represent any number of patterned transistor gates over the thicker region 406 of the first dielectric 404.

[0048] Although the second dielectric layer 412 is shown over the cap layer 410 in the region where the first transistor gate 420 is patterned, it is not required for the patterning step. In another embodiment, the second dielectric layer 412 is removed across the entire peripheral region of the substrate 402 before any of the various transistor gates are formed in the peripheral region.

[0049] After the first transistor gate 420 has been patterned, according to one embodiment, the doped source and drain regions (not shown) are formed adjacent to each side of the first transistor gate in the substrate 402. The junction depth of each doped region may be deep to accommodate the high magnitude voltages associated with the field effect device with the first transistor gate 420. According to one embodiment, the high ionization energy of the dopants to be implanted in the substrate is insufficient to penetrate both the thickness of the cap layer 410 and the gate layer 408. If the cap layer 410 were not present during the implantation process, the dopants may have been able to penetrate the first transistor gate 420, effectively shorting the transistor.

[0050] Fig. 4G illustrates another cross-section of the semiconductor device 400 with the cap layer 410 removed, according to one embodiment. Optionally, the second dielectric layer 412 has also been removed in all areas except between the memory gate 418 and the substrate 402 and between the memory gate 418 and the select gate 414. After removal of the cap layer 410, the thickness of the first transistor gate is substantially the same as the thickness of the gate layer 408. The field-effect device with the first transistor gate 420 may be formed in a region on the substrate 402 that is separate from the memory cell region in which a plurality of memory cells 422 are formed.

[0051] Fig. 4H illustrates another cross-section of the semiconductor device 400 wherein a second transistor gate 424 has been patterned, according to one embodiment. The gate layer 408 is etched to define one or more transistor gates 424 in a region on the substrate 402 that may be separate from the memory cell region in which the plurality of split-gate memory cells 422 are formed. In one embodiment, the second transistor gate is formed over the first dielectric layer 404 and thus has a thinner gate dielectric than that associated with the first transistor gate 420. In one example, the second transistor gate 424 is patterned in a different region on the substrate 402 than the first transistor gate 420. It should be understood that the single illustrated second transistor gate 424 may represent any number of similarly patterned transistor gates in the same region on the substrate 402.

[0052] After the second transistor gate 424 has been patterned, the source and drain doped regions are formed adjacent to each side of the second transistor gate in the substrate 402. According to one embodiment, the doped regions associated with the second transistor gate 424 are less deep in the substrate 402 than those associated with the first transistor gate 420. After the second transistor gate 424 has been formed, the thickness of the second transistor gate 424 is substantially similar to the thickness of the first transistor gate 420.

[0053] At this stage, the various field-effect devices have been formed across the different regions of substrate 402. As an optional final step, a layer of silicide may be disposed over the various gates and doped regions to increase conductivity and reduce parasitic effects such as RC delay times for each interconnect. It should be understood that the order and details of each of the illustrated manufacturing steps are merely exemplary. Some of the processes may be performed in a different order or may be combined to create semiconductor device 400. For example, the same etching process may be used to define select gate 414 and first transistor gate 420.Other examples may include first forming the field-effect devices in the peripheral region (including the first transistor gate 420 and the second transistor gate 424), while subsequently forming the split-gate memory cells 422 in the memory cell region. Other similar modifications or variations may be contemplated by one skilled in the relevant art(s) based on the description herein.

[0054] Fig. 5 illustrates an exemplary cross-section of a semiconductor device 500 including a first transistor 501 and a second transistor 503. In one embodiment, the semiconductor device 500 is formed using a substantially similar process to that previously described for forming the peripheral transistors of the semiconductor device 400. The first transistor 501 includes a first gate 502 patterned over a thick dielectric layer 508 and also includes doped source / drain regions 510A and 510B. The second transistor 503 includes a second gate 504 patterned over a thin dielectric layer 506 and also includes doped source / drain regions 512A and 512B.

[0055] In one embodiment, the first transistor 501 is a high-voltage transistor capable of handling voltages up to 20 volts. The thicker gate dielectric protects the first transistor 501 from dielectric breakdown when the high voltage levels are applied. Furthermore, the doped regions 510A and 510B are implanted deep into the substrate 402 to accommodate the larger depletion regions and electric fields generated.

[0056] In one embodiment, the second transistor 503 is a low-voltage transistor designed for fast switching speeds and capable of handling lower voltage levels of up to about 5 volts. The short gate length (L1) characteristic reduces the switching speed of the second transistor 503. In one embodiment, the gate length (L1) of the second transistor 503 is less than or equal to half the gate length (L2) of the first transistor 501. In one such example, L1 is 45 nm, while L2 is at least 90 nm. In another example, L1 is between 10 and 40 nm. The junction depths of the doped regions 510A and 510B are also deeper than the junction depths of 512A and 512B, according to one embodiment.However, the thickness of the first gate 502 is substantially equal to the thickness of the second gate 504, even with the difference in gate lengths and junction depths between the first transistor 501 and the second transistor 503. A discrepancy caused by the additional thickness due to the thicker dielectric layer 508 is considered negligible.

[0057] The one in the Fig. The manufacturing process flow illustrated in Figures 4A-4H demonstrates an example in which the various split-gate memory cells are formed, with the select gate being defined first, followed by the storage gate, which is self-aligned to a sidewall of the select gate. Such a process ultimately results in the storage gate being thicker than the select gate, as shown in Fig. 4H, according to one embodiment. However, the invention is not limited to forming the select gate before the memory gate, and in another embodiment, the memory gate is formed first, followed by a self-aligned select gate. An exemplary process flow for forming the memory gate first is shown in Fig. 6A-6F. It should be noted that Fig. 6A-6F only illustrate cross-sections of the memory cell region and therefore do not illustrate the formation of the various transistors in the other regions (e.g., peripheral regions).

[0058] Fig. 6A illustrates a cross-section of a semiconductor device 600 comprising a substrate 602 having a charge-trapping dielectric 604 disposed thereon, according to one embodiment. A gate layer 606 is also disposed over the charge-trapping dielectric 604, followed by a cap layer 608. The cap layer 608 and the first gate layer 606 may be substantially similar to the gate layer 408 and the cap layer 410, as previously described with respect to FIG. Fig. 4A-4H.

[0059] The charge-trapping dielectric 604 may be similar to the previously described second dielectric layer 412. As such, the charge-trapping dielectric 604 may be an "ONO" stack, according to one embodiment.

[0060] Fig. 6B illustrates another cross-section of the semiconductor device 600 wherein a plurality of memory gates 610 have been formed, according to one embodiment. The memory gates 610 are defined in a similar manner as previously described for creating select gates 414.

[0061] The charge-trapping dielectric 604 has been etched so that portions exist only beneath the memory gates 610. A second dielectric layer 612 is then deposited over the substrate 602. The second dielectric layer 612 may be silicon dioxide and also covers the sidewalls of the memory gates 410 during the deposition process.

[0062] Fig. Figure 6C illustrates another cross-section of the semiconductor device 600, wherein a second gate layer 614 has been disposed. In one embodiment, the second gate layer 614 is a polysilicon layer.

[0063] Fig. 6D illustrates another cross-section of the semiconductor device 600, wherein a plurality of select gates 616 are formed adjacent to both sidewalls of each memory gate 610. The select gates 616 may be formed using a similar "etch-back" process as previously used to form the memory gates 418 with respect to Fig. 4D. It should also be noted that in this example, the select gates 616 are taller (e.g., thicker) than the memory gates 610. This is due to the presence of the cap layer 608 over the memory gates 610 during the formation of the select gates 616.

[0064] Fig. 6E illustrates another cross-section of the semiconductor device 600 with some of the previously patterned select gates 616 removed. Each memory cell requires only a single select gate and a single memory gate, according to one embodiment. The removal of unnecessary gates creates free space on the substrate 602 in the memory cell region and also enables the implantation of a doped region in the substrate 602, aligned adjacent to each memory gate 610.

[0065] Fig. 6F illustrates another cross-section of the semiconductor device 600, wherein the cap layer 608 has been removed and the formation of a plurality of split-cell memory cells 618 is almost complete, according to one embodiment. Optionally, the second dielectric layer 612 has also been removed in all areas except under the select gates 616 and between the select gates 616 and the memory gates 610.

[0066] Although not shown in the figure, according to one embodiment, after the final patterning of the select gates 616 and / or the removal of the cap layer 608, the doped source and drain regions are formed in the substrate for each split-gate memory cell. As mentioned above, the drain region is formed adjacent to the select gates 616 in the substrate 602, while the source region is formed adjacent to the memory gates 610 in the substrate 602. In one embodiment, the two illustrated memory cells may share the same drain region between two select gates 616.

[0067] Once the split gate memory cells 618 have been fully formed, up to Fig. 6E, other transistors in the peripheral region can be connected in a similar manner as before with respect to Fig. 4F-4H. In addition, similar to the process flow illustrated for the semiconductor device 400, the Fig.6A-6F illustrates only one example of forming the semiconductor device 600. The steps may be performed in a different order or, in some aspects, combined to produce a substantially similar final structure.

[0068] The present invention has been described above using functional building blocks that illustrate the implementation of specific functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined here for convenience of description. Alternative boundaries may be defined as long as the specific functions and relationships thereof are adequately implemented.

Claims

[1] A method of manufacturing a semiconductor device (400) having first, second and third regions on a substrate (402), comprising: Disposing a first gate layer (408) over a first dielectric (404) on the substrate (402); Arranging a cap layer (410) over the first gate layer (408); Forming a plurality of memory cells (422) in the first region, each comprising: Etching through the cap layer (410) and the first gate layer (408) in the first region to define at least one selection gate (414) disposed over the first dielectric (404); Disposing a second dielectric (412) over the at least one selection gate (414) and the substrate (402) in at least the first region; Disposing a second gate layer (416) over the second dielectric (412); Etching the second gate layer (416) to define at least one memory gate (418) disposed over the second dielectric (412), each of the at least one memory gate (418) being disposed adjacent to a corresponding sidewall of one of the at least one selection gate (414); Forming a first doped region in the substrate (402) adjacent to one side of the at least one selection gate (414) and a second doped region in the substrate (402) adjacent to an opposite side of the memory gate (418) adjacent to the at least one selection gate (414); and wherein disposing the cap layer (410) includes disposing a silicon nitride layer; Etching through the cap layer (410) and the first gate layer (408) in the second region to define a first transistor gate (420) having an initial thickness substantially equal to a thickness of the cap layer (410) and the first gate layer (408); Forming a third doped region in the substrate (402) adjacent to the first transistor gate (420); Removing the cover layer (410); Etching through the first gate layer (408) in the third region to define a second transistor gate (424) having a thickness substantially equal to the thickness of the first gate layer (408); and Forming a fourth doped region in the substrate (402) adjacent to the second transistor gate (424), wherein the third doped region extends deeper into the substrate (402) than the fourth doped region, and wherein a final thickness of the first transistor gate (420) is substantially equal to the thickness of the second transistor gate (424). [2] The method of claim 1, wherein disposing the second dielectric (412) includes disposing one or more dielectric layers by sequentially disposing oxide, nitride, and oxide (ONO) layers. [3] The method of any preceding claim, wherein etching the second gate layer (416) includes performing an etch-back process to define the memory gate (418) that is self-aligned adjacent to the sidewall of the select gate (414). [4] The method of any preceding claim, further comprising forming the first dielectric (404) on the substrate (402) prior to disposing the first gate layer (408), the first dielectric (404) having a first thickness in the second region associated with the first transistor gate (420) and a second thickness in the third region associated with the second transistor gate (424). [5] A method according to any one of the preceding claims, wherein disposing a capping layer (410) includes disposing one or more layers of silicon nitride or silicon dioxide. [6] The method of any preceding claim, further comprising forming silicide over at least one upper surface of the first transistor gate (420), the second transistor gate (424), the at least one select gate (414), and the at least one memory gate (418).

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