Management of performance policies based on the scalability of workloads

Abstract

Mobile platform (44) comprising: a battery (46) for powering the mobile platform (44); a memory module (56); and a system-on-chip, SoC, (48) connected to the memory module (56), wherein the SoC (48) comprises scalability logic (68) for determining the scalability of a workload (18) associated with the mobile platform (44), and management logic (70) for managing a performance policy (20) of the mobile platform (44) based at least partially on the scalability of the workload (18), and wherein the scalability logic (68) is configured to determine a ratio of requested performance to delivered performance in order to determine the scalability.

Description

BACKGROUNDTechnical Field of ApplicationEmbodiments generally relate to managing the performance (or power level) of computing platforms. In particular, embodiments relate to managing performance policies based on the scalability of the workload.Discussion Of DiscussionComputing platforms may manage processor performance by inputting various performance states ranging from a relatively high operating frequency and a relatively high power consumption (e.g., maximum performance) to a relatively low operating frequency and a relatively low power consumption (e.g., minimum performance). The determination of which performance state to select may conventionally be made in a demand based switching (DBS) mode that is limited to meeting the quality of service (QoS) requirements of the workloads to be processed. Such an approach may provide insufficient efficiency and responsiveness in certain circumstances.US 2010 / 0 057 404 A1 describes a method for maximizing the performance of a processor chip within a predefined power consumption budget. The method comprises the following steps. The power consumption and performance of the processor chip at all possible combinations of voltage level and frequency is predicted. The processor chip is set to the voltage level and frequency combination that provides the highest power at a power consumption that does not exceed the power budget. After a time interval t 1, the frequency of the processor chip is varied to compensate for any offset in workload and maintain the highest power within the power budget. After a time interval t2, the steps of setting and varying are repeated, wherein the time interval t2 is greater than the time interval t1.US 2011 / 0 113 274 A1 describes an electronic device comprising: at least one processing unit (CPU) for processing at least one application, an operating system (OS) for controlling the at least one application executed by the at least one processing unit (CPU), at least one workload setup detector (WBD) for detecting a setup of the workload of the at least one processing unit (CPU), at least one workload reduction detector (WDD) for detecting a reduction of the workload of the at least one processing unit (CPU), and at least one power management unit (SPM) for controlling an operating frequency and / or an operating voltage of the at least one processing unit depending on the detected workload increase or the detected workload reduction.US 2011 / 0 213 950 A1 describes a technique for reducing power consumption required for executing processing operations. A processing complex, such as a CPU or a GPU, includes a first set of cores comprising one or more fast cores and a second set of cores comprising one or more slow cores. A processing mode of the processing complex may switch between a first operating mode and a second operating mode based on one or more of workload characteristics, performance characteristics of the first and second sets of cores, performance characteristics of the first and second sets of cores, and operating conditions of the processing complex. A controller causes the processing operations to be performed by either the first group of cores or the second group of cores to achieve the lowest total power consumption.SUMMARY OF THE INVENTIONThe object on which the invention is based is to improve the performance (performance policy) of a computing platform with respect to efficiency and responsiveness. This object is achieved by the subject matter of the independent claims. Further advantageous embodiments are specified in the dependent claims.BRIEF DESCRIPTION OF THE DRAWINGSThe various advantages of the embodiments of the present invention will become apparent to those skilled in the art upon reading the following specification and appended claims, and upon reference to the following drawings, in which: FIG. 1 is a block diagram of an example of a scheme for managing performance, according to an embodiment; FIG. 2 is a graphical representation of an example of a set of workload scalability relationships, according to an embodiment; FIG. 3 is a flow diagram of an example of a method for managing performance, according to an embodiment; and FIG. 4 is a block diagram of an example of a platform according to an embodiment.DETAILED DESCRIPTIONFIG. 1 illustrates a scheme for managing performance in a computing platform such as a mobile device with computing functionality (e.g., a personal digital assistant / PDA, a laptop, a smart tablet), communication functionality (e.g., a wireless smart phone), mapping functionality, media playback functionality (e.g., smart television / TV), or any combination thereof (e.g., mobile internet device / MID). The illustrated scheme may also be used with a stationary platform, such as a server, a desktop computer, a workstation, etc. In the illustrated example, a performance controller 10 receives scalability information 12 and quality of service (QoS) information 14 associated with the workload 18 to be processed and / or scheduled for processing on the platform. The workload 18 may include instructions / operations associated with the activities, such as for network communication (e.g., transmission and / or reception), storage communication (e.g., read and / or write), computational processing (e.g., general operations, graphics operations), etc.Scalability can be considered a ratio of the percentage change in performance of a system or subsystem (requested) to a percentage change in estimated performance (provided) achieved by the workload. For example, if a workload experiences 5% higher performance as processor performance increases 10%, scalability may be 5% / 10%=50% (0.5). The realized performance for a particular workload may be estimated in various ways. The determination of scalability can be a function of the type of workload and / or the hardware processing of the workload. For example, a non-graphics workload may be considered to have no correlation (thus 0% scalability) to the operating frequency of a graphics processing unit (GPU), whereas the same workload may have 80% scalability with respect to the core (processor core) of the central processing unit (CPU), 50% scalability with respect to a network controller, and 70% scalability with respect to main memory.While the operating frequency may be an example of a requested performance metric, other parameters and / or variables may also be used. For example, the number of active cores in a multi-core system, the amount of memory available, the operating voltage, etc. may also be used to request a particular level of performance.The performance controller 10 may also obtain other information, such as power consumption information 16 from one or more areas (e.g., devices, subsystems, modules, etc.) of the platform, thermal conditions / constraints of the platform (not shown), etc., where the scalability information 12, QoS information 14, power consumption information 16, and thermal conditions may be used to manage a performance policy 20 for the platform. As will be explained in more detail, consideration of workload scalability information 12 may allow performance controller 10 to make more efficient decisions regarding performance policy 20 and ultimately make the platform more responsive. Referring now to FIG. 2, a graph 22 is shown depicting the relationship between the requested performance and the provided performance for a group of workloads. In particular, the relationships in graph 22 may be understood as indicative of the scalability of the workload in the sense that higher scalable workloads may provide more performance per unit of requested performance than lower scalable workloads. For example, a curve 24 may correspond to a workload that is less scalable than a workload corresponding to a curve 26, where the scalability may be a function of one of many factors, such as network bandwidth, available memory, complexity of code, etc. Moreover, these factors may be efficiently quantified in a "productive cycle counter" that enables determination of the scalability of the workload.Thus, the workload scalability model described herein may be compared to driving a motor vehicle: the productive cycle counter may provide findings similar to sensor data, such as kilometers per hour data, gasoline consumption per liter data, road grade data, etc., wherein a performance controller, such as performance controller 10 (FIG. 1 ), may use one or more control registers to realize a particular performance (e.g., operating frequency, number of active cores, amount of available memory, operating voltage) in a similar manner to the operation of an accelerator pedal. For example, the performance controller may request more performance to obtain a particular provided performance if the productive cycle counter indicates that the workload has a relatively low scalability as a driver would press the accelerator pedal more heavily when a relatively strong slope is encountered. Similarly, the performance controller may request less performance to obtain the same delivered performance from a more scalable workload as a driver more easily presses the accelerator pedal when driving on a road without an incline (or slope). Simply stated, higher efficiency and other advantages may be achieved by making use of knowledge of the expected level of performance actually achieved from a particular requested level of performance.It is particularly emphasized that the performance controller may also use scalability information to prioritize workloads to utilize limited power / thermal resources with maximum efficiency when the system is constrained. Prioritizing scalable workloads may result in more tasks being accomplished over time (i.e., higher efficiency). However, higher scalability may sometimes also result in higher power consumption (e.g., CPU-bound workloads may substantially increase CPU performance). Therefore, if a power / thermal problem is detected for the core (versus platform), the most appropriate policy is to prioritize a less scalable workload or execute the scalable workload at a lower level of performance (i.e., core performance). The workload scalability information can be used in any case to substantially improve the performance policy.FIG. 3 illustrates a method 30 of managing performance in a computing platform. The method 30 may be implemented as a set of logic instructions stored in a machine- or computer-readable storage medium, such as random access memory (RAM), read only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., in configurable logic such as programmable logic arrays (PLAs), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), in fixed-functionality logic hardware using circuit technology such as application specific integrated circuit (ASIC), complementary metal oxide semiconductor (CMOS, Complementary Metal Oxide Semiconductor) or Transistor-Transistor Logic (TTL) technology, or any combination thereof. For example, computer program code for carrying out operations illustrated in method 30 may be written in any combination of one or more programming languages, including object oriented programming languages such as Java, Smalltalk, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages.The illustrated processing block 32 enables identification of a workload, such as network communication, storage communication, and / or compute-based processing of a workload. One or more hardware counters may be accessed at block 34, where the counters may include a productive cycle counter (e.g., PCNT), an actual cycle counter (e.g., ACNT), a nominal counter (e.g., MCNT), etc. The productive cycle counter may determine the number of unblocked cycles since the last reset of the counter, and the actual cycle counter may determine the number of total cycles since the last reset of the counter. As such, a so-called blocked cycle may be adjustable (e.g., via a programmable threshold), where the count of the resulting productive cycles may support different polling (cyclic polling) intervals and multiple consumer units, and may be easily converted to workload scalability. In block 36, the scalability of the identified workload may be determined based on the counter values. For example, the ratio of productive cycles (e.g., PCNT value) to actual cycles (e.g., ACNT value) may provide a useful metric of productivity / scalability of the workload in question. Thus, in this example, a ratio near 1 would correspond to relatively high scalability, whereas a ratio near 0 would correspond to relatively low scalability.A determination of one or more QoS conditions may be made at block 38, where the QoS conditions may include latency information and other quality-related information. Moreover, in the illustrated block 40, a power consumption of one or more areas of the platform is determined, wherein the power consumption information may be particularly useful for the settings of the mobile platform. At block 40, one or more thermal conditions for the platform may also be determined. Moreover, in block 42, workload may be prioritized and a performance level may be set based on scalability, QoS conditions, thermal conditions, and power consumption. The determining the performance level may include accessing one or more control registers. The illustrated method 30 therefore offers significant advantages in terms of efficiency and responsiveness over pure demand-based switching solutions (DBS) that are limited to QoS information.Variations of the illustrated method 30 may be readily made. For example, if scalability can be evaluated relatively quickly in the hardware, the determination of the workload in block 32 may be superfluous and can therefore be bypassed. Moreover, an operating system (OS) may provide QoS inputs regardless of whether the hardware knows the identity or type of workload to process. Moreover, the use of blocked versus unblocked cycles, as discussed with respect to blocks 34 and 36, may be a detail of the counter implementation particularly suitable for a CPU core. However, other scalability solutions may be more appropriate for other types of devices (e.g., memory, graphics, network connectivity, offloading computing tasks from the core (uncore)).Referring to FIG. 4, a mobile platform 44 is shown. Platform 44 may be a component of a mobile device with computing functionality (e.g., PDA, laptop, smart tablet), communication functionality (such as a wireless smart phone), imaging functionality, media playback functionality (e.g., smart TV), or any combination thereof (e.g., MID). In the illustrated example, platform 44 includes a battery 46 for powering platform 44, a system memory 56, a network controller 58, one or more user interface (UI) devices 60, a solid state hard disk drive (SSD) 62, and a system-on-chip (SoC) 48. The SoC 48 may include a processor 50 and an input / output (I / O) module 54, where the illustrated processor 50 includes an integrated memory controller (IMC) 52 and a core portion including one or more processor cores 64. The processor 50 and the I / O module 54 may alternatively be implemented on separate semiconductor devices depending on the situation.The illustrated I / O module 54, sometimes referred to as a chipset southbridge or south complex, acts as a host controller and communicates with the network controller 58, which may provide off-platform communication functionality for a wide variety of purposes, such as a mobile phone (e.g., W-CDMA (UMTS), CDMA2000 (IS-856 / IS-2000), etc.), WiFi (Wireless Fidelity, e.g., Institute of Electrical and Electronics Engineers / IEEE 802.11-2007, Wireless Local Area Network / LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications), 4G LTE (Fourth Generation Long Term Evolution), Bluetooth (e.g., IEEE 802.15.1-2005, Wireless Personal Area Networks), WiMax (e.g., IEEE 802.16-2004, LAN / MAN Broadband Wireless LANS), GPS (Global Positioning System), frequency spreading (e.g., 900 MHz), and other radio frequency (RF) telephony fields of use. I / O module 54 may also include one or more wireless hardware circuit blocks to support this functionality.System memory 56 may include, for example, double data rate (DDR) dynamic random access memory (SDRAM) modules, such as DDR3 SDRAM JESD79-3C standard, April 2008). The modules of system memory 56 may be integrated into a single inline memory module (SIMM), dual inline memory module (DIMM), small inline DIMM (SODIMM), etc. The SSD 62 may include one or more NAND (negated AND) chips and may be used to provide data storage in high capacity and / or with a very high degree of parallelism. Also possible are solutions that include NAND controllers implemented as separate ASIC controllers that are connected to the I / O module 54 via standard buses such as a serial ATA (SATA, e.g., SATA Rev. 3.0 specification, May 27, 2009, SATA International Organization / SATA-IO) bus or a PCI Express Graphics (PEG, e.g., Peripheral Components Interconnect / PCI Express x16 Graphics 150W-ATX specification 1.0, PCI Special Interest Group) bus. The SSD 62 may also be used as a USB (Universal Serial Bus, e.g., USB Specification 3.0, USB Implements Forum) flash memory device.The illustrated cores 64 of the processor 50 may generally process workloads associated with one or more applications executing on the processor 50, where the workloads may be associated with communications performed via the network controllers 58 and / or in communication with the system memory 56 and / or the SSD 62. In particular, the cores 64 may be configured to execute workload logic 66 that identifies workloads associated with the platform 44, scalability logic 68 that determines the scalability of the workload, and management logic 70 that manages the performance policy of the platform 44 based at least in part on the scalabilitys. Workload logic 66, scalability logic 68, and management logic 70 may therefore operate similarly to performance controller 10 (FIG. 1 ) discussed above.In one example, the SoC 48 further includes a productive cycle counter 72 and an actual cycle counter 74, wherein the scalability logic 68 accesses the counters 72, 74 and determines the ratio of the productive cycles to the actual cycles to determine the scalabilitys. The SoC 48 may also include one or more control registers 76 that are used by the management logic 70 to set the performance levels associated with the performance policies. For example, management logic 70 could write one or more parameter values to control registers 76 based on workload scalabilitys to place processor 50 and / or platform into one or more Advanced Configuration and Power Interface (ACPI Specification, Rev. 5.0a, Dec. 6, 2011) performance states.Thus, the techniques described herein may explain reactions of hardware (as provided desired / requested versus delivered) without presenting the complexity of many scalability-related factors, such as network bandwidth, available memory, complexity of code, etc. Moreover, the general costs of achieving a different rate of performing tasks in a variety of settings and environments may be formulated.Embodiments may therefore include a method including determining scalability of a workload associated with the platform. The method may also provide for managing a performance policy of the platform based at least in part on the scalability of the workload.Embodiments may also include a non-transitory computer readable storage medium having an instruction set that, when executed by a processor, cause a platform to determine scalability of a workload associated with a platform. The instructions, when executed, may also cause the platform to manage a performance policy of the platform based at least in part on the scalability of the workload.Embodiments may also include an apparatus including scalability logic for determining scalability of a workload associated with a platform. The apparatus may also include management logic to manage a performance policy of the platform based at least in part on the scalability of the workload.Embodiments may also include a mobile platform including a battery to power the platform, a memory module, and a SoC coupled to the memory module, the SoC including scalability logic to determine scalability of a workload associated with the platform. The SoC may also include management logic to manage a performance policy of the platform based at least in part on the scalability of the workload.Embodiments of the present invention are usable for use with all types of semiconductor integrated circuit ("IC") chips. Examples of these IC chips include, but are not limited to, processors, controllers, chipset components, PLAs, memory chips, network chips, SoCs, SSD / NAND controller ASICs, and the like. Moreover, in some drawings, signal line lines are represented by lines. Some may be different to indicate more basic signal paths, have a numbering label to indicate a number of the basic signal paths, and / or be provided with arrows at one end or multiple ends to indicate the primary direction of information flow. However, this should not be construed as limiting. Rather, such added detail may be used in conjunction with one or more example embodiments to facilitate easier understanding of a circuit. All illustrated signal lines, whether with or without further information, may in fact comprise one or more signals that may run in multiple directions and may be implemented with any suitable type of signal scheme, for example digital or analog lines that may be implemented with differential line pairs, fiber optic lines, and / or single-ended lines.Exemplary sizes / models / values / ranges have been given, although embodiments of the present invention are not limited to these. As manufacturing processes (e.g., photolithography) become more sophisticated over time, it is believed that smaller size devices could be manufactured. Moreover, known current / ground connections to IC chips and other components may or may not be illustrated in the figures for ease of illustration and discussion, and thus not to obscure certain aspects of embodiments of the invention. Furthermore, arrangements may be presented in block diagram form to avoid obscuring embodiments of the invention, and also in view of the fact that specifics regarding the implementation of such block diagram arrangements are highly dependent upon the platform on which the embodiment is to be implemented, i.e., such specifics should be within the purview of those skilled in the art. While specific details (e.g., circuits) are set forth to describe example embodiments of the invention, it should be apparent to those skilled in the art that embodiments of the invention may be practiced without or with variation of the specific details. The description is therefore to be regarded as illustrative rather than restrictive.The term "connected" may be used herein to refer to any type of relationship, directly or indirectly, between the respective components, and may be applied to electrical, mechanical, fluid, optical electromagnetic, electromechanical, or other connections. Moreover, the terms "first," "second," etc. are used herein only for ease of discussion and do not have any particular temporal or chronological significance unless otherwise indicated.It will be apparent to those skilled in the art from the above description that the broad techniques of the embodiments of the present invention may be implemented in a variety of different forms. Therefore, while the embodiments of the invention have been described in connection with specific examples thereof, the true scope of the embodiments of the invention should not be limited herein, as other modifications will become apparent to one skilled in the art upon a study of the drawings, the specification, and the following claims.

Claims

A mobile platform (44), comprising: a battery (46) for powering the mobile platform (44); a memory module (56); and a system on chip, SoC, (48) coupled to the memory module (56), the SoC (48) comprising scalability logic (68) for determining scalability of a workload (18) associated with the mobile platform (44), and management logic (70) for managing a performance policy (20) of the mobile platform (44) based at least in part on the scalability of the workload (18), and wherein the scalability logic (68) is configured to determine a ratio of the requested performance to the delivered performance to determine the scalability.The mobile platform (44) of claim 1, wherein the SoC (48) further comprises a productive cycle counter (72), and the scalability logic (68) is operable to access the productive cycle counter to determine the ratio of the requested performance to the provided performance.The mobile platform (44) of claim 1, wherein the management logic (70) is set to a performance level of the mobile platform (44) for managing the performance policy (20).The mobile platform (44) of claim 3, wherein the SoC (48) further comprises one or more control registers (76), and the management logic (70) is to access at least one of the one or more control registers (76) to set the performance level.The mobile platform (44) of claim 1, wherein the management logic (70) for prioritizing the workload is for managing the performance policy (20).The mobile platform (44) of any of claims 1 to 5, wherein the performance policy (20) is to be further managed based on one or more Quality of Service, QoS, conditions of the workload and a power consumption of the mobile platform (44).An apparatus (48) comprising: scalability logic (68) for determining scalability of a workload (18) associated with a platform (44); and management logic (70) for managing a performance policy (20) of the platform (44) based at least in part on the scalability of the workload (18), wherein the scalability logic (68) is configured to determine a ratio of the requested performance to the provided performance to determine the scalability.The apparatus (48) of claim 7, wherein the scalability logic (68) is configured to access a productive cycle counter (72) to determine the ratio of the requested performance to the provided performance.The apparatus (48) of claim 7, wherein the management logic (70) is set to a performance level of the platform (44) for managing the performance policy (20).The apparatus (48) of claim 9, wherein the management logic (70) is to access one or more control registers (76) on the platform to set the performance level.The apparatus (48) of claim 7, wherein the management logic (70) is for prioritizing the workload to manage the performance policy (20).The apparatus (48) of any of claims 7 to 11, wherein the performance policy (20) is to be further managed based on one or more Quality of Service, QoS, conditions of the workload and a power consumption of the platform (44).A method (30) comprising: determining (36) scalability of the workload (18) associated with a platform (44); and managing (42) a performance policy of the platform (44) based at least in part on the scalability of the workload (18), wherein determining the scalability comprises determining a ratio of the requested performance to the provided performance.The method (30) of claim 13, wherein determining the ratio of the requested performance to the delivered performance includes accessing a productive cycle counter (72).The method (30) of claim 13, wherein managing the performance policy includes setting a performance level of the platform (44).The method (30) of claim 15, wherein the determining the performance level includes accessing one or more control registers (76) on the platform (44).The method (30) of claim 13, wherein managing the performance policy (20) includes prioritizing the workload (18).The method (30) of any of claims 13 to 17, wherein the performance policy (20) is to be further managed based on one or more Quality of Service, QoS, conditions of the workload and a power consumption of the platform (44).A non-transitory computer readable storage medium comprising an instruction set that, when executed by a processor (50), causes a platform (44) to: determine scalability of a workload (18) associated with the platform (44); and manage a performance policy (20) of the platform (44) based at least in part on the scalability of the workload (18), wherein the instructions, when executed, cause the platform (44) to determine a ratio of the requested performance to the delivered performance to determine the scalability.The medium of claim 19, wherein the instructions, when executed, cause the platform (44) to access a productive cycle counter (72) to determine the ratio of the requested performance to the provided performance.The medium of claim 19, wherein the instructions, when executed, cause the platform to set a performance level of the platform to manage the performance policy.The medium of claim 21, wherein the instructions, when executed, cause the platform (44) to access one or more control registers (76) on the platform (44) to set the performance level.The medium of claim 19, wherein the instructions, when executed, cause the platform (44) to prioritize the workload (18) to manage the performance policy (20).The medium of any of claims 19 to 23, wherein the performance policy (20) is to be further managed based on one or more quality of service, QoS, conditions of the workload (18) and a power consumption of the platform (44).

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