Device and method for rapid phase locking

Abstract

Integrated circuit (IC), comprising: a node to provide a reference clock; a digitally controlled oscillator (DCO) to generate an output clock; a divider coupled to the DCO, the divider for dividing the output clock and generating a feedback clock; Control logic designed to reset the DCO and the divider or deactivated, and designed to release the reset synchronously with the reference clock; and a clock distribution network for receiving an output clock from the DCO, wherein the divider divides a clock received from the clock distribution network.

Description

BACKGROUND

[0001] Power management granularity and power state exit latencies are affected by the lock time of a phase-locked loop (PLL). One way to accelerate the lock time for a PLL is to apply look-up tables (LUTs), which store PLL signal conditions for fast locking. However, such conventional uses of LUTs still have long phase lock times (e.g., 40 to 100 reference cycles). Power management control can conserve power through clocked control and, to some extent, by turning off PLLs when they are not in use. However, a limiting factor for the power reduction from power management of the entire system's clock generation is the latency of PLL turn-on. Since processors are expected to operate in various power states (e.g., sleep, hibernate, normal, etc.), the PLL's power-on latency is significantly lower than the PLL's power-on latency.), transitioning from one power state to another may cause the PLL to relock, which consumes time and power. US 2012 0 319 748 A1 discloses an integrated circuit comprising a node for providing a reference clock, a digitally controlled oscillator (DCO) for generating an output clock, a divider coupled to the DCO, the divider for dividing the output clock and generating a feedback clock; and control logic configured to reset or disable the DCO and the divider, and configured to release the reset synchronously with the reference clock.

[0002] The present invention provides an integrated circuit according to claim 1 and a system according to claim 10.

[0003] The respective subclaims relate to respective advantageous embodiments thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The embodiments of the disclosure will become more fully understood from the following detailed description and the accompanying drawings of various embodiments of the disclosure, which, however, are not to be construed as limiting the disclosure to the specific embodiments, but are for purposes of explanation and understanding only. Fig. 1 illustrates a digital phase locked loop (DPLL) for fast locking according to an embodiment of the disclosure. Fig. 2 illustrates a digitally controlled oscillator (DCO) of the DPLL configured to be reset for quick locking according to one embodiment of the disclosure. Fig. 3 illustrates a waveform graph illustrating the operation of the quick locking scheme according to one embodiment of the disclosure. Fig. 4 illustrates a waveform graph illustrating the operation of the fast locking scheme with the effect of clock distribution, with both the DCO and the divider being reset, according to one embodiment of the disclosure. Fig. 5 illustrates a waveform graph illustrating the operation of the fast lock scheme with the effect of clock distribution with only the divider being reset, according to one embodiment of the disclosure. Fig. 6 illustrates a finite state machine (FSM) for implementing the fast locking scheme according to an embodiment of the disclosure. Fig. 7 illustrates a DPLL with fast frequency calibration using a time derivative method according to an embodiment of the disclosure. Fig. 8 illustrates a state machine for fast frequency calibration according to an embodiment of the disclosure. Fig. 9 illustrates graphs depicting frequency and phase with and without phase error nulling techniques according to one embodiment of the disclosure. Fig. 10 illustrates a DPLL with phase error nulling according to an embodiment of the disclosure. Fig. 11A-C illustrate a flowchart for quick locking a DPLL according to an embodiment of the disclosure. Fig. 12 is a smart device or a computer system or system chip (SOC) including a DPLL with fast-lock circuitry according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0005] The embodiments describe a digital phase-locked loop (DPLL), where the DPLL achieves phase locking in only a few reference clock (RefClk) cycles (e.g., 2 to 6 reference cycles after frequency locking). In one embodiment, a controller (or a finite state machine) resets the frequency divider and / or the digitally controlled oscillator (DCO) and then releases both the divider and / or the DCO from reset such that an edge of the DCO output clock (OutClk) is synchronized with an edge of the reference clock (RefClk). In such an embodiment, the feedback clock (FBClk), which is an output of the divider, is phase-aligned with the RefClk.

[0006] Although the embodiments are described with reference to a DCO for a DPLL, other types of oscillators and PLLs may also be used. For example, a voltage-controlled oscillator (VCO) or an LC (inductor-capacitor) tank-based oscillator may be used.

[0007] In one embodiment, the controller also reduces the phase error between RefClk and FbClk to a very small value. In such an embodiment, the time-to-digital converter (TDC) does not need to cover a large phase error range. Reducing the TDC coverage range is reflected as power and area savings in the DPLL. In such an embodiment, FbClk (i.e., the low-frequency version of OutClk) can be used by the TDC to realize further power savings in the DPLL.

[0008] Typically, the frequency lock required to lock the PLL requires many reference clock cycles. In one embodiment, a fast frequency calibration method and circuit are provided that use a TDC to frequency lock the PLL in a pair of reference clock cycles. In one embodiment, the fast frequency calibration method and circuit adjust the DCO frequency control code from a previous lock upon the occurrence of frequency drift.

[0009] In one embodiment, the DPLL provides hardware for instantaneous (or substantially instantaneous) phase locking using a phase error zeroing technique (also referred to as a phase shift subtraction technique). In one embodiment with the phase error zeroing technique, the DPLL achieves near-instantaneous locking, or locking on the first edge of the RefClk signal cycle, instead of the many RefClk signal cycles typically required without this technique.

[0010] In one embodiment, the fast-lock process following PLL reactivation may combine any or all of the methods discussed in the disclosure. For example, the fast-lock process may include: restoring the stored frequency control codeword for the DCO; correcting the frequency to compensate for temperature drift (i.e., performing fast frequency calibration); resetting the divider and / or the DCO depending on the clock-giving network delay; and correcting the phase error using loop dynamics and the phase error nulling method.

[0011] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. However, those skilled in the art will recognize that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the present disclosure.

[0012] It should be noted that in the corresponding drawings of the embodiments, signals are depicted with lines. Some lines may be thicker to indicate multi-component signal paths and / or may have arrows at one or more ends to indicate the primary information flow direction. Such depictions are not intended to be limiting. Rather, the lines may be used in conjunction with one or more example embodiments to convey a better understanding of a circuit or logical unit. Each depicted signal, as dictated by design requirements or preferences, may in fact comprise one or more signals capable of traveling in any direction, and may be implemented with any suitable signal scheme type.

[0013] Throughout this specification and in the claims, the term "connected" refers to a direct electrical connection between connected things without any devices in between. The term "coupled" refers to either a direct electrical connection between connected things or an indirect connection through one or more passive or active intervening devices. The term "circuit" refers to one or more passive and / or active components arranged to cooperate with each other to provide a desired function. The term "signal" refers to a current signal, voltage signal, or data / clock signal. The meaning of "a" and "the" includes plural references. The meaning of "in" includes "in" and "on."

[0014] The term "scaling" generally refers to converting a design (schematic and layout) from one process technology to another. The term "scaling" also refers to reducing the size of the layout and facilities within the same technology node. The term "scaling" can also refer to adjusting (e.g., slowing down) a signal frequency relative to another parameter, such as power supply levels. The terms "substantially," "at," "approximately," "near," and "about" are generally understood to mean within + / - 20% of a target value.

[0015] Unless otherwise noted, the use of the ordinal numbers "first", "second", "third", etc., to describe a common object merely indicates that reference is made to different instances of similar objects, and is not intended to imply that the objects so described must be in any particular temporal, spatial, rank, or any other order.

[0016] For the purposes of the embodiments, the transistors are metal-oxide-semiconductor (MOS) transistors, which include drain, source, gate, and ground terminals. The transistors may also include tri-gate and FinFET transistors, GAAC (Gate All Around Cylindrical) transistors, or other devices implementing transistor functionality, such as carbon nanotubes or spintronic devices. Source and drain terminals may be identical terminals and are used interchangeably herein. Those skilled in the art will appreciate that other transistors, such as bipolar junction transistors (BJT PNP / NPN, BiCMOS, CMOS, eFET, etc.), may also be used without departing from the scope of the disclosure. The term "MN" refers to an n-type transistor (e.g., NMOS, NPN BJT, etc.), and the term "MP" refers to a p-type transistor (e.g., PMOS, PNP BJT, etc.).

[0017] Fig. 1 illustrates a digital phase-locked loop (DPLL) 100 for fast locking according to one embodiment of the disclosure. In one embodiment, the DPLL 100 includes a phase detector (PD) 102, a TDC 103, a digital controller 104, a digital loop filter 105, a DCO 106, a clock distributor 107 (optional), and a frequency divider 108. In one embodiment, the PD 102 compares a RefClk signal and an FbClk signal to generate phase difference signals. In one embodiment, the phase difference signals are uplink and downlink signals. In one embodiment, the TDC 103 also receives the RefClk signal and FbClk signals to generate a phase error signal. Herein, terms for signals and nodes that carry these signals are used interchangeably. For example, FbClk is used to represent an FbClk signal or an FbClk node, depending on the context of the sentence.

[0018] In one embodiment, digital controller 104 (or finite state machine) receives the phase error, up-conversion, and down-conversion signals to generate a control signal for adjusting coefficients of digital filter 105 according to the phase error and / or up-conversion and down-conversion signals. In one embodiment, digital filter 105 generates code for regulating the oscillation frequency of DCO 106. In one embodiment, the output of the DCO (i.e., OutClk) is received directly by frequency divider 108, which generates the FbClk signal by down-dividing the OutClk signal. In one embodiment, an output Outb4Clk of DCO 106 is received by a clock distribution network 107, which then provides OutClk to divider 108. In one embodiment, digital controller 104 generates resetDiv and / or resetDCO signals to reset divider 108 and DCO 106, respectively.

[0019] In one embodiment, after the DPLL 100 is locked (i.e., the RefClk signal and the FbClk signal are substantially in phase), the code for controlling the oscillation frequency of the DCO 106 is stored in memory. In one embodiment, when the DPLL 100 is locked, the coefficients of the digital filter 105 are also stored in memory. The following fast-locking embodiments are discussed with respect to reactivating and relocking the DPLL after it is turned off and enters a low-power state.

[0020] In one embodiment, digital controller 104 causes the DCO 106 and divider 108 to be reset when the clock distribution 107 is very small or nonexistent. The term "reset" herein generally refers to causing a circuit to enter a deterministic state. "Releasing from reset" refers to terminating the reset process, allowing the circuit (which was previously reset) to resume normal operation.

[0021] In one embodiment, the DCO 106 and divider 108 are reset and enabled synchronously with the RefClk signal. In such an embodiment, the divider 108 begins dividing the OutClk signal synchronously with the RefClk signal. In one embodiment, the DPLL 100 acquires frequency lock before the digital controller 104 resets the divider 108 and / or the DCO 106. In such an embodiment, the digital controller 104 applies the digital code previously stored in a lookup table or memory. In this embodiment, the falling (or rising) edge of the FbClk signal is synchronized to the falling (or rising) edge of the RefClk signal with minimal phase error (which is the delay from the output of the DCO 106 to the output of the divider 108).In one embodiment, the falling (or rising) edge of the OutClk (or Outb4Clk) signal is synchronized with the falling (or rising) edge of the RefClk signal. In one embodiment, the DPLL 100 can correct this small phase error in a very short time.

[0022] Fig. Figure 2 illustrates a DCO 200 of the DPLL 100 configured to be reset for quick locking according to an embodiment of the disclosure. It should be noted that the elements of Fig. 2 with the same reference numerals (or designations) as the elements in any other figure may operate or function in a similar manner to that described, but are not limited to that.

[0023] In one embodiment, the DCO 200 includes a plurality of delay cells coupled in series with each other and a ring for causing the DCO 200 to oscillate. To avoid obscuring embodiments, neither inputs nor circuit elements of the DCO 200 are shown. In this embodiment, the plurality of delay cells includes a logic gate 201 (e.g., NAND gate) and inverters 202, 203, 204, and 205. In one embodiment, an output node n1 of the logic gate 201 is coupled to a switch s1 and an input of the inverter 202. In one embodiment, an output node n2 of the inverter 202 is coupled to a switch s2 and an input of the inverter 203. In one embodiment, an output node n3 of the inverter 203 is coupled to a switch s3 and an input of the inverter 204.In one embodiment, an output node n4 of inverter 204 is coupled to a switch s4 and an input of inverter 205. In one embodiment, an output node n5 of inverter 205 is coupled to a switch s5 and an input of logic gate 201. In one embodiment, node n5 is coupled to the OutClk signal or the Outb4Clk signal. Although the embodiments illustrate a ring with five delay cells, any number of delay cells in a ring may be used to form a DCO. For example, for single-ended delay cells, an odd number of delay cells may be used in a ring, while for symmetrical delay cells, an even number of delay cells may be used in a ring.

[0024] In one embodiment, logic gate 201 receives the resetDCO signal from controller 104 to reset DCO 200. In one embodiment, the resetDCO signal is used to control switches s1 through s5 so that a known state is applied to nodes n1 through n5. In one embodiment, known states are applied to nodes n1 through n5 by coupling switches s1 through s5 to either Vdd (i.e., power supply) or Vss (i.e., ground), respectively. In this embodiment, switch s1 is configured to couple Vdd to node n1 when switch s1 is closed by the resetDCO signal. In this embodiment, switch s2 is configured to couple Vss to node n2 when switch s2 is closed by the resetDCO signal. In this embodiment, switch s3 is designed to couple Vdd to node n3 when switch s3 is closed by the resetDCO signal.In this embodiment, switch s4 is configured to couple Vss to node n4 when switch s4 is closed by the resetDCO signal. In this embodiment, switch s5 is configured to couple Vdd to node n5 when switch s5 is closed by the resetDCO signal. Other methods and means may be used to apply deterministic voltage levels to nodes n1 through n5 so that when the DCO 200 is reset, it stops oscillating and produces a stable, known output.

[0025] Fig. Figure 3 illustrates a graph 300 with waveforms illustrating the operation of the quick locking scheme according to an embodiment of the disclosure. It should be noted that the elements of Fig. 3 with the same reference numerals (or designations) as the elements in any other figure may operate or function in a similar manner to that described, but are not limited to that.

[0026] Here, the x-axis is time, and the y-axis is voltage. For each signal in Graph 200 except the phase_error signal, the y-axis runs from zero to Vdd volts. For the phase_error signal, the y-axis represents time. The first waveform from the top is the resetDCO signal. The second waveform from the top is the RefClk signal. The third waveform from the top is the Outb4Clk signal (i.e., the output of the DCO 106). The fourth waveform from the top is the FbClk signal. The fifth waveform from the top is the phase_error signal (i.e., the output of the TDC 103). The sixth signal from the top is a signal indicating a frequency (freq) lock signal.

[0027] In this embodiment, the clock distribution 107 is absent or negligible (i.e., when the delay of the clock distribution 107 is less than one cycle of Outb4Clk). As with respect to Fig. 1, after the DPLL 100 acquires frequency lock, the controller 104 causes the reset of the divider 108 and the DCO 106, respectively, through the resetDiv and resetDCO signals. The low pulse of resetDCO indicates a reset operation (i.e., an active low reset). During the reset operation, Outb4Clk is maintained at a stable, non-oscillating voltage level (in this case, a Vdd level). In this embodiment, the resetDiv signal causes the reset of the divider 108 so that FbClk is zero. In one embodiment, after one RefClk cycle, the resetDCO and resetDiv signals are released (i.e., the reset operation ends) such that the falling (or rising) edge of the Outb4Clk signal is synchronized with the falling (or rising) edge of the FbClk signal. As soon as the reset is released, the DCO 106 begins to oscillate.In this example, phase_error begins to settle to a steady-state peak-to-peak state at a mean of zero (ps) level, indicated by the "lock" time region. Approximately four RefClk signal cycles after reset is enabled, the DPLL 100 achieves phase lock, indicated by the "locked" time region.

[0028] In one embodiment, divider 108 includes counters (not shown) that can be reset by the resetDiv signal. In one embodiment, to reset divider 108, its counters are reset and stopped from counting. The counters can remain in reset until the resetDiv signal indicates a reset enable operation, where the counters count to cause the FbClk signal edge to synchronize with the RefClk signal edge. In one embodiment, to synchronize an edge (rising or falling) of the FbClk signal with an edge (rising or falling) of the RefClk signal, the resetDiv signal causes divider 108 to be released from reset such that the counter value equals half the value of the counter setting. In such an embodiment, falling and rising edges of the FbClk signal are generated when the counter value equals the counter setting.

[0029] With further reference to Fig. 1, the reset scheme for resetting both the DCO 106 and the divider 108 can also be applied to DPLLs with small clock slicing 107 (i.e., clock slicing with low propagation delay). In this embodiment, the delay of the clock slicing 107 contributes to the phase error (i.e., phase_error) between the RefClk signal and the FbClk signal, i.e., the phase error after resetting the DCO 106 and the divider 108 and their release from reset may depend on the delay of the clock slicing 107. Here, as the delay of the clock slicing 107 increases, the time it may take the DPLL 100 to phase lock may become longer than when there is no clock slicing. However, the reset scheme of the embodiments still improves the phase lock time over conventional fast phase lock schemes.

[0030] Fig. 4 illustrates a waveform graph 400 illustrating the operation of the fast locking scheme with the effect of clock distribution, where both the DCO 106 and the divider 108 are reset, according to one embodiment of the disclosure. It should be noted that the elements of Fig. 4 with the same reference numerals (or designations) as the elements in any other figure may operate or function in a similar manner to that described, but are not limited to that.

[0031] Here, the x-axis is time, and the y-axis is voltage. For each signal in Figure 400, the y-axis runs from zero to Vdd volts. The first waveform from the top is the resetDCO signal. The second waveform from the top is the RefClk signal. The third waveform from the top is the Outb4Clk signal (i.e., the output of the DCO 106). The fourth waveform from the top is the OutClk signal (i.e., the output of the clock distribution 106). The fourth waveform from the top is the FbClk signal.

[0032] As with regard to Fig. As discussed in Figure 1, after the DPLL 100 acquires frequency lock, the controller 104 causes the reset of the divider 108 and the DCO 106, respectively, through the resetDiv and resetDCO signals. The low pulse of the resetDCO signal indicates a reset operation (i.e., an active low reset). During the reset operation, the Outb4Clk signal and the OutClk signal (after a delay of the clock distributor 107) are maintained at a stable, non-oscillating voltage level (in this case, a Vdd level). In this embodiment, the resetDiv signal causes the reset of the divider 108, so that the FbClk signal is zero. In one embodiment, after one RefClk signal cycle, the resetDCO and resetDiv signals are released (ie, the reset operation ends) such that the falling (or rising) edge of the Outb4Clk signal is synchronized with the falling (or rising) edge of the FbClk signal.Once reset is enabled, DCO 106 begins to oscillate. This embodiment may have some phase error, as illustrated by the two vertical dashed lines on the FbClk signal pulse at right, but the phase error is small enough to keep DPLL 100 locked. Again, in this embodiment, after enabling and enabling reset, the lock time is reduced to a few RefClk signal cycles.

[0033] With further reference to Fig. 1, in one embodiment, the controller 104 only resets the divider 108 (i.e., the DCO 106 is not reset) when the clock distribution is long and has a large delay (e.g., the clock distribution delay is significantly greater than one period of the Outb4Clk signal). In this embodiment, the DCO 106 continues to oscillate when the divider 108 is reset. In such an embodiment, the delay of the clock distribution 107 does not affect the phase error because the DCO 106 continues to oscillate. In one embodiment, the rising (or falling) edge of the FbClk signal is synchronized with the rising (or falling) edge of the RefClk signal when the reset is released. In one embodiment, the divider 108 is modified to be a double-edge triggered divider to minimize the worst-case delay of the loop divider (e.g.,1 OutClk cycle) to half an OutClk cycle, and consequently reduce the worst-case phase error between RefClk and FbClk after the reset signal is released to half an OutClk cycle.

[0034] Fig. 5 illustrates a graph 500 with waveforms illustrating the operation of the fast locking scheme with the effect of clock distribution, with only the divider 108 being reset, according to one embodiment of the disclosure. It should be noted that the elements of Fig. 5 with the same reference numerals (or designations) as the elements in any other figure may operate or function in a similar manner to that described, but are not limited to that.

[0035] Here, the x-axis is time, and the y-axis is voltage. For each signal in graph 500, the y-axis runs from zero to Vdd volts. The first waveform from the top is the resetDCO signal. The second waveform from the top is the RefClk signal. The third waveform from the top is the OutClk signal (i.e., the output of the DCO 106). The fourth waveform from the top is the FbClk signal. In this embodiment, the DCO 106 continues to oscillate when the controller 104 resets the divider 108 through the resetDiv signal.

[0036] In one embodiment, controller 104 adjusts coefficients of digital filter 105 when reset (resetDIV and / or resetDCO) is enabled. In such an embodiment, controller 104 adjusts filter coefficients to increase the bandwidth of DPLL 100 to quickly achieve phase lock.

[0037] Fig. Figure 6 illustrates a finite state machine (FSM) 600 for implementing the fast locking scheme according to an embodiment of the disclosure. It should be noted that the elements of Fig. 6 with the same reference numerals (or designations) as the elements in any other figure may operate or function in a similar manner to that described, but are not limited to that.

[0038] In one embodiment, the controller 104 implements the FSM 600. In one embodiment, upon reactivation at block (or state) 601, the DPLL 100 proceeds to phase lock acquisition. At block 601, the FSM 600 samples an output of a frequency comparator (not shown) and applies a binary search to lock the frequency near the target frequency. During the execution of block 601, the controller 104 periodically checks for frequency lock, as indicated by arrow 602. If frequency lock is acquired, as indicated by arrow 603, the FSM 600 proceeds to block 604. In one embodiment, after acquiring frequency lock, the FSM 600 transitions to the phase detector 102 and the TDC 103 to lock the phase and correct the frequency error linearly through a proportional-integral filter (or digital filter 105).

[0039] At block 604, the controller 104 determines whether an intermediate clock distribution network 107 is present between the DCO 106 and the divider 108. If there is a clock distribution 107, then it is determined whether the delay due to the clock distribution 107 is less than or greater than one cycle of Outb4Clk. If the delay due to the clock distribution 107 is less than one cycle of Outb4Clk, or if the clock distribution 107 is not present, then the controller 104 asserts reset signals resetDiv and resetDCO for the divider 108 and the DCO 106, respectively. If the delay due to the clock distribution 107 is significantly greater than one cycle of the Outb4Clk signal, then the controller 104 asserts only the resetDiv signal for the divider 108. At block 601, the code for controlling the oscillation frequency of the DCO 106 is also stored in a memory area.The stored code is applied with the reset signal at block 604 to bring the DCO oscillation frequency as close as possible to the target frequency when the reset is enabled.

[0040] After resetting the divider 108 and / or the DCO 106, the FSM 600 proceeds to block 606 on the next reference clock cycle, as indicated by arrow 605. At block 606, the divider 108 and / or the DCO 106 are released from the reset operation and allowed to function normally. In such an embodiment, the divider 108 begins dividing the OutClk signal synchronously with RefClk. That is, the falling (or rising) edge of the FbClk signal is synchronous with the falling (or rising) edge of the RefClk signal. Upon releasing the DPLL 100 from the reset state, the FSM 600 proceeds to block 608 on the next RefClk signal cycle, as indicated by arrow 607.

[0041] At block 608, the phase error is tracked by the TDC 103 and / or the phase detector 102. If the phase error is below a predetermined threshold, then the DPLL 100 is declared locked. In such an embodiment, the controller 104 continues monitoring the phase error, as indicated by arrow 609. In one embodiment, at the end of the lock acquisition, the digital code for the DCO 106 is stored in a lookup table or memory unit to be retrieved when the DPLL switches to that frequency. In one embodiment, if the DPLL 100 is commanded to operate at a different frequency, the FSM 600 proceeds to block 601 to begin the frequency determination process, as indicated by arrow 610.In one embodiment, the storage and recovery mechanism in the event of a temperature drift results in a small frequency error (± one frequency band due to the dense band coverage of the DCO), which is corrected by the fast frequency calibration in two RefClk cycles or by the normal frequency determination algorithm. In one embodiment, conditions in the dashed region 611 result in fast lock acquisition of the DPLL 100.

[0042] Fig. Figure 7 illustrates a DPLL 700 with fast frequency calibration using a time derivative method according to an embodiment of the disclosure. It should be noted that the elements of Fig. 7, elements in any other figure may operate or function in a manner similar to that described, but are not limited thereto, with the same reference numerals (or labels) as those in any other figure. To avoid complicating the embodiment, differences between DPLL 100 and DPLL 700 will be discussed.

[0043] In one embodiment, the DPLL 700 includes a frequency quick calibration unit 701 that calibrates the frequency of the DCO 106 using fine-tuning control of the DCO 106 such that the frequency of the FbClk signal matches the frequency of the RefClk signal within a predefined acceptable tolerance limit (e.g., within 5%). Typically, many RefClk signal cycles are used for a DPLL to achieve frequency lock. In one embodiment, the frequency quick calibration unit 701 enables the DPLL 700 to achieve frequency lock in two RefClk signal cycles.

[0044] In one embodiment, the frequency quick calibration unit 701 uses the TDC 103 to analyze the frequency difference between the RefClk and FbClk signals over two points in time—dT(i1) and dT(i2), where "i" is an integer representing a specific reference clock edge, or an instant in time after the DPLL reset, for which the TDC measurement is taken. For example, if the DPLL cycle i = 1, and measurement is started at i = 1, then i1 = 1 and i2 = 2 or greater. In some cases, i2 = 3 or i2 = 4 or greater. In such embodiments, each additional cycle provides a more accurate measurement against possible jitter in the RefClk. Embodiments are not limited to using the TDC 103 to determine the frequency difference.Other hardware and / or software (capable of phase measurement with sub-DCO period granularity) may also be used to determine the frequency difference between the RefClk and FbClk signals over two points in time. In one embodiment, the frequency quick calibration unit 701 uses the frequency difference information to adjust the DCO frequency control code (i.e., k * period delta, where "k" is a constant that depends on the gain of the DCO 106).

[0045] In one embodiment, before starting the frequency calibration process by the quick frequency calibration unit 701, fine and coarse control codes for the digital loop filter 105 and / or the DCO 106 are retrieved from a memory area 702 and applied to the digital loop filter 105 and / or the DCO 106. In such an embodiment, the frequency of the FbClk signal is close to the frequency of the RefClk signal, and the difference between these two frequencies is then calibrated by the digital loop filter 105 and / or the DCO 106.

[0046] In one embodiment, information from the TDC 103 regarding the two measurements is also used by the digital loop filter 105 to adjust its filter coefficients to achieve fast lock. For example, the digital loop filter 105 increases the bandwidth of the DPLL 700 to achieve frequency lock more quickly.

[0047] Fig. Figure 8 illustrates a state machine 800 for fast frequency calibration according to an embodiment of the disclosure. It should be noted that the elements of Fig. 8 with the same reference numerals (or designations) as the elements in any other figure may operate or function in a similar manner to that described, but are not limited to that.

[0048] At block 801, the first cycle of the TDC 103, dT(i1), is measured. At block 802, the second cycle of the TDC 103, dT(i2), is measured. At block 803, the time derivative period_delta(i) is measured as: period_delta(i)=(ΔdT) / (Δreference clock periods) period_delta(i)=(dT(i2)−dT(i1)) / (i2−i1)

[0049] At block 804, the oscillation frequency of the DCO 106 is adjusted by the frequency quick calibration unit 701 by multiplying "k" by period_delta(i), where "k" is a predetermined scalar value related to the gain of the DCO 106. In one embodiment, after adjusting the oscillation frequency of the DCO 106, the phase of the RefClk and FbClk signals is adjusted by resetting the divider 108 and / or the DCO 106 and releasing them from the reset state such that RefClk is synchronized with FbClk.

[0050] In one embodiment, instantaneous phase locking is provided in the DPLLs 100 / 700 using a phase error zeroing technique (also referred to as a phase shift subtraction technique). In one embodiment with the phase error zeroing technique, the DPLLs 100 / 700 achieve near-instantaneous locking, or locking on the first edge of the RefClk signal cycle, instead of the many RefClk signal cycles typically required without this technique.

[0051] Fig. Figure 9 illustrates graphs 900 depicting frequency and phase with and without phase error zeroing techniques according to one embodiment of the disclosure. It should be noted that the elements of Fig. 9 with the same reference numerals (or designations) as the elements in any other figure may operate or function in a similar manner to that described, but are not limited to that.

[0052] For Graph 901, the x-axis is time, and the y-axis is frequency (f) in Hz. For Graph 902, the x-axis is time, and the y-axis is phase (Φ). The solid waveforms in Graphs 901 and 902 are waveforms for the DPLLs without using the phase-zeroing technique. The dashed waveforms in Graphs 901 and 902 are waveforms for the DPLLs when the phase-zeroing technique is applied. The graphs show that the phase-error zeroing technique enables constant frequency and phase locking at the beginning of the time when the 100 / 700 DPLLs are activated, whereas a normal technique without the phase-zeroing technique requires significantly more time.

[0053] Fig. Figure 10 illustrates a DPLL 1000 with phase error zeroing according to an embodiment of the disclosure. It should be noted that the elements of Fig. 10 with the same reference numerals (or labels) as the elements in any other figure may operate or function in a manner similar to that described, but are not limited thereto. To avoid complicating the embodiments, differences between the DPLL 100 (or 700) and the DPLL 1000 will be discussed.

[0054] In one embodiment, the DPLL 1000 comprises a phase zeroing circuit 1001 and a subtractor 1002. In one embodiment, the circuit 1001 is an FSM for performing and / or controlling the phase zeroing process. In one embodiment, the subtractor 1002 subtracts an initially measured phase error (Phase_error0) from the TDC phase error measurement (Phase_error). Here, Phase_error0 is measured after resetting the divider 108, i.e., Phase_error0 is the first phase error measurement after synchronization. As discussed with respect to Fig. As discussed in Figure 1, synchronization is achieved by releasing the divider 108 and / or the DCO 106 from reset such that the falling (or rising) RefClk and FbClk signal edges are synchronized in time. In one embodiment, the output ('Phase_Error') of the subtractor 1002 is the corrected TDC phase error measurement and is applied to the digital filter 105 for all subsequent cycles until the DPLL 1000 is disabled (or turned off). The correct TDC phase error is expressed as: Phase_Error'=Phase_error−Phase_error0 In the above embodiment, the DPLL 1000 acquires phase lock in the first RefClk cycle after the reset of the divider 108 substantially immediately (i.e., taking into account non-ideal conditions that may introduce some delay in phase lock).

[0055] Fig. 11A to C illustrate flow diagrams for quick locking of a DPLL according to an embodiment of the disclosure. It should be noted that the elements of Fig. 11A to C with the same reference numerals (or designations) as the elements in any other figure may operate or function in a similar manner to that described, but are not limited to that.

[0056] In one embodiment, flowchart 1100a is executed in an open loop for frequency drift compensation. Once the DPLL 100 (700 or 1000) is reactivated, a determination is made at block 1101 whether a change in temperature (from the time the DPLL previously locked before being shut down until the current restart of the DPLL) is below a predetermined change in temperature. If the temperature change is below the predetermined temperature change, then the process proceeds from point A to Fig. 11B; otherwise, the process proceeds to block 1102. In one embodiment, if the elapsed time (e.g., the time the PLL is off) is below a threshold, the frequency calibration process may be skipped because the temperature drift is small enough to be ignored. In one embodiment, the elapsed time is measured by a counter that counts a number of RefClk cycles or other clock cycles.

[0057] At block 1102, an FbClk signal period drift ΔT is measured as related to Fig. 8 (i.e., blocks 801 to 803). At block 1103, a determination is made as to whether the period drift ΔT is within a threshold (e.g., a locking range for the DPLL). If the period drift ΔT is within the predetermined threshold, then the process proceeds from point A and C to Fig. 11B, otherwise the process proceeds to block 1104. At block 1104, the frequency of the DCO 106 is adjusted to compensate for the period drift ΔT, as described with respect to block 804 in Fig. 8. After completion of block 1104, the process proceeds from point B to Fig. 11B above.

[0058] In one embodiment, flowchart 1100b is also performed in an open loop. At block 1105, the process continues from 1100a for points A and B. At block 1105, a determination is made whether the first cycle of OutClk or Outb4Clk has a delay greater than half a period of OutClk or Outb4Clk, respectively, where the period of OutClk or Outb4Clk is the period the DPLL was previously locked. In one embodiment, block 1105 is executed in the design phase and is not part of the FSM. In such an embodiment, depending on the design, if the DCO startup latency and the DCO clock distribution delay together are greater than half a period of the DCO cycle (i.e., Outb4Clk cycle), then inputs A and B proceed to block 1107; otherwise, inputs A and B proceed to block 1106.

[0059] At block 1106, control releases the divider 108 and / or the DCO 106 from reset such that the falling (or rising) edge of the FbClk signal is synchronized with the falling (or rising) edge of the RefClk signal. The process then proceeds to points D and E of Fig. 11C. At block 1107, the controller 104 resets the DCO 106 and the divider 108, and releases the DCO 106 from reset so that the DCO 106 is enabled to oscillate. If the DCO 106 is an LC (inductor-capacitor) tank-based oscillator, then the DCO 106 is enabled (by the controller 104) to oscillate at block 1107. For example, an LC DCO with a long start-up time and / or an RO (ring oscillator) DCO with a long loop feedback may follow the process of block 1107. In one example, if the RO DCO has a shorter start-up time and a shorter feedback loop, the process may continue from block 1106. After activating the DCO 106 at block 1107, the process then proceeds to block 1108. At block 1108, the divider 108 is released from reset synchronously with the OutClk signal edge after synchronizing the reset with the RefClk signal edge.In one embodiment, after synchronizing the reset with the RefClk signal edge, the divider 108 is released from reset synchronously with the OutClk signal edge. In such an embodiment, the FbClk signal starts with a minimal phase error with respect to RefClk. The process then proceeds to point D of FIG. Fig. 11C above.

[0060] In one embodiment, flowchart 1100c performs a phase zeroing procedure. At block 1109, the process of 1100a for point C and the process of 1100b for point D continue. At block 1109, the phase error Φ0 (i.e., Phase_error0) between RefClk and FbClk is measured, and the process proceeds to 1110. At block 1110, the process of 1100b for point E continues. At 1110, Phase_error0 is recorded, and the phase zeroing procedure is performed, as with respect to Fig. 9 to 10. At block 1111, the DPLL loop is closed to achieve phase locking with static phase shift correction.

[0061] In one embodiment, the fast lock process after reactivating the PLL includes: restoring the stored frequency control codeword for the DCO; correcting the frequency to compensate for temperature drift (i.e., performing fast frequency calibration); resetting the divider and / or the DCO depending on the clock generation network delay; and correcting the phase error using loop dynamics and the phase error nulling method.

[0062] Fig. 12 is a smart device or a computer system or a system chip (SOC) including a DPLL with fast-lock circuits according to an embodiment of the disclosure. It should be noted that the elements of Fig. 12 with the same reference numerals (or designations) as the elements in any other figure may operate or function in a similar manner to that described, but are not limited to that.

[0063] Fig. Figure 12 illustrates a block diagram of one embodiment of a mobile device wherein flat interface connectors could be used. In one embodiment, computing device 1600 represents a mobile computing device, such as a computer tablet, a mobile phone or smartphone, a wireless-enabled e-book reader, or other wireless mobile device. It should be understood that certain components are depicted generically, and not all components of such a device are depicted in computing device 1600.

[0064] In one embodiment, computing device 1600 includes a first processor 1610 having a DPLL with fast-lock circuits according to the discussed embodiments. Other blocks of computing device 1600 may also include a PLL with fast-lock circuits. The various embodiments of the present disclosure may further include a network interface within 1670, such as a wireless interface, so that a system embodiment may be integrated into a wireless device, for example, a cellular phone or a personal digital assistant.

[0065] In one embodiment, processor 1610 (and / or processor 1690) may include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. Processor 1690 may be optional in one embodiment. The processing operations performed by processor 1610 include executing an operating platform or operating system on which applications and / or device functions execute. The processing operations include operations related to input / output (I / O) with a human user or with other devices, operations related to power management, and / or operations related to connecting computing device 1600 to another device. The processing operations may also include operations related to audio I / O and / or display I / O.

[0066] In one embodiment, computing device 1600 includes an audio subsystem 1620, which represents hardware components (e.g., audio hardware and audio circuitry) and software components (e.g., drivers, codecs) associated with providing audio functions for the computing device. Audio functions may include speaker and / or headphone output, as well as microphone input. Provisions for such functions may be integrated into computing device 1600 or connected to computing device 1600. In one embodiment, a user interacts with computing device 1600 by providing audio commands that are received and processed by processor 1610.

[0067] A display subsystem 1630 represents hardware components (e.g., display devices) and software components (e.g., drivers) that provide a visual and / or tactile display for a user to interact with the computing device 1600. The display subsystem 1630 includes a display interface 1632, which includes the respective screen or hardware device used to provide a display to a user. In one embodiment, the display interface 1632 includes logic separate from the processor 1610 to perform at least some processing related to the display. In one embodiment, the display subsystem 1630 includes a touchscreen (or touchpad) device that provides both output and input to a user.

[0068] An I / O controller 1640 represents hardware devices and software components related to interaction with a user. The I / O controller 1640 is configured to control hardware that is part of the audio subsystem 1620 and / or the display subsystem 1630. Additionally, the I / O controller 1640 represents a connection point for additional devices that connect to the computing device 1600 and through which a user can interact with the system. For example, devices that could connect to the computing device 1600 include microphone devices, speaker and stereo systems, video systems or other display systems, keyboard and keypad devices, or other I / O devices for use with specific applications, such as card readers, or other devices.

[0069] As previously mentioned, the I / O controller 1640 may interact with the audio subsystem 1620 and / or the display subsystem 1630. For example, input from a microphone or other audio device may provide input or commands for one or more applications or functions of the computing device 1600. Furthermore, audio output may be provided instead of or in addition to display output. In another example, if the display subsystem 1630 includes a touchscreen, the display device may also function as an input device that may be at least partially controlled by the I / O controller 1640. Additionally, additional buttons or switches may be present on the computing device 1600 to provide I / O functions controlled by the I / O controller 1640.

[0070] In one embodiment, I / O controller 1640 controls devices such as accelerometers, cameras, light sensors, or other environmental sensors, or other hardware that may be included in computing device 1600. The input may be part of a direct user interaction, as well as providing environmental input to the system to affect its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash to a camera, or other features).

[0071] In one embodiment, computing device 1600 includes power management 1650 that controls battery power usage, battery charging, and features related to power-saving operation. A storage subsystem 1660 includes storage devices for storing information in computing device 1600. The storage may include non-volatile (the state does not change when power to the storage device is interrupted) and / or volatile (the state is indeterminate when power to the storage device is interrupted) storage devices. Storage subsystem 1660 may store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of computing device 1600.

[0072] Elements of embodiments are also provided as a machine-readable medium (e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions for implementing any other processes discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD-ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase-change memory (PCM), or other types of machine-readable media for storing electronic or computer-executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) that is transmitted via data signals over a communications link (e.g., a modem or network connection) from a remote computer (e.g., a server) to a requesting computer (e.g., a client).

[0073] Connectivity 1670 includes hardware devices (e.g., wireless and / or wired connectors and communications hardware) and software components (e.g., drivers, protocol stacks) to enable computing device 1600 to communicate with external devices. Computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

[0074] Connectivity 1670 may include several different types of connectivity. Generally, computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 generally refers to cellular network connectivity provided by wireless carriers, such as through the Global System for Mobile Communications (GSM) or variants or derivatives, Code Division Multiple Access (CDMA) or variants or derivatives, Time Division Multiplexing (TDM) or variants or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular and includes personal area networks (such as Bluetooth, near field, etc.).), local area networks (such as Wi-Fi) and / or long-distance networks (such as WiMax) or other wireless communications.

[0075] Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) for establishing peripheral connections. It should be understood that computing device 1600 could be a peripheral ("to" 1682) for other computing devices, as well as have peripherals ("from" 1684) attached thereto. Computing device 1600 typically includes a "docking" connector for connecting to other computing devices for purposes such as handling (e.g., downloading and / or uploading, modifying, synchronizing) content on computing device 1600. In addition, a docking connector of computing device 1600 may enable connection to certain peripherals that enable computing device 1600 to control content output to, for example, audiovisual or other systems.

[0076] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1600 may establish peripheral connections 1680 through common or standards-based connectors. Common types may include a USB (Universal Serial Bus) connector (which may include a number of different hardware interfaces), DisplayPort, including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[0077] Reference in the specification to "a particular embodiment," "any embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The variously appearing terms "any embodiment," "a particular embodiment," or "some embodiments" do not necessarily all refer to the same embodiments. When the specification states that components, features, structures, or characteristics "may," "could," or "may" be included, those particular components, features, structures, or characteristics need not be included.If the specification or a claim refers to "one" element, this does not mean that only one of the elements is present. If the specification or a claim refers to "an additional" element, this does not preclude the presence of more than one of the additional elements.

[0078] Furthermore, the respective features, structures, functions, or characteristics may be combined in one or more embodiments as appropriate. For example, a first embodiment may be combined with a second embodiment whenever the respective features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0079] Although the disclosure has been described in connection with specific embodiments thereof, many alternatives, modifications, and alterations to such embodiments will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures, e.g., dynamic RAM (DRAM), may utilize the discussed embodiments. The embodiments of the disclosure are intended to encompass all such alternatives, modifications, and alterations so as to fall within the broad scope of the appended claims.

[0080] In addition, well-known power / ground connections for integrated circuit (IC) chips and other components may be shown in the presented figures or may not be shown for simplicity of illustration and discussion and in order not to obscure the disclosure. Furthermore, arrangements may be shown in block diagram form to avoid obscuring the disclosure and to reflect the fact that specific details regarding the implementation of such block diagram arrangements depend heavily on the platform in which the present disclosure is to be implemented, i.e., such specific details should be within the technical field of those skilled in the art. Those skilled in the art will appreciate that where specific details (e.g.,While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of the disclosure, the disclosure may be practiced without these specific details or with modification thereof. Accordingly, the description is to be considered illustrative rather than restrictive.

[0081] The following examples relate to further embodiments. Details in the examples may be used throughout one or more embodiments. Any optional features of the apparatus described herein may also be implemented with respect to a method or process.

[0082] For example, in one embodiment, an integrated circuit (IC) is provided comprising: a node for providing a reference clock; a digitally controlled oscillator (DCO) for generating an output clock; a divider coupled to the DCO, the divider for dividing the output clock and generating a feedback clock; and control logic configured to reset or disable the DCO and the divider, and configured to release the reset synchronously with the reference clock. In one embodiment, the DCO comprises a plurality of DCO cells and switches, each switch coupled to an output of a DCO cell of the plurality of DCO cells, and each switch configured to couple the output of the DCO cell to a known voltage level.

[0083] In one embodiment, the DCO is an LC-based DCO configured to be enabled to oscillate when reset is enabled. In one embodiment, the control logic is configured to control the switches. In one embodiment, the divider is configured to divide the output clock synchronously with the reference clock when the control logic enables reset. In one embodiment, the IC further includes a digital loop filter (DLF) coupled to provide a digital control word for the DCO. In one embodiment, the control logic is configured to adjust filter coefficients of the DLF when the control logic is to reset the divider.

[0084] In one embodiment, the IC further comprises a clock distribution network for receiving an output clock from the DCO, and wherein the divider divides a clock received from the clock distribution network. In one embodiment, the control logic resets only the divider if the delay of the clock distribution network is significantly greater than one cycle of the output clock. In one embodiment, the control logic resets the divider and the DCO if the delay of the clock distribution network is less than one cycle of the output clock.

[0085] In another example, a system is provided that includes: a memory; an integrated circuit coupled to the memory, the integrated circuit according to the IC discussed above; and a wireless interface to enable the integrated circuit to communicate with another device. In one embodiment, the integrated circuit forms part of a digital phase-locked loop (DPLL). In one embodiment, the system includes a display unit. In one embodiment, the display unit is a touchscreen.

[0086] In another example, a method for fast frequency calibration of a digital phase-locked loop (DPLL) is provided. In one embodiment, the method comprises: determining, at a first time, by a time-to-digital converter (TDC), a first time difference between the feedback clock and the reference clock; determining, at a second time, by the TDC, a second time difference between the feedback clock and the reference clock, the second time being longer than the first time; determining a difference between the first and second time differences; and adjusting an oscillation frequency of a digitally controlled oscillator (DCO) according to the determined difference. In one embodiment, the determining and adjusting operations are to be performed when the DPLL is reactivated from a low-power mode or an off-state.

[0087] In another example, an apparatus is provided comprising: a first node for providing a reference clock; a second node for generating a feedback clock; a time-to-digital converter (TDC) coupled to the first and second nodes for measuring phase errors between the reference clock and the feedback clock; a digital filter; and a controller for adjusting the measured phase error and providing the adjusted phase error to the digital loop filter.

[0088] In one embodiment, the controller adjusts the measured phase error by subtracting an initial measured phase error from the measured phase error. In one embodiment, the device further comprises a divider configured to be reset by the controller, wherein the TDC provides the initial measured phase error when the divider is reset.

[0089] In another example, a system is provided that includes: a memory; a processor coupled to the memory, the processor including a digital phase-locked loop (DPLL) according to the apparatus previously discussed; and a wireless interface to enable the processor to communicate with another device. In one embodiment, the system further includes a display unit.

[0090] An abstract is provided to enable the reader to determine the nature and essence of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

[1] Integrated circuit (IC) comprising: a node for providing a reference clock; a digitally controlled oscillator (DCO) for generating an output clock; a divider coupled to the DCO, the divider for dividing the output clock and generating a feedback clock; Control logic designed to reset the DCO and the divider or disabled, and designed to enable the reset synchronously with the reference clock; and a clock distribution network for receiving an output clock from the DCO, wherein the divider divides a clock received from the clock distribution network. [2] The IC of claim 1, wherein the DCO comprises a plurality of DCO cells and switches, each switch coupled to an output of a DCO cell of the plurality of DCO cells, and each switch configured to couple the output of the DCO cell to a known voltage level. [3] The IC of claim 1, wherein the DCO is an LC-based DCO configured to be enabled to oscillate when reset is enabled. [4] The IC of claim 2, wherein the control logic is configured to control the switches. [5] The IC of claim 1, wherein the divider is configured to divide the output clock synchronously with the reference clock when the control logic enables reset. [6] The IC of claim 1, further comprising a digital loop filter (DLF) coupled to provide a digital control word to the DCO. [7] The IC of claim 6, wherein the control logic is configured to adjust filter coefficients of the DLF when the control logic is to reset the divider. [8] The IC of claim 1, wherein the control logic only resets the divider when the delay of the clock distribution network is substantially greater than one cycle of the output clock. [9] The IC of claim 1, wherein the control logic resets the divider and the DCO when the delay of the clock distribution network is less than one cycle of the output clock. [10] System comprising: a memory; an integrated circuit coupled to the memory, the integrated circuit according to an integrated circuit according to any one of claims 1 to 9; and a wireless interface to enable the integrated circuit to communicate with another device. [11] The system of claim 10, wherein the integrated circuit forms part of a digital phase locked loop (DPLL). [12] The system of claim 10, further comprising a display unit. [13] The system of claim 12, wherein the display unit is a touch screen.

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