NANO WIRE TRANSISTOR WITH UNDERLAYER Etching Stops

Abstract

A nanowire device according to the present description can be fabricated, incorporating at least one sublayer etch stop that is formed during the fabrication of at least one nanowire transistor to aid in the protection of source and / or drain structures from damage that may result from the fabrication process. The sublayer etch stop can prevent damage to source and / or drain structures if the material used to fabricate the source and / or drain structures is susceptible to being etched by the processes used to remove the sacrificial materials, i.e., is not very selective with respect to the source and / or drain structure materials, thus preventing a potential short circuit between the transistor gate electrodes and the contacts formed for the source and / or drain structures.

Description

FIELD OF THE INVENTION

[0001] Embodiments of the present description generally relate to the field of microelectronic nanowire devices, and more particularly to a nanowire structure formed using at least one underlayer etch stop to prevent the removal of portions of a source structure or a drain structure during the removal of sacrificial layers in the course of fabricating nanowire channels. BACKGROUND

[0002] Higher performance, lower costs, a greater degree of miniaturization of integrated circuit components, and higher packing density of integrated circuits are ongoing goals of the microelectronics industry with regard to the manufacture of microelectronic devices. As these goals are achieved, microelectronic devices are becoming smaller, making it even more imperative that each integrated circuit component delivers optimal performance. For example, reference is made to the disclosures in US 2004 / 0 227 181 A1 and US 2006 / 0 049 429 A1.

[0003] Maintaining enhanced mobility and short-channel control while reducing dimensions to less than 15 nanometers (nm) represents a challenge in the fabrication of microelectronic devices. Nanowires can be used to create microelectronic devices that provide enhanced short-channel control. Nanowire channel structures made of silicon germanium (Si x Ge 1-x ) (where x < 0.5) provide improved mobility with a reasonable Eg value, which is suitable for use in many conventional products operating at higher voltages. Furthermore, nanowire channels made of silicon germanium (Si x Ge 1-x ) (where x < 0.5) provides improved mobility at lower Eg values ​​(e.g. suitable for low-voltage products in the field of mobile devices).

[0004] Many different methods have been tested to fabricate and size nanowire-based devices. However, there is still a need for improvements in the fabrication of reliable nanowire transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The subject matter of the present disclosure is particularly pointed out and expressly claimed in the concluding portion of the specification. The above-noted portion and other features of the present disclosure will become more apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings. It is understood that the accompanying drawings illustrate only some embodiments according to the present disclosure and are therefore not to be considered limiting of the scope of protection. The disclosure will be described more specifically and in more detail with reference to the accompanying drawings so that the advantages of the present disclosure may be better appreciated, in which: Fig. 1-11 and 13 to 15 are oblique and cross-sectional views of a method of forming a nanowire transistor according to an embodiment of the present description; Fig. Figure 12 is a side cross-sectional view showing etch-induced damage that can occur without an underlayer etch stop; Fig. 16 is a flowchart of a method of manufacturing a microelectronic device according to an embodiment of the present description; Fig. 17 shows a computing device according to an implementation of the present description. DESCRIPTION OF THE EMBODIMENTS

[0006] The invention is defined in the independent patent claims. Further developments are the subject of the dependent patent claims.

[0007] In the following detailed description, reference is made to the accompanying drawings, which show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. It is to be understood that the various embodiments, while different, are not necessarily exclusive of one another. For example, a particular feature, structure, or characteristic described herein in connection with one embodiment may be practiced in other embodiments without departing from the spirit or scope of the claimed subject matter.References in this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is part of at least one embodiment that is within the scope of this specification. Therefore, use of the phrase "one embodiment" or "an embodiment" does not necessarily refer to the same embodiment. In addition, it is understood that the position or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter.The following detailed description is therefore not to be taken in a limiting sense, and the scope of the subject matter is defined solely by the appended claims, which are to be interpreted as appropriate, and includes the full scope of those equivalents to which the appended claims are entitled. In the drawings, like reference numerals refer to the same or similar elements or functionality throughout the different views, and elements shown in the drawings are not necessarily to scale with respect to one another, but individual elements may be shown enlarged or reduced in size to make the elements easier to appreciate in the context of the present description.

[0008] To fabricate nanowire transistors, a plurality of stacked channel nanowires can be formed, which requires the removal of a sacrificial gate electrode material formed over a ridge structure comprising layers of sacrificial materials and channel gate materials. Removal of the sacrificial gate electrode can be followed by the removal of sacrificial materials between channel gate material layers to form a plurality of stacked nanowires, known as a "nanowire release process." The removal of the sacrificial materials in the replacement gate process or the nanowire release process can be performed by etching processes such as dry etching, wet etching, a combination of oxidation and wet etching, and the like.However, these methods may pose the risk that the source and / or drain structures of the nanowire transistors may also be etched by the processes used to remove the sacrificial materials if the material used to fabricate the source and / or drain structures is susceptible to being etched by the processes used to remove the sacrificial materials, i.e., is poorly selective with respect to the source and / or drain structure materials. Accordingly, the nanowire release process may result in damage to the source and / or drain structures, which may lead to a short circuit between a transistor gate electrode and contacts formed for the source and / or drain structures, as will be understood by those skilled in the art.

[0009] Embodiments of the present description include incorporating at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor to assist in protecting the source structures and / or drain structures from damage that may result from fabrication processes, such as those that are part of the nanowire release process.

[0010] Fig. 1 to 11 and 13 to 15 show methods for forming a nanowire transistor. For conciseness and clarity, the formation of a single nanowire transistor is illustrated. As shown in Fig. 1, a microelectronic substrate 110 may be provided or formed from any suitable material. In one embodiment, the microelectronic substrate 110 may be a bulk substrate made of a single crystal of a material including, but not limited to, silicon, germanium, silicon germanium, or a III-V compound semiconductor material. In other embodiments, the microelectronic substrate 110 may comprise a silicon-on-insulator (SOI) substrate, with a top insulator layer made of a material including, but not limited to, silicon dioxide, silicon nitride, or silicon oxynitride disposed on the bulk substrate. Alternatively, the microelectronic substrate 110 may be formed directly from a bulk substrate, and local oxidation is applied to form electrically insulating portions in place of the top insulator layer described above.

[0011] As also in Fig. 1, a plurality of sacrificial material layers (shown as elements 1221, 1222, and 1223) may be formed alternating with a plurality of channel material layers (shown as elements 1241, 1242, and 1243) on the microelectronic substrate 110 by any known method, such as epitaxial growth, to form a layer stack 126. In one embodiment, the sacrificial material layers 1221, 1222, and 1223 may be silicon layers, and the channel material layers 1241, 1242, and 1243 may be silicon germanium layers. In another embodiment, the sacrificial material layers 1221, 1222, and 1223 may be silicon germanium layers and the channel material layers 1241, 1242, and 1243 may be silicon layers.Although three sacrificial material layers and three channel material layers are shown, it is clear that any suitable number of sacrificial material layers and channel material layers may be used.

[0012] The layer stack 126 from Fig. 2 can be patterned using conventional patterning / etching techniques to form at least one rib structure 128, as shown in Fig. 3. The layer stack 126 from Fig. 2 may, for example, be etched in a trench etching process, such as a trench isolation (STI) process, in which trenches 144 may be formed in the microelectronic substrate 110 during the formation of the fin structure 128 and may be formed on opposite sides of the fin structures 128. As will be appreciated by those skilled in the art, a plurality of substantially parallel fin structures 128 are generally formed simultaneously.

[0013] As in Fig. 3, dielectric material structures 146, such as silicon dioxide, may be formed or deposited in the trenches 144 near the microelectronics substrate 110 to electrically isolate the fin structures 128. As will be appreciated by those skilled in the art, the method of forming the dielectric material structures 146 may include various methods, including, but not limited to, depositing dielectric material, polishing / planarizing the dielectric material, and etching back the dielectric material to form the dielectric material structures 146.

[0014] As in Fig. 4, spacers 160 may be formed on and above the rib structure 128 and disposed substantially at right angles with respect to the rib structure 128. In one embodiment, the spacers 160 may comprise any material that is selective during subsequent processing of the materials of the rib structure 128, as explained below. As shown in Fig. 4, a sacrificial gate electrode material 152 may be formed within the spacers 160 / between the spacers 160 and may be formed around portions of the fin structures 128 between the spacers 160. In one embodiment, the sacrificial gate electrode material 152 may be formed around portions of the fin structure 128, and the spacers 160 may be present on both sides of the sacrificial gate electrode material 152. The sacrificial gate electrode material 152 may comprise any sacrificial material, including, but not limited to, polysilicon. As shown in Fig. 6, a portion of each fin structure 128 (outside of the sacrificial gate electrode material 152 and the spacers 160) may be removed to expose portions 112 of the microelectronic substrate 110 and form a first fin structure end 1281 and a second fin structure end 1282 (where the first fin structure end 1281 is not specifically illustrated, but is substantially a mirror image of the second fin structure end 1282). The portions of each fin structure 128 may be removed by any method known in the art, including, but not limited to, a dry etching process.

[0015] A sublayer etch stop structure (illustrated as first sublayer etch stop structure 1301 and second sublayer etch stop structure 1302) may be formed to adjoin the fin structure 128 at opposite ends of the fin structure 128. The first sublayer etch stop structure 1301 and the second sublayer etch stop structure 1302 may be formed from any suitable material that is selective with respect to the sacrificial material layers 122" such that the sacrificial material layers 122" may be removed without removing the first sublayer etch stop structure 1301 or the second sublayer etch stop structure 1302, as explained below. In one embodiment, the first sublayer etch stop structure 1301 and the second sublayer etch stop structure 1302 may be formed from a material that provides a structure for the growth of epitaxial material.In another embodiment of the present description, the first underlayer etch stop structure 1301 and the second underlayer etch stop structure 1302 may be made of the same material as the channel material layer 124. n . In a specific embodiment, the first underlayer etch stop structure 1301 and the second underlayer etch stop structure 1302 may thus be formed by epitaxial growth of silicon or silicon germanium to form the channel material layer 124 n to fit. The epitaxial growth of the first underlayer etch stop structure 1301 and the second underlayer etch stop structure 1302 may result in the first underlayer etch stop structure 1301 and the second underlayer etch stop structure 1302 also being formed, as shown, on the exposed portion 112 of the microelectronic substrate.

[0016] As in Fig. As shown in Figure 7, a source structure 170 adjacent to a first underlayer etch stop structure 1301 and a drain structure 180 adjacent to a second underlayer etch stop structure 1302 may be formed at opposite ends of the fin structure 128, such as by epitaxial growth of silicon or silicon germanium. In one embodiment, the source structures 170 or the drain structures 180 may be n-doped silicon for an NMOS device, or p-doped silicon / silicon germanium for a PMOS device, depending on the type of device for the particular application. Doping may be performed during the epitaxial process by implantation, plasma doping, solid-source doping, or other methods known in the art.

[0017] As in Fig. 8, a dielectric interlayer 190 may be formed on the microelectronic substrate 110 over the source structures 170, the drain structures 180, the sacrificial gate electrode material 152, and the spacers 160, wherein the dielectric interlayer 190 may be planarized, such as by chemical mechanical polishing, to expose the sacrificial gate electrode material 152. As shown in Fig. 9, the sacrificial gate electrode material 152 may then be removed from between the spacer materials 160, such as by an etching process.

[0018] As in Fig. 10 and Fig. 11 (cross section along line 11-11 in Fig. 10) can be shown the sacrificial material layers 1221, 1222 and 1223 (see Fig. 9) selectively from the rib structure 128 (see Fig. 9) between the channel material layers 1241, 1242 and 1243 (see Fig. 9) to form channel nanowires (represented as elements 1201, 1202 and 1203, may be referred to herein collectively as “channel nanowires 120 n “), which are located between the source structure 170 (see Fig. 7) and the drain structure 180 extend with the first underlayer etch stop structure 1301 between the channel nanowires 102 nand the source structure 170 and the second underlayer etch stop structure 1302 between the channel nanowires 102" and the drain structure 180. As illustrated, the channel nanowires 120" may be vertically aligned (e.g., in the z-direction) and spaced apart from each other. In one embodiment, the sacrificial material layers 1221, 1222, and 1223 may be etched by a wet etching process that selectively removes the sacrificial material layers 1221, 1222, and 1223 while leaving the channel material layers 1241, 1242, and 1243 or the first underlayer etch stop structure 1301 or the second underlayer etch stop structure 1302 unetched.In one embodiment, where sacrificial material layers 1221, 1222, and 1223 are silicon, and channel material layers 1241, 1242, and 1243, and first underlayer etch stop structure 1301 and second underlayer etch stop structure 1302 are silicon germanium, the wet etch may include, but is not limited to, aqueous hydroxide chemicals, including ammonium hydroxide and potassium hydroxide. In another embodiment, the silicon germanium may be removed rather than the silicon, where first underlayer etch stop structure 1301 and second underlayer etch stop structure 1302 would be made of silicon. The silicon germanium material layers 1241, 1242, and 1243. ncan be selectively removed from the fin structure between the silicon material layers 122". In one embodiment, the silicon germanium can be selectively etched by wet etching, whereby the silicon germanium is selectively removed while the silicon is not etched, where the wet etch can include, but is not limited to, a carboxylic acid / nitric acid / hydrofluoric acid solution and citric acid / nitric acid / hydrofluoric acid solutions. In some embodiments of the invention, the same silicon / silicon germanium stack is used to form both silicon channel nanowire transistors and silicon germanium nanowire transistors. In another embodiment of the invention, the layer order of the silicon / silicon germanium stack can vary depending on whether silicon channel nanowires or silicon germanium channel nanowires are formed.

[0019] In one embodiment, both silicon and silicon germanium channel nanowires 120" may be present on the same wafer, die, or circuit, such as NMOS-Si and PMOS-SiGe in an inverter structure. In an embodiment with NMOS-Si and PMOS-SiGe in the same circuit, the Si channel thickness (SiGe interlayer) and the SiGe channel thickness (Si interlayer) may be selected to improve circuit performance and / or the minimum operating voltage of the circuit. In one embodiment, the number of nanowires on different devices in the same circuit may be varied by an etching process to improve circuit performance and / or the minimum operating voltage of the circuit.

[0020] As in Fig. 12, the removal of the sacrificial material layers 1221, 1222 and 1223 without an underlayer etch stop may result in the source structures 170 and / or the drain structures 180 being etched or otherwise damaged (shown as etch holes 132).

[0021] As in Fig. 13 (cross section along line 13-13 in Fig. 10), a gate dielectric material 192 may be formed to surround the channel nanowires 1201, 1202, and 1203 between the spacers 160. In one embodiment, the gate dielectric material 192 may comprise a high-k gate dielectric material, wherein the dielectric constant may have a value greater than about 4. Examples of high-k gate dielectric materials may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titania, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium oxide, and lead zinc niobate. In one embodiment, the gate dielectric material 192 may be substantially conformally formed around channel nanowires 1201, 1202, and 1203 and form a substantially conformal layer on the spacers 160.The gate dielectric material 192 may be deposited using any method known in the art, such as, but not limited to, atomic layer deposition (ALD) and various types of chemical vapor deposition (CVD) processes, such as atmospheric pressure CVD (APCVD), low pressure CVD (APCVD), and plasma enhanced CVD (PECVD).

[0022] As in Fig. 14 and Fig. 15 (cross section along line 15-15 in Fig. 14), a gate electrode material 154 may then be formed around the channel nanowires 1201, 1202, and 1203 to form a gate electrode 150, thus forming a multi-stacked nanowire transistor 100. The gate electrode material 154 may comprise any suitable conductive material, including, but not limited to, pure metal and alloys of titanium, tungsten, tantalum, aluminum, copper, ruthenium, cobalt, chromium, iron, palladium, molybdenum, manganese, vanadium, gold, silver, and niobium. Less conductive metal carbides, such as titanium carbide, zirconium carbide, tantalum carbide, and tungsten carbide, may also be used. The gate electrode material may also be comprised of a metal nitride, such as titanium nitride and tantalum nitride, or a conductive metal oxide, such as ruthenium oxide. The gate electrode material may also include alloys with rare earth metals, such as terbium and dysprosium, or with precious metals, such as platinum.

[0023] As in Fig. 14, the nanowire transistor 100 may comprise: the at least one nanowire channel 1201, 1202 and 1203 having a first end 1621, 1622 and 1623 respectively and an opposite second end 1641, 1642 and 1643 respectively, and the source structure 170 proximate the first end 1621, 1622 and 1623 of the at least one nanowire channel, wherein the first underlayer etch stop structure 1301 is arranged between the source structure 170 and the first end 1621, 1622 and 1623 of the at least one nanowire channel, and the drain structure 180 proximate the second end 1641, 1642 and 1643 of the at least one nanowire channel, wherein the second underlayer etch stop structure 1302 is arranged between the drain structure 180 and the second end 1641, 1642 and 1643 of the at least one nanowire channel.Furthermore, the gate dielectric material 192 may be adjacent to the at least one nanowire channel 1201, 1202, and 1203 between the first end 1621, 1622, and 1623 of the nanowire channel and the second end 1641, 1642, and 1643 of the nanowire channel, respectively. Furthermore, the gate electrode 150 may be adjacent to the gate dielectric material 192. Furthermore, the gate electrode 150 may be adjacent to the first underlayer etch stop structure 1301 and the second underlayer etch stop structure 1302.

[0024] It will be appreciated that further processing may be performed, such as forming trench contacts 196 on the source structure 170 and the drain structure 180, and the like.

[0025] Fig. 16 shows a flowchart of a method 200 for fabricating a nanowire transistor structure according to an embodiment of the present description. As indicated in block 202, a microelectronic substrate may be formed. A stacked layer comprising at least one sacrificial material layer and at least one channel material layer may be formed on the microelectronic substrate, as indicated in block 204. At least one fin structure may be formed from the layer stack and the hard mask layer, as indicated in block 206. As indicated in block 208, at least two spacers may be formed on the fin structure. A sacrificial gate electrode material may be formed between the at least two spacers, as indicated in block 210.As indicated in block 212, a portion of the fin structure outside the sacrificial gate electrode material and the spacers may be removed to form a first end of the fin structure and an opposite second end of the fin structure, as indicated in block 214. As indicated in block 216, a source structure and a drain structure may be formed to abut the underlayer etch stop structures at opposite ends of the fin structure. As indicated in block 218, an interlayer dielectric layer may be formed over the source structure and the drain structure. The sacrificial gate electrode material may be removed between the spacers, as indicated in block 220. As indicated in block 222, the sacrificial material layers between the channel material layer may be selectively removed to form at least one channel nanowire.As indicated in block 224, a gate dielectric material may be formed to surround the channel nanowire between the spacers. A gate electrode material may be formed on the gate dielectric material, as indicated in block 226.

[0026] Fig. Figure 17 shows a computing device 300 according to one embodiment of the present description. Computing device 300 includes a circuit board 302. Circuit board 302 may include a number of components, including, but not limited to, a processor 304 and at least one communications chip 306. Processor 304 is physically and electrically connected to circuit board 302. In further embodiments, communications chip 306 is part of processor 304.

[0027] Depending on its applications, computing device 300 may include additional components that may or may not be physically and electrically connected to circuit board 302. These additional components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a GPS (Global Positioning System) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (e.g., a hard disk drive, a CD (Compact Disk), a DVD (Digital Versatile Disk), etc.).

[0028] The communication chip 306 enables wireless communication for transferring data to and from the computing device 300. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that transfer data using modulated electromagnetic radiation over a non-solid medium. The term does not imply that the devices associated with it do not contain wires, although in some cases this is not the case. The communication chip 306 may implement any number of wireless standards or protocols, including, but not limited to, WiFi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and all other wireless protocols referred to as 3G, 4G, 5G, and beyond. Computing device 300 may include a plurality of communication chips 306. For example, a first communication chip 306 may be provided for shorter-range wireless communication, such as Wi-Fi and Bluetooth, while a second communication chip 306 may be provided for longer-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0029] The processor 304 of the computing device 300 includes an integrated circuit die incorporated within the processor 304. In some embodiments of the present description, the integrated circuit die of the processor includes one or more such devices, such as nanowire transistors, constructed according to embodiments of the present description. The term "processor" refers to any device or portion of a device that processes electronic data from registers and / or memories to transform that electronic data into other electronic data that can be stored in registers and / or memories.

[0030] The communication chip 306 also includes an integrated circuit die that is part of the communication chip 306. According to another embodiment of the present description, the integrated circuit die of the communication chip includes one or more devices, such as nanowire transistors, constructed according to embodiments of the present description.

[0031] In further embodiments, another component included in computing device 300 may include an integrated circuit die including one or more devices, such as nanowire transistors, constructed according to embodiments of the present description.

[0032] In various embodiments, computing device 300 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment controller, a digital camera, a portable music player, or a digital video recorder. In further embodiments, computing device 300 may be any other electronic device that processes data.

[0033] It is clear that the subject matter of the present description is not necessarily limited to the specific applications described in the Fig.1 to 17. The subject matter may also be applied to other microelectronic device and assembly applications, as well as suitable transistor applications, as will be apparent to those skilled in the art.

[0034] The following examples relate to further embodiments, wherein Example 1 is a nanowire transistor comprising: at least one nanowire channel having a first end and an opposite second end; a source structure proximate the first end of the at least one nanowire, wherein a first underlayer etch stop structure is disposed between the source structure and the first end of the at least one nanowire; and a drain structure proximate the second end of the at least one nanowire, wherein a second underlayer etch stop structure is disposed between the drain structure and the second end of the at least one nanowire.

[0035] In Example 2, the article of Example 1 can optionally comprise: a dielectric gate material adjacent to the nanowire channel between the first end of the nanowire channel and the second end of the nanowire channel.

[0036] In Example 3, the subject matter of Example 2 can optionally comprise: a gate electrode material adjacent to the gate dielectric material.

[0037] In Example 4, the subject matter of Example 3 can optionally comprise: the gate electrode material adjacent to the first underlayer etch stop structure and the second underlayer etch stop structure.

[0038] In Example 5, the article of any of Examples 1 to 4 can optionally comprise: the nanowire channel, the first underlayer etch stop structure, and the second underlayer etch stop structure, all made of the same material.

[0039] In Example 6, the article of any one of Examples 1 to 4 can optionally comprise: the nanowire channel, the first underlayer etch stop structure, and the second underlayer etch stop structure made of silicon germanium.

[0040] In Example 7, the article of any one of Examples 1 to 4 can optionally comprise: the nanowire channel, the first underlayer etch stop structure, and the second underlayer etch stop structure made of silicon.

[0041] In Example 8, with respect to the subject matter of any one of Examples 1 to 7, the at least one nanowire channel may comprise a plurality of nanowire channels formed on a microelectronic substrate, wherein the nanowire channels are spaced apart from one another.

[0042] In Example 9, a method of forming a microelectronic structure may include: forming a fin structure on a microelectronic substrate, the fin structure comprising at least one sacrificial material layer alternating with at least one channel material layer; forming at least two spacers on the fin structure; forming a sacrificial gate electrode material between the at least two spacers; removing a portion of the fin structure outside the sacrificial gate electrode material and the spacers to form a first end of the fin structure and an opposite second end of the fin structure; forming underlayer etch stop structures adjacent to the first end and the second end of the fin structure; and forming a source structure and a drain structure adjacent to the underlayer etch stop structures at opposite ends of the fin structure.

[0043] In Example 10, the subject matter of Example 9 can optionally comprise forming an interlayer dielectric layer over the source structure and the drain structure; removing the sacrificial gate electrode material between the spacers; and selectively removing the sacrificial material layers between the channel material layers to form at least one channel nanowire.

[0044] In Example 11, the subject matter of Example 10 can optionally comprise forming a gate dielectric material to surround the channel nanowire between the spacers and forming a gate electrode material on the gate dielectric material.

[0045] In Example 12, the subject matter of any of Examples 9 to 11 can optionally comprise: forming the fin structure on the microelectronic substrate by forming a microelectronic substrate; forming a stacked layer comprising at least one sacrificial electrode material alternating with at least one channel material layer; and forming at least one fin structure from the layer stack.

[0046] In Example 13, the subject matter of any of Examples 9 to 12 can optionally comprise: the channel material layer, the first underlayer etch stop structure, and the second underlayer etch stop structure, all made of the same material.

[0047] In Example 14, the subject matter of any one of Examples 9 to 12 can optionally comprise: the channel material layer, the first underlayer etch stop structure, and the second underlayer etch stop structure, all made of silicon germanium.

[0048] In Example 15, the subject matter of any one of Examples 9 to 12 can optionally comprise: the channel material layer, the first underlayer etch stop structure, and the second underlayer etch stop structure, all made of silicon.

[0049] In Example 16, a computing device may include a board including at least one component, the at least one component including at least one microelectronic structure including at least one nanowire transistor comprising: at least one nanowire channel having a first end and an opposite second end; a source structure proximate the first end of the at least one nanowire, wherein a first underlayer etch stop structure is disposed between the source structure and the first end of the at least one nanowire; and a drain structure proximate the second end of the at least one nanowire, wherein a second underlayer etch stop structure is disposed between the drain structure and the second end of the at least one nanowire.

[0050] In Example 17, the subject matter of Example 16 can optionally comprise: a gate dielectric material adjacent to the nanowire channel between the first end and the second end of the nanowire channel.

[0051] In Example 18, the subject matter of Example 17 can optionally comprise: a gate electrode material adjacent to the gate dielectric material.

[0052] In Example 19, the subject matter of Example 18 can optionally comprise: the gate electrode material adjacent to the first underlayer etch stop structure and the second underlayer etch stop structure.

[0053] In Example 20, the subject matter of any one of Examples 16 to 19 can optionally comprise: the nanowire channel, the first underlayer etch stop structure, and the second underlayer etch stop structure, all made of the same material.

[0054] In Example 21, the subject matter of any one of Examples 16 to 19 can optionally comprise: the nanowire channel, the first underlayer etch stop structure, and the second underlayer etch stop structure, all made of silicon germanium.

[0055] In Example 22, the subject matter of any one of Examples 16 to 19 can optionally comprise: the nanowire channel, the first underlayer etch stop structure, and the second underlayer etch stop structure, all made of silicon.

[0056] In Example 23, the subject matter of at least one of Examples 16 to 22 comprises the at least one nanowire channel, which may comprise a plurality of nanowire channels formed on a microelectronic substrate, wherein the nanowire channels are spaced apart from one another.

Claims

[1] Nanowire transistor (100) comprising: at least one nanowire channel (1201, 1202, 1203) made of silicon or silicon germanium having a first end (1621, 1622, 1623) and an opposite second end (1641, 1642, 1643); at least two spacers (160) above the at least one nanowire channel (1201, 1202, 1203); a source structure (170) near the first end (1621, 1622, 1623) of the at least one nanowire channel (1201, 1202, 1203), wherein a first structure made of silicon or silicon germanium (1301) is arranged between the source structure (170) and the first end (1621, 1622, 1623) of the at least one nanowire channel (1201, 1202, 1203); and a drain structure (180) near the second end (1641, 1642, 1643) of the at least one nanowire channel (1201, 1202, 1203), wherein a second structure made of silicon or silicon germanium (1302) is arranged between the drain structure (180) and the second end (1641, 1642, 1643) of the at least one nanowire channel (1201, 1202, 1203), and the source structure (170), the first structure made of silicon or silicon germanium (1301), the at least one nanowire channel (1201, 1202, 1203), the second structure made of silicon or silicon germanium (1302), and the drain structure (180) are arranged in this order along a lateral direction. [2] The nanowire transistor (100) of claim 1, further comprising a gate dielectric material (192) adjacent to the nanowire channel (1201, 1202, 1203) between the first end (1621, 1622, 1623) and the second end (1641, 1642, 1643) of the nanowire channel (1201, 1202, 1203). [3] The nanowire transistor (100) of claim 2, further comprising a gate electrode material (154) adjacent to the gate dielectric material (192). [4] The nanowire transistor (100) of claim 3, wherein the gate electrode material (154) is adjacent to the first silicon or silicon germanium structure (1301) and the second silicon or silicon germanium structure (1302). [5] Nanowire transistor (100) according to one of claims 1 to 4, wherein the nanowire channel (1201, 1202, 1203), the first structure of silicon or silicon germanium (1301) and the second structure of silicon or silicon germanium (1302) are made of the same material. [6] Nanowire transistor (100) according to one of claims 1 to 4, wherein the nanowire channel (1201, 1202, 1203), the first structure of silicon or silicon germanium (1301) and the second structure of silicon or silicon germanium (1302) are made of silicon germanium. [7] Nanowire transistor (100) according to one of claims 1 to 4, wherein the nanowire channel (1201, 1202, 1203), the first structure of silicon or silicon germanium (1301) and the second structure of silicon or silicon germanium (1302) are made of silicon. [8] The nanowire transistor (100) of claim 1, wherein the at least one nanowire channel (1201, 1202, 1203) comprises a plurality of nanowire channels formed on a microelectronic substrate (110), the nanowire channels (1201, 1202, 1203) being spaced apart from each other. [9] A method for forming a microelectronic structure, comprising: forming a rib structure (128) on a microelectronic substrate (110), wherein the rib structure (128) comprises at least one sacrificial material layer (1221, 1222, 1223) alternating with at least one channel material layer (1241, 1242, 1243) made of silicon or silicon germanium; forming at least two spacers (160) on the rib structure (128); forming a sacrificial gate electrode material (152) between the at least two spacers (160); removing a portion of the fin structure (128) outside the sacrificial gate electrode material (152) and the spacers (160) to form a first end (1281) of the fin structure (128) and an opposite second end (1282) of the fin structure (128); forming silicon or silicon germanium structures (1301, 1302) adjacent to the first end (1281) and the second end (1282) of the rib structure (128); and forming a source structure (170) and a drain structure (180) adjacent to the silicon or silicon germanium structures (1301, 1302) at opposite ends of the fin structure (128). [10] The method of claim 9, further comprising: forming a dielectric interlayer (190) over the source structure (170) and the drain structure (180); removing the sacrificial gate electrode material (152) between the spacers (160); and selectively removing the sacrificial material layers (1221, 1222, 1223) between the channel material layers (1241, 1242, 1243) to form the at least one channel nanowire (1201, 1202, 1203). [11] The method of claim 10, further comprising: forming a dielectric gate material (192) to surround the channel nanowire (1201, 1202, 1203) between the spacers (160), and forming a gate electrode material (154) on the gate dielectric material (192). [12] The method of claim 9, wherein forming the rib structure (128) on the microelectronic substrate (110) comprises the following, wherein the rib structure (128) comprises at least one sacrificial material layer (1221, 1222, 1223) alternating with at least one channel material layer (1241, 1242, 1243): forming a microelectronic substrate (110); forming a stack layer comprising at least one sacrificial material layer (1221, 1222, 1223) alternating with at least one channel material layer (1241, 1242, 1243); and forming at least one rib structure (128) from the layer stack. [13] A method according to any one of claims 9 to 12, wherein the channel material layer (1241, 1242, 1243) and the silicon or silicon germanium structures (1301, 1302) are made of the same material. [14] A method according to any one of claims 9 to 12, wherein the channel material layer (1241, 1242, 1243) and the silicon or silicon germanium structures (1301, 1302) are made of silicon germanium. [15] A method according to any one of claims 9 to 12, wherein the channel material layer (1241, 1242, 1243) and the silicon or silicon germanium structures (1301, 1302) are made of silicon. [16] A computer device (300) comprising: a circuit board comprising at least one component; wherein the at least one component comprises at least one microelectronic structure comprising at least one nanowire transistor (100) comprising: at least one nanowire channel (1201, 1202, 1203) having a first end (1621, 1622, 1623) and an opposite second end; at least two spacers (160) above the at least one nanowire channel (1201, 1202, 1203); a source structure (170) near the first end (1621, 1622, 1623) of the at least one nanowire channel (1201, 1202, 1203), wherein a first structure made of silicon or silicon germanium (1301) is arranged between the source structure (170) and the first end (1621, 1622, 1623) of the at least one nanowire channel (1201, 1202, 1203), and a drain structure (180) near the second end (1641, 1642, 1643) of the at least one nanowire channel (1201, 1202, 1203),wherein a second structure made of silicon or silicon germanium (1302) is arranged between the drain structure (180) and the second end (1641, 1642, 1643) of the at least one nanowire channel (1201, 1202, 1203), and the source structure (170), the first structure made of silicon or silicon germanium (1301), the at least one nanowire channel (1201, 1202, 1203), the second structure made of silicon or silicon germanium (1302), and the drain structure (180) are arranged along a lateral direction in this order. [17] The computing device (300) of claim 16, further comprising a gate dielectric material (192) adjacent to the nanowire channel (1201, 1202, 1203) between the first end (1621, 1622, 1623) and the second end (1641, 1642, 1643) of the nanowire channel (1201, 1202, 1203). [18] The computing device (300) of claim 17, further comprising a gate electrode material (154) adjacent to the gate dielectric material (192). [19] The computer device (300) of claim 18, wherein the gate electrode material (154) is adjacent to the first silicon or silicon germanium structure (1301) and the second silicon or silicon germanium structure (1302). [20] The computing device (300) of any one of claims 16 to 19, wherein the nanowire channel (1201, 1202, 1203), the first silicon or silicon germanium structure (1301) and the second silicon or silicon germanium structure (1302) are made of the same material. [21] The computing device (300) of any one of claims 16 to 19, wherein the nanowire channel (1201, 1202, 1203), the first structure of silicon or silicon germanium (1301) and the second structure of silicon or silicon germanium (1302) are made of silicon germanium. [22] The computing device (300) of any one of claims 16 to 19, wherein the nanowire channel (1201, 1202, 1203), the first structure of silicon or silicon germanium (1301) and the second structure of silicon or silicon germanium (1302) are made of silicon. [23] The computing device (300) of claim 16, wherein the at least one nanowire channel (1201, 1202, 1203) comprises a plurality of nanowire channels formed on a microelectronic substrate (110), the nanowire channels (1201, 1202, 1203) being spaced apart from each other.

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