Light-emitting nanostructure device

Abstract

Light-emitting nanostructure device comprising: a base layer (152) formed of a nitride semiconductor material of a first conductivity type; an insulating layer (153) disposed on the base layer (152) and having a plurality of openings (H), each of which exposes a portion of the base layer (152); a plurality of nanocores (155a) respectively arranged in the plurality of openings (H) and formed of the nitride semiconductor material of the first conductivity type, each of the plurality of nanocores (155a) having a tip portion (T) with a crystal face different from that of a side face; an active layer (155b) and a nitride semiconductor layer of a second conductivity type (155c) sequentially arranged on surfaces of each of the plurality of nanocores (155a); a first current-blocking intermediate layer (154) disposed at the tip portion (T) of each of the plurality of nanocores (155a) between each of the nanocores (155a) and the active layer (155b); and a second current-blocking intermediate layer (157) disposed between the active layer (155b) and the second conductivity type nitride semiconductor layer (155c) and disposed at a region corresponding to the tip portion (T) of each of the plurality of nanocores (155a).

Description

TECHNICAL FIELD

[0001] The present invention relates to a light-emitting nanostructure device. STATE OF THE ART

[0002] A semiconductor light-emitting device, such as a light-emitting diode (LED), is a device in which materials within it emit light. In an LED, energy generated by electron-hole recombination is converted into light that can be emitted. LEDs are widely used as light sources in lighting devices and display devices, and as such, their development has tended to accelerate.

[0003] Recently, semiconductor light-emitting devices using nanostructures have been developed as a new semiconductor light-emitting device technology. Semiconductor light-emitting devices using nanostructures have significantly improved light efficiency because nanostructures significantly increase the light-emitting area and exhibit improved crystal quality. Furthermore, efficiency degradation due to piezoelectric polarization can be prevented and static properties can be improved.

[0004] However, in a nanostructure, one tip thereof may have a different crystal face than the other faces thereof. In this case, even if an active layer is grown under the same conditions, the active layer positioned at the tip may have a different composition. Thus, light with a wavelength different from that from other regions may be emitted. Furthermore, a semiconductor layer formed on the tip is relatively thin, and there is a high probability of generating a leakage current.

[0005] Semiconductor devices from the technical field of the present invention are known, for example, from the documents US 2004 / 0 048 409 A1, KR 10 2010 0 080 094 A or KR 10 2012 0 055 390 A. DISCLOSURE TECHNICAL PROBLEM

[0006] The present invention has a technical object to provide a novel nanostructure light-emitting device capable of eliminating a leakage current caused in a nanostructure and reducing a deviation of a wavelength of emitted light. TECHNICAL SOLUTION

[0007] According to the invention, this object is achieved by a light-emitting nanostructure device according to the main claim 1 or the independent claim 11. Advantageous further developments are the subject of the dependent claims. EFFECT OF THE INVENTION

[0008] Leakage current generated due to the light-emitting nanostructures can be mitigated. In particular, leakage current in a region located at a tip portion of the light-emitting nanostructure can be effectively blocked, thereby providing a highly efficient semiconductor light-emitting device. In a specific embodiment, leakage current generated between an insulating layer and a semiconductor layer can also be improved. Furthermore, since only a region of the active layer formed on a single crystal face in a light-emitting nanostructure can participate in emitting light, homogeneous optical properties are promoted.

[0009] The foregoing and other objects, features, aspects and advantages of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view illustrating a nanostructure semiconductor light-emitting device for explaining some aspects of an embodiment of the present invention. Fig. 2 and Fig. 3 are perspective views schematically illustrating examples of a nanocore that can be used in an embodiment of the present invention. Fig. 4 to 8 are cross-sectional views illustrating main processes of an example of a method for manufacturing a nanostructure semiconductor light-emitting device according to some exemplary aspects of an embodiment of the present invention. Fig. 9 and Fig. 10 are plan views showing various examples of a mask having an opening of different shapes. Fig. 11 and Fig. 12 are cross-sectional views showing various examples of a mask having an opening of different shapes. Fig. 13 and Fig. 14 are schematic views illustrating a heat treatment or regrowth applied to Fig. 7 is applicable. Fig. 15 to 19 are cross-sectional views showing main processes of forming an electrode with respect to the Fig. 8 represent the device shown. Fig. 20 to 23 are cross-sectional views illustrating processes for obtaining nanocores, wherein the Fig. The mask shown in Figure 11 is used. Fig. Figure 24 is a scanning electron microscopy (SEM) photograph obtained by imaging a mask used in an experimental example. Fig. 25(a) and Fig. Figure 25(b) are SEM photographs obtained by imaging a planar array of nanocores and a cross-sectional structure grown using a mask applied in an experimental example. Fig. 26(a) and Fig. Figure 26(b) are SEM photographs obtained by imaging a planar array of nanocores and a cross-sectional structure that was heat-treated in an experimental example. Fig. 27 is a cross-sectional view illustrating a nanostructure semiconductor light-emitting device according to an embodiment of the present invention. Fig. 28 to 30 are cross-sectional views illustrating main processes of another example of a manufacturing method of a nanostructure semiconductor light-emitting device according to an exemplary embodiment. Fig. 31 to 35 are cross-sectional views showing main processes of an example of forming an electrode with reference to the Fig. 30 represent the device shown. Fig. 36 to 39 are cross-sectional views showing main processes of an example of forming an electrode with reference to the Fig. 30 represent the device shown. Fig. 40 is a cross-sectional view showing a package with a Fig. 39 represents the light-emitting nanostructure semiconductor device. Fig. 41 is a cross-sectional view illustrating a nanostructure semiconductor light-emitting device according to an exemplary embodiment of the present invention. Fig. 42 to 44 are views illustrating wavelength spectra according to application of current to the nanostructure semiconductor light-emitting device obtained in Embodiment 1 to Embodiment 3. Fig. 45 is a graph illustrating an effect of improving a leakage current of the nanostructure semiconductor light-emitting device obtained in Embodiment 2. Fig. Figure 46 is a graph showing a change in current density versus doping concentration of a current-blocking interlayer. Fig. Figure 47 is a graph showing a change in current density across a thickness of the current-blocking interlayer. Fig. Figure 48 is a graph showing a change in current density over a thickness and doping concentration of the current blocking interlayer. Fig. 49 and Fig. 50 are views illustrating various examples of a semiconductor light-emitting device package using a semiconductor light-emitting device according to an exemplary embodiment of the present invention. Fig. 51 and Fig. 52 are views illustrating a backlight unit using a semiconductor light-emitting device according to an exemplary embodiment of the present invention. Fig. 53 is a view illustrating an example of a lighting device using a semiconductor light-emitting element according to an exemplary embodiment of the present invention. Fig. 54 is a view illustrating an example of a headlight using a semiconductor light-emitting element according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0010] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0011] In the drawings, shapes and dimensions may be exaggerated for clarity.

[0012] Fig. 1 is a cross-sectional view illustrating a nanostructure semiconductor light-emitting device for explaining some aspects of an embodiment of the present invention.

[0013] As in Fig. 1, a nanostructure semiconductor light-emitting device 10 according to an embodiment of the invention includes a base layer 12 formed from a semiconductor material of a first conductivity type and a plurality of light-emitting nanostructures 15 formed on the base layer 12.

[0014] The base layer 12 may be formed on a substrate 11 to provide a growth surface for the light-emitting nanostructures 15 and may serve to electrically connect to the polarity of one side of the light-emitting nanostructures 15.

[0015] The substrate 11 may be an insulating, conductive, or semiconducting substrate. For example, the substrate 11 may be formed of sapphire, SiC, Si, MgAl 2 O 4 , MgO, LiAlO 2 , LiGaO 2 or GaN. The base layer 12 is a nitride semiconductor, which contains Al x In y Ga 1-x-yN (0≤x<1, 0≤y<1, 0≤x+y<1) and can be doped with an n-type impurity, such as silicon (Si), to have a specific conductivity type.

[0016] An insulating layer 13 is formed on the base layer 12 with openings H, which allow light-emitting nanostructures 15 (in particular, nanocores) to grow therein. The base layer 12 is exposed through the openings, and nanocores 15a can be formed in the exposed areas. The insulating layer 13 can be used as a mask for growing the nanocores 15a. The insulating layer 13 can be made of an insulating material, such as SiO 2 or SiN x which is used in a semiconductor process.

[0017] The light-emitting nanostructures 15 may include the nanocore 15a formed from a semiconductor of a first conductivity type, and an active layer 15b and a semiconductor layer of a second conductivity type 15c formed sequentially on a surface of the nanocore 15a.

[0018] The nanocore 15a is a nitride semiconductor layer which, similar to the base layer 12, contains n-doped Al x In y Ga 1-x-yN (0≤x<1, 0≤y<1, 0≤x+y<1). For example, the nanocore 15a may be formed of n-doped GaN. The active layer 15b may have a multi-quantum well (MQW) structure in which quantum well layers and quantum barrier layers are alternately stacked. For example, in a case of a nitride semiconductor, a GaN / InGaN structure may be used. The active layer 15b may also have a single-quantum well (SQW) structure. The second conductivity type nitride semiconductor layer 15c may be a crystal comprising p-doped Al x In y Ga 1-x-yN (0≤x<1, 0≤y<1, 0≤x+y<1).

[0019] The nanostructure semiconductor light-emitting device 10 may include a contact electrode 16 that forms an ohmic contact with the second conductivity-type nitride semiconductor layer 15c. The contact electrode 16 used in the present exemplary embodiment may be formed from a transparent electrode material to emit light toward the light-emitting nanostructures (in the direction opposite to the substrate side). For example, the contact electrode 16 may be formed from a transparent electrode material such as indium tin oxide (ITO), and may be formed from graphene, as needed.

[0020] The contact electrode 16 may include materials such as Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, or the like, and may have a structure including two or more layers, such as Ni / Ag, Zn / Ag, Ni / Al, Zn / Al, Pd / Ag, Pd / Al, Ir / Ag, Ir / Au, Pt / Ag, Pt / Al, Ni / Ag / Pt, or the like, but the present disclosure is not limited thereto. A reflective electrode structure may be implemented as a flip-chip structure, as needed.

[0021] An insulating protective layer 17 may be formed on upper surfaces of the light-emitting nanostructures 15. The insulating protective layer 17 may be a passivation layer that protects the light-emitting nanostructures 15. In the present exemplary embodiment, a space exists between the plurality of light-emitting nanostructures even after the contact electrode 16 is formed, so the insulating protective layer 17 may be formed to fill the space. The insulating protective layer 17 may be made of an insulating material such as SiO 2 or SiN x In particular, the insulating protective layer 17 can be made of tetraethoxysilane (TEOS), borophosphosilicate glass (BPSG), CVD-SiO 2 , spin-on glass (SOG) or a spin-on dielectric (SOD) material to fill the space between the light-emitting nanostructures 15.

[0022] However, filling using the insulating protective layer 17 is not limited to this. For example, in another configuration, an electrode element associated with the contact electrode 16 may fill all or a portion of the space between the light-emitting nanostructures 15.

[0023] The nanostructure semiconductor light-emitting device 10 may include first and second electrodes 19a and 19b. The first electrode 19a may be disposed in a partially exposed region of the base layer 12 formed of the first conductivity type semiconductor. Furthermore, the second electrode 19b may be disposed in an exposed portion of an extended region of the contact electrode 16.

[0024] As in Fig. 1, the nanocore 15a has a tip portion T with a crystal face that is different from the surfaces of the other regions. As shown in Fig. As shown in Figure 1, the tip portion T may have a slanted crystal face, unlike the side surface of the nanocore 15. For example, the tip portion T of the nanocore 15 may have a hexagonal pyramid shape.

[0025] A current-blocking intermediate layer 14 is formed on a surface of the tip portion T of the nanocore 15a. The current-blocking intermediate layer 14 is disposed between the active layer 15b and the nanocore 15a.

[0026] The current-blocking intermediate layer 14 is formed of a material with high electrical resistance for blocking a leakage current that may be caused in the tip portion T of the nanocore 15a. For example, the current-blocking intermediate layer 14 may be a semiconductor layer that is not intentionally doped or may be a semiconductor layer doped with an impurity of a second conductivity type opposite to that of the nanocore 15a. For example, in a case where the nanocore 15a is n-doped GaN, the current-blocking intermediate layer 14 may be undoped GaN or GaN doped with a p-type impurity such as magnesium (Mg). The current-blocking intermediate layer 14 may be a high-resistance region formed of the same material (e.g., GaN) but implemented with different doping concentrations or doping materials, without being particularly distinguished from an adjacent layer.For example, GaN may be grown while supplying an n-type impurity thereto to form the nanocore 15a, and GaN may be grown throughout while preventing the supply of the n-type impurity, or while supplying a p-type impurity, such as magnesium (Mg), thereto to form a desired current-blocking interlayer 14. Furthermore, while growing a GaN nanocore 15a, a source of aluminum (Al) and / or indium (In) may be additionally supplied to form a current-blocking interlayer 14 composed of a different composition than Al. x In y Ga 1-x-yN (0≤x<1, 0≤y<1, 0≤x+y<1).

[0027] When the current-blocking intermediate layer 14 is formed as a semiconductor layer, it may have a thickness equal to or greater than about 50 nm to provide sufficient electrical resistance. The second conductivity type impurity of the current-blocking intermediate layer 14 may be about 1.0 10 16 / cm 3 or more. In the case of the current-blocking interlayer 14 doped with the second conductivity type impurity, a thickness and a concentration thereof may be appropriately implemented to be complementary to each other. For example, when the thickness is thin, a doping concentration may be increased to ensure resistance, and vice versa.

[0028] The current-blocking intermediate layer 14 used in the present exemplary embodiment is restrictedly disposed only on the tip portion T of the nanocore 15a. Due to the selective deposition of the current-blocking intermediate layer 14, the active region disposed on the surface of the tip portion T of the nanocore 15a may not significantly contribute to light emission. Thus, current flow through the active layer region formed on a side surface of the nanocore 15a is normally guaranteed, while current flow through the active layer region formed on the tip portion T of the nanocore 15a is blocked by the current-blocking intermediate layer 14.

[0029] In this way, since only the active layer region formed on the same crystal face (side face) contributes substantially to light emission, even if the active layer region disposed on the different crystal face (tip portion) has a different composition ratio, an influence thereof on a wavelength of emitted light (e.g., an increase in a half-width) can be minimized, and as a result, a desired wavelength of emitted light can be accurately designed.

[0030] An influence of a crystal face of a nanocore used in the present exemplary embodiment will be described in detail with reference to Fig. 2 and Fig. 3. A Fig. 2 can be divided into a main part M providing a side surface with a first crystal face, and a tip portion T providing a surface with a second crystal face different from the first crystal face depending on growth directions.

[0031] In a case where the nanocore 25 has a crystal structure with a hexagonal system, such as a nitride single crystal, a first crystal face may be a non-polar plane (m-plane), and the second crystal face may be a plurality of non-polar planes (r-planes). Similar to the one described with reference to Fig. 1, the nanocore 25 may have a columnar structure in which the tip portion T has a hexagonal pyramid shape.

[0032] Even in the case where an active layer is grown on the surface of the nanocore 25 using the same method, the compositions of the active layer (particularly, the indium content when an InGaN layer is grown) vary due to the difference between the properties of the respective crystal faces, and a wavelength of light generated from the active layer portion grown on the surface (r-plane) of the tip portion of the nanocore 25 and a wavelength of light generated from the side surface (m-plane) of the nanocore 25 may be different. As a result, a half-width of the wavelength of the emitted light is different, making it difficult to accurately plan light with a desired wavelength.In addition, since semiconductor layers (active layer and second conductivity type semiconductor layer) are grown relatively thin at the tip portion as a non-polar plane, a leakage current may be concentrated.

[0033] To solve this problem, as in Fig. 1, the current-blocking intermediate layer 14 is formed at the tip portion of the nanocore to reduce a leakage current to increase a light output, and since the active layer portion positioned at the tip portion is not active in emitting light, a wavelength of the emitted light can be accurately designed.

[0034] In addition to the Fig. 2, the preceding current-blocking intermediate layer can also be advantageously applied to nanocores with different crystal structures and shapes, where a specific region has a different crystal face. For example, as in Fig. 3, the current-blocking interlayer can be applied in a similar manner even if the tip portion of the nanocore does not have a non-polar plane.

[0035] As in Fig. 3, a nanocore 25' has a length similar to the case of Fig. 2 a main part M provided with a side surface having a first crystal face m, while a tip portion T has a crystal face c' different from the first crystal face m, but it is not a completely non-polar plane.

[0036] Even with this configuration, an active layer may have different compositions and grown semiconductor layers may have different thicknesses due to the difference in the properties of the respective crystal faces, thereby causing different wavelengths of emitted light and resulting in a leakage current. In this case, by applying the current-blocking intermediate layer 14 as described above with reference to Fig. 1 to the tip portion T of the nanocore 25' before growing an active layer, a current flow from the tip portion T of the nanocore 25' to the active layer can be suppressed. As a result, a problem caused by generation of a leakage current and a difference in wavelengths of emitted light can be addressed to provide a highly efficient nanostructured semiconductor light-emitting device.

[0037] The nanostructure semiconductor light-emitting device according to the present exemplary embodiment can be manufactured by various manufacturing methods. Fig. 4 to 8 illustrate an example of a method of manufacturing a nanostructure semiconductor light-emitting device, in particular, they illustrate a method of growing nanocores such that the nanocores are deposited with a mask as a molding structure.

[0038] As in Fig. As shown in Figure 4, a semiconductor of a first conductivity type can be grown on a substrate 31 to provide a base layer 32. The base layer 32 provides a crystal growth surface for growing light-emitting nanostructures and serves to electrically connect polarities of one side of the light-emitting nanostructures. Thus, the base layer 32 can be formed as a semiconductor single crystal with electrical conductivity. If the base layer 32 is grown directly, the substrate 31 can be a crystal growth substrate. Before the base layer 32 is grown, a multilayer structure with a buffer layer of Al x In y Ga 1-x-yN(0≤x≤1, 0≤y≤1, 0≤x+y<1) may be formed on the substrate 31. The multilayer structure may include intermediate layers consisting of an undoped GaN layer and an AlGaN layer, or combinations thereof, thereby preventing leakage current to the buffer layer from the base layer 32 and increasing a crystal quality of the base layer 32.

[0039] Then, as in Fig. 5, a mask 33 having a plurality of openings H and an etch stop layer is formed on the base layer 32.

[0040] The mask 33 used in the present exemplary embodiment may include a first material layer 33a formed on the base layer 32 and a second material layer 33b formed on the first material layer 33a and having an etching rate greater than that of the first material layer 33a.

[0041] The first material layer 33a may be provided as the etch stop layer. Thus, the first material layer 33a has an etch rate lower than that of the second material layer 33b under etching conditions of the second material layer 33b. The first material layer 33a may be formed from at least one material having electrically insulating properties, and, as needed, the second material layer 33b may also be formed from an insulating material.

[0042] The first and second material layers 33a and 33b may be formed from different materials to achieve a desired difference in etching rates. For example, the first material layer 33a may be formed from a SiN-based material, while the second material layer 33b may be formed from SiO 2is formed. Alternatively, a difference in etching rates can be achieved by utilizing an air inclusion density. The second material layer 33b or both the first and second material layers 33a and 33b can be formed from a porous material, and a difference in etching rates between the first and second material layers 33a and 33b can be ensured by adjusting a difference in porosity. In this case, the first and second material layers 33a and 33b can be formed from the same material. For example, the first material layer can be made of SiO 2 with a first porosity, and the second material layer 33b may be made of SiO 2but with a second porosity greater than the first porosity. Accordingly, under conditions where the second material layer 33b is etched, the first material layer 33a may have a lower etching rate than that of the second material layer 33b.

[0043] A total thickness of the first and second material layers 33a and 33b can be designed taking into account the height of a desired light-emitting nanostructure. An etching stop level can be designed through the first material layer 33a taking into account a total height of the mask 33 from a surface of the base layer 32. After the first and second material layers 33a and 33b are sequentially formed on the base layer 32, a plurality of openings H are formed to expose the area of ​​the base layer 32. The openings H can be formed by forming photoresist on the mask layer 33 and performing lithography and a wet / dry etching process thereon. A size of each opening H can be planned taking into account a size of a desired light-emitting nanostructure.For example, each opening H exposing the surface of the base layer 32 may have a width (diameter) equal to or less than 600 nm, or further in a range of 50 nm to 500 nm.

[0044] Each opening H may be formed using a semiconductor process, and for example, each opening H may be formed with a high aspect ratio using a deep etching process. The aspect ratio of each opening H may be equal to or greater than 5:1, or further equal to or greater than 10:1.

[0045] While varying depending on etching conditions, each opening H may generally have a width in the first and second material layers 33a and 33b that decreases toward the base layer 32 (see the experimental example and Fig. 24).

[0046] Generally, a dry etching method is used as the deep etching method, and reactive ions generated from a plasma or ion beams generated in a high vacuum may be used. Compared with wet etching, dry etching allows precision machining of a microstructure without geometric restrictions. A CF-based gas may be used for oxide film etching of the mask 33. For example, a gas formed by combining at least one of O 2 and Ar with a gas such as CF 4 , C 2 F 6 , C 3 F 8 , C 4 F 8 or CHF 3 obtained etchant can be used.

[0047] A planar shape and arrangement of the openings H can be realized in various ways. For example, in a case of a planar shape, the openings H can be realized in such a way that they have various shapes, such as polygonal, square, oval, and circular shapes. Fig. The mask 33 shown in Figure 5 may have an arrangement of openings H with a round cross-section as in Fig. 9, but the mask 33 may have any other shapes and arrangements as required. For example, the mask 33 may have an array of openings with a regular hexagonal cross-section, such as one shown in Fig. 10 shown mask 33'.

[0048] The Fig. The openings H shown in Figure 5 may have a columnar structure with a constant diameter (or width), but the present disclosure is not limited thereto, and the openings H may have various other structures using a suitable etching process. For example, in Fig. 11 and Fig. 12 masks with openings H are shown, which have different shapes. In the case of Fig. 11, a mask 43 having first and second material layers 43a and 43b may have openings H having a columnar shape with a cross section that increases toward an upper portion thereof. In the case of Fig. 12, a mask 43' having first and second material layers 43a' and 43b' may have openings H having a columnar shape with a cross-section decreasing toward an upper portion thereof.

[0049] Afterwards, as in Fig. 6, a semiconductor of a first conductivity type is grown on the exposed regions of the base layer 32 to fill the plurality of openings H, thereby forming a plurality of nanocores 35a, and a current-blocking intermediate layer 34 is subsequently formed on tip portions T of the nanocores 35a.

[0050] The first conductivity type semiconductor of the nanocores 35a may be an n-doped nitride semiconductor and may be a material identical to that of the first conductivity type semiconductor of the base layer 32. For example, the base layer 32 and the nanocores 35a may be formed of n-doped GaN.

[0051] A nitride single crystal forming the nanocores 35a may be formed using metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), and in this case, the mask 33 acts as a mold for the grown nitride single crystal to provide nanocores 35 that correspond to the shape of the openings H. Thus, the nitride single crystal may be selectively grown on the regions of the base layer 32 exposed by the openings H, may be filled (or inserted) into the openings H, and the inserted nitride single crystal may have a shape corresponding to that of the openings H.

[0052] By leaving the mask layer 33 as it is, the current-blocking intermediate layer 34 is formed on surfaces of the tip portions T of the nanocores 35a. Thus, the current-blocking intermediate layer 34 can be easily formed on the desired tip portions T even without performing a process of forming an additional mask.

[0053] The current-blocking interlayer 34 may be a semiconductor layer that is not intentionally doped, or may be a semiconductor layer doped with an impurity of a second conductivity type opposite to that of the nanocores 35a. For example, in a case where the nanocores 35a are n-doped GaN, the current-blocking interlayer 34 may be undoped GaN or may be GaN doped with a p-type impurity such as magnesium (Mg). In this case, the nanocores 35a and the current-blocking interlayer 34 may be continuously formed by changing only the type of impurity during the same growth process. In this way, the process of forming the current-blocking interlayer 34 and the molding process are combined to further simplify the overall process.

[0054] Then, as in Fig. 7, the first material layer 33a, an etch stop layer of the mask 33, is removed so that side surfaces of the plurality of nanocores 35a are partially exposed.

[0055] In the present exemplary embodiment, by applying an etching process of selectively removing the second material layer 33b, only the second material layer 33b may be removed while leaving the first material layer 33a. The remaining first material layer 33a may serve to prevent the active layer 35b and the second conductivity type semiconductor layer 35c from being connected to the base layer 32 in a subsequent growth process.

[0056] In the present exemplary embodiment, an additional heat treatment process may be introduced during the process of forming the light-emitting nanostructures using the mask with openings as a mold to improve crystallinity.

[0057] First, before forming the current-blocking intermediate layer 34, a stabilization process (heat treatment process) may be performed while growing the nanocores 35a to improve the crystal quality of the nanocores 35a. Thus, when the nanocores 35a have grown to a desired intermediate growth point (a height in a range of about 0.2 µm to 1.8 µm from the base layer), supply of a TMGa source, a group III element source of GaN, may be terminated, and a heat treatment may be performed at a temperature (in a range of about 1000°C to 1200°C) similar to that of the substrate during growth for about 5 seconds to 5 minutes in an NH 3 -Atmosphere.

[0058] Furthermore, after the nanocores 35a are completely grown and the upper layer 33b of the mask 33 is removed, the surfaces of the nanocores 35a may be heat-treated under predetermined conditions to change a crystal face of each nanocore 35a into a stable face favorable for crystal growth, such as a non-polar or polar crystal face. This method will be described with reference to Fig. 13 and Fig. 14 should be written.

[0059] Fig. 13 and Fig. 14 are schematic views illustrating a heat treatment or regrowth based on the method of Fig. 7 are applicable.

[0060] Fig. 13 represents Fig. 7. The nanocores 35a have a crystal face determined depending on the shape of the openings. Although they differ depending on the shape of the openings, the resulting surfaces of the nanocores 35a may have a relatively unstable crystal face, which is not a favorable condition for subsequent crystal growth.

[0061] In the present exemplary embodiment, when the openings have a cylindrical columnar shape, the side surface of each nanocore 35a may be formed by a curved surface instead of a specific crystal face as shown in Fig. 13 is shown.

[0062] When such nanocores are heat-treated, unstable crystals are arranged on the surfaces thereof in such a way that they have a stable crystal face, such as a non-polar or a polar plane, as in Fig. 14 is shown.

[0063] Regarding the heat treatment conditions, the nanocores can be heat-treated at a temperature equal to or greater than 600°C, and in a specific example, at a temperature in a range of 800°C to 1200°C for a few seconds to several tens of minutes (1 second to 60 minutes) to have a desired stable crystal face. In the heat treatment process, when the substrate temperature is lower than 600°C, it is difficult for crystals of the nanocores to grow and rearrange, making it difficult to achieve a heat treatment effect. When the substrate temperature is higher than 1200°C, nitrogen (N) will outgas from the GaN crystal faces, thus deteriorating the crystal quality. Furthermore, when the time is less than one second, it is difficult to achieve a sufficient heat treatment effect, and heat treatment lasting for several tens of minutes, for example,for a period of more than 60 minutes, may degrade the efficiency of the manufacturing process.

[0064] The regrowth process introduced in this step can be performed under conditions similar to those used to grow the nanocores 35a. For example, n-doped GaN can be regrown on the surfaces of the nanocores 35a by resuming an MOCVD process under conditions similar to those used to grow n-doped GaN for the nanocores 15a after removing the mask.

[0065] As in Fig. 13, when the nanocores 35a are grown on a C(0001) plane of a sapphire substrate (a (111) plane in the case of a silicon substrate), the nanocores 35a having a cylindrical shape can be heat-treated or regrown in a suitable temperature range as mentioned above to change a curved surface (side surface), an unstable crystal face, into a hexagonal crystal column (35a' in Fig. 14) with a non-polar plane (m-plane) as a stable crystal face. Stabilization of the crystal face can be achieved by a heat treatment process conducted at a high temperature or by a regrowth process.

[0066] As for the heat treatment, when crystals arranged on the surface are rearranged at a high temperature or a source gas remains inside a chamber, such residual source gas is separated to perform partial regrowth to form a stable crystal face.

[0067] Especially if the regrowth procedure is carried out as in Fig. 13, TMGa and NH 3 into a MOCVD chamber, and the supplied TMGa and NH 3 can react on the surfaces of the nanocores 35a to perform regrowth and form stable crystal planes. Due to this regrowth, widths of the regrown nanocores 35a' can be slightly increased relative to those of the nanocores 35a before the regrowth process (see Fig. 13 and Fig. 14).

[0068] In this way, the crystallinity of the nanocores can be increased by introducing the additional heat treatment or regrowth process. Thus, through the heat treatment and regrowth processes, irregularities (e.g., defects or the like) present on the surfaces of the nanocores after mask removal can be removed, and crystal stability can be greatly increased by rearranging the internal crystals. The regrowth process can be performed by in-situ growth under conditions similar to those used to grow the nanocores after mask removal.

[0069] Then, as in Fig. 8, the active layer 35b and the semiconductor layer 35c of the second conductivity type are grown on the surfaces of the plurality of nanocores 35a'.

[0070] By this method, each light-emitting nanostructure 35 can have a core-shell structure including the nanocore 35a' formed from the semiconductor of the first conductivity type, the active layer 35b covering the nanocore 35a', and a shell layer formed from the semiconductor layer of the second conductivity type 35b.

[0071] The nanocore 35a' may have a tip portion with a crystal face different from the side surface thereof. As mentioned above, portions II of the active layer 35b and the second conductivity-type semiconductor layer formed on the tip portion and portions I of the active layer and the second conductivity-type semiconductor layer may have different compositions and / or thicknesses. To address leakage current and a problem of emitted light wavelength, the current-blocking intermediate layer 34 is disposed on the tip portion of the nanocore 35a.Due to the selective deposition of the current-blocking intermediate layer 34, current flow through the active region formed on the tip portion of the nanocore 35a' can be blocked by the current-blocking intermediate layer 34, while current flow through the active layer region formed on the side surface of the nanocore 35a' can be normally ensured.

[0072] Accordingly, a leakage current concentrated at the tip portion of the nanocore 35a' can be suppressed, increasing the efficiency, and a desired wavelength of the emitted light can be accurately designed.

[0073] The mask used in the exemplary embodiment described above includes the two material layers, but the present disclosure is not limited thereto, and the mask may also be realized with three or more layers.

[0074] For example, in a case where a mask has first to third material layers sequentially formed on the base layer, the second material layer as an etch stop layer may be formed from a material different from that of the first and third material layers. The first to third material layers may be formed from the same material if necessary.

[0075] Under etching conditions of the third material layer, at least the second material layer has an etch rate that is lower than that of the third material layer, so that the second material layer acts as an etch stop layer. The at least first material layer can be formed from a material with electrically insulating properties, and the second or third material layer can also be formed from an insulating material if necessary.

[0076] At the Fig. Electrodes with different structures can be formed in the light-emitting nanostructure semiconductor device shown in Figure 8. Fig. 15 to 19 are cross-sectional views illustrating main processes of an example of forming an electrode.

[0077] First, as in Fig. 15 shows a contact electrode 36 on the Fig. 8 obtained light-emitting nanostructures 35.

[0078] The contact electrode 36 may contain a suitable material that realizes an ohmic contact with the semiconductor layer of the second conductivity type 35c on surfaces of the light-emitting nanostructures 35. The material for the ohmic contact may contain at least one of materials such as ITO, ZnO, a graphene layer, Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt and Au, and may have a structure with two or more layers, such as Ni / Ag, Zn / Ag, Ni / Al, Zn / Al, Pd / Ag, Pd / Al, Ir / Ag, Ir / Au, Pt / Ag, Pt / Al or Ni / Ag / Pt. In a specific example, the Fig. The contact electrode 36 shown in Figure 15 may be formed by applying an electroplating process to the ohmic contact material used as a seed layer. For example, Cu / Ni may be plated to form the desired contact electrode 36 after Ag / Ni / Cr layers are formed as seed layers.

[0079] The contact electrode used in the present exemplary embodiment may be a reflective metal layer for coupling out light in a direction toward the substrate, but the present disclosure is not limited thereto, and the contact electrode 36 may be formed of a transparent electrode material, such as indium tin oxide (ITO), for coupling out light in a direction toward the light-emitting nanostructures 35.

[0080] Afterwards, as in Fig. 16, exposed regions e1 in which the light-emitting nanostructures 35 are exposed are formed in regions in which an electrode with a polarity is to be formed, and are formed as shown in Fig. 17, the exposed light-emitting nanostructures 36 are selectively removed to form exposed base regions e2 in which portions of the base layer 32 are exposed. Fig. The process shown in Figure 16 is an etching process for an electrode material such as metal, and the Fig. The process shown in Figure 17 is an etching process for a semiconductor material. Both processes can be performed under different conditions.

[0081] Then, as in Fig. As shown in Figure 18, an insulating layer 37 is formed such that contact regions Ta and Tb of an electrode are exposed. The contact regions T1 of a first electrode may be provided as at least partial regions of the exposed regions e2 of the base layer 32, and the contact region Tb of a second electrode may be provided as a region in which a portion of the contact electrode 36 is exposed.

[0082] Afterwards, as in Fig. 19, first and second electrodes 39a and 39b are formed so as to be connected to the contact regions Ta and Tb of the first and second electrodes, respectively. As an electrode material used in this method, a common electrode material of the first and second electrodes 39a and 39b may be used. For example, a material for the first and second electrodes 39a and 39b may be Au, Ag, Al, Ti, W, Cu, Sn, Ni, Pt, Cr, NiSn, TiW, AuSn, or a eutectic metal thereof.

[0083] Fig. 20 to 23 are cross-sectional views showing main processes of forming light-emitting nanostructures using the Fig. 5 shown mask 43.

[0084] As in Fig. As shown in Figure 20, nanocores 65a can be grown on a base layer 62 using the mask 43. The mask 43 has openings with a width that decreases toward a lower portion thereof. The nanocores 65a can be grown to have a shape corresponding to that of the openings.

[0085] To further improve the crystal quality of the nanocores 65a, a heat treatment process may be performed one or more times during the growth of the nanocores 65a. Specifically, a surface of a tip portion of each nanocore 65a may be rearranged to have a hexagonal-pyramidal crystal face, thus maintaining a stable crystal structure and ensuring high quality of a crystal grown in a subsequent process.

[0086] The heat treatment process can be performed under the temperature conditions described above. For example, for convenience, the heat treatment process may be performed at a temperature equal to or similar to the growth temperature of the nanocores 65a. Furthermore, the heat treatment process may be performed such that a metal source such as TMGa is stopped while maintaining a pressure and temperature equal to or similar to the growth pressure and growth temperature of the nanocores 65a. The heat treatment process may be continued for a few seconds to a few tens of minutes (e.g., 5 seconds to 30 minutes), but a sufficient effect can be achieved even with a time period in a range of about 10 seconds to 60 seconds.

[0087] The heat treatment process introduced during the growth process of the nanocores 65a can prevent the deterioration of crystallinity caused when the nanocores 65a are grown at a high speed, and thus can promote rapid crystal growth and excellent crystal quality.

[0088] The time of a heat treatment process step and the number of heat treatment processes for stabilization can be variously modified according to the height and diameter of the final nanocores. For example, in a case where the width of each aperture is in a range of 300 nm to 400 nm and the height of each aperture (thickness of the mask) is about 2.0 µm, a stabilization period in a range of about 10 seconds to 60 seconds can be introduced at a center point, i.e., about 1.0 µm, to grow cores with the desired high quality. The stabilization process can be omitted according to the core growth conditions.

[0089] Afterwards, as in Fig. 21, a current-blocking intermediate layer 64 may be formed on tip portions of the nanocores 65a.

[0090] After the nanocores 65a are formed with a desired height, the current-blocking intermediate layer 64 can be formed on the surfaces of the tip portions of the nanocores 65a while maintaining the mask 43 as it is. Thus, since the mask 43 is used as it is, the current-blocking intermediate layer 64 can be easily formed in the desired areas (the surface of the tip portions) of the nanocores 65a without forming an additional mask.

[0091] The current-blocking interlayer 64 may be a semiconductor layer that is not intentionally doped, or may be a semiconductor layer doped with an impurity of a second conductivity type opposite to that of the nanocores 65a. For example, in a case where the nanocores are n-doped GaN, the current-blocking interlayer 64 may be undoped GaN or GaN doped with magnesium (Mg) as a p-type impurity. In this case, the nanocores 65a and the current-blocking interlayer 64 may be continuously formed by changing impurity types during the same growth process.For example, in a case of stopping silicon (Si) doping and introducing magnesium (Mg) and growing it for about one minute under the same conditions as those for growing the n-doped GaN nanocores, the current-blocking interlayer 64 can be formed with a thickness ranging from about 200 nm to 300 nm, and such a current-blocking interlayer 64 can effectively block a leakage current of several µA or more. In this way, the current-blocking interlayer can be easily formed during the mold-type process as in the present exemplary embodiment.

[0092] Then, as in Fig. 22 shows portions of the mask layer 43 to reach the first material layer 43a as an etch stop layer removed to expose side surfaces of the plurality of nanocores 65a.

[0093] In the present exemplary embodiment, by applying the etching process of selectively removing the second material layer 43b, only the second material layer 43b may be removed, while the first material layer 43a may be retained. The remaining first material layer 43a may serve to prevent the active layer and the second conductivity type semiconductor layer from being connected to the base layer 62 in a subsequent growth process.

[0094] In the present exemplary embodiment, an additional heat treatment or regrowth may be introduced during the process of forming the light-emitting nanostructures using the mask with openings as a mold to increase crystallinity.

[0095] After the second material layer 43b of the mask 43 has been removed, the surfaces of the nanocores 65a can be heat-treated or regrown under predetermined conditions to convert unstable crystal faces of the nanocores 65a into stable crystal faces (see Fig. 13 and Fig. 14). Specifically, in the present exemplary embodiment, the nanocores 65a are grown on the openings with slanted sidewalls to have the slanted sidewalls corresponding to the shape of the openings, but as shown in Fig. As shown in Figure 23, after the heat treatment or regrowth is performed, crystals are rearranged or regrown on the surfaces of the nanocores 65a so that the nanocores 65a' have a substantially uniform diameter (or width). Furthermore, the tip portions of the nanocores 65a immediately after they are grown have an incomplete hexagonal-pyramidal shape, but the nanocores 65a' can have a hexagonal-pyramidal shape with uniform surfaces after the heat treatment or regrowth. In this way, the nanocores with a non-uniform width can be regrown (and rearranged) after mask removal to have a hexagonal-pyramidal columnar structure with a uniform width by the heat treatment or regrowth process.

[0096] In the following, the results of regrowth (rearrangement) of the nanocores based on the heat treatment process as described above will be described through a specific experimental example. Experimental example (heat treatment process)

[0097] Two layers of SiN / SiO 2 are formed on an n-doped GaN base layer and openings are formed. Here, the SiN layer (“a” in Fig. 24) was formed to have a thickness of about 100 nm, and the SiO 2 -layer (“b” in Fig. 24) was formed to have a thickness of 2500 nm. Openings of the mask were formed by performing etching with a plasma obtained by combining C 4 F 8 , O 2 and Ar for about 5 minutes through a photoresist (a layer arranged on “b” in Fig. 24) procedure. Fig. Figure 24 is a scanning electron microscopy (SEM) photograph obtained by imaging a cross-section of an opening obtained by the method. As shown in Fig. As shown in Figure 24, the opening of the mask has a width which decreases towards a lower section thereof.

[0098] Nanocores were grown on the openings of the mask using a MOCVD process. TMGa and NH 3 were used as source gases, and nanonuclei were grown for about 20 minutes while the temperature of a substrate was maintained at about 1100°C.

[0099] To improve the crystal quality of the nanocores, a stabilization process (heat treatment) was additionally performed during the growth of the nanocores. Thus, when the nanocores 35a reached a height of approximately 1.0 µm during growth, the supply of the nanocores with a TMGa source was stopped at a desired intermediate point (approximately 10 minutes), and a heat treatment was performed at a temperature (approximately 1100°C) similar to that of the substrate during growth for approximately 30 seconds to 50 seconds in an NH 3 atmosphere. The regrowth process was then carried out under conditions similar to those used to grow the nanocores.

[0100] After the growth of the desired nanocores was completed, the SiO 2 -layer (“b” in Fig. 24) of the mask. The nanocores corresponding to the shape of the openings appeared with a cylindrical shape with sloping side walls (see Fig. 25). The nanocores with the cylindrical structure were investigated and had a height of about 2467 nm and a diameter of about 350 nm.

[0101] After the mask was removed, a heat treatment process was applied. The heat treatment process was carried out at a substrate temperature of approximately 1100°C (1000°C to 1200°C) for approximately 20 minutes (15 minutes to 25 minutes).

[0102] After the heat treatment process, crystals of the nanocores were regrown and rearranged, and it was confirmed that the diameter, which was not uniform in the height direction, was changed to a substantially uniform diameter, and the incomplete hexagonal-pyramidal shape of the tip portions of the nanocores was changed to a hexagonal-pyramidal shape with uniform surfaces after the heat treatment processes (see Fig. 26).

[0103] In detail, the diameter w1 of each nanocore was 350 nm before the heat treatment process, but after the heat treatment process, the width (w2: interval between two faces of the hexagon) was about 410 nm, about 60 nm or larger. Furthermore, it was confirmed that while the degree of increase was small, the height of the nanocore changed from 2467 nm to 2470 nm, showing an increase of about 3 nm.

[0104] As in the experimental example, it was confirmed that the nanocores with an uneven width were regrown (and rearranged) after the mask was removed to have the hexagonal-pyramidal columnar structure with a uniform width due to the heat treatment process.

[0105] During the preceding heat treatment process, the size and shape of the nanocores after regrowth can be relatively changed depending on the heat treatment process temperature (namely, the substrate temperature) and the heat treatment process time, whether a source gas is supplied or not, or the amount of the supplied source gas. For example, the heat treatment is performed at a temperature of 1000°C or more for 5 minutes or more in a state where the supply of a source gas is stopped. Crystals are rearranged on the surface of the nanocores, and the change in the size of the nanocores due to an etching effect (namely, N outgassing) is reduced. The change in the diameter of the nanocores can be kept at a level of 50% or less, considering the process time, conditions, and cost.As described above, the uniformity of the diameter (or width) of the nanocores can also be maintained at 95% or more by adding the regrowth process. In this case, the diameter of each nanocore grown in a group where the mask aperture sizes are equal can be substantially the same.

[0106] With the foregoing exemplary embodiment, the example of a method for manufacturing a nanostructure semiconductor light-emitting device for growing nanonuclei using a mask with openings as a molding structure has been described, but the exemplary embodiment may be modified or improved in various specific examples.

[0107] At least a portion of the plurality of nanocores may be designed such that at least a cross section (or a diameter) thereof or an interval therebetween is different from that of other nanocores.

[0108] In the foregoing exemplary embodiment, the n-side current-blocking interlayer disposed on the tip portions of the nanocores below the active layer was described, but such a current-blocking interlayer may also be implemented below the second conductivity type semiconductor layer as a p-side current-blocking interlayer formed on the region of the active layer corresponding to the tip portions of the nanocores. Fig. 27 is a cross-sectional view illustrating a nanostructure semiconductor light-emitting device having a p-side current-blocking interlayer according to another embodiment of the present invention.

[0109] A light-emitting nanostructure semiconductor device 80 which is Fig. 27, includes a base layer 82 formed on a semiconductor material of a first conductivity type, and a plurality of light-emitting nanostructures 85 formed on the base layer 82.

[0110] Each light-emitting nanostructure 85 includes a nanocore 85a formed of a semiconductor of the first conductivity type, and an active layer 85b and a semiconductor layer of a second conductivity type 85c, which are sequentially formed on a surface of the nanocore 85.

[0111] The nanostructure semiconductor light-emitting device 80 may include a contact electrode 86 connected to the second conductivity-type semiconductor layer 85c. An insulating protective layer 88 may be formed on the nanostructure light-emitting device 85. The nanostructure semiconductor light-emitting device 80 may include first and second electrodes 89a and 89b. The first electrode 89a may be disposed in a partially exposed region of the base layer 82 formed of the first conductivity-type semiconductor. Furthermore, the second electrode 89b may be disposed in an exposed portion of an extended region of the contact electrode 86.

[0112] The present exemplary embodiment may be similar to that shown in Fig. 1, and a description of the respective corresponding elements which are described with reference to Fig. 1 may be combined with descriptions of the present exemplary embodiment unless otherwise mentioned.

[0113] As in Fig. As shown in Figure 27, the nanocore 85 has a tip portion T with a crystal face different from those of the other regions.

[0114] Unlike the Fig. 1, the current-blocking intermediate layer 87 used in the present exemplary embodiment is formed in a region 87a corresponding to a tip portion T of the nanocore 85a so as to be disposed between the active layer 85b and the second conductivity type semiconductor layer 85c, and extends from the region 87a to a region 87b corresponding to a side surface of the nanocore 85a.

[0115] The current-blocking intermediate layer 87 may be an undoped semiconductor layer or a semiconductor layer doped with an impurity of a first conductivity type. The current-blocking intermediate layer 87 may be undoped GaN or GaN doped with an n-type impurity such as silicon (Si).

[0116] In particular, as in Fig. As shown in Fig. 27, the current-blocking intermediate layer 87 may be formed on the entire surface of the nanostructure such that portions located on the side surface and the tip portion of the nanocores 85a have different thicknesses. Thus, in the current-blocking intermediate layer 87, a thickness t2 of the portion 87b located in the region corresponding to the side surface of the nanocore 85a is smaller than a thickness t1 of the portion 87a located in the region corresponding to the tip portion of the nanocore 85a. The thickness variations can be easily realized by setting growth conditions for the semiconductor single crystal such that growth in a vertical direction dominates. The thickness variations can be controlled by appropriately adjusting growth process factors (e.g., pressure, source flow rate, temperature, and the like).

[0117] In the present exemplary embodiment, the current-blocking intermediate layer 87 has the sufficient thickness t1 in the tip portion T of the nanocore 85a, a leakage current LC can be effectively prevented, and since the current-blocking intermediate layer 87 has a relatively small thickness t2 on the side surface of the nanocore 85a, a desired electrical conductivity for driving the light-emitting device can be ensured.

[0118] To effectively ensure selective blocking and electrical conduction, the current-blocking intermediate layer 87 is formed to have sufficient thickness variation. In the current-blocking intermediate layer 87, the thickness t1 of the portion 87a corresponding to the tip portion of the nanocore 85a may be about 50 nm or more, and the thickness t2 of the portion 87b located in the region corresponding to the side surface of the nanocore 85a may be about 20 nm or less.

[0119] Accordingly, a current flow C1 to the active layer region formed on the side surface of the nanocore 85a is normally ensured, while a current flow C2 to the active layer region formed at the tip portion of the nanocore 85a is interrupted by the current-blocking intermediate layer 87.

[0120] The resistance adjustment can also be realized by the impurity concentration, but in a case where two regions are grown by the same method, it may be easier to adjust the thicknesses of the respective regions to form a desired selective high resistance structure.

[0121] In the case of adjusting the thicknesses of the two portions of the current-blocking intermediate layer 87, the portion 87b located in the region corresponding to the side surface of the nanocore 85a and the portion 87a located in the region corresponding to the tip portion of the nanocore 85a may have substantially the same impurity concentration. The current-blocking intermediate layer 87 may be doped with the first conductivity type impurity at a concentration such that the current-blocking intermediate layer 87 has a suitable resistance of about 1.0 10 16 / cm 3 or more.

[0122] In the present exemplary embodiment, the current-blocking intermediate layer 87 may extend to be adjacent to a surface of the insulating layer 83. The portion 87b located in the region corresponding to the side surface of the nanocore 85a may extend to the insulating layer 83 to effectively block a leakage current LC generated in a space between the insulating layer 83 and the semiconductor layer (particularly, the active layer 85b). Here, the generated leakage current LC is small relative to that in the tip portion T, and thus, an additional leakage current suppression effect can be achieved even if the thickness t2 is small. To achieve such a leakage current suppression effect, the thickness t2 of the portion 87b located in the region corresponding to the side surface of the nanocore 85a may be about 5 nm or more.

[0123] Hereinafter, the method of manufacturing a nanostructure semiconductor light-emitting device according to the present exemplary embodiment will be described with reference to Fig. 28 to 30 and Fig. 31 to 35 are described.

[0124] Fig. 28 to 30 are cross-sectional views illustrating main processes of forming a nano-light-emitting structure in the method of manufacturing a nano-light-emitting semiconductor device according to the present exemplary embodiment.

[0125] As in Fig. 28, an insulating layer 93 is formed as a mask on a base layer 92 formed of a semiconductor of a first conductivity type, a plurality of nanocores 95a are formed on exposed portions of the base layer 92, and an active layer 95b is formed on surfaces of the plurality of nanocores 95a (the heat treatment method or the regrowth method described above with reference to Fig. 13 and Fig. 14 can also be applied to this procedure and detailed descriptions thereof are omitted).

[0126] The mask 93 has openings H for growing the nanocores 95. Such an opening H may not be formed in regions E1 and E2 where electrodes are to be formed to grow the nanocores 95a therein. As described above, a tip portion T of each nanocore 95a has a crystal face (e.g., an r-plane) different from a crystal face (e.g., m-plane) of a side surface thereof, thereby causing the active layer 95b to have different compositions according to the crystal faces and to have a relatively small thickness, resulting in a change in the emitted light wavelength characteristic and generation of a leakage current.

[0127] Then, as in Fig. 29, a current-blocking intermediate layer 97 is formed on a surface of the active layer 95b. The current-blocking intermediate layer 97 may be formed to extend from a region corresponding to the tip portion T of the nanocore 95a to a region corresponding to the side surface of the nanocore 95a.

[0128] In this way, the current-blocking intermediate layer 97 is formed on the entire surfaces of the nanostructure, but a thickness t2 of the portion located in the region corresponding to the side surface of the nanocore 95a may be smaller than a thickness t1 of the portion located in the region corresponding to the tip portion of the nanocore 95a.

[0129] The current-blocking intermediate layer 97 may be an undoped semiconductor layer or a semiconductor layer doped with an impurity of a first conductivity type. The current-blocking intermediate layer 97 may be undoped GaN or GaN doped with an n-type impurity, such as silicon (Si).

[0130] Afterwards, as in Fig. As shown in Figure 30, a second conductivity-type semiconductor layer 95c is formed on the current-blocking intermediate layer 97. Accordingly, the current-blocking intermediate layer 97 can be disposed between the active layer 95b and the second conductivity-type semiconductor layer 95c. With this structure, current flow to a region of the active layer 95b formed on the side surface of the nanocore can be ensured normally, while current flow to the region of the active layer 95b formed at the tip portion of the nanocore 95a can be ensured.

[0131] At the Fig. Electrodes with various arrangements can be formed in the nanostructure semiconductor light-emitting device shown in Figure 30. Fig. 31 to 35 are cross-sectional views illustrating main processes for forming electrodes.

[0132] As in Fig. As shown in Figure 31, a contact electrode 96 is formed on the light-emitting nanostructures 95, and then a first passivation layer 98a is formed. Such a first passivation layer 98a may be formed from various insulating protective layer materials as mentioned above in the previous exemplary embodiment.

[0133] Then, as in Fig. 32, the first passivation layer 98a is selectively removed to expose portions of the base layer 92 and the contact electrode 96 to provide electrode formation regions (e1). Additionally, the exposed regions e1 may be designated as regions in which a first electrode is to be formed. This process can be implemented using a general photolithography method.

[0134] Afterwards, as in Fig. 33, a photoresist PR is formed to define contact areas e2 of a first and a second electrode. Subsequently, as shown in Fig. 34, first and second electrodes 99a and 99b are formed in the contact regions of the first and second electrodes. As an electrode material used in this method, a general electrode material of the first and second electrodes 99a and 99b can be used. For example, a material for the first and second electrodes 99a and 99b can be Au, Ag, Al, Ti, W, Cu, Sn, Ni, Pt, Cr, NiSn, TiW, AuSn, or a eutectic metal thereof.

[0135] Then, as in Fig. 35, an additional second passivation layer 98b may be formed as needed. The second passivation layer 98b may provide a protective layer 98 along with the first passivation layer 98a. The second passivation layer 98b may cover the exposed semiconductor region to protect it and may also firmly hold the first and second electrodes 99a and 99b.

[0136] The second passivation layer 98b may be formed from a material identical to that of the first passivation layer 98a.

[0137] Fig. 36 to 39 are cross-sectional views showing main processes of an example of forming an electrode with respect to the Fig. 30 shown device.

[0138] First, as in Fig. 36 shows a contact electrode 106 on the Fig. 30 obtained light-emitting nanostructure 95. The contact electrode 106 can be similar to the one described above with reference to Fig. 5 described.

[0139] The contact electrode 106 may include a suitable material capable of establishing ohmic contact with the second conductivity type semiconductor layer 95c on a surface of the light-emitting nanostructure 95. The ohmic contact material may include at least one of ITO, ZnO, a graphene layer, Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, and the like, and may include a two- or multi-layer structure such as Ni / Ag, Zn / Ag, Ni / Al, Zn / Al, Pd / Ag, Pd / Al, Ir / Ag, Ir / Au, Pt / Ag, Pt / Al, Ni / Ag / Pt, and the like. Preferably, the ohmic contact material used to form the contact electrode 106 may be a reflective metal layer in consideration of light outcoupling efficiency. In a specific example, the Fig. The contact electrode 106 shown in Figure 36 may be formed by applying an electroplating process to the ohmic contact material as a seed layer. For example, after forming Ag / Ni / Cr as seed layers, Cu / Ni may be electroplated to form the desired contact electrode 106.

[0140] Afterwards, as in Fig. 37, a permanent substrate 115 can be bonded to the contact electrode 106.

[0141] The permanent substrate 115 may be an insulating or a conductive substrate. For example, the permanent substrate 115 may be a silicon (Si) substrate or a Si-Al alloy substrate. The permanent substrate 115 may be bonded to the contact electrode 106 using a bonding metal layer 111. The bonding metal layer 111 may be formed from a metal selected from the group consisting of Ni, Pt, Au, Cu, Co, Sn, In, Zn, Bi, Au, and combinations thereof, or alloys thereof. For example, the bonding metal layer 111 may be a eutectic metal layer such as Ni / Sn.

[0142] Afterwards, as in Fig. 38, a substrate 81 used for growing crystals is removed from the semiconductor base layer 92 of the first conductivity type.

[0143] This process can be performed using a laser lift-off (LLO) method or a grinding / etching method. For example, in a case where the substrate 81 is a sapphire substrate, the growth substrate 81 can be separated from the first conductivity-type semiconductor base layer 92 by irradiating a laser beam onto an interface between the substrate 81 and the first conductivity-type semiconductor base layer 92. Meanwhile, in a case where the substrate 81 is an opaque substrate such as silicon (Si), the substrate 81 can be removed using a grinding / etching method.

[0144] Then, as in Fig. As shown in Fig. 39, an electrode pad 116 is formed on a surface of the first conductivity-type semiconductor base layer 92 from which the growth substrate 81 has been removed to obtain a desired nanostructure semiconductor light-emitting device 110. The permanent substrate 115, a conductive substrate, can be used as an electrode connected to an external circuit.

[0145] Fig. 40 is a cross-sectional view showing a light-emitting device package having the Fig. 15 represents the light-emitting nanostructure semiconductor device.

[0146] One in Fig. The light-emitting device package shown in Figure 40 includes a package substrate 121 having first and second electrode units 122a and 122b, and a nanostructure semiconductor light-emitting device 110 mounted on the package substrate 121.

[0147] A permanent substrate 115 of the nanostructure semiconductor light-emitting device 110 is connected to the first electrode unit 122a of the package substrate 121, and an electrode pad of the nanostructure semiconductor light-emitting device 110 may be connected to the second electrode unit 122b of the package substrate 121 with a wire W.

[0148] In the package 100 according to the present exemplary embodiment, a contact electrode 96 is formed as a highly reflective electrode, whereby a light outcoupling efficiency of the nanostructure semiconductor light-emitting device can be significantly improved.

[0149] Fig. 41 is a cross-sectional view illustrating a nanostructure semiconductor light-emitting device according to another exemplary inventive embodiment of the present disclosure. In the exemplary embodiment, an n-side current-blocking interlayer and a p-side current-blocking interlayer are combined as described above.

[0150] One in Fig. 41 includes a base layer 152 formed from a semiconductor material of a first conductivity type and a plurality of light-emitting nanostructures 155 formed on the base layer 152.

[0151] Each light-emitting nanostructure 155 includes a nanocore 155a formed from a semiconductor material of the first conductivity type, and an active layer 155b and a semiconductor layer of a second conductivity type 155c formed sequentially on a surface of the nanocore 155a.

[0152] In the present exemplary embodiment, descriptions may be made with reference to Fig. 1 and Fig. 27 combined with detailed descriptions of an electrode structure according to the present exemplary embodiment, and descriptions of the respective elements corresponding to the Fig. 1 can be combined with the descriptions of the present exemplary embodiment.

[0153] As in Fig. As shown in Figure 41, the nanocore 155a contains a tip portion T with a crystal face different from those of the other regions.

[0154] The nanostructure semiconductor light-emitting device 150 according to the present exemplary embodiment includes a first current-blocking interlayer 154 formed on an n-side and a second current-blocking interlayer 157 formed on a p-side, based on the active layer 155b as a reference. The first current-blocking interlayer 154 is formed at a tip portion T of the nanocore 155a such that it is sandwiched between the active layer 155b and the nanocore 155a. Furthermore, the second current-blocking interlayer 157 is formed in a region corresponding to the tip portion T of the nanocore 155a such that it is sandwiched between the active layer 155b and the second conductivity-type semiconductor layer 155c.

[0155] The first current-blocking intermediate layer 154 may be an undoped semiconductor or a semiconductor doped with an impurity of the second conductivity type, and the second current-blocking intermediate layer 157 may be an undoped semiconductor layer or a semiconductor layer doped with an impurity of the first conductivity type.

[0156] A thickness t0 of the first current-blocking intermediate layer 154 may be about 20 nm or more, preferably 50 nm or more, to obtain a sufficient electrical resistance. With the second conductivity type impurity of the first current-blocking intermediate layer 154, a desired high resistance of about 1.0 10 16 / cm 3 or more can be achieved.

[0157] Unlike the first current-blocking intermediate layer 154, the second current-blocking intermediate layer 157 may be formed on the entire surface of the nanostructure, so that portions thereof located on the side surface and on the tip portion T may have different thicknesses. Thus, in the second current-blocking intermediate layer 157, a thickness t2 of the portion 157b located in the region corresponding to the side surface of the nanocore 155a may be smaller than a thickness t1 of the portion 157a located in the region corresponding to the tip portion T of the nanocore 155a.

[0158] In the present exemplary embodiment, since the second current-blocking intermediate layer 157 has the sufficient thickness t1 in the tip portion T of the nanocore 155, a leakage current can be effectively prevented, and since the second current-blocking intermediate layer 157 has a relatively small thickness t2 on the side surface of the nanocore 155a, a desired electrical conduction for driving the light-emitting device can be ensured.

[0159] To effectively ensure selective blocking and electrical conduction, the second current-blocking intermediate layer 157 is formed with appropriate thickness variations. In the second current-blocking intermediate layer 157, the thickness t1 of the portion 157a corresponding to the tip portion T of the nanocore 155a is about 50 nm or more, and the thickness t2 of the portion 157b located in the region corresponding to the side surface of the nanocore 155 may be about 20 nm or less.

[0160] Furthermore, the second current-blocking intermediate layer 157 may extend to be adjacent to a surface of the insulating layer 153. The portion 157b located in the region corresponding to the side surface of the nanocore 155a may extend to the insulating layer 153 to effectively block a leakage current generated in a region between the insulating layer 153 and the semiconductor layer (particularly, the active layer 155b). To achieve such a leakage current suppression effect, the thickness t2 of the portion 157 located in the region corresponding to the side surface of the nanocore 155 may be about 5 nm or more.

[0161] In the following, conditions of a current-blocking interlayer along with effects of the present disclosure will be described in detail by certain exemplary embodiments. Embodiment 1

[0162] A mask with a two-layer structure with SiN x (120 nm) / SiO 2 (1900 nm) was formed on an n-doped GaN layer as a base layer. A plurality of openings, each with a diameter of approximately 300 nm, were formed in the mask by an etching process. N-doped GaN nanocores were grown to a height of approximately 1800 nm using the mask as a mold.

[0163] Then, keeping the mask as it is, a p-doped GaN layer containing a magnesium (Mg) impurity with a concentration of about 5 10 17 / cm 3 was doped, with a thickness of about 100 nm on the upper surfaces of the nanocores. Afterwards, the SiO 2-layer, an upper layer of the mask, was removed, and the nanocores were heat-treated at a temperature of about 1100°C. Subsequently, an active layer with a plurality of In 0,2 Ga 0,8 N-well layers and a plurality of GaN barrier layers, a p-doped AlGaN EBL layer and p-doped GaN on surfaces of the nanocores as shell layers are formed to form light-emitting nanostructures.

[0164] An ITO layer was deposited on surfaces of the thus-obtained light-emitting nanostructures, spaces between the light-emitting nanostructures were filled so that the light-emitting nanostructures were covered by using spin-on glass (SOG), and electrode structures were formed, thereby fabricating a light-emitting nanostructure semiconductor device.

[0165] With the nanostructure semiconductor light-emitting device obtained in Embodiment 1, a current blocking effect by the current-blocking interlayer was tested while increasing an applied current stepwise from 30 mA to 120 mA. The results are shown as a graph in Fig. 42 shown.

[0166] As in Fig. 42, experimental results of this embodiment show that a width of wavelength fluctuations was 27 nm. It can be seen that such a width of wavelength fluctuations is significantly smaller than a width (about 39 nm) of wavelength fluctuations in the case where no current-blocking intermediate layer was provided.

[0167] Since the active layer disposed on the surface (r-plane) of the tip portion of each nanocore has a large variation width of wavelength according to an applied current relative to the active layer in other regions, such a reduction (smaller width) indicates that the current-blocking intermediate layer disposed on the surface (r-plane) of the tip portion of the nanocore according to this embodiment effectively blocks a current in the corresponding region. Embodiment 2

[0168] Similar to Embodiment 1, a mask having a two-layer structure with SiN x (120 nm) / SiO 2(1900 nm) was formed on an n-doped GaN layer as a base layer. A plurality of openings, each having a diameter of approximately 300 nm, were formed in the mask by an etching process. Nanocores (n-doped GaN) were grown with a height of approximately 1800 nm using the mask as a mold.

[0169] However, in this embodiment, unlike Embodiment 1, a current-blocking intermediate layer was formed after forming an active layer. Thus, the SiO 2 -layer, an upper layer of the mask, was first removed, nanocores were heat-treated at a temperature of about 1100°C, an active layer with a plurality of In 0,2 Ga 0,8 N-well layers and a plurality of GaN barrier layers were formed, and a current-blocking intermediate layer, an n-doped GaN layer containing a silicon (Si) impurity with a concentration of about 5 10 17 / cm 3was doped, formed on the active layer. The current-blocking intermediate layer was formed on one side surface in such a way that it was connected to the remaining SiN x -layer. Here, growth conditions of the current-blocking interlayer were enhanced in a vertical direction to set a thickness of the current-blocking interlayer in the tip portion larger than that of the current-blocking interlayer on the side surface (a thickness of the current-blocking interlayer in the tip portion was about 80 nm, and a thickness thereof on the side surface was about 15 nm).

[0170] Subsequently, a p-doped AlGaN EBL layer and a p-doped GaN layer were sequentially formed on the current-blocking interlayer to form light-emitting nanostructures. An ITO layer was deposited on the surfaces of the light-emitting nanostructures, and an ITO layer was deposited on the surfaces of the thus-obtained light-emitting nanostructures. Spaces between the light-emitting nanostructures were filled to cover the light-emitting nanostructures using spin-on glass (SOG), and electrode patterns were formed, thereby fabricating a light-emitting nanostructure semiconductor device.

[0171] With the nanostructure semiconductor light-emitting device obtained in Embodiment 2, a current blocking effect by the current-blocking interlayer was tested while increasing an applied current stepwise from 10 mA to 120 mA. The results are shown as a graph in Fig. 43 shown.

[0172] As in Fig. As shown in Figure 43, experimental results of this embodiment showed that a width of wavelength deviation was 24 nm. Thus, compared with the case (50 nm) without a current-blocking interlayer, the width of wavelength deviation is significantly smaller. This is because the current-blocking interlayer formed at the r-plane, i.e., the tip portion, according to this embodiment reduces the influence of wavelength variations according to an applied current through the r-plane. In this way, it can be seen that the current-blocking interlayer according to this embodiment efficiently blocks a current in the tip portion of the nanostructure.

[0173] In addition, as in Fig. 45, in the structure of the related art C2, a leakage current was 150 mA at -4 V, but it can be seen that when a current-blocking intermediate layer according to this embodiment E2 was provided, a leakage current was significantly suppressed to 5 mA. This is because, as described above with reference to Fig. 27, the effect of the presence of the current-blocking intermediate layer increases when a leakage current generated in a semiconductor layer disposed on a surface of an insulating layer and a leakage current generated at the tip portion of the nanocore are suppressed. Embodiment 3

[0174] In this exemplary embodiment, both current-blocking interlayers according to Embodiment 1 and Embodiment 2 were used. Thus, the n-side current-blocking interlayer (Mg-doped GaN or undoped GaN) was formed on an upper surface of the nanocores before the upper layer (SiO 2 ) of the mask was removed according to the method of Embodiment 1, and then the upper layer of the mask was removed, the active layer was formed on the surface of the nanocore, and the p-side current-blocking intermediate layer (Si-doped GaN or undoped GaN) was formed according to the method of Embodiment 2.

[0175] Next, similarly to the previous exemplary embodiment, an electrode and passivation forming process was performed to manufacture a semiconductor light-emitting device.

[0176] With the nanostructure semiconductor light-emitting device obtained in Embodiment 3, a current-blocking effect of the current-blocking interlayer was tested while increasing an applied current stepwise from 10 mA to 120 mA. The results are shown as a graph in Fig. 44. As shown in Fig. As shown in Figure 44, experimental results of this embodiment showed that the wavelength deviation width was 19 nm. Thus, the wavelength deviation width is significantly smaller compared to the case (50 nm) without a current-blocking interlayer.

[0177] Thus, it was confirmed that by using two types of current-blocking interlayer, a current was effectively blocked in the tip portion of the nanostructure.

[0178] Fig. 46 is a graph showing a change in current density versus doping concentration of a current-blocking interlayer, and Fig. Figure 47 is a graph showing a change in current density across a thickness of the current-blocking interlayer.

[0179] First, as in Fig. 46, in a configuration using the n-side current-blocking interlayer (between the active layer and the tip portion of the nanocore) and the p-side current-blocking interlayer (between the active layer and the p-doped semiconductor layer), with a thickness of the p-side current-blocking interlayer of 50 nm, a current density of about 160 arbitrary units when a concentration of the impurity of the opposite conductivity type is about 1.0 10 17 / cm 3Thus, the current density was reduced to 1 / 10 compared to the case without the current-blocking interlayer (current density ~1600 arbitrary units). In a case where a thickness of the p-side current-blocking interlayer was 100 nm, a current density was about 160 arbitrary units at a relatively low concentration of 1.0 10 16 / m 3 , which was reduced by 1 / 10 compared to the case (current density ~1600 arbitrary units) without the current-blocking intermediate layer.

[0180] As in Fig. As shown in Figure 47, it was confirmed that in the case where the n-side current-blocking interlayer and the p-side current-blocking interlayer were used separately, a current density was reduced to 1 / 10 when both current-blocking interlayers had a thickness of 50 nm or more. In the configuration where the two types of current-blocking interlayer were used, a desired effect was obtained even when the current-blocking interlayers had a smaller thickness of 30 nm or more.

[0181] In order to confirm the effect of improving the leakage current under high doping concentration conditions in the nanostructure semiconductor light-emitting device according to Embodiment 1, the occurrence of a leakage current was checked by changing an impurity concentration (p-type impurity) of the current-blocking intermediate layer up to 1 10 19 / cm 3. The doping concentration of silicon (Si), the n-type impurity of the nanocore used in this embodiment, was approximately at a level of 1~9 10 19 / cm 3 , and the occurrence of the leakage current was defined by a percentage of the leakage current when the current-blocking interlayer was used relative to a leakage current (current density: 1600 arbitrary units) when no current-blocking interlayer was used, and the measurement results are shown in Fig. 48 shown.

[0182] Referring to Fig. 48, it was confirmed that the leakage current improvement effects were slightly different according to the thicknesses. It can be seen that the occurrence of leakage current was reduced with increasing thickness from 50 nm to 200 nm. Thus, in a case where the impurity concentration was 1 10 17 / cm 3The occurrence of leakage current was 15% when the thickness of the current-blocking interlayer was 50 nm, 12% when the thickness was 100 nm, and 6.5% when the thickness was 200 nm, indicating that leakage current was significantly suppressed. Furthermore, when the impurity concentration was 1 10 18 / cm 3 or more, the occurrence of leakage current was 5% or less, and when the impurity concentration was 1·10 19 / cm 3 or more, the occurrence of leakage current was 1% or less regardless of a thickness of the current-blocking interlayer, indicating that the leakage current was completely suppressed.

[0183] The nanostructure semiconductor light-emitting device according to the exemplary embodiment as described above can be implemented in various packages other than the one shown in Fig. 40 package shown.

[0184] Fig. 49 and Fig. 50 are views illustrating examples of a package using the foregoing semiconductor light-emitting device.

[0185] One in Fig. 49 may include a semiconductor light-emitting device 501, a package body 502, and a pair of lead frames 503.

[0186] The semiconductor light-emitting device 501 may be a nanostructure semiconductor light-emitting device. The semiconductor light-emitting device 501 may be mounted on the lead frame 503 and electrically connected to the lead frame by a wire W.

[0187] If necessary, the semiconductor light-emitting device 501 may be mounted on another portion, e.g., on the package body 502 instead of the lead frame 503. Furthermore, the package body 502 may have a shell shape to improve the efficiency of reflecting light. An encapsulant 505 made of a light-transmitting material may be formed in the reflective shell to encapsulate the semiconductor light-emitting device 501, the wire W, and the like.

[0188] One in Fig. The semiconductor light-emitting device package shown in Figure 50 may include a semiconductor light-emitting device 601, a mounting plate 610, and an encapsulation 603.

[0189] A wavelength conversion unit 602 may be formed on a surface and a side surface of the semiconductor light-emitting device 601. The semiconductor light-emitting device 601 may be mounted on the mounting plate 610 and electrically connected to the mounting plate 610 by a wire W.

[0190] The mounting plate 610 may include an upper electrode 613, a lower electrode 614, and a through electrode 612 connecting the upper electrode 613 and the lower electrode 614. The mounting plate 610 may be provided as a board such as a PCB, MCPCB, MPCB, FPCB, or the like, and the structure of the mounting plate 610 may have various shapes.

[0191] The wavelength conversion unit 602 may include a phosphor, a quantum dot, or the like. The encapsulant 603 may be configured to have a lens structure with a top surface having a convex dome shape. However, according to an exemplary embodiment, the encapsulant 603 may have a lens structure with a convex or concave surface for adjusting a radiation angle of the light emitted through a top surface of the encapsulant 603.

[0192] The nanostructure semiconductor light-emitting device and a package including the same according to the exemplary embodiment described above can be advantageously applied to various application products.

[0193] Fig. 51 and Fig. 52 are views illustrating a backlight unit using a semiconductor light-emitting element according to an exemplary embodiment of the present disclosure.

[0194] Referring to Fig. 51, a backlight unit 1000 includes light sources 1001 mounted on a substrate 1002 and one or more optical layers 1003 arranged over the light sources 1001. The aforementioned semiconductor light-emitting device or a package using the semiconductor light-emitting device can be used as the light sources 1001.

[0195] Unlike the backlight unit 1000 in Fig. 51, in which light sources 1001 emit light toward a top surface on which a liquid crystal display is arranged, a backlight unit 2000 is provided as another Fig. 52 is configured such that the light sources 2001 on a substrate 2002 emit light in a lateral direction, and the emitted light can be made incident on a guide plate 2003 to thereby be converted into an area light unit. Light passing through the light guide plate 2003 is emitted upward, and in order to improve light extraction efficiency, a reflective layer 2004 can be disposed on a lower surface of the light guide plate 2003.

[0196] Fig. 53 is a view illustrating an example of a lighting device using a semiconductor light-emitting device package thereof according to an exemplary embodiment of the present disclosure.

[0197] A lighting device 3000 is shown, for example, as an incandescent lamp type in Fig. 53 and includes a light-emitting module 3003, a driver unit 3008 and an external connection unit 3010.

[0198] In addition, the lighting device 3000 may further include external structures such as outer and inner casings 3006 and 3009, and a cover unit 3007. The light-emitting module 3003 may include a light source 3001 having the aforementioned semiconductor light-emitting device package structure or a structure similar thereto, and a circuit board 3002 with the light source 3001 mounted thereon. For example, the first and second electrodes of the aforementioned semiconductor light-emitting device may be electrically connected to an electrode pattern of the circuit board 3002. In the present exemplary embodiment, it is illustrated that a single light source 3001 is mounted on the circuit board 3002, but a plurality of light sources may be mounted as needed.

[0199] The outer casing 3006 may serve as a heat dissipation unit and may include a heat dissipation plate 3004, which is in direct contact with the light-emitting module 3003 to increase heat dissipation, and heat dissipation fins 3005 surrounding the side surfaces of the lighting device 3000. Furthermore, the cover unit 3007 may be installed on the light-emitting module 3003 and have a convex lens shape. The drive unit 3008 is installed in the inner casing 3009 and connected to the external connection unit 3010, which has a socket structure for receiving power from an external power source. Furthermore, the drive unit 3008 may serve to convert power into and supply a suitable power source for driving the semiconductor light-emitting device 3001 of the light-emitting module 3003.For example, the driver unit 3008 may be configured as an AC-to-DC converter, a rectification circuit component, or the like.

[0200] Fig. 54 is a view illustrating an example of a lighting device using a semiconductor light-emitting element according to an exemplary embodiment of the present disclosure.

[0201] Referring to Fig. 54, a headlight 4000 or the like may include a light source 4001, a reflecting unit 4005, and a lens cover unit 4004. The lens cover unit 4004 includes a hollow guide 4003 and a lens 4002. The light source 4001 may include the aforementioned semiconductor light-emitting device or a package including the semiconductor light-emitting device.

[0202] The headlight 4000 may further include a heat dissipation unit 4012 that dissipates heat generated by the light source 4001 to the outside. To effectively dissipate heat, the heat dissipation unit 4012 may include a heat sink 4010 and a cooling fan 4011. Furthermore, the headlight 4000 may include a housing 4009 that supports the heat dissipation unit 4012 and the reflective unit 4005, and the housing 4009 may have a central hole 4008 formed in a surface thereof, in which the heat dissipation unit 4012 is coupled.

[0203] Furthermore, the housing 4009 may have a front hole 4007 formed in another surface integrally connected to the one surface and bent at a right angle in one direction. The front hole 4007 can allow the reflecting unit 4005 to be fixedly disposed above the light source 4001. Accordingly, a front surface is opened by the reflecting unit 4005, and the reflecting unit 4005 is fixed to the housing 4009 such that the opened front surface corresponds to the front hole 4007, and the light reflected by the reflecting unit 4005 can pass through the front hole 4007 to be output to the outside.

Claims

[1] Light-emitting nanostructure device comprising: a base layer (152) formed of a nitride semiconductor material of a first conductivity type; an insulating layer (153) disposed on the base layer (152) and having a plurality of openings (H), each of which exposes a portion of the base layer (152); a plurality of nanocores (155a) respectively arranged in the plurality of openings (H) and formed of the nitride semiconductor material of the first conductivity type, each of the plurality of nanocores (155a) having a tip portion (T) with a crystal face different from that of a side face; an active layer (155b) and a nitride semiconductor layer of a second conductivity type (155c) sequentially arranged on surfaces of each of the plurality of nanocores (155a); a first current-blocking intermediate layer (154) disposed at the tip portion (T) of each of the plurality of nanocores (155a) between each of the nanocores (155a) and the active layer (155b); and a second current-blocking intermediate layer (157) disposed between the active layer (155b) and the second conductivity type nitride semiconductor layer (155c) and disposed at a region corresponding to the tip portion (T) of each of the plurality of nanocores (155a). [2] The nanostructure light-emitting device of claim 1, wherein the first current-blocking interlayer (154) comprises an undoped nitride or a nitride doped with an impurity of the second conductivity type. [3] The nanostructure light-emitting device of claim 2, wherein the first current-blocking intermediate layer (154) has a thickness of 50 nm or more. [4] The nanostructure light-emitting device according to claim 3, wherein the first current-blocking intermediate layer (154) has an impurity concentration of 1.0 10 16 / cm 3 or more. [5] The nanostructure light-emitting device according to claim 1, wherein the crystal faces on the side surfaces of the nanocores (155a) are perpendicular to an upper surface of the base layer (152). [6] The nanostructure light-emitting device according to claim 1, wherein each of the nanocores (155a), the active layer (155b) and the second conductivity type semiconductor layer (155c) comprises a nitride single crystal, and wherein the first current-blocking intermediate layer (154) comprises a nitride single crystal. [7] The nanostructure light-emitting device of claim 1, wherein the second current-blocking interlayer (157) comprises an undoped nitride or a nitride doped with an impurity of the first conductivity type. [8] The nanostructure light-emitting device according to claim 1, wherein the second current-blocking intermediate layer (157) is formed to extend from the region corresponding to the tip region (T) to a region corresponding to the side surface of each of the nanocores (155a). [9] The nanostructure light-emitting device according to claim 8, wherein in the second current-blocking intermediate layer (157), a thickness (t1) of the portion at the region corresponding to the side surface is smaller than a thickness (t2) of the portion at the region corresponding to the tip portion (T). [10] The nanostructure light-emitting device according to claim 8, wherein the portion at the region corresponding to the side surface extends to a surface of the insulating layer (153). [11] Light-emitting nanostructure device comprising: a base layer (82; 152) formed of a nitride semiconductor material of a first conductivity type; an insulating layer (83; 153) disposed on the base layer (82; 152) and having a plurality of openings (H), each of which exposes a portion of the base layer (82; 152); a plurality of nanocores (85a; 155a) respectively arranged in the plurality of openings (H) and formed of the nitride semiconductor material of the first conductivity type, each of the plurality of nanocores (85a; 155a) including a tip portion (T) having a crystal face different from that of a side face perpendicular to a top surface of the base layer (82; 152); an active layer (85b; 155b) and a nitride semiconductor layer of a second conductivity type (85c; 155c) arranged sequentially on surfaces of each of the plurality of nanocores (85a; 155a); and a current-blocking intermediate layer (87; 157) disposed between the active layer (85b; 155b) and the second conductivity type nitride semiconductor layer (85c; 155c), the current-blocking intermediate layer (87; 157) having a first portion (87a; 157a) disposed at a region corresponding to the tip portion (T) of each of the plurality of nanocores (85a; 155a) and a second portion (87b; 157b) disposed at a region corresponding to the side surface of each of the plurality of nanocores (85a; 155a), wherein the first portion (87a; 157a) has a first thickness (t1) sufficient to block a current required to drive the light-emitting nanostructure device, and wherein the second portion (87b; 157b) has a second thickness (t2) sufficient to conduct the current, the second thickness (t2) being less than the first thickness (t1). [12] The nanostructure light-emitting device according to claim 11, wherein the current-blocking intermediate layer (87; 157) comprises an undoped nitride or a nitride doped with an impurity of the first conductivity type, and wherein in the current-blocking intermediate layer (87; 157), the thickness (t1) of the first portion (87a; 157a) at the region corresponding to the tip portion (T) is 50 nm or more, and the thickness (t2) of the second portion (87b; 157b) at the region corresponding to the side surface is 20 nm or less. [13] The nanostructure light-emitting device according to claim 12, wherein the second portion (87b; 157b) at the region corresponding to the side surface has the same impurity concentration as that of the first portion (87a; 157a) at the region corresponding to the tip portion (T). [14] The light-emitting nanostructure of claim 11, wherein the current-blocking intermediate layer (87; 157) extends to a surface of the insulating layer (83; 153). [15] The nanostructure light-emitting device according to claim 14, wherein in the current-blocking intermediate layer (87; 157), the thickness of the first portion (87a; 157a) at the region corresponding to the tip portion (T) is 50 nm or more, and the thickness of the second portion (87b; 157b) at the region corresponding to the side surface is 5 nm to 20 nm. [16] The nanostructure light-emitting device according to claim 1, wherein the second current-blocking intermediate layer (157) extends to a surface of the insulating layer (153), and in the second current-blocking intermediate layer (157), a thickness (t2) of the portion (157b) at a region corresponding to the side surface of each of the plurality of nanocores (155a) is smaller than a thickness (t1) of a portion (157a) at the region corresponding to the tip portion (T). [17] The nanostructure light-emitting device of claim 16, wherein the first current-blocking interlayer (154) comprises an undoped nitride or a nitride doped with an impurity of the second conductivity type, and wherein the second current-blocking interlayer (157) comprises an undoped nitride or a nitride doped with an impurity of the first conductivity type.

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