Semiconductor device

Abstract

Semiconductor device with: a first switching element (20) having a first electrode (22) and a second electrode (24), and forming an upper branch of upper and lower branches, wherein the first electrode (22) and the second electrode (24) of the first switching element (20) each form both sides of the first switching element (20) in a first direction (Z), a second switching element (30) which is aligned with the first switching element (20) in a second direction (X), has a first electrode (32) and a second electrode (34), and forms the lower branch of the upper and lower branches, wherein the first electrode (32) and the second electrode (34) of the second switching element (30) each form both sides of the second switching element (30) in the first direction (Z), a first metal element (50) which is electrically connected to the first electrode (22) of the first switching element (20) in the first direction (Z), a second metal element (54) which is electrically connected to the first electrode (32) of the second switching element (30) in the first direction (Z), a first connection (40) which has a potential on a high-potential side of the upper and lower branches, a second terminal (42) which has a potential on a low-potential side of the upper and lower branches, a third connection (44) which has a midpoint potential of the upper and lower branches, and a resin part (66) which in one piece covers the first switching element (20), the second switching element (30), at least a part of the first metal element (50), at least a part of the second metal element (54), a part of the first terminal (40), a part of the second terminal (42) and a part of the third terminal (44), wherein, if a part having a potential equal to a potential of the first terminal (40) is assumed to be a first potential part (P), a part having a potential equal to a potential of the second terminal (42) is assumed to be a second potential part (N), and a part having a potential equal to a potential of the third terminal (44) is assumed to be a third potential part (O), a comparative tracking index of a first material present between the first potential part (P) and the second potential part (N) in the resin part (66) is higher than at least one of the comparative tracking indices of a second material and a third material, wherein the second material is present between the first potential part (P) and the third potential part (O) in the resin part (66), and the third material is present between the second potential part (N) and the third potential part (O) in the resin part (66), wherein, if a minimum value of creepage distances between the first potential part (P) and the second potential part (N) in the resin part (66) is set to L1, a minimum creepage distance allowed for the first material between the first potential part (P) and the second potential part (N) is set to L1min, a minimum value of creepage distances between the first potential part (P) and the third potential part (O) in the resin part (66) is set to L2, the minimum creepage distance allowed for the second material between the first potential part (P) and the third potential part (O) is set to L2min, the minimum value of creepage distance between the second potential part (N) and the third potential part (O) along the surface of the resin part (66) is set to L3, and the minimum creepage distance allowed for the third material between the second potential part (N) and the third potential part (O),is set to L3min, and at least one of the following two equations is satisfied, . (L 2 − L 2 min) / L 2 min < (L 1 − L 1 min) / L 1 min (L 3 − L 3 min) / L 3 min < (L 1 − L 1 min) / L 1 min, and the first direction (Z) is perpendicular to the second direction (X).

Description

BACKGROUND OF THE INVENTION 1. Field of the invention

[0001] The present invention relates to a semiconductor device. 2. Description of the state of the art

[0002] A semiconductor device is known comprising first to fourth thick plate sections and first and second thin plate sections, in which the first and second thin plate sections are attached to one another and electrically connected (see JP 2012-235081A), which corresponds to US 2014 / 0035112A1. In JP 2012-235081A, the first thick plate section is electrically connected to an electrode on a lower surface side of a first semiconductor element. Furthermore, the second thick plate section is electrically connected to an electrode on a lower surface side of a second semiconductor element, which is arranged parallel to the first semiconductor element. Furthermore, the third thick plate section is connected to an electrode on an upper surface side of the first semiconductor element. Furthermore, the fourth thick plate section is connected to an electrode on an upper surface side of the second semiconductor element.Furthermore, the first thin plate section is arranged on top of the second thick plate section. Then, the second thin plate section is arranged on top of the third thick plate section.

[0003] In this type of semiconductor device, the semiconductor elements and the like are sealed with resin. Terminals exposed within the resin include a first terminal, which has a potential on the high-potential side of the upper and lower branches; a second terminal, which has a potential on the low-potential side of the upper and lower branches; and a third terminal, which has a midpoint potential of the upper and lower branches. In such a configuration, it is advantageous to prevent the occurrence of a short circuit between a location with a potential on the high-potential side (for example, the first terminal) and a location with a potential on the low-potential side (for example, the second terminal).

[0004] US 2013 / 0003305A1 discloses a half-bridge circuit with a common heat sink, wherein switching transistors are arranged in an insulating body.

[0005] DE 10 2009 000 588 A1 discloses a power semiconductor module with a housing having a coating with high resistance to surface creepage, wherein several electrical conductors are provided on the housing. The coating is provided on a creepage path that is provided between the electrical conductors. SUMMARY OF THE INVENTION

[0006] It is an object of the present invention to provide a semiconductor device that can reduce the probability of a short circuit between a location having a potential of a high-potential side and a location having a potential of a low-potential side.

[0007] This problem is solved by a semiconductor device as specified in claim 1.

[0008] Advantageous embodiments are specified in the dependent patent claims.

[0009] According to the present invention, a semiconductor device can be obtained which can reduce the probability of a short circuit between a location having a potential on a high-potential side and a location having a potential on a low-potential side. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Features, advantages, and technical and industrial significance of exemplary embodiments of the invention are described below with reference to the accompanying drawings, in which the same reference numerals denote the same elements, and wherein: Fig. 1 shows a top view illustrating a semiconductor device according to an embodiment (first embodiment), Fig. Figure 2 shows a representation that is achieved by omitting a resin part in the semiconductor device according to Fig. 1 will be received, Fig. 3 a cross-sectional view along a line III-III of Fig. 1 shows, Fig. 4 a cross-sectional view along a line IV-IV of Fig. 1 shows, Fig. 5 shows a diagram that schematically illustrates a principle of magnetic flux cancellation between a high-potential power connection and a low-potential power connection, Fig. 6A, Fig. 6B and Fig. 6C each show a representation that shows a relationship between the respective creepage distances in the semiconductor device of Fig. 1 illustrates, Fig. 7A and Fig. 7B each show a representation showing a semiconductor device according to an embodiment variant of the first embodiment, Fig. 8A and Fig. 8B each show a representation that shows a semiconductor device according to a further embodiment variant of the first embodiment, Fig. 9 a top view illustrating a semiconductor device according to a further embodiment variant of the first embodiment, Fig. 10 a top view illustrating a semiconductor device according to a further embodiment variant of the first embodiment, Fig. Figure 11 shows a top view illustrating a semiconductor device according to a further embodiment variant of the first embodiment, Fig. 12A, Fig. 12B and Fig. Figures 12C each show a representation illustrating a semiconductor device according to a further embodiment variant of the first embodiment, Fig. 13A and Fig. Figure 13B shows a top view illustrating a semiconductor device according to a further embodiment variant of the first embodiment, Fig. 14A and Fig. Figure 14B shows a representation illustrating a semiconductor device according to a second embodiment, Fig. 15 shows a representation illustrating a semiconductor device according to a further example variant of the second embodiment, Fig. 16 shows a representation illustrating a semiconductor device according to a third embodiment, and Fig. Figure 17 shows a top view illustrating a semiconductor device according to a further embodiment variant of the third embodiment. DETAILED DESCRIPTION OF EXAMPLES OF EXECUTION

[0011] Each embodiment is described in detail below with reference to the accompanying drawings.

[0012] Fig. Figure 1 shows a top view illustrating a semiconductor device 10 according to an embodiment (first embodiment). Fig. Figure 2 shows a representation that is achieved by omitting a resin part in the semiconductor device of Fig. 1 will be received. Fig. Figure 3 shows a cross-sectional view along a line III-III of Fig. 1. Fig. Figure 4 shows a cross-sectional view along a line IV-IV of Fig. 1.

[0013] The semiconductor device 10 is typically used in a power conversion device such as an inverter and converter for driving a traction motor in a hybrid vehicle and an electric vehicle. However, the semiconductor device 10 can be used in other applications in a vehicle (for example, for an electric power steering device), or it can be used in applications other than a vehicle (for example, a power supply unit or the like for other electrical devices).

[0014] For the sake of simplicity, in the following description, the thickness direction of a bipolar transistor with insulated gate element (IGBT element) is taken as the Z direction. Furthermore, a direction perpendicular to the Z direction, in which two IGBT elements forming upper and lower branches are arranged, is taken as the X direction. A direction perpendicular to both the X and Z directions is taken as the Y direction. In the following description, although for the sake of simplicity the Z direction corresponds to a vertical direction, and a side on which a first terminal 60 is located with respect to a first heat sink 50 is taken as the "top side," the mounting direction of the semiconductor device 10 is optional.

[0015] The semiconductor device 10 comprises IGBT elements 20 and 30, freewheeling diodes (FWD) 28 and 38, a high-potential power terminal 40, a low-potential power terminal 42, an output terminal 44, and a control terminal 46, which includes a gate terminal 46g. Furthermore, the semiconductor device 10, as shown in Fig. 1 to Fig. Figure 4 shows four heat sinks 50, 52, 54 and 56, a connecting part 58, two terminals 60 and 62, a solder joint 64 and a resin part 66.

[0016] The IGBT element 20 and the FWD 28 form an upper branch of the upper and lower branches, and the IGBT element 30 and the FWD 38 form a lower branch of the upper and lower branches.

[0017] The IGBT element 20, as shown in Fig. 2 and Fig. Figure 3 shows a collector electrode 22 on a lower surface side and an emitter electrode 24 and a gate electrode 26 on an upper surface side.

[0018] A first heat sink 50 is arranged on the lower surface of the IGBT element 20. The collector electrode 22 of the IGBT element 20 is electrically and mechanically connected to a surface 50a on an upper side of the first heat sink 50 via the solder joint 64. According to a Fig. In the embodiment shown in Figure 2, a cathode electrode of the FWD element 28 is also connected to the surface 50a on the upper side of the first heat sink 50.

[0019] As it is in Fig. As shown in Figure 2, the first heat sink 50 is essentially a rectangular metal plate and has the high-potential power terminal 40 extending from one side of the rectangle in the Y-direction. The first heat sink 50 can be formed from a single heteromorphic conductor frame together with the high-potential power terminal 40 and the like. Alternatively, the high-potential power terminal 40 can be formed in a body separate from the first heat sink 50 and attached to the first heat sink 50. The high-potential power terminal 40 is electrically connected to the IGBT element 20 and the FWD element 28 via the first heat sink 50. Part of the high-potential power terminal 40 is, as shown in Figure 2, Fig. 2 is shown, set off to the outside from a lateral surface of the resin part 66 (a lateral surface which has the Y direction as a perpendicular line).

[0020] A surface 50b on a lower side of the first heat sink 50 is, as shown in Fig. 3 and Fig. As shown in Figure 4, a surface 66a on a lower side of the resin part 66 is exposed. Thus, heat generated by the IGBT element 20 and the FWD element 28 can be radiated outwards from the surface 50b of the first heat sink 50. According to a Fig. In the embodiment shown in Figure 3, although the surface 50b on the lower side of the first heat sink 50 is flush with the surface 66a on the lower side of the resin part 66, the surface 50b may have an offset in the Z direction with respect to the surface 66a.

[0021] On an upper surface of the IGBT element 20, the first terminal 60 is arranged such that it does not overlap the gate electrode 26 in the Z-direction, but rather faces the emitter electrode 24. The first terminal 60 is a flat metal plate (metal block), but may have a curved portion. A surface on a lower side of the first terminal 60 is electrically and mechanically connected to the emitter electrode 24 of the IGBT element via the solder joint 64. An anode electrode of the FWD element 28 is also connected to the surface on the lower side of the first terminal 60. The first terminal 60 has a relay function for electrically connecting the IGBT element 20 and the FWD element 28 to a second heat sink 52, as well as a function to ensure sufficient height for wire bonding to the gate electrode 26.

[0022] The gate electrode 26 is connected to the gate terminal 46 of the control terminal 46 corresponding to the upper branch via a bond wire 48. The control terminal 46 corresponding to the upper branch can be formed by the single heteromorphic conductor frame together with the first heat sink 50, the high-potential power terminal 40, and the like. In addition to the gate terminal 46, the control terminal 46 corresponding to the upper branch can have a terminal connected to a temperature-sensing diode, a sensing emitter, and the like. The control terminal 46 corresponding to the upper branch is, as shown in Fig. 1 and Fig. 2 is shown, offset to the outside from a lateral surface (a lateral surface which has the Y direction as a perpendicular line) on a side opposite a recessed side of the high potential power connection 40 in the resin part 66.

[0023] The second heat sink 52 is located on a surface on the upper side of the first terminal 60. A surface 52a on the lower side of the second heat sink 52 is electrically and mechanically connected to the surface on the upper side of the first terminal 60 via the solder joint 64. Thus, the second heat sink 52 is electrically connected to the emitter electrode 24 of the IGBT element 20 and the anode electrode of the FWD element 28 via the first terminal 60.

[0024] The second heat sink 52 is an essentially rectangular metal plate and is arranged such that an almost complete portion overlaps with the first heat sink 50 in a top view (a downward view in the Z direction). As shown in Fig. As shown in Figure 2, the second heat sink 52 has an essentially identical rectangular shape to the outer shape of the first heat sink 50. A surface 52b on the upper side of the second heat sink 52 is exposed to a surface 66b on the upper side of the resin part 66. Thus, heat generated by the IGBT element 20 and the FWD element 28 can be radiated outwards from the surface 52b of the second heat sink 52 via the first terminal 60. According to the figure shown in Fig. 3 and Fig. In the embodiment shown in Figure 4, although the surface 52b on the upper side of the second heat sink 52 is flush with the surface 66b on the upper side of the resin part 66, the surface 52b may have an offset in the Z direction with respect to the surface 66b.

[0025] In the second heat sink 52, a first connecting element 58a, which is a component of the connecting element 58, is integrally arranged. However, the first connecting element 58a can be formed in a separate body from the heat sink 52 and attached to the second heat sink 52. The first connecting element 58a extends towards the IGBT element 30 in the X direction.

[0026] The IGBT element 30, as shown in Fig. 2 and Fig. Figure 3 shows a collector electrode 32 on a lower surface and an emitter electrode 34 and a gate electrode 36 on an upper surface. The IGBT element 30 is aligned with the IGBT element 20 in the X direction. According to the Fig. In the embodiment shown in Figure 3, although the IGBT element 30 is arranged in such a relationship that the IGBT element 30 is not offset in the Y direction with respect to the IGBT element 20, the latter may have an offset in the Y direction.

[0027] A third heat sink 54 is arranged on a lower surface of the IGBT element 30. The collector electrode 32 of the IGBT element 30 is electrically and mechanically connected to a surface 54a on an upper side of the third heat sink 54 via the solder joint 64. According to the Fig. In the embodiment shown in Figure 2, a cathode electrode of the FWD element 38 is also connected to the surface 54a on the upper side of the third heat sink 54.

[0028] The third heat sink 54 is, as it is in Fig. Figure 2 shows a substantially rectangular metal plate and is provided with the output terminal 54, which extends from one side of the rectangle in the Y direction. The third heat sink 54 can be formed from a single heteromorphic conductor frame together with the output terminal 44 and the like. Alternatively, the output terminal 44 can be formed in a body separate from the third heat sink 54 and attached to the first heat sink 54. Thus, the output terminal 44 is electrically connected to the IGBT element 30 and the FWD element 38 via the third heat sink 54. Part of the output terminal 44 is, as shown in Figure 2, Fig. As shown in Figure 2, the output terminal 44 is set off to the outside from a side surface of the resin part 66 (a side surface which has the Y direction as the vertical line). The side surface of the resin part 66 from which the output terminal 44 is set off is the same as the side surface of the resin part 66 from which the high-potential power terminal 40 is set off.

[0029] A surface 54b is located on a lower side of the third heat sink 54, as shown in Fig. 3 and Fig. As shown in Figure 4, the surface 66a on the lower side of the resin part 66 is free. Thus, the heat generated by the IGBT element 30 and the PWD element 38 can be radiated outwards from the surface 54b of the third heat sink 54. According to the figures shown in Fig. 3 and Fig. In the embodiments shown in Figure 4, although the surface 54b on the lower side of the third heat sink 54 is flush with the surface 66a on the lower side of the resin part 66, the surface 54b may have an offset in the Z direction with respect to the surface 66a.

[0030] In the third heat sink 54, a second connecting part 58b, which is an element of the connecting part 58, is arranged integrally. However, the second connecting part 58b can be formed in a body separate from the third heat sink 54 and attached to the third heat sink 54. According to the Fig. In the embodiment shown in Figure 3, the second connecting part 58b extends in an upper direction towards the surface 56a on a lower side of a fourth heat sink 56, and extends towards the side of the IGBT element 20 in the X direction. The second connecting part 58b is, as shown in Fig. As shown in Figure 3, the first connecting part 58a is electrically and mechanically connected via the solder joint 64. The second connecting part 58b and the first connecting part 58a are formed in the X-direction between the second heat sink 52 and the third heat sink 54 and are electrically and mechanically connected to each other in the X-direction between the second heat sink 52 and the third heat sink 54.

[0031] On an upper surface of the IGBT element 30, a second terminal 62 is arranged such that it does not overlap the gate electrode 36 in the Z-direction, but rather faces the emitter electrode 34. The second terminal 62 is a flat metal plate (metal block), but may have a curved portion. A surface on a lower side of the second terminal 62 is electrically and mechanically connected to the emitter electrode 34 of the IGBT element 30 via the solder joint 64. An anode electrode of the FWD element 38 is also connected to the surface on the lower side of the second terminal 62. The second terminal 62 has a relay function for electrically connecting the IGBT element 30 and the FWD element 38 to the fourth heat sink 56 and a function for providing sufficient height for wire bonding to the gate electrode 36.

[0032] The gate electrode 36 is connected to the gate terminal 46g of the control terminal 46 corresponding to the lower branch via the bond wire 48. The control terminal 46 corresponding to the lower branch can be formed by a single heteromorphic conductor frame together with the third heat sink 54, the output terminal 44, and the like. In addition to the gate terminal 46g, the control terminal 46 corresponding to the lower branch can have a terminal connected to the temperature sensing diode, the sensing emitter, and the like. The control terminal 46 corresponding to the lower branch is, as shown in Fig. 1 and Fig. 2 is shown, offset to the outside from a side surface (a side surface which has the Y direction as a perpendicular line) on a side opposite to a recessed side of the high potential power connection 40 in the resin part 66.

[0033] The fourth heat sink 56 is located on a surface on the upper side of the second terminal 62. The surface 56a on the lower side of the fourth heat sink 56 is electrically and mechanically connected to the surface on the upper side of the second terminal 62 via the solder joint 64. Thus, the fourth heat sink 56 is electrically connected to the emitter electrode 34 of the IGBT element 30 and the anode electrode of the FWD element 38 via the second terminal 62.

[0034] The fourth heat sink 56 is an essentially rectangular metal plate and is arranged such that an almost complete portion overlaps with the third heat sink 54 in a top view (a downward view in the Z direction). As shown in Fig. As shown in Figure 2, the fourth heat sink 56 has a rectangular shape, essentially the same as the outer shape of the third heat sink 54. A surface 56b on an upper side of the fourth heat sink 56 is exposed to the surface 66b on the upper side of the resin part 56. Thus, heat generated by the IGBT element 30 and the FWD element 38 can be radiated outwards from the surface 56b of the fourth heat sink 56 via the second terminal 62. According to the figure shown in Fig. 3 and Fig. In the embodiment shown in Figure 4, although the surface 56b on the upper side of the fourth heat sink 56 is flush with the surface 66b on the upper side of the resin part 66, the surface 56b may have an offset in the Z direction.

[0035] The fourth heat sink 56 has a body part 56c, which defines the surfaces 56a and 56b, and an extension part 56d, which extends from a side surface of body part 56c to the side of the IGBT element 20 in the X-direction. The extension part 56d is formed integrally with body part 56c. However, the extension part 56d can be formed in a separate body from body part 56c and attached to body part 56c. The extension part 56d is formed in the X-direction between body part 56c of the fourth heat sink 56 and the second heat sink 52 (the body part excluding the first extension part 58a), in the same manner as the connecting part 58. However, the extension part 56d has an offset relative to connecting part 58 in the Y-direction to avoid interfering with connecting part 58.

[0036] The low-potential power connection 42 is electrically connected to the fourth heat sink 56. In particular, as shown in Fig. As shown in Figure 4, the low-potential power terminal is electrically and mechanically connected to the extension part 56d of the fourth heat sink 56 via the solder joint 64. The low-potential power terminal 42 can be formed from a single heteromorphic conductor frame together with the third heat sink 54, the output terminal 54, the control terminal 46 corresponding to the lower branch, and the like. As shown in Fig. As shown in Figure 2, a portion of the low-potential power connection 42 is offset outwards from the side surface of the resin part 66 (a side surface having a perpendicular line in the Y direction). The side surface of the resin part 66 from which the low-potential power connection 42 is offset is the same as the side surface of the resin part 66 from which the high-potential power connection 40 and the output connection 44 are offset.

[0037] The low-potential power connection 42 is located in a region 70 (the body part excluding the first connecting part 58a) between the body part 46c of the fourth heat sink 56 and the second heat sink 52 in the X-direction, that is, in the region 70 where the extension part 56d is located. Thus, as shown in Fig. As shown in Figure 2, the high-potential power terminal 40, the low-potential power terminal 42, and the output terminal 44 are arranged in a positional relationship such that the low-potential power terminal 42 is located between the output terminal 44 and the high-potential power terminal 40 in the Y-direction. According to the illustrated embodiment, the entire low-potential power terminal 42 is located in a region between the body part 56c of the fourth heat sink 56 and the second heat sink 52 (the body part excluding the first connecting part 48a).

[0038] The resin part 66 integrally seals the IGBT elements 20 and 30, the FWD elements 28 and 38, a portion of the high-potential power connection 40, a portion of the low-potential power connection 42, a portion of the output connection 44, a portion of the control connection 46, a portion (excluding surfaces 50b, 52b, 54b, and 56b) in the respective heat sinks 50, 52, 54, and 56, the connecting part 58, and the respective connections 60 and 62. According to the illustrated embodiment, the resin part 66 is formed into an outer cuboid shape. As described above, the high-potential power connection 40, the low-potential power connection 42, and the output connection 44 are, as shown in Fig. As shown in Figure 2, the high-potential power terminal 40, the low-potential power terminal 42, and the output terminal 44 are offset from the side surface of the resin part 66 in the Y-direction. Although the offset positions of the high-potential power terminal 40, the low-potential power terminal 42, and the output terminal 44 on the side surface of the resin part 66 can be optional positions in the Z-direction, they can, for example, be located near a center point on the side surface of the resin part 66 in the Z-direction (see Figure 2). Fig. 6C).

[0039] The semiconductor device 10 configured in this way is a so-called 2-in-1 package, which integrally incorporates two IGBT elements 20 and 30 forming the upper and lower branches (including the single resin part 66). Furthermore, since heat sinks 50, 52, 54, and 56 are arranged on both sides in the Z-direction of each of the IGBT elements 20 and 30, heat can be radiated from the IGBT elements 20 and 30 from both sides in the Z-direction; that is, this is a configuration with excellent heat dissipation characteristics.

[0040] Since the high-potential power terminal 40 and the low-potential power terminal 42 remain adjacent in the X-direction (without the output terminal 44 in between), the distance between the high-potential power terminal 40 and the low-potential power terminal 42 in the X-direction can be reduced compared to a configuration where the output terminal 44 is located between the high-potential power terminal 40 and the low-potential power terminal 42 in the X-direction. Therefore, the surge voltage generated during the switching of the IGBT elements 20 and 30 can be reduced. In particular, as shown in Fig. As shown in Figure 5, since the directions of currents flowing in the high-potential power terminal 40 and the low-potential power terminal 42 are opposite to each other, the effect of canceling a magnetic flux is increased when the high-potential power terminal 40 and the low-potential power terminal 42 are arranged close to each other. Thus, the impulse voltage can be reduced because parasitic inductance can be reduced.

[0041] Since the first heat sink 50, the third heat sink 54, the high-potential power connector 40, the low-potential power connector 42, the output connector 44, and the control connector 46 can be formed from a single heteromorphic conductor frame corresponding to the upper and lower branches, the configuration exhibits excellent manufacturability. However, a manufacturing process is not limited to specific methods.

[0042] Furthermore, by using region 70 in the X-direction, the emitter electrode 24 of the IGBT element 20 and the anode electrode of the FWD element 28 are each connected to the collector electrode 37 of the IGBT element 30 and the cathode electrode of the FWD element 38, respectively, via the connecting part 58. Additionally, the low-potential power connection 42 can be arranged using a space (region 70) that utilizes the connecting part 58. This results in a configuration that enables miniaturization in the X-direction.

[0043] Fig. 6A, Fig. 6B and Fig. Figures 6C each show a representation illustrating a relationship between the respective creepage distances in the semiconductor device 10. Fig. Figure 6A shows a top view when the semiconductor device 10 is viewed from a top side. Fig. Figure 6B shows a top view when the semiconductor device 10 is viewed from a bottom side, and Fig. Figure 6C shows a perspective view when the semiconductor device 10 is viewed from a top side.

[0044] According to the present embodiment, each of the creepage distances is set such that the following relationships are satisfied.Under a conductor location that is not sealed with the resin part 66 in the semiconductor device 10 (that is, a conductor location that is free from the resin part 66), if a part that assumes the same potential as the high-potential power terminal 40 is set to a first potential part P, a part that assumes the same potential as the low-potential power terminal 42 is set to a second potential part N, and a part that assumes the same potential as the output terminal 44 is set to a third potential part O, a first creepage distance L1, L6, L7 between the first potential part P and the second potential part N is longer than a second creepage distance L3, L9 between the first potential part P and the third potential part O, and longer than a third creepage distance L2, L4, L5, L8 between the second potential part N and the third potential part O.This means that a minimum value under L1, L6, and L7 is greater than a minimum value under L3, L9, L2, L4, L5, and L8. However, each of the creepage distances is set to be equal to or greater than a lower limit (for example, a minimum creepage distance based on the JIS standard). Fig. 6A and Fig. 6B, although L1, L3, L4 and the like are shown in a flat layout, these distances are actually as shown in Fig. 6C is shown, along two surfaces of the resin part 66 (a front surface and a side surface on the top side).

[0045] Therefore, according to the present embodiment, since the creepage distance between the first potential part P and the third potential part O or between the second potential part N and the third potential part O is shorter than the creepage distance between the first potential part P and the second potential part N, even if the insulating behavior is worsened due to deterioration of the resin part 66, the probability of a short circuit (short circuit of the upper and lower branches) between the first potential part P and the second potential part N can be reduced.This means that even if the insulating performance deteriorates due to a deterioration of the resin section 66, before a short circuit occurs between the first potential section P and the second potential section N, a short circuit will occur between the first potential section P and the third potential section O (for example, between the collector and the emitter of the IGBT element 20) or between the second potential section N and the third potential section O (for example, between the collector and the emitter of the IGBT element 30). If the short circuit occurs between the first potential section P and the third potential section O or between the second potential section N and the third potential section O (that is, if the short circuit occurs between the collector and the emitter), a protective function is activated, and the short circuit between the upper and lower branches can thereby be prevented.For example, if a short circuit occurs between the first potential part P and the third potential part O, IGBT element 30 is kept in an off state, thus preventing a short circuit between the upper and lower branches. Furthermore, if a short circuit occurs between the second potential part N and the third potential part O, IGBT element 20 is kept in the off state, thus preventing a short circuit between the upper and lower branches.

[0046] Fig. 7A and Fig. Figures 7B each show a representation that depicts a semiconductor device 10A according to an embodiment variant of the first embodiment. Fig. Figure 7A shows a top view of the semiconductor device 10A and Fig. Figure 7B shows a cross-sectional view of the semiconductor device 10A.

[0047] The semiconductor device 10A differs from the semiconductor device 10 according to the embodiment described above in one respect: an assembly of the second heat sink 52 and an assembly of the fourth heat sink 56 are enclosed in the resin part 66. In this case, since the creepage distances corresponding to the second heat sink 52 and the fourth heat sink 56 (L1, L2 and the like) are Fig. 6A and Fig. 6C) are not generated, these are not taken into account.

[0048] According to the in Fig. 7A and Fig. In the illustrated embodiment 7B, the second heat sink 52 and the fourth heat sink 56 essentially function as a busbar (essentially single-sided radiation due to the first heat sink 50 and the third heat sink 54). The respective connections 60 and 62 can be omitted.

[0049] Fig. 8A and Fig. Figures 8B each show a representation illustrating a semiconductor device 10B according to a further embodiment variant of the first embodiment. Fig. Figure 8A shows a top view of the semiconductor device 10B and Fig. Figure 8B shows a cross-sectional view of the semiconductor device 10B.

[0050] The semiconductor device 10B differs from the semiconductor device 10 according to the first embodiment described above in that an entire assembly of the respective heat sinks 50, 52, 54 and 56 is enclosed in the resin part 66. In this case, since the creepage distances correspond to the respective heat sinks 50, 52, 54 and 56 (L1, L2 and the like according to Fig. 6A and Fig. 6C) are not generated, and these are not taken into account. This means that the creepage distances corresponding to the high-potential power connection 40, the low-potential power connection 42, and the output connection 44 (for example, L5, L6 in Fig. 6A, Fig. 6B and Fig. 6C) can be taken into account. This means that in this case a condition of L6 > L5 can be set.

[0051] According to the in Fig. 8A and Fig. In the embodiment shown in Figure 8B, the second heat sink 52, the fourth heat sink 56, and the like essentially function as the busbar. The respective connections 60 and 62 can be omitted.

[0052] Fig. Figure 9 shows a top view showing a semiconductor device 10C according to a further embodiment variant of the first embodiment.

[0053] The semiconductor device 10C differs from the semiconductor device 10 according to the first embodiment described above in that new connections 47 and 49 are exposed from the resin part 66. According to the Fig. In the illustrated embodiment shown in Figure 9, terminal 47 can be formed in the third heat sink 54 and forms the third potential part O. Terminal 49 can be formed in the first heat sink 50 and forms the first potential part P. Terminals 47 and 49 can be used to detect a voltage. In this case, creepage distances corresponding to terminals 47 and 49 can be additionally considered. For example, a creepage distance L10 between terminal 47 and the control terminal 46 (which forms the second potential part N), a creepage distance L11 between terminal 47 and surface 56b of the fourth heat sink 56, a creepage distance L12 between terminal 49 and the control terminal 46 (which forms the third potential part O), a creepage distance L13 between terminal 49 and surface 52b of the second heat sink 52, and the like, can be additionally considered.

[0054] Thus, the number and types of connections exposed by the resin part 66, a side to be exposed, and the like are optional.

[0055] Fig. Figure 10 shows a top view illustrating a semiconductor device 10D according to a further embodiment variant of the first embodiment.

[0056] The semiconductor device 10D differs from the semiconductor device 10 according to the first embodiment described above in that the resin 66 is replaced by a resin part 66D. The resin part 66D has a recess 67 on one side surface. The recess 67 is formed between the low-potential power terminal 42 and the high-potential power terminal 40. This allows the creepage distance between the low-potential power terminal 42 and the high-potential power terminal 40 to be efficiently increased, and it is likely that the relationship between the respective creepage distances described above will be satisfied. The recess 67 can only be formed within a positional range that defines the creepage distance in the Z-direction.Furthermore, a projection can be formed between the low-potential power connection 42 and the high-potential power connection 40 instead of a recess 67. Similarly, the recess or projection can be formed on the surface 66b on an upper side of the resin part 66D (or the resin part 66) or on the surface 86a on a lower side thereof, thereby increasing the creepage distance between the first potential part P and the second potential part N.

[0057] Fig. Figure 11 shows a top view illustrating a semiconductor device 10E according to another embodiment of the first embodiment.

[0058] The semiconductor device 10E differs from the semiconductor device 10 according to the first embodiment described above in that the arrangement of the high-potential power terminal 40, the low-potential power terminal 42, and the output terminal 44 differs in the X-direction. That is, according to the Fig. In the illustrated embodiment of Figure 11, the output terminal 44 is arranged between the high-potential power terminal 40 and the low-potential power terminal 42 in the X-direction. Therefore, the arrangement of the high-potential power terminal 40, the low-potential power terminal 42, and the output terminal 44 is optional. The Fig. The illustrated embodiment 11, as described above, is a configuration that is less favorable than the semiconductor device 10 according to the first embodiment described above with respect to parasitic inductance, but is advantageous with respect to ensuring a necessary creepage distance between the high-potential power terminal 40 and the low-potential power terminal 42. In other words, the semiconductor device 10 according to the first embodiment described above allows a correct creepage distance to be maintained between the high-potential power terminal 40 and the low-potential power terminal 42 while reducing parasitic inductance.

[0059] Fig. 12A, Fig. 12B and Fig. Figures 12C each show a representation that shows a semiconductor device 10F according to a further embodiment variant of the first embodiment. Fig. Figure 12A shows a top view of the semiconductor device 10F, Fig. Figure 12B shows a cross-sectional view of the semiconductor device 10F and Fig. Figure 12C shows a cross-sectional view that schematically illustrates a state of a circuit board on which the semiconductor device 10F is mounted.

[0060] The semiconductor device 10F differs from the semiconductor device 10 according to the first embodiment described above in that the semiconductor device 10F is a surface-mount design, as described in Fig. Figure 12C shows that the semiconductor device 10F is mounted on a surface of a circuit board 90. The circuit board 90 contains conductor sections (or conductor patterns) 92, 94, and 96. The surface 50b on the underside of the first heat sink 50 is electrically and mechanically connected to the conductor section 92 via the solder joint (or conductor prong or the like) 80. Furthermore, the control terminal 46 corresponding to the IGBT element 20 is electrically and mechanically connected to the conductor section 96 via a solder joint (or conductor prong or the like) 80. Likewise, the surface 54b of the underside of the third heat sink 54 is electrically and mechanically connected to the conductor section 94 via the solder joint (or conductor prong or the like) 80. Furthermore, the control connection 46 is electrically and mechanically connected to the conductor part 96 via the solder joint (or conductor wart or the like) 80, corresponding to the IGBT element 30.

[0061] Also according to the in Fig. 12A, Fig. 12B and Fig. In the embodiment shown in Figure 12C, the respective creepage distances in the semiconductor device 10F are configured such that they exhibit the relationships described above. In particular, in the case of the semiconductor device 10F, the functions of the high-potential power terminal 40 and the output terminal 44 (external connection function) are implemented by the surface 50b on the lower side of the first heat sink 50 and the surface 54b on the lower side of the third heat sink 54, rendering the high-potential power terminal 40 and the output terminal 44 unnecessary. Therefore, since the creepage distances corresponding to the high-potential power terminal 40 and the output terminal 44 are not generated, they are not taken into account.

[0062] Fig. 13A and Fig. Figures 13B each show a representation illustrating a semiconductor device 10G according to a further embodiment variant of the first embodiment. Fig. Figure 13A shows a top view when the semiconductor device 10G is viewed from a top side and Fig. Figure 13B shows a top view when the semiconductor device 10G is viewed from a bottom side. Fig. 13A and Fig. Figure 13B illustrates the resin part 66 in a perspective view such that the interior of the resin part can be viewed.

[0063] The semiconductor device 10G differs from the semiconductor device 10 according to the first embodiment described above mainly in one respect, that, as described in Fig. 13A and Fig. As shown in Figure 13B, the semiconductor device 10G is a so-called 6-in-1 package that integrally incorporates the IGBT elements 20 and 30 of the respective upper and lower branches of three phases (U-phase, V-phase, W-phase) in a single resin part 66. Furthermore, the semiconductor device 10G differs from the semiconductor device 10 according to the first embodiment described above, which has the double-sided heat dissipation configuration, in that, as shown in Figure 13B, Fig. 13A and Fig. As shown in Figure 13B, the semiconductor device 10G has a single-sided heat dissipation configuration. However, a double-sided heat dissipation configuration can also be used in the semiconductor device 10G. This means that a double-sided heat dissipation configuration can also be used in the 6-in-1 package.

[0064] The IGBT elements 20 of the respective phases are mounted on a surface of a common first heat sink 50A. Furthermore, the IGBT elements 30 of the respective phases are each mounted on separate third heat sinks 54. A high-potential power terminal 400 serves as the first busbar, and one end of it is electrically and mechanically connected to the first heat sink 50A. The other end of the high-potential power terminal 400 is exposed to the outside of the resin part 66. A low-potential power terminal 420 also serves as the busbar, and one end of it is electrically and mechanically connected to the emitter electrodes of the IGBT elements 30 of the respective phases. The other end of the low-potential power terminal 420 is exposed to the outside of the resin part 66. The high-potential power terminal 400 and the low-potential power terminal 420 are preferably adjacent to each other and exposed to the outside of the resin part 66, as shown in Fig. 13A and Fig. Figure 13B shows this. Thus, as described above, the effect on canceling the magnetic flux can be improved and the parasitic inductance can be reduced. However, even in this case, a creepage distance L14 between the high-potential power terminal 400 and the low-potential power terminal 420 is set greater than a minimum value of the respective creepage distances (e.g., L16) between the first potential part P and the third potential part O, or a minimum value of the respective creepage distances (e.g., L15) between the second potential part N and the third potential part O. According to the Fig. 13A and Fig. In the embodiment shown in Figure 13B, the output terminals 440 of the respective phases are exposed to the outside from a side surface of the resin part 66 on a side surface opposite in the Y direction from a side surface from which the high potential power terminal 400 and the low potential power terminal 420 in the resin part 66 are exposed.

[0065] Although that in Fig. 13A and Fig. Since the illustrated embodiment in Figure 13B features a single-sided heat dissipation configuration in the so-called 6-in-1 package, a similar configuration can also be applied in the single-sided heat dissipation configuration in the 2-in-1 package with respect to the high-potential power terminal, the low-potential power terminal, and the output terminal. In this case, the output terminal 440 (1) and the low-potential power terminal 420 are connected to the emitter electrode of a single IGBT element 30.

[0066] Another embodiment (second embodiment) is described below.

[0067] Fig. 14A and Fig. Figures 14B each show a representation illustrating a semiconductor device 12 according to the second embodiment. Fig. Figure 14A shows a top view of the semiconductor device 12 and Fig. Figure 14B shows a side view of the semiconductor device 12, which is oriented in one direction of arrow Y from Fig. 14A. The semiconductor device 12 according to the second embodiment differs from the semiconductor device 10 according to the first embodiment described above mainly in that the resin part 66 is replaced by a resin part 660. Other configurations may be the same, which is why their descriptions are omitted. Furthermore, the following approach (formation of a High Comparative Tracking Index part 662 (High-CTI part 662)) can also be applied with regard to the various embodiment variants of the first embodiment described above.

[0068] The resin part 660 comprises a body part 661 and the high-CTI part 662. The high-CTI part 662 is formed from a material that has a higher CTI than that of the body part 661. A relationship between the material group and the CTI is established such that material group I is a group of materials with a CTI of 600 or more, and material group II is a group of materials with a CTI of 400 or more and less than 600. The material group to be selected can be determined by applying functional isolation according to JISC 60664 (IEC 60664). For example, according to JISC 60664, when an effective stress value and a contamination level to be used are determined with respect to material groups I, II, III, or the like, the minimum creepage distances to be observed are determined.For example, if the contamination level is set to 2 and the RMS voltage is 800 V, the minimum creepage distance for resin material group I is 4.0 mm and the minimum creepage distance for resin material group III is 8.0 mm. This is calculated, for example, according to the [reference to be added]. Fig. 14A and Fig. 14B illustrated embodiment in the case that a place with the exception of the high-CTI part 662 in the resin part 660 (i.e. the body part 661) is formed from a material of material group III, and in the case in which the creep distance L6 is less than 8.0 mm but 4.0 mm or greater, the high-CTI part 662 is formed from a material of material group III.

[0069] The high-CTI part 662 can be formed only at a necessary location within the resin part 660. For example, if the first creep distance is less than the minimum creep distance according to the material group of the body part 661, a location defining the relevant first creep distance is formed from a material of a material group that has the minimum creep distance that is the relevant first creep distance, or less (a material of the material group with a higher CTI), and this becomes the high-CTI part 662.

[0070] Although the high-CTI part 662, as indicated by a dotted line in Fig. As shown in Figure 14A, the high-CTI part 662 can only be formed on a superficial layer of the resin part 660. However, it can be formed to a certain depth (Y-direction). The high-CTI part 662 can also be formed by casting a resin material with a corresponding CTI after shaping the body part 661, or the high-CTI part 662 can be formed by coating the resin material with the corresponding CTI after shaping the body part 661. According to the [reference to figure] Fig. 14A and Fig. In the embodiment shown in Figure 14B, since the creepage distance L6 between the high-potential power terminal 40 and the low-potential power terminal 42 is smaller than the minimum creepage distance corresponding to the material group of the body part 661, the high-CTI part 662 is formed between the high-potential power terminal 40 and the low-potential power terminal 42. The high-CTI part 662 is formed as shown in Fig. Figure 14B shows that it is shaped such that it surrounds a perimeter of both the high-potential power terminal 40 and the low-potential power terminal 42 in a side view. However, as shown in Fig. As shown in Figure 15, the high-CTI part 662 can be formed only in an entire region between the high-potential power terminal 40 and the low-potential power terminal 42 in the X-direction, or, provided that a necessary insulating behavior is met, the high-CTI part 662 can be formed only in a part of the region between the high-potential power terminal 40 and the low-potential power terminal 42 in the X-direction.

[0071] In the semiconductor device 12 according to the second embodiment, unlike the semiconductor device 10 according to the first embodiment described above, the first creepage distance between the first potential part P and the second potential part N can be smaller than a minimum value of the second creepage distance between the first potential part P and the third potential part O, and can be smaller than a minimum value of the third creepage distance between the second potential part N and the third potential part O. However, according to the present embodiment 2, the respective creepage distances are set such that the following relationships are satisfied. If the minimum value of the creepage distance between the first potential part P and the second potential part N is set to L1,If the minimum creepage distance corresponding to a material between the first potential part P and the second potential part N (i.e., a material of the high-CTI part 662) is set to L1min, the minimum creepage distance between the first potential part P and the third potential part O is set to L2min, the minimum creepage distance corresponding to a material between the first potential part P and the third potential part O (i.e., a material of body part 661) is set to L2min, the minimum creepage distance between the second potential part N and the third potential part O is set to L2min, and the minimum creepage distance corresponding to a CTI material between the second potential part N and the third potential part O (i.e., a material of body part 661) is set to L3min, then at least one of the following two equations is satisfied. (L2−L2min) / L2min<(L1−L1min) / L1min (L3−L3min) / L3min<(L1−L1min) / L1min

[0072] The two equations are based on the fact that the minimum creepage distance is represented by a linear proportional expression with respect to the RMS stress value. That is, the minimum creepage distance increases proportionally with increasing RMS stress value. The (L k -L k min) / L kmin(k=1,2,3) in the two preceding equations represents a margin with respect to the minimum creepage distance. For example, if the contamination level is set to 2 and the RMS voltage is set to 800 V, the minimum creepage distance, corresponding to resin material group I, is 4.0 mm. If the creepage distance is 6 mm, the margin is 1.5. Since the minimum creepage distance is proportional to the RMS voltage, the margin is a comparable parameter even if the RMS voltages differ. The margin is an indicator showing that as the margin approaches 1, a short circuit is more likely to occur. Therefore, if either of the two preceding equations is satisfied, the same effect as that described in the first embodiment above can be obtained.This means that even if the insulating behavior deteriorates due to a deterioration of the resin part 66, before the short circuit between the first potential part P and the second potential part N is caused, a short circuit can be caused between the first potential part P and the third potential part O (for example, between the collector and the emitter of the IGBT element 20) or between the second potential part N and the third potential part O (for example, between the collector and the emitter of the IGBT element 30).

[0073] According to the second embodiment, if the resin part 660 is formed from a material with a different CTI, although this results in a disadvantage in terms of productivity, the creepage distance can be reduced. Thus, for example, if a part between the high-potential power terminal 40 and the low-potential power terminal 42 is formed from a material with a relatively high CTI, the creepage distance between the high-potential power terminal 40 and the low-potential power terminal 42 can be made smaller, and the parasitic inductance can be further reduced, compared to a case in which the material with the relatively low CTI is used for forming.

[0074] Although according to this in Fig. 14A, Fig. 14B and Fig. In the illustrated embodiment 15, where the high-CTI part 662 is formed between the high-potential power terminal 40 and the low-potential power terminal 42, the high-CTI part 662 can be formed between another first potential part P and the second potential part N.

[0075] A further embodiment (third embodiment) is described below.

[0076] Fig. Figure 16 shows a diagram illustrating a semiconductor device 13 according to the third embodiment. The semiconductor device 13 differs from the semiconductor device 10 according to the first embodiment described above in that a spatial distance relationship, described below, is satisfied. Similarly, a spatial distance concept described below can be applied to the various embodiment variants of the first embodiment described above.In the semiconductor device 13, although the first creepage distance between the first potential part P and the second potential part N may be smaller than the minimum value of the second creepage distance between the first potential part P and the third potential part O, and may be smaller than the minimum value of the third creepage distance between the second potential part N and the third potential part O, it is preferable to have a creepage distance relationship similar to that described above in the first embodiment.

[0077] In particular, a first spatial distance between the first potential part P and the second potential part N (given a multitude of them, a minimum value thereof) is greater than a second spatial distance between the first potential part P and the third potential part O (given a multitude of them, a minimum value thereof), or greater than a third spatial distance between the second potential part N and the third potential part O (given a multitude of them, a minimum value thereof). However, the second and third spatial distances are set such that they are the lower limit (for example, the minimum spatial distance based on the JIS standard) or greater. Thus, the probability of a short circuit between the first potential part P and the second potential part N due to a space discharge can be reduced.This means that even if a space discharge is caused before a short circuit is caused between the first potential part P and the second potential part N, a short circuit will be caused between the first potential part P and the third potential part O (for example, between the collector and the emitter of the IGBT element 20) or between the second potential part N and the third potential part O (for example, between the collector and the emitter of the IGBT element 30).

[0078] According to the in Fig. In the illustrated embodiment 16, the high-potential power terminal 40, the low-potential power terminal 42, and the output terminal 44 are shaped such that the first spatial distance Ls1 between the high-potential power terminal 40 and the low-potential power terminal 42 is longer than the third spatial distance Ls3 between the low-potential power terminal 42 and the output terminal 44. Thus, before a short circuit is caused between the first potential part P and the second potential part N, a short circuit can be caused between the second potential part N and the third potential part O (for example, between the collector and the emitter of the IGBT element 30).

[0079] According to the in Fig. In the illustrated embodiment 16, based on a positional relationship between the high-potential power terminal 40, the low-potential power terminal 42, and the output terminal 44, the second spatial distance Ls2 between the high-potential power terminal 40 and the output terminal 44 is sufficiently long, which is why the second spatial distance Ls2 essentially does not need to be considered. However, in a configuration that, for example, Fig. As shown in Figure 9, since the second spatial distance between terminal 49 and control terminal 46 (from the third potential part O) can be made smaller, the first spatial distance can be set larger than such a second spatial distance.

[0080] Fig. Figure 17 shows a top view illustrating a semiconductor device 13B according to another embodiment of the third embodiment. The semiconductor device 13B differs from the semiconductor device 13 according to the third embodiment described above, as shown in Fig. Figure 17 shows that the low potential power terminal 42 and the output terminal 44 are replaced by a low potential power terminal 42B and an output terminal 44B.

[0081] The low-potential power terminal 42B has a projection 43 extending in the X direction towards the output terminal 44B, and the output terminal 44B has a projection 45 extending in the X direction towards the low-potential power terminal 42B. Thus, the third spatial distance Ls3 between the low-potential power terminal 42B and the output terminal 44B can be made significantly smaller. However, the third spatial distance Ls3 is set such that it is at or above the lower limit (for example, the minimum spatial distance based on the JIS standard). Therefore, the first spatial distance Ls1 between the high-potential power terminal 40 and the low-potential power terminal 42 can be made slightly longer than the third spatial distance Ls3 between the low-potential power terminal 42B and the output terminal 44B.

[0082] According to the in Fig.In the embodiment shown in Figure 17, either of the projecting parts 43 and 45 can be omitted. Furthermore, the projecting part 43 and the projecting part 45 can be formed over an entirety of the exposed parts of the low-potential power terminal 42B and the output terminal 44B. That is, by extending the widths (widths in the X-direction) of the exposed parts of the low-potential power terminal 42B and the output terminal 44B, the first spatial distance Ls1 between the high-potential power terminal 40 and the low-potential power terminal 42B can be made longer than the third spatial distance Ls3 between the low-potential power terminal 42B and the output terminal 44B.

[0083] According to the embodiments described above, the IGBT elements 20 and 30 are used as a switching element. However, a switching element other than an IGBT element, such as a MOSFET (metal oxide-semiconductor field-effect transistor), can be used. Furthermore, the IGBT elements 20 and 30 can form a reverse-conducting IGBT (RC-IGBT) containing the FWD elements 28 and 38.

Claims

[1] Semiconductor device with: a first switching element (20) having a first electrode (22) and a second electrode (24), and forming an upper branch of upper and lower branches, wherein the first electrode (22) and the second electrode (24) of the first switching element (20) each form both sides of the first switching element (20) in a first direction (Z), a second switching element (30) which is aligned with the first switching element (20) in a second direction (X), has a first electrode (32) and a second electrode (34), and forms the lower branch of the upper and lower branches, wherein the first electrode (32) and the second electrode (34) of the second switching element (30) each form both sides of the second switching element (30) in the first direction (Z), a first metal element (50) which is electrically connected to the first electrode (22) of the first switching element (20) in the first direction (Z), a second metal element (54) which is electrically connected to the first electrode (32) of the second switching element (30) in the first direction (Z), a first connection (40) which has a potential on a high-potential side of the upper and lower branches, a second terminal (42) which has a potential on a low-potential side of the upper and lower branches, a third connection (44) which has a midpoint potential of the upper and lower branches, and a resin part (66) which in one piece covers the first switching element (20), the second switching element (30), at least a part of the first metal element (50), at least a part of the second metal element (54), a part of the first terminal (40), a part of the second terminal (42) and a part of the third terminal (44), wherein, if a part having a potential equal to a potential of the first terminal (40) is assumed to be a first potential part (P), a part having a potential equal to a potential of the second terminal (42) is assumed to be a second potential part (N), and a part having a potential equal to a potential of the third terminal (44) is assumed to be a third potential part (O), a comparative tracking index of a first material present between the first potential part (P) and the second potential part (N) in the resin part (66) is higher than at least one of the comparative tracking indices of a second material and a third material, wherein the second material is present between the first potential part (P) and the third potential part (O) in the resin part (66), and the third material is present between the second potential part (N) and the third potential part (O) in the resin part (66), wherein, if a minimum value of creepage distances between the first potential part (P) and the second potential part (N) in the resin part (66) is set to L1, a minimum creepage distance allowed for the first material between the first potential part (P) and the second potential part (N) is set to L1min, a minimum value of creepage distances between the first potential part (P) and the third potential part (O) in the resin part (66) is set to L2, the minimum creepage distance allowed for the second material between the first potential part (P) and the third potential part (O) is set to L2min, the minimum value of creepage distance between the second potential part (N) and the third potential part (O) along the surface of the resin part (66) is set to L3, and the minimum creepage distance allowed for the third material between the second potential part (N) and the third potential part (O),is set to L3min, and at least one of the following two equations is satisfied, (L2−L2min) / L2min<(L1−L1min) / L1min (L3−L3min) / L3min<(L1−L1min) / L1min, and the first direction (Z) is perpendicular to the second direction (X). [2] Semiconductor device according to claim 1, wherein the second terminal (42) is located between the first terminal (40) and the third terminal (44), and the first connection (40), the second connection (42) and the third connection (44) extend on one side of the resin part (66). [3] Semiconductor device according to claim 2, wherein the first terminal (40), the second terminal (42) and the third terminal (44) are aligned to each other in the second direction (X), while extending in a third direction (Y) perpendicular to both the first direction (Z) and the second direction (X), and the second connection (42) extends in the third direction from a position between the first metal element (50) and the second metal element (54) in the second direction (X). [4] Semiconductor device according to any one of claims 1 to 3, wherein the first metal element (50) has a first surface (50b) exposed by the resin part (66) and a second surface (50a) which is opposite to the first surface (50b) of the first metal element (50) and faces the first electrode (22) of the first switching element (20) in the first direction (Z), the first surface (50b) of the first metal element (50) forms the first potential part (P) together with the first terminal (40), the second metal element (54) has a first surface (54b) exposed by the resin part (66) and a second surface (54a) which is opposite to the first surface (54b) of the second metal element (54) and faces the first electrode (32) of the second switching element (30) in the first direction (Z), and the first surface (54b) of the second metal element (54) forms the third potential part (O) together with the third terminal (44). [5] Semiconductor device according to claim 4, further comprising a third metal element (52) which is electrically connected to the second electrode (24) of the first switching element (20), wherein the second electrode (24) of the first switching element (20) is opposite to the first electrode (22) of the first switching element (20) in the first direction (Z), and a fourth metal element (56) which is electrically connected to the second electrode (34) of the second switching element (30), wherein the second electrode (34) of the second switching element (30) is opposite to the first electrode (32) of the second switching element (30) in the first direction (Z), wherein the third metal element (52) has a first surface (52b) exposed by the resin part (66) and a second surface (52a) which is opposite to the first surface (52b) of the third metal element (52) and faces the second electrode (24) of the first switching element (20) in the first direction (Z), the first surface (52b) of the third metal element (52) forms the third potential part (O) together with the third terminal (44) and a surface of the second metal element (54), the fourth metal element (56) has a first surface (56b) exposed by the resin part (66) and a second surface (56a) which is opposite to the first surface (56b) of the fourth metal element (56) and faces the second electrode (34) of the second switching element (30) in the first direction (Z), and the first surface (56b) of the fourth metal element (56) forms the second potential part (N) together with the second terminal (42).

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