Lean serial interface for a wrapper boundary register (device and method)

Abstract

Serially operable interface device on a chip (1), the interface device (201) for generating control signals for a wrapper boundary register (40, WBR) on chip level (1), wherein the wrapper control signals (30) conform to a given standard for testing a core device (100), wherein the core device is also provided on the chip (1) and contains the WBR, the serial interface device (201) contains: - a physical data input (2a) and a physical data output (2b) and no more than the input (SDI) and output (SDO) of the serial interface device (201), which are coupled to a respective terminal (1a, 1b) on the chip (1) containing the interface device (201) and the core device (100) with the wrapper boundary register (40); and a physical clock input (2c), which is coupled to a third terminal (1c) on the chip (1) at the chip level for injecting a clock signal (SCLK) into the serial interface device (201); the serial interface device (201) also includes: - an address register (214) for recording a received address for comparison with a device address (214a); - an instruction register (213) for receiving and holding wrapper instructions supplied via the port (1a) supplying the data input (SDI) on the chip (1); - a control logic (209) containing a state machine (210) for processing transactions from an external master (10), which provides a logical data input (SDI) to the physical data input port (1a), and the serial interface device (201) sends a logical data output (SDO) to the physical data output port (2b) and back to the external master (10) from the WBR (40) of the core device (100); - wherein the state machine (210) is configured to provide the wrapper control signals (30) of the given standard for the core device (100) containing the wrapper boundary register (40; WBR); - to read an address recorded by the address register (214) and compare it with the device address (214a); - to read a currently active wrapper instruction held by the instruction register (213); - Send (logical) output test (SDO) data as taken from the wrapper boundary register (40, WBR).

Description

[0001] The invention relates to a serially operable interface device (in the sense of a "device" as an arrangement) for test purposes (STI) on a chip, as well as its applications and fields of use. The interface device is configured to generate control signals for a wrapper boundary register (WBR) at the chip level of a chip. The wrapper control signals meet a given standard for testing a core device, which is surrounded by the wrapper boundary register with multiple cells. The core device is also provided on the chip and contains the wrapper boundary register consisting of multiple cells for internal testing.

[0002] The IEEE 1500 Standard was created to address the testing complexity of Systems on Chips (SoCs). See "Overview of the IEEE 1500 Standard," daSilva, Whetsel et al., ITC INTERNATIONAL TEST CONFERENCE, Document 38, 2003, and THE CORE TEST WRAPPER HANDBOOK, Springer, 2006, Chapter 2. The standard provides a standard interface and a set of rules for creating an isolation boundary between a core and the logic outside the core. The purpose of the isolation boundary, or wrapper, is to enable isolated testing of the core with minimal signals that need to be ported out to the SoC layer. The wrapper contains multiple wrapper cells for each functional input and output port. See ITC INTERNATIONAL TEST CONFERENCE, Section 2.2.2.2 above. Flip-flops can be used as wrapper cells and are connected to a wrapper scan chain or wrapper scan chains.The wrapper chains are used instead of the functional ports during testing to control and monitor the core logic.

[0003] This allows the core to be isolated from any external logic during testing and still obtain a complete capture of the core for its screening, see "IEEE Standard 1500 Compliant Wrapper-Boundary-Register Cell" by Teresa L. McLaurin and "An IEEE 1500 Compatible Wrapper Architecture for Testing Cores at Transaction Level" by Fatemeh Refan et al., University of Tehran, EWDTS 08-80, December 2008, item 2.2.

[0004] Further IEEE 1500 compliant interfaces using a TAP IEEE 1149 controller (as state machine) are shown in US 8 412 992 (Whetsel, TI), see Fig.83 and this claim 1, item B in column 26, which identify the precise signal designations. US 7 404 129 (Whetsel, TI) discloses the test port and its environment, see this claim 1 in column 31, with signals TDI, TDO and TMS as well as a clock TCK (in group A of claim 1) and a wrapper serial port WSP that is IEEE 1500 compliant (in group B of claim 1) which uses the signals WSO, WSI of the core test signals of the standard. Another approach in US 2012 / 0459 275 (Whetsel, TI) uses a TAP-controlled WSP, finally combining them to form a single optimized test interface. The claim to this invention is free of specific signal designations, see this claim 1 in column 17, but publishes 59 pages of figures and drawings alongside a meager 3 claims.

[0005] The relationship in electronics testing between IEEE Standard 1500 and IEEE Standard 1149.1 is very close, with IEEE Standard 1149.1 focusing on board testing and IEEE Standard 1500 focusing on testing embedded cores in Systems on Chips (SoC) on the boards.

[0006] IEEE 1500 applies to wrapped embedded cores in an SoC using an IEEE 1149.1 test access port (TAP). The test controller can be based on a conventional IEEE 1149.1 state machine. The input / output signals of each core are typically not accessible from the highest SoC level, so efficient mechanisms are required to transport test vectors to and from the embedded wrapped cores, called test access mechanisms (TAMs). Efficient allocation of the wires forming the TAMs between the wrapped cores can reduce overall test time. For example, for a test SoC design with ten wrapped cores and 15 TAM lines, a TAM allocation algorithm calculated that Core 1 uses TAM lines 1 to 9 for test data, Core 2 uses TAM lines 10 to 14 for test data, and the remaining cores use the remaining TAM line(s).The TAM was effectively divided into three TAM sections, TAM Section 1 comprising TAM lines 1 to 9, TAM Section 2 comprising TAM lines 10 to 14, and finally TAM Section 3 comprising the remaining TAM line(s).

[0007] It was not possible to individually control each WIR (wrapper instruction register) from off-chip resources, as each WIR requires eight signals (simultaneous testing of IEEE 1500-compliant wrapped cores). For example, if there were ten wrapped cores on the chip, eighty SoC clock / input / output pins would be required to control the wrapper chains. This is undoubtedly a lot. The test controller presented in this paper utilized the five IEEE 1149.1 TAP signals to control all WIRs in the SoC. The test controller also reduced the complexity of the off-chip Automated Test Equipment (ATE) by performing WIR control. See paper ISSC 2008, Galway, June 18-19, "IEEE 1500 Wrapper Control using an IEEE 1149.1 Test Access Port" by Michael Higgins, Ciaran MacNamee, and Brendan Mullane.

[0008] The above document by Michael Higgins et al. followed an approach of using multiple cores which are tested by a TAP (Test Access Port) controlled state machine, see Fig. 5, Fig. 6 of this document and page 201, right column, second paragraph. They use a TAM section state machine in the test controller to provide the function of routine test data between the off-chip test intelligence and the cores under test (which they refer to as CUTs (Cores Under Test)). The test port of the TAP state controller is common and in IEEE standard 1149.1, and it uses five signals as in Fig. 5 of this document by Higgins. If one added this Fig. 6, a TAM controller was added to the state machine shown, this identified which of the digital cores would be tested with the signals provided by the TAP state machine and its states (referred to here as a “multi-arm test”).

[0009] A similar approach with a multi-arm test is described in our Fig. 5b shows how the same TAP state controller with these five standard signals establishes a connection to several wrapped cores using IEEE 1500 standard signals via an interface logic. Such a controller does not work without this additional, in our Fig. Interface logic shown in Figure 5b.

[0010] Simplifying such multi-arm test control of a multi-core system-on-chip is one of the objectives of this invention (which aims to meet the needs identified in the prior art). Another objective is to minimize or reduce the number of connections (pins or leads) required to deliver test information from an external intelligence such as an External Testing Master (eTM). For example, IEEE Standard 1149.1 uses five test signals (TDI, TDO, TCK, TRST, TMS). IEEE Standard 1500 uses at least eight signals for operating the wrapper in a test mode (one clock, one input, one output, and five control signals).

[0011] WHETSEL, Lee: Addressable test ports: an approach to testing embedded cores. In: Proceedings / International Test Conference, 1999. Piscataway, NJ: IEEE, 1999. pp. 1055 to 1064 - ISBN 0-7803-5753-1 proposes many variants of a test register. The motivation behind all variants is to enable the testing of embedded cores within a system IC. For this purpose, each embedded core is assigned an addressable test port, making the embedded core directly addressable. The test port is scalable. Fig. 2 illustrates such an addressable test port, which is serially supplied with an address, and the “embedded core” addressed by it, see there Fig. 7. A unique address is loaded serially into each of the test ports. SI / SO are external connections.

[0012] US 2011 / 0 161 762 A1 describes a different test structure using DDR signaling technology to efficiently test embedded cores. IEEE 1500 and IEEE 1149.1 test structures are mentioned, where test responses are evaluated by an internal compare circuit to avoid the need to output a test response. A programmable test controller (with an instruction) is proposed to avoid increasing the number of test interface signals. The required number of external connections is not specified.

[0013] Thus, one object of the invention is to reduce the number of pins used to control the test mode, test function, and test results of at least one wrapped core. Furthermore, the aim is to at least maintain or even increase test flexibility and, moreover, to increase the speed of testing the wrapped cores. The required chip area should also be reduced.

[0014] This is achieved by any of independent claims 1, 15, 25, 28 and 30, 31, 32, 34, 38 or 41, which propose a serially operating interface device controlled by wrapper instructions.

[0015] The subclaims are advantageous embodiments. One highlight is the generation of a CaptureWR signal by a state machine immediately after the WBR control signal UpdateWR (claim 38). Another highlight is a test method for testing wrapped cores in a system-on-chip, where each wrapped core is equipped with its own serial interface device (claims 25, 1 or 25, 15). Another highlight is a method for skipping a state of a state machine by skipping the reading of a device address using a first bit (FIN) in a corresponding FIN register to determine whether multiple transactions are implemented for the selected interface device (claim 28). Another highlight is a method for generating additional wrapper boundary register (WBR) control signals by the state machine on a chip.wherein the additional WBR control signal is generated upon completion of a READ_INSTRUCTION by the state machine (claim 31). Another highlight is a method for generating IEEE 1500 Wrapper Boundary Register (WBR) control signals by the state machine with multiple states, wherein the state machine is part of a functional slave in a system-on-chip (SoC) configuration. Another highlight is the generation of an active-low wrapper reset signal WRSTN by the state machine upon completion of a READ_INSTRUCTION state in an IDLE state, whenever an instruction register contains a WS_RESET instruction (claim 30).

[0016] The problem is also solved or fulfilled by an independent layout for a customer (claim 32). This invention and all embodiments thereof (claim 33 as well as several alternatives) relate to a layout created for designing a real chip. The layout is delivered to a customer, who adds custom features such as the number of cores on their chip or hard-coded device addresses of each serial test interface used on the customer chip. Then, the masks are created, and the chip is produced. The functions are created in the layout, and the claim is to be read accordingly.

[0017] The serial test interface device (claim 1) includes a physical data input, a physical data output, and a physical clock input. These physical mappings are understood as terminals or pins on a chip or as representations thereof in a layout. The chip itself is usually referred to in the term "at chip level," which means that the serially operable test interface is located on the chip and could be present multiple times on the chip for multiple cores, each of which has the surrounding wrapper boundary register. Therefore, each serial interface device also includes an address register for holding a received address for comparison with its own device address. Thus, many cores can be tested, and each core is linked to one of the serially operable interface devices. Each of the devices has its own address.This address is unique and will not be reused on this chip. Testing can therefore be directed to the serially operable test interface with a specific address, which tests a core device that has a wrapper boundary chain around it (see claim 25 for its operation).

[0018] By reducing the number of interfaces to a single serially operable test interface, the structure and thus the function are explained (claim 15); an address register can be omitted for this purpose. This basic idea can then be multiplied for the multiple use of several such interface devices for several such core devices linked with wrapper boundary registers (claim 25).

[0019] The physical data input, the physical output, and the physical clock signal are the only signals physically used by no more than three pins. Thus, the number of pins enabling testing is further reduced to a maximum of three, and will not increase if more cores are provided on the chip (claims 25, 26, 27).

[0020] Using the three terminals carrying the signals SDI, SDO, and SCLK, the serially operable interface device is coupled to these signals (or vice versa). The interface device has control logic containing a state machine. This control logic is supplemented with an address register and an instruction register, preferably also a counter (register) (claims 2, 14, 18). The embedded state machine generates the required control signals for the wrapper boundary register from an instruction contained in the instruction register. The SCLK clock and the SDI input provide the instruction register with an instruction to generate at least four on-chip control signals (as "output" from the state machine), which are fed into the wrapper boundary register for on-chip control of the tests of the core surrounded by the (one or more) wrapper boundary register(s) (WBR).These signals meet the given standard such as the IEEE 1500 standard, although the physical input pins to the chip are much fewer than required for this standard, such as the IEEE 1500 standard.

[0021] The third connection (pin or lead) on the chip or layout (representing a physical connection in the layout) is an output that provides the SDO signal of the SoC, which originates from the WSO signal of the WBR.

[0022] This creates a lean serial interface (SSI) or chip interface (CI) for a wrapper boundary register, offering fully functional test performance and fewer pins or leads required for such tests. It still meets the established standard for core testing using wrapper boundary registers and increases test flexibility. The pin count is reduced because wrapper instructions for use by the state machine (which is embedded in the control logic) are sent serially to the instruction register via the SDI pin. Delay testing can still be performed because it can be ensured that certain signals follow one another immediately (claim 38).

[0023] The state machine has a specific configuration that utilizes the one or two registers mentioned above: the instruction register and, preferably, a counter (also called a register containing a specific count value).

[0024] A destination address can be input and held by the address register, and the value of this address register addresses a specific serial interface device (which serves one core among many other cores, each with its own serial interface device STI). The contents of the address register are compared with a given address associated with this "device" (this STI and the associated core). The address of each device can be hard-coded (in a layout) or can be assigned to the STI by a register or specific on-chip hardware such as DIL switches or jumpers.

[0025] The instruction register contains a wrapper instruction, and the counter can be used to handle the state changes of the state machine (claims 14 and 18). The state machine in the control logic is then configured to provide wrapper control signals WSC according to the wrapper instruction held by the instruction register.

[0026] On the chip, the state machine thereby generates and provides at least most of the control signals of the given standard for the core device containing the wrapper boundary register (WBR), preferably all control signals of the WBR (claim 4). The control signals that are optional can also be optional; see the optional ninth control signal from "IEEE Standard 1500 Compliant Wrapper Boundary Register Cell" by Teresa L. McLaurin, page 2, first paragraph. Even another signal of the given standard may not and will not be generated by the state machine, such as the SelectWIR signal. Nominally, the control signals that can be generated by the state machine for one or more consecutively active instructions in the IR (Instruction Register), which itself receives the bits of each instruction serially via the SDI port, can be CaptureWR, ShiftWR, UpdateWR, and WRSTN of IEEE Standard 1500.

[0027] The SelectWIR signal is not a WBR control signal, but a WSP (Wrapper Serial Port) control signal.

[0028] These control signals generated on the chip were not routed through separate pins, but were created by the on-chip state machine and in response to instructions received via the chip's test input pin SDI.

[0029] The state machine controls the test behavior using self-generated control signals. It can control the wrapper chain with respect to its signal paths and the signals contained in the cells. The return signals from the wrapper cells to the individual output of the chip are organized by the control logic by "coupling" the WSO test output of the wrapper boundary register with the chip's SDO output (at the end of interface claim 34). This ensures the state machine full control of the WBR, even though no control signals need to pass through the bottleneck of the chip's physical interface.

[0030] The serial interface can return signals from the wrapper boundary register, initiated by processing instructions from the external master and returning data (such logical data) as output data (SDO) to the physical data output pin and to the external test master eTM for evaluation (claim 1, last feature group). Alternatively, the return signal from the wrapper boundary register can be routed directly to the chip's individual output pin.

[0031] The serial test interface (claims 34, 41) includes an instruction register for receiving and holding wrapper instructions supplied via the physical data input port. A state machine is provided for processing transactions from an external master. The state machine is configured to read a currently active wrapper instruction (WI) as held by the instruction register and, in accordance with a wrapper instruction read from the instruction register, to generate and provide one or more on-chip wrapper control signals of the given standard to a core device containing the wrapper boundary register.

[0032] There may be more than one wrapper control signal generated from a WI, and there may be WIs that are not directly related to generate wrapper control signals, but control other units or circuits on the chip, preferably in the serial test interface, which contains the state machine and control logic.

[0033] The "currently active wrapper instruction" can generate various control signals (as briefly outlined in claim 30). In a more general approach (claims 41, 42, 43), a wrapper instruction (WI) in the instruction register (IR) can provide for up to three different wrapper boundary register (WBR) control signals generated by the state machine. These are caused by the specific WI and generated by the state machine.

[0034] The single pin feeding the input test signal is coupled to the wrapper boundary register as an on-chip logical input test signal (WSI). It can also be fed into the control logic (containing the state machine) to enable certain functions there, but it is securely connected to the instruction register for providing the wrapper instruction and can be connected to the address register, if present, to send a device address request to it. The address register is configured to select one of several serial test interfaces when read and compared with the serial test interface device address present in each serial test interface. The address register can be omitted if only a single serial test interface is present on the chip.

[0035] Please note that this description of several inventions uses several abbreviations that have become common in the art when applying the IEEE 1500 and IEEE 1149.1 standards. These signal designations are acronyms, some of which have been further abbreviated in our disclosure. For example, the IEEE 1500 signal CaptureWR is called "CW" and ShiftWR is called "SW," making them still unambiguous but shorter for descriptive purposes.

[0036] Claims 1, 15, 34, and 41, and their interpretation, are intended to address not only IEEE Standard 1500, but also other, further, or future standards that may develop in the future, which also require certain given signals. Therefore, the designations of these signals were not used as limiting features in the respective independent claim, but, where they specifically concern IEEE Standard 1500, were included in the dependent claims (claims 3 to 5). In contrast, independent claim 30 expressly claims the generation of the IEEE Standard 1500 signals (but does not prohibit generating or using the standard signals in other ways—the standard is still open; claim 31 generates the standard control signals in a specific way).

[0037] For this IEEE Standard 1500, we should note that not all signals need to be present in the implementation using the state machine in the control logic. There could be redundant signals that might not be generated. And there could be additional (new) signals added to the standard. As before, those signals that are used, those generated by the state machine, and those included in the standard will conform to the standard used, such as IEEE Standard 1500. Thus, mentioning this standard in a claim does not necessarily include all of its standardized signals in that claim, unless specific signal designations of the standard are explicitly identified in the claim.

[0038] We should mention that the chip containing the one or more cores (core devices) could and will have many other terminals (leads or pins) related to the function of the chip, but the set of terminals dedicated to testing is limited according to the invention to a set that is smaller than previously known in the prior art.

[0039] The invention allows for skipping a state during operation of the state machine (claim 28). This means skipping the reading of a device address, e.g., READ_DEV_ADR, so that the reading of the device address is skipped in the next transaction. A serial interface device, preferably the one disclosed in claim 1 or 15, receives a device address with the first bit (FIN) in a register.

[0040] A one-bit FIN (Following INstruction) can be sent with the device address. If FIN=1, further instructions for the selected serial test interface (as a slave) follow. This means the device address only needs to be sent once. This is a further advantage of the invention according to claim 28.

[0041] Each wrapped core can have its own serial test interface, which is directly and individually controlled by the individual off-chip test master (eTM) (claim 25). The master is located off-chip, e.g., in the test fixture. Additional superfluous on-chip operational logic is not required.

[0042] The eTM selects the desired serial test interface (referred to as the "desired slave" in this configuration, since a master operates multiple slaves in parallel). This is done by sending the device address of the targeted slave.

[0043] In this configuration, the one-bit FIN (Following Instruction) can also be used and sent with the device address. Only when FIN has determined the "following instruction state(s)" (this can be done by either a ONE or a zero as the FIN bit status) will further instructions follow for the selected slave. This means the device address only needs to be sent once.

[0044] The selection was made by device address matching.

[0045] If the "Follow Instruction Bit" has the other (opposite) value as its status (which can be either ZERO or ONE), the device address is sent in the next cycle (during the next transaction). Claim 28 can be applied to the invention according to claim 25 or the serial test interface according to claim 1 or 15 if the STI is provided multiple times on the chip. Claim 28 can also be combined with a "delay time testing" feature according to claim 38.

[0046] The methods of claims 31 and 30 are incorporated herein by reference (without reference numerals).

[0047] The "currently active wrapper instruction" can generate various signals (as briefly outlined in claim 30). In a more general approach, a wrapper instruction (WI) in the instruction register (IR) can provide up to three different wrapper boundary register (WBR) control signals generated by the state machine.

[0048] Normally, three such control signals are generated for an active WI (wrapper instruction). These are CaptureWR, ShiftWR, and UpdateWR. But there are other WIs that generate fewer wrapper boundary register control signals, e.g., WS_SHIFTUPDATE, since WI does not generate the CaptureWR control signal because the READ_DATA state is skipped. Without having, using, or reaching the READ_DATA state, there is no generation of CaptureWR (as understood from the claimed conditions "in a READ_DATA state" in the first feature group of claim 30). The claimed method of this claim has a significant advantage. When compared with the control of a WBR by the known port TAP / WSP, the generation of CaptureWR may not be skipped and UpdateWR is used for, e.g.,WS_PRELOAD is not generated as a WI, see the conditions of claim 30 in the third feature group requiring "based on the currently active wrapper instruction." This WI blocks or prevents an update (UpdateWR).

[0049] Claim 32 and its ultimate embodiment in claim 33 (as well as several alternatives) relate to a layout created for designing a real chip. The layout is supplied to a customer, who adds custom features such as the number of cores on their chip or hard-coded device addresses of each serial test interface used on the customer chip. The functions are created in the layout, and the claim is to be read as being at the layout level, designed or configured to create a corresponding real function during production of the chip, e.g., an instruction register in the layout is designed to create an instruction register in the real chip, and the same applies to the address register and the state machine. The pins are represented in the layout as representative pins on the chip.

[0050] The layout is designed for a serial test interface (claim 32). It includes a layout for an instruction register for receiving and holding wrapper instructions delivered via a representation of a physical data input port, and a layout of a state machine for processing transactions delivered to it. The state machine is "layouted" to read a wrapper instruction from the instruction register and, in accordance with the wrapper instruction read from the instruction register, to generate and provide wrapper control signals of the given standard for the core device containing the wrapper boundary register. A representation of a single input port is provided to feed an input test signal (SDI) coupled to the wrapper boundary register as a logical input test signal.A representation of a single output port is provided to return an output test signal coupled to the representation of the output port from an output (WSO) of the wrapper boundary register of the core device.

[0051] The IEEE 1500 standard was developed to test embedded cores in a system-on-chip (SoC). The embedded cores have IEEE 1500 wrappers around all their inputs and outputs. Serial access to the wrapper is possible via the IEEE 1500 Wrapper Serial Port (WSP). The WSP contains eight mandatory Wrapper Serial Control (WSC) pins. To reduce the pin count, the IEEE 1149.1 Test Access Port (TAP) controller is often used to generate WSC signals without using the WSC pins. For this purpose, the IEEE 1500 WSP was controlled by an on-chip IEEE 1149.1 TAP controller, see Fig.5. The IEEE 1149.1 TAP (Test Access Port) contains four to five pins. However, using a WSP without a TAP controller offers greater test flexibility because the WSC signals can be applied directly. More test pins are still required on the chip.

[0052] In addition to achieving a lower number of test connections (pins or leads or corresponding representations in the layout) in the claimed interface, the test flexibility is even higher and can offer the testing of delay times compared to the IEEE 1149.1 TAP state machine used to generate WSC signals.

[0053] Furthermore, it is not possible to skip Capture-DR and Capture-IR when the IEEE 1500 WSP is controlled by an on-chip IEEE 1149.1 TAP controller. This results in longer test times in the current state of the art.

[0054] Delay testing is not possible when the IEEE 1500 WSP is controlled by the on-chip IEEE 1149.1 TAP controller because the CAPTURE signal is not generated by the IEEE 1149.1 state machine in the state-of-the-art configuration immediately after the UPDATE signal.

[0055] Controlling multiple IEEE 1500-compliant wrapped cores via the IEEE 1149.1 TAP on a single chip (SoC design) would require additional interface logic. The invention avoids this according to claim 25 and saves chip area.

[0056] The key advantage of the claimed invention is the fact that the slim serial test interface can operate at a high clock frequency with a small number of pins. The claimed invention requires only one input pin, one output pin, and one clock pin, which are to be connected to terminals at the SoC (chip) level.

[0057] Furthermore, the claimed invention offers greater test flexibility because the wrapper boundary register signals CaptureWR, ShiftWR, and UpdateWR are generated based on a currently active wrapper instruction in the corresponding instruction register. Thus, it is possible to skip the CAPTURE signal and / or omit the UPDATE signal.

[0058] Testing the WBR delay time is available by generating CaptureWR immediately after UpdateWR (claim 38). The method for generating a proper wrapper boundary register (WBR) control signal CaptureWR by a state machine. The generation occurs immediately after the WBR control signal UpdateWR. The WBR control signal CaptureWR is generated by the state machine in a READ_UPDATE state based on the count content of a counter register—this occurs whenever an instruction register contains an instruction requesting "testing the delay time."

[0059] A further advantage of another claimed invention is the generation of at least one additional wrapper boundary register control signal (claim 31), e.g., WCH_RESET. The WCH_RESET signal makes it possible to reset one or more access signals. The contents of the other shift registers are not changed because the state machine does not generate CaptureWR, ShiftWR, and UpdateWR. This avoids time-consuming shift cycles in the wrapper boundary register and significantly reduces test time.

[0060] Examples are shown to enable the inventions as claimed. They are not intended to limit the claimed inventions, but rather to enable them to be used by a person "skilled in the art" (persons skilled in the art of chip and wrapped core testing). Fig.Figure 1 functionally illustrates the registers of an example serial test interface 201 with fewer SDI and SDO pins for test functions. A clock pin must be added. Fig. 1a is an assignment table which relates the mentioned signals to the control logic 209 and the state machine 210 in the Fig. 1 and Fig. 2 connects. Fig. 2 illustrates the architecture of the Fig. 1 with a Wrapped CORE 100 according to IEEE 1500 and with more structural definitions than the functional sketch in Fig. 1 provides the reader. Fig. 3 illustrates an example state machine 210 and states 500 through 550 in a state transition diagram 301. Fig. 4 illustrates the connection of several serial test interfaces 201a, 201b, 201c at IC level, each of which is assigned to a core 100a, 100b, 100c. Fig.Figure 5a shows the state-of-the-art and illustrates the architecture with a wrapped CORE according to IEEE 1500 and WSP and WSC signals. Fig. Figure 5b shows the state of the art and illustrates the IEEE 1149.1 finite state machine (TAP controller) operating multiple Wrapped Cores according to IEEE 1500 with additional on-chip logic. Fig. Figure 6 shows the state of the art and illustrates the state sequence as dependent on the TMS signal of the TAP port, as described in ISSC 2008, Galway, June 18-19, “IEEE 1500 Wrapper Control using an IEEE 1149.1 Test Access Port” by Michael Higgins, Ciaran MacNamee, Brendan Mullane, therein Fig. 2. All state changes are based on the TMS signal (1) of the TAP state machine. Fig. Figure 7 illustrates a comparison of Fig.5b (state of the art) and the new configuration of several serial test interfaces 201a, 201b, 201c at IC level, each of which is assigned to a core 100a, 100b, 100c and has its own device address as in Fig. 4. The advantage achieved by reduced wiring and logic miniaturization is obvious. Fig. Figure 8 is a diagram of the timing of a bit transmission. Fig. Figure 9 illustrates the RESET / RUN (R / R) state for slave 201. Fig. Figure 10 illustrates the generation of the internal WRSTN signal. Fig. Figure 11 illustrates the STOP_SHIFT sequence when the last shift bit (SDI) is “HIGH”. Fig. Figure 12 illustrates the STOP_SHIFT sequence when the last shift bit (SDI) is LOW. Fig. Figure 13 illustrates a general transaction sending data according to the WS instruction. Fig.Figure 14 illustrates a special transaction for a non-data transfer function. Fig. Figure 15 illustrates a “Send ID Code” transaction 215a. Fig. Figure 16 illustrates an example with two subsequent transactions and FIN=0. Fig. Figure 17 illustrates an example with multiple subsequent transactions and FIN=1.

[0061] Fig. Figure 6 illustrates the well-known finite TAP state machine according to IEEE 1149.1. Wrapper Serial Control (WSC) signal generation via the TAP controller is based on this TAP state machine. In this state machine, it is not possible to skip, for example, Capture-DR and Capture-IR.

[0062] Fig.1 illustrates the new architecture with a Wrapped CORE 100 according to IEEE 1500 and with the serial test interface 201, both on a chip 1 and linked to the Test Master eTM 10 via a reduced set of connectors 1a, 1b and 1c.

[0063] Only two signals (SDO and SDI) and one clock signal (SCLK) need to be connected to corresponding test pins at IC level 1. The wrapper boundary register 40 control signals 30 are: CaptureWR, ShiftWR, UpdateWR, and WRSTN and are generated by the state machine 210 of the serial test interface 201. These wrapper control signals 30 operate the IEEE 1500 wrapper 40 in test mode.

[0064] Additional wrapper boundary register control signals, e.g., WCH_RESET, may also be generated by the state machine 210.

[0065] Fig. Figure 2 illustrates the registers and structural connections of the serial test interface 201 in more detail.

[0066] The Core 100 is equipped with one or more wrapper chains across all IOs to achieve full testability. Wrapper Boundary Register (WBR) 40 is the register through which test data pulses are applied via SDI as WSI.

[0067] Via SDI pins 1a and 2a (the SDI signal pin), the address register 214 is loaded with an address, and the instruction register 213 is loaded with a wrapper instruction. An ID code 215a can be shifted beyond SDO, for which purpose a control logic 209 is provided, which either enables the WSO output of the wrapper boundary register 40 for the SDO output pin 1b or enables the ID code 215a as read from register 215 for the SDO output pin—this under the control of the state machine 210 controlled by wrapper instructions.

[0068] Slave 201 (with Core 100) may have an m-bit, e.g., 16-bit chip ID (ID code 215a), which may contain information about the type and structure of Core 100. The length of this identification is longer than each of the following register lengths of counter 211, address register 214, and instruction register 213.

[0069] Bit transfer is not limited to 8-bit words. All examples are for illustrative purposes only. Other bit lengths of registers and words can also be used.

[0070] The device address 214a can be n bits, e.g. 4 bits to 7 bits long and is sent after the 1-bit FIN (Following Instruction), see Fig. 13 and Fig. 14.

[0071] The slave 201 has a 4-bit instruction register 213 for loading and storing wrapper instructions transmitted via port 1a, e.g., IEEE 1500 standard instructions.

[0072] The serial test interface 201 and its terminals 1a, 1b, 1c of the IC are intended to access one or more IEEE 1500 wrapper cell chains surrounding a Core 100 in a SoC 1.

[0073] The 201 serial test interface reduces the pin count while maintaining a high clock frequency. Each Core 100 is Fig. 4 equipped with its own slave.

[0074] The slim serial interface SSI has only three logical signals: SCLK serial clock SDI serial data SDO serial data.

[0075] The associated ports operate with a single master 10 off-chip 1 and one or more slave devices 201a, 201b, 201c on-chip. The master 10 selects the desired slave by sending a device address, which corresponds, for example, to the hard-coded STI device address 214a.

[0076] The slave(s) 201 do not have an external reset signal. Therefore, a power-on reset 20 (POR) is provided to enable initialization of the slave(s) and prevent damage to Core 100 (or to COREs 100a, 100b, and 100c).

[0077] The SSI protocol used is as follows, see: Fig. 3.

[0078] Master 10 (outside the layout or chip) issues a RESET / RUN sequence.

[0079] The master sends 8 bits: FIN and the 7-bit slave address, see Fig. 13, via the SDI connection into address register 214.

[0080] All slaves 201a, 201b, ... receive and compare the transmitted address as held by the address register 214 with their own device address 214a (fed from a source such as a register in the serial test interface 201 or hard-coded in a layout).

[0081] This slave 201a is selected if, in step 510, the transmitted address matches its device address 201a. For example, device 201a (having state machine 210a) has device address 214a. If the address fed into address register 214 via SDI input pin 1a matches address 214a, this serial test interface 201a is selected, and it receives the wrapper commands in its instruction register 213 and connects output test signals from the associated core 100a and its wrapper boundary register 40a (40 as labeled for core 100a with serial test interface 201a). The other serial test interface 201b would have 214b as its device address and the associated core 100b with a wrapper chain 40b. The same applies to the serial test interface 201c.

[0082] The leading FIN bit determines whether multiple transactions are implemented for the selected slave. If, for example, FIN=1, further instructions follow for the selected slave, see Fig. 16, Fig. 17.

[0083] If the address does not match in step 510 and FIN = 0, each unselected slave waits for the Reset / Run sequence and then for a new slave address in step 510 (RUN=1, FIN=0).

[0084] If the address does not match and FIN = 1, each unselected slave waits until the master 10 sends the WS_RESET instruction (WRSTN) from the master output port 10a via the SDI input port 1a.

[0085] The selected slave continues with READ 520 if RUN=1, FIN=1.

[0086] The WS instruction (e.g. 4 bits) follows a standard instruction such as WS_EXTEST, WS_ID or WS_PRELOAD.

[0087] Data bits DATA for the instruction INSTR [3:0] follow, e.g. shift data from wrapper IO (length IO) and shift stop sequence, if required for an instruction, see Fig. 13.

[0088] To end the transaction, Master 10 sends the RESET sequence. After the RESET / RUN sequence, a new transaction begins with if FIN = 0 ... a new slave address if FIN = 1 ... the 4-bit instruction

[0089] To end a transaction with FIN=1 and deselect the slave, the master sends the WS_RESET instruction to generate WRSTN (see Fig. 14), followed by the RESET sequence. After WS_RESET and the RESET / RUN state, the master sends eTM a new address to select another slave.

[0090] The connection of the multiple serial test interfaces (STI) at IC level of this IC 1* as in Fig. 4 shown.

[0091] Each Core 100a, 100b, and 100c has its own STI 201a, 201b, and 201c. Each STI (serial test interface) is directly controlled by Master 10. The master is located outside the chip or layout, e.g., as the test intelligence eTM.

[0092] The SDO data lines are tied together and fed back to the master 10. The SDO outputs 2b of the non-selected slaves on the chip in Fig. 4 are hi-Z and therefore inactive (tri-state output).

[0093] The Fig. 1 and Fig. 2 shows the serial test interface (STI) with these three logical signals and with a power-on reset 20 on chip 1. POR 20 is supplied to the serial test interface 201 and the WBR 40.

[0094] If multiple wrapper boundary register chains are implemented for the core, the WSO data lines 31 are switched via the logic 209 to the output 2b and 1b carrying the SDO signal.

[0095] The output values ​​change on the negative (falling or trailing) edge of SCLK.

[0096] The serial interface device 201 contains a 4-bit instruction register 213. The following WS instructions are used to access the Core 100 via the serial test interface STI... Instruction name Explanation WS_EXTEST used to apply data to all IP pins WS_ID is used to query the ID code WS_PRELOAD used to preload the chain WS_SHIFTUPD just PUSH and update ATE WS_RESET used to generate WRSTN (as internal signal) WS_BYPASS puts the wrapper into a bypass configuration

[0097] Some further instructions are explained in the table below. Instruction name Explanation WS_CAPTURE capture only WS_WCHRESET only wrapper chain reset for selected wrapper cells, used to generate WCH_RESET (as internal signal) WS_TACC used to measure the access time (testing the delay time)

[0098] Fig. 3 illustrates the exemplary states of the state machine 210. The slave 201a has this state machine 210a to - to process the various transactions between the external master 10 and the slave 201 from the slave side: -- Reading the address with the 1-bit FIN (e.g. 8 bits) to select a slave, -- Reading the wrapper instruction (e.g. 4 bits), -- Enable sending of the ID code in the Send_IDCode state -- Entering or skipping the READ-DATA, READ-SHIFT and READ-UPDATE states required to generate the WBR control signals. - to generate the WBR control signals 30 such as CaptureWR, ShiftWR, UpdateWR and WRSTN; - to generate additional WBR control signals 30, e.g. WCH_RESET.

[0099] State machine 210 contains seven states. State transitions are controlled by a clock edge of the SCLK clock (e.g., the negative edge of the clock). The power-on reset POR and the internal RESET signal return state machine 210 to the IDLE state. All transactions begin with the RUN state. The power-on reset POR resets all flip-flops (not shown).

[0100] The changes of state (or changes of states) are based on - a counter value - the currently active wrapper statement ("INSTR==" / "INSTR!=") - FIN=1 following instructions for the selected device (state: IDLE) - Device address = valid (or invalid) In state 510: READ_DEV_ADR - WBYPASS_SEL =1 Bypass path between SDI and SDO (state 520: READ_INSTRUCTION), e.g. for wrapper instruction (= WI) WS_RESET or WS_WCHRESET - STOP_SHIFT = 1 Shift operation was completed (state 540: READ_SHIFT)

[0101] Fig. Figure 8 is a diagram of the timing of a bit transmission.

[0102] The data at the SDI connector must be stable during the high phase of the SCLK clock. The low or high state of the data signal can only change when the clock signal is low. The bits are sent to the SDI connector 2a, starting with the MSB (most significant bit). According to the Fig.13 to 15, serial data SDI is transmitted in sequences of 8 bits (slave or device address including FIN), 4 bits (WS instruction), and with a variable word size (according to the wrapper instruction). Counter 211 counts each bit of the SDI input and increments or decrements its counter value. State machine 210 reads the counter value and changes states as shown in Fig. 3 after all bits have been received, such as 8 bits, 4 bits or 2 bits according to Fig. 3. The corresponding state changes are shown there, such as a transition from state 510 to state 520 upon receipt of the 8 bits, corresponding to 8 bits (of the SDI signal). This can be achieved by using the counter to determine when the required bits have passed through the SDI port for bit transmission. One of the counters has increased its value by 8, for example, or decreased by 8, both of which indicate that 8 bits are present ("Get 8 Bit").

[0103] Fig.Figure 9 illustrates the RESET / RUN state for the slave. The clock idle state is low. The RESET / RUN sequence and the STOP_SHIFT sequence are the only places where SDI may change while SCLK is high. The RESET signal for the slave is generated with the LOW-to-HIGH transition in the SDI signal while SCLK is high. The internal RESET signal initializes a portion of the slave.

[0104] The internal RESET signal terminates the actual transaction. The first HIGH-to-LOW transition in the SDI signal while SCLK is high after RESET starts a new data transfer. Starting a new data transfer is only possible after the RESET / RUN sequence. The RESET / RUN sequence has no effect on the wrapper chains. After the RESET / RUN sequence, master 10 sends a new address for another serial test interface (slave) or a new wrapper instruction for instruction register 213.

[0105] Fig.Figure 10 illustrates the generation of the internal WRSTN signal. The instruction shown there is WS_RESET contained in instruction register 213, and when read by state machine 210, it will provide the WRSTN signal. Additional clock and data inputs are shown in Fig. 10 shown.

[0106] All slaves 201 in Fig. 2 (a single slave 201 on the chip) or multiple slaves 201a, 201b and 201c in Fig. 4 do not have external RESET signals, but only a common power-on reset 20 on the chip. Therefore, an internal WRSTN signal is generated by the WS_RESET instruction, which is delivered via SDI pin 1a. This is actually one of the control signals of the IEEE 1500 standard. WRSTN is the active-low wrapper reset signal. It belongs only to its associated wrapper chain and does not leave the corresponding serial test interface, which controls the control signals 30 of this wrapper chain.

[0107] WRSTN active-low forces its corresponding slave into a locked state. If FIN = 1, only the WRSTN signal can terminate transactions for its selected slave. After WRSTN is active-low and following the RESET / RUN sequence, data transmission is started with a new device address.

[0108] WRSTN resets the instruction register 213 and puts the WBR 40 into its normal system mode (reset of the wrapper chain cells). If FIN = 1, the WS_RESET instruction is executed by all slaves located on the chip, for example, slaves 201a, 201b, and 201c in Fig. 4, is evaluated. This results in the evaluation of the WS_RESET instruction by all selected and unselected slaves on chip 1*. A slave is selected if its device address matches the value of address register 214. The other slaves on the chip are not selected.

[0109] One problem with shift operations is that the length of the wrapper chains is not fixed. The slave requires information to complete the shift operation of the wrapper chain cells. A shift stop is an improvement.

[0110] The master 10 sends a shift stop sequence to the slave to stop shifting data. One drawback may be that the shift stop depends on the value of the last SDI bit.

[0111] Fig. Figure 11 illustrates the STOP_SHIFT sequence when the last shift bit (SDI) is “HIGH”.

[0112] Fig. Figure 12 illustrates the STOP_SHIFT sequence when the last shift bit (SDI) is LOW.

[0113] Fig. Figure 13 illustrates a general transaction with sending data according to the WS instruction (INSTR).

[0114] A transaction begins with the RUN sequence. The 1-bit FIN and the 7-bit device address are followed by the 4-bit WS instruction. DATA is sent according to the WS instruction. - e.g. DATA for CaptureWR, ShiftWR and UpdateWR - and DATA for a special operation, e.g. DATA for reading or writing an NVM (non-volatile memory) like Core 100.

[0115] The size of the data to be transferred is not specified. A transaction ends with a reset (RES) state.

[0116] Fig. Figure 14 illustrates a special transaction for a non-data transfer function. Special transactions are non-data transfer functions. After the 4-bit INSTR, only 1 bit is required to enter the wrapper serial control. The reset sequence follows the 1-bit ESC. Only two special transactions are currently defined: - The first is used to generate WRSTN. - The second is used to generate WCH_RESET.

[0117] Fig. Figure 15 illustrates a "Send ID Code" transaction. The transaction begins with the RUN sequence. The 1-bit FIN and the 7-bit device address are followed by the 4-bit WS instruction. The 4-bit WS_INSTRUCTION is set to WS_ID.

[0118] The slave sends the 16-bit ID code 215a via control logic 209 and locks the ID code for SDO port 1b (via port 2b of slave 201). SDO output port 1b changes state on the falling edge of SCLK. The transaction ends with a reset state (RES). State 525 changes to IDLE state 500 after 16 bits have been sent, see Fig. 3 for Send_IDCode. As long as the sending process does not end, state 525 remains. Counter 211 is used to count the number of bits sent serially, e.g., 16 bits as identified.

[0119] Fig.Figure 16 illustrates an example with two transactions and FIN=0. In the example, FIN is set to zero. This means "no subsequent instructions" for the selected slave. A device address is sent after the end of the first transaction.

[0120] Fig. Figure 17 illustrates an example with multiple transactions and FIN=1. In this example, FIN is set to one. Therefore, further instructions follow for the selected slave. To deselect the slave, the WS_RESET instruction must be sent.

[0121] All bit lengths given above are just examples.

Claims

[1] Serially operable interface device on a chip (1), the interface device (201) for generating control signals for a wrapper boundary register (40, WBR) at chip level (1), wherein the wrapper control signals (30) correspond to a given standard for testing a core device (100), wherein the core device is also provided on the chip (1) and contains the WBR, wherein the serial interface device (201) includes: - a physical data input (2a) and a physical data output (2b), and no more than the input (SDI) for the and the output (SDO) of the serial interface device (201), which are coupled to a respective terminal (1a, 1b) on the chip (1) containing the interface device (201) and the core device (100) with the wrapper boundary register (40); and a physical clock input (2c) coupled to a third terminal (1c) on the chip (1) at chip level for feeding a clock signal (SCLK) to the serial interface device (201); wherein the serial interface device (201) further includes: - an address register (214) for holding a received address for comparison with a device address (214a); - an instruction register (213) for receiving and holding wrapper instructions supplied via the terminal (1a) supplying the data input (SDI) on the chip (1); - a control logic (209) comprising a state machine (210) for processing transactions from an external master (10) which provides a logical data input (SDI) to the physical data input port (1a), and the serial interface device (201) sends a logical data output (SDO) to the physical data output port (2b) and back for the external master (10) from the WBR (40) of the core device (100); - wherein the state machine (210) is configured to provide the wrapper control signals (30) of the given standard to the core device (100) containing the wrapper boundary register (40; WBR); - to read an address held by the address register (214) and to compare it with the device address (214a); - to read a currently active wrapper instruction held by the instruction register (213); - to send (logical) output test (SDO) data as taken from the wrapper boundary register (40, WBR). [2] Apparatus according to any one of the preceding claims, further comprising a counter (211) for controlling a data transfer size in certain states (READ_DEV_ADR, READ_INSTRUCTION, SEND_IDCODE, READ_DATA and READ_UPDATE) of the state machine (210), the counter receiving the clock signal (SCLK) fed to the serial interface device. [3] Device according to one of the preceding claims, wherein the state machine (210) processes transactions between the external master (10) and itself, wherein the state machine (210) is capable of generating an additional wrapper boundary register control signal (WT), e.g. WCH_RESET, to and for the wrapper boundary register (WBR, 40) of the core device (100). [4] Apparatus according to any one of the preceding claims, wherein the state machine (210) is configured and capable of generating all wrapper boundary register control signals (30; CW, SW, UW, WN) of the given standard, preferably CaptureWR, ShiftWR, UpdateWR and WRSTN of IEEE Standard 1500, wherein the SelectWIR signal of IEEE Standard 1500 is not a WBR control signal. [5] Apparatus according to any one of the preceding claims 1 to 3, wherein the state machine (210) generates at least some wrapper boundary register control signals (30) containing one or more of the control signals for the IEEE 1500 wrapper boundary register (WBR). [6] Device according to one of the preceding claims, wherein an output signal (WSO) of the wrapper boundary register (40; WBR) is fed into the serial interface device (201) or directly into the terminal (2b) of the physical data output (SDO). [7] Device according to one of the preceding claims, wherein the logical data input signal (SDI) is fed into the WBR (40) at the physical data input connection (1a), preferably directly, as an input signal (WSI). [8] Device according to one of the preceding claims, wherein the clock signal (SCLK) from the third terminal (1c) is also fed, preferably directly, as a clock signal (WRCK) into the WBR (40). [9] Device according to one of the preceding claims, wherein the clock signal (SCLK) is fed from the third terminal (1c) into the serial interface device (201), preferably thus into the control logic (209) containing the state machine (210), the address register (214) and the instruction register (213). [10] Device according to one of the preceding claims, wherein the logical data input signal (SDI) at the physical data input terminal (1a) is fed into the address register (214), the instruction register (213) and the control logic (209) containing the state machine (210), but not into the state machine (210). [11] Device according to one of the preceding claims, wherein the coupling is an electrically conductive connection. [12] Device according to one of the preceding claims, further comprising an identification register (215) containing an identification code (215a) of the core device (100). [13] The device of any preceding claim, wherein the serial interface device (201) further includes an additional device address source that provides a device address (214a) of a corresponding core device (100a) associated with the interface device when multiple cores (100a, 100b) are present on the chip (1) and each core has its own dedicated serial interface device (201a, 201b). [14] Device according to one of the preceding claims, further comprising a counter (211) which is supplied with the clock signal (SCLK) via the third terminal (1c) in order to control the state changes (510, 520, 525, 530, 550) of the state machine (210). [15] Serially operable interface device on a chip (1), the interface device (201) for generating control signals for a wrapper boundary register (40; WBR) at chip (1, 1*) level, wherein the wrapper control signals (30) correspond to a given standard for testing a core device (100), wherein the core device is also provided on the chip (1) and contains the WBR (40), wherein the chip (1; 1*) contains: - a physical data input (1a) for test purposes and a physical data output (1b) for test purposes and no more than one input and one output terminal of the serial interface device (201) coupled to the terminals (1a, 1b) on the chip (1) containing the interface device (201) and the core device (100) with the WBR; - and a physical clock input (1c) for test purposes, which is coupled to a third terminal (1c) on the chip (1; 1*) at chip level for feeding a clock signal (SCLK) into the serial interface device (201); - wherein the on-chip serial interface device (201) further includes an instruction register (213) for receiving and holding wrapper instructions supplied via the physical data input port (1a); wherein the state machine (210) is configured to - read a currently active wrapper instruction as held by the instruction register (213); - to generate and provide on-chip wrapper control signals (30) of the given standard for the core device (100) containing the wrapper boundary register (40; WBR) according to the wrapper instruction read from the instruction register (213). [16] Device according to one of the preceding claims, wherein the serial interface device (201) further comprises an address register (214) for receiving and holding an address fed via the physical data input port (1a) for comparison with an individual device address (214a) of this serial interface device (201a) and a corresponding core (100a) when a plurality of serial interface devices (201a, 201b, 201c), each associated with a corresponding core (100a, 100b, 100c), are present on the chip (1*). [17] The apparatus of any preceding claim, wherein the control logic (209) has access to an address register (214) configured to hold a received address, the control logic (209) being configured to read the address as held by the address register (214). [18] Device according to one of the preceding claims, further comprising a counter (211) which is supplied with the clock signal (SCLK) via the third terminal (1c) in order to control at least some state changes (510, 520, 525, 530, 550) of the state machine (210). [19] Apparatus according to the preceding claim, wherein at least some state changes of the state machine (210) depend on at least a counter value of the counter (211) and a wrapper instruction as read from the instruction register (213), the instruction register (213) having received the wrapper instruction via the physical data input port (1a). [20] Apparatus according to any preceding claim, further comprising an identification register (215) for holding an ID code (215a) identifying the core device (100). [21] Device according to the preceding claim, wherein the ID code of the identification register (215) identifying the core device (100) is sent to the single output terminal (1b) to the external master (10) upon a corresponding wrapper instruction as read from the instruction register (213) by controlling the state machine (210) and a control logic (209) in the serial test interface (201). [22] Device according to the preceding claim, wherein the control logic (209) in the serial test interface (201) acts as a gateway to the single output port (1b) to feed either - but not both simultaneously - the ID code (215a) of the identification register (215) or the logical output test signal (WSO) coming back from the WBR (40) of the core device (100) into the external master (10) by controlling the control logic (209) in the case of a corresponding wrapper instruction as read from the instruction register (213). [23] Device according to one of the preceding claims, further comprising a power-on detector (20) for feeding a power-on reset signal into the serial test interface (201) and the wrapper boundary register (40) of the core (100) for common initialization. [24] Device according to one of the preceding claims, wherein the clock signal (SCLK) fed via the third terminal (1c) is fed into the WBR (40) and the serial test interface (201). [25] Test procedure for testing wrapped cores (100a, 100b, 100c) in a system-on-chip (SoC;1*), where - each core of the wrapped cores (100a, 100b, 100c) contains an associated serial interface device (201a, 201b, 201c) with a structure; - each serial interface device has a unique device address (214a, 214b, 214c) which are not the same even though the structures of all serial interface devices (201a, 201b, 201c) are the same; - wherein each serial interface device (201a, 201b, 201c) has the structure according to one of claims 1 to 23. [26] The method of claim 25, wherein each serial interface device (201a, 201b, 201c) further includes an address register (214) receiving and holding an address input via a test input terminal (1a), each serial interface device comparing the input address with an individual device address such as the unique device address (214a) of each serial interface device (201a) of the associated wrapped core (100a) present on the chip (1, 1*), and selecting the serial interface device (201a, 201b, 201c) whose device address matches the input address held by the address register (214). [27] The method of claim 25, wherein each serial interface device (201a, 201b, 201c) has the structure of claim 24. [28] A method for skipping a state of a state machine (210) in a selected serial interface device (201), the state machine (210) having a state (510) of reading a device address (READ_DEV_ADR), the method comprising: - the serial interface device (201) receives a device address with a first bit (FIN) as the FIN bit; - a value of the received FIN bit as recorded in a corresponding FIN register determines whether multiple transactions are implemented for the selected interface device (201), - if the FIN register contains ONE (= logical 1), further instructions follow for the selected interface device (201), and - in a next transaction, reading the or a new device address is skipped. [29] The method of claim 28, wherein each serial interface device (201) has a structure according to any one of claims 1 to 24. [30] A method for generating IEEE 1500 Wrapper Boundary Register (WBR) control signals (30) by a multi-state state machine (210), the state machine being part of a functional slave (201) in a system-on-chip (SoC) configuration, the method comprising the following steps: - generating a WBR control signal CaptureWR by the state machine (210) in a READ_DATA state resulting from a currently active wrapper instruction in an instruction register (213) and a count content of a counter (211) of the slave (201); - generating a WBR control signal ShiftWR by the state machine (210) in a READ_SHIFT state based on the currently active wrapper instruction in the instruction register (213) and the value of a STOP_SHIFT FLAG; - generating a WBR control signal UpdateWR by the state machine (210) in a READ_UPDATE state on the basis of the currently active wrapper instruction in the instruction register (213) and a count content of the counter register (211); - generating an active-low wrapper reset signal WRSTN by the state machine (210) upon termination of a READ_INSTRUCTION state in an IDLE state whenever the instruction register (213) contains a WS_RESET instruction. [31] A method for generating additional wrapper boundary register (WBR) control signals (30) by a state machine (210) on a chip (1,1*), the method comprising the following steps: - generating at least one additional WBR control signal by the state machine (210) upon termination of a READ_INSTRUCTION state in an IDLE state whenever the instruction register (213) contains an additionally defined wrapper instruction with a non-data transfer function; - Defining an additional signal (WCH_RESET), and thereby the additional signal resets one or more access signals in the wrapper boundary register (40). [32] Layout for a serial test interface, comprising a layout for an instruction register (213) for receiving and holding wrapper instructions delivered via a representation of a physical data input port (2a) and a layout of a state machine (210) for processing transactions delivered thereto, the state machine being "laid out" to read a wrapper instruction from the instruction register (213) and to generate and provide wrapper control signals (30) of the given standard for a core device (100) having the wrapper boundary register (40) according to the wrapper instruction read from the instruction register; and - the representation of the individual input terminal (2a) is intended to feed in an input test signal (SDI) coupled to the wrapper boundary register (40) as a logical input test signal (WSI); - a representation of a single output terminal (2b) is provided to return an output test signal (SDO) coupled (209) to the representation of the output terminal (2b) from an output (WSO) of the wrapper boundary register (40) of the core device (100). [33] Layout according to the preceding claim 32, wherein a layout representation of the third terminal (2c) is provided to feed a clock signal (SCLK, WRCK) for test purposes into the layout of the serial interface device (201) and the wrapper boundary register (40) of the core device (100), and / or comprising a layout of a counter (211) which is supplied with the clock signal (SCLK) via the representation of the third terminal (2c) in order to influence at least some state changes (510, ..., 550) of the layout of the state machine (210), preferably in conjunction with a representation of the data input terminal (2a) supplied, held by the instruction register (213) and read by the state machine, currently active wrapper statement; and / or wherein the layout of the serial interface device (201) further includes a layout of an address register (214) for receiving and holding an address input via the layout representation of the individual input port (2a) for comparison with an individual device address (214a) of that serial interface device (201a) and a corresponding core (100a) when multiple serial interface devices (201a, 201b, 201c), each associated with a corresponding core (100a, 100b, 100c), are present in the layout. [34] A serial test interface comprising an instruction register (213) for receiving and holding wrapper instructions supplied via a physical data input port (1a) and a state machine (210) for processing transactions supplied by an external master (10), the state machine being configured to read wrapper instructions as held by the instruction register (213) and to generate and provide on-chip wrapper control signals (30) of a given standard for a core device (100) having a wrapper boundary register (40) according to wrapper instructions read from the instruction register; and comprising: - the physical data input terminal (1a), which is a single input terminal provided for feeding an input test signal (SDI) coupled to the wrapper boundary register (40) as a logical on-chip input test signal (WSI); - a single output terminal (1b) which is intended to return an output test signal (SDO) coupled (209) to the output terminal (1b) from an output (WSO) of the wrapper boundary register (40) of the core device (100). [35] Serial test interface according to preceding claim 34, wherein a third terminal (1c) on the chip (1; 1*) is provided to feed a clock signal (SCLK, WRCK) for test purposes into the serial interface device (201) and the wrapper boundary register (40) of the core device (100). [36] Serial test interface according to one of the preceding claims 34 or 35, further comprising a counter (211) which is supplied with the clock signal (SCLK) via the third terminal (1c) in order to influence at least some state changes between states (510 to 550) of the state machine (210), preferably in connection with a currently active wrapper instruction supplied via the physical data input terminal (1a), held by the instruction register (213) and read by the state machine. [37] Serial test interface according to one of the preceding claims 34 to 36, wherein the serial interface device (201) further comprises an address register (214) for receiving and holding an address fed via the single input terminal (1a) for comparison with an individual device address (214a) of this serial interface device (201a) and a corresponding core (100a) when a plurality of serial interface devices (201a, 201b, 201c), each associated with a corresponding core (100a, 100b, 100c), are present on the chip (1, 1*). [38] A method for generating a proper wrapper boundary register (WBR) control signal CaptureWR by a state machine (210) of a slave device (201) immediately after the WBR control signal UpdateWR, the method comprising: - the generation of the WBR control signal CaptureWR by the state machine (210) in a READ_UPDATE state on the basis of a count content of a counter register (211) of the slave device (201) whenever an instruction register (213) contains an instruction requiring "testing the delay time". [39] The method of claim 38, wherein control logic (209) is provided including the state machine (210), the counter register (211), the instruction register (213), and an address register (214) to provide a serial interface device (201) acting as an on-board slave device for an off-board master (10). [40] A method according to claim 38 or 39, wherein the prescribed control signal complies with a given standard, preferably IEEE Standard 1500. [41] Serial test interface for a core device (100) with a wrapper boundary register (40) and an output (WSO) of the wrapper boundary register (40), the serial test interface comprising: - an instruction register (213) for receiving and holding wrapper instructions supplied via a physical data input port (1a); -- wherein the physical data input terminal is a single input terminal (1a) which is intended to feed in an input test signal (SDI) so that it is coupled to the wrapper boundary register (40) as a logical on-chip input test signal (WSI); - and a state machine (210) for processing transactions supplied by an external master (10); -- wherein the state machine (210) is configured to read wrapper instructions as captured by the instruction register (213) and to generate on-chip wrapper control signals (30) of a given standard for the wrapper boundary register (40); -- wherein the on-chip wrapper control signals are provided according to wrapper instructions read from the instruction register (213); - wherein a single output terminal (1b) is provided to return a coupled (209) output test signal (SDO) from the output (WSO) of the wrapper boundary register (40) to the single output terminal (1b). [42] Test interface according to the preceding interface claim 41, wherein one of the wrapper instructions as held by the instruction register (213) causes at least two different control signals (30) generated by the state machine (210) after the wrapper instruction has been read by the state machine. [43] Test interface according to one of the preceding interface claims 41 or 42, wherein the wrapper instruction causes three different wrapper boundary register control signals (30) generated by the state machine (210). [44] Test interface according to one of the preceding interface claims 41 to 43, wherein a further one of the wrapper instructions (WS_ID) as held by the instruction register (213) causes a transmission of an ID code (215a) identifying the core device (100) from an identification register (215) after the further wrapper instruction (WS_ID) has been read by the state machine (210).

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