HIGHLY EFFICIENT LEDS AND METHODS FOR THEIR MANUFACTURE

Abstract

A light-emitting diode (LED) chip (50) comprising:an active LED structure (52) comprising an active region between two oppositely doped layers (54, 56), the active region emitting light in response to an electrical signal applied to the oppositely doped layer (54, 56);a first reflective layer (60) adjacent to one of the oppositely doped layers (54, 56);a second reflective layer (62) on the first reflective layer, the second reflective layer (62) reflecting light not reflected by the first reflective layer, the second reflective layer extending beyond an edge of the active LED structure (52) into a connection contact region (80) formed on the LED chip (50) to retain a contact (82) in the connection region (80) on the second reflective layer (62) that extends through the first reflective layer (60) and is in contact with the second reflective layer (62);

Description

BACKGROUND OF THE INVENTIONField of the invention

[0001] This invention relates to light-emitting diodes and, more particularly, to light-emitting diodes having high reflectivity mirrors. Description of the state of the art

[0002] The documents US 2009 / 0 283 787 A1, US 2012 / 0 074 441 A1 and DE 10 2012 217 533 A1 show LEDs according to the state of the art.

[0003] Light-emitting diodes (LEDs) are solid-state devices that convert electrical energy into light and generally comprise one or more active layers of semiconductor material sandwiched between opposing n-type and p-type doped layers. When a bias voltage is applied to the doped layers, holes and electrons are injected into the active layer, where they recombine to produce light. Light is emitted from the active layer and from all surfaces of the LED.

[0004] For typical LEDs, it is desirable to operate at the highest possible light emission efficiency, and one way to measure emission efficiency is by measuring emission intensity relative to input power, or lumens per watt. One way to maximize emission efficiency is to maximize the harvesting of light emitted from the active region or active structure of the LED. For conventional LEDs with a single output surface, the external quantum efficiency can be limited by a number of factors, such as the total internal reflection (TIR) of light from the emitting region of the LED. TIR can be caused by the large difference in refractive index between the LED semiconductor and the surrounding environment.Some LEDs have relatively low light extraction efficiency due to the high refractive index of the substrate compared to the refractive index of the surrounding material, such as epoxy resin. This difference results in a small exit cone through which light rays from the active region can escape from the substrate into the epoxy and ultimately from the LED device. Light that does not escape can be absorbed by the semiconductor material or by surfaces that reflect the light.

[0005] Various approaches have been developed to reduce TIR and improve overall light output, with surface texturing being one of the more popular. Surface texturing increases the likelihood of light escaping by providing a varying surface that gives photons multiple opportunities to find an exit cone. For light that does not find an exit cone, TIR can still occur, and the light will reflect off the textured surface at different angles until it finds one. The benefits of surface texturing have been discussed in several articles. [See Windisch et al., Impact of Texture-Enhanced Transmission on High-Efficiency Surface Textured Light Emitting Diodes, Appl. Phys. Lett., Vol. 79, No. 15, October 2001, pages 2316-2317; Schnitzer et al.30% External Quantum Efficiency From Surface Textured, Thin Film Light Emitting Diodes, Appl. Phys. Lett., Vol. 64, No. 16, October 1993, pages 2174-2176; Windisch et al. Light Extraction Mechanisms in High-Efficiency Surface Textured Light Emitting Diodes, IEEE Journal on Selected Topics in Quantum Electronics, Vol. 8, No. 2, March / April 2002, pages 248-255; Streubel et al. High Brightness AlGaNInP Light Emitting Diodes, IEEE Journal on Selected Topics in Quantum Electronics, Vol. 8, No. March / April 2002]. US Patent No. 6,657,236, also granted to Cree Inc., discloses structures formed on the semiconductor layers to improve the light output of LEDs.

[0006] Another way to increase the efficiency of the light output is to provide reflective surfaces that reflect light so that it contributes to the usable emission from the LED chip or LED unit. In a typical LED unit 10, as shown inFig. 1, a single LED chip 12 is mounted on a reflective can 13 using a solder bond or conductive epoxy. One or more wire bonds 11 may connect the ohmic contacts of the LED chip 12 to leads 15A and / or 15B, which may be attached to or integral with the reflective can 13. The reflective can may be filled with an encapsulant 16, which may include a wavelength conversion material, such as a phosphor. At least a portion of the light emitted by the LED at a first wavelength may be absorbed by the phosphor, which may in response emit light at a second wavelength. The entire assembly is then encapsulated in a transparent protective resin 14, which may be shaped like a lens to collimate the light emitted by the LED chip 12.Although the reflective cup 13 can direct light upward, optical losses can occur when the light is reflected. Some light may be absorbed by the reflective cup because reflector surfaces in practice have less than 100% reflectivity. Some metals can have less than 95% reflectivity in the relevant wavelength range.

[0007] Fig. 2 shows another LED package in which one or more LED chips 22 may be mounted on a carrier, such as a printed circuit board carrier, a substrate, or a submount 23. A metal reflector 24 mounted on the submount 23 surrounds the LED chip(s) 22 and reflects light emitted by the LED chips 22 away from the package 20. The reflector 24 also provides mechanical protection to the LED chips 22. One or more wire bonds 11 are made between ohmic contacts on the LED chips 22 and electrical traces 25A, 25B on the submount 23. The mounted LED chips 22 are then covered with an encapsulant 26, which may provide environmental and mechanical protection to the chips and also serves as a lens. The metal reflector 24 is typically attached to the carrier by a solder or epoxy bond.The metal reflector 24 can also experience optical losses when the light is reflected, as it also has less than 100% reflectivity.

[0008] The Fig. 1 and Fig. The reflectors shown in Figure 2 are arranged to reflect light escaping from the LED. LEDs have also been developed with internal reflective surfaces or layers that reflect light within the LEDs. Fig. Figure 3 shows a schematic representation of an LED chip 30 with an LED 32 mounted by means of a metal bond layer 36 on a submount 34. The LED further includes a p-contact / reflector 38 between the LED 32 and the metal bond layer 36, with the reflector 38 typically comprising a metal such as silver (Ag). This arrangement is used in commercially available LEDs, such as those from Cree® Inc., available as part of the EZBright™ family of LEDs. The reflector 38 is integral with the LED chip 30 and can reflect light emitted from the active area of the LED chip toward the submount back toward the primary emitting surface of the LED. The reflector also reflects TIR light back toward the primary emitting surface of the LED. Like the metal reflectors mentioned above, the reflector 38 reflects less than 100% of the light, and in some cases less than 95%.The reflectivity of a metal film on a semiconductor layer can be calculated from the optical constants of the materials using thin film design software such as TFCalc™ from Software Spectra, Inc. (www.sspectra.com).

[0009] Additional LED chips with internal reflectors have also been developed, with some of these LED chips also incorporating other structures to allow the active epitaxial structure to be touched. Some of these features allow a signal to be applied to the active structure of the LED chip through other layers. These structures can include various combinations of conductive components (e.g., layers, contacts, and / or vias) and insulating features (e.g., dielectric and / or passivation layers). These features can be incorporated into LED chips with both vertical and lateral geometries. The structures can be relatively complex and require complex manufacturing processes, with some of these structures requiring nine or more manufacturing steps to achieve the desired configuration. SUMMARY OF THE INVENTION

[0010] The present invention relates to simplified chip architectures or chip configurations that require simpler manufacturing processes with fewer steps. The LED structure can have fewer layers than conventional LED chips, with the layers arranged in various ways for efficient manufacturing and operation.

[0011] An embodiment of an LED chip according to the present invention comprises an active LED structure comprising an active region between two oppositely doped layers, wherein the active region emits light in response to an electrical signal applied to the oppositely doped layer. A first reflective layer is included adjacent to one of the oppositely doped layers. A second reflective layer is included on the first reflective layer, wherein the second reflective layer reflects light not reflected by the first reflective layer, wherein the second reflective layer extends beyond the edge of the active LED structure.

[0012] Another embodiment of an LED chip according to the present invention comprises an active LED structure having an active region between two oppositely doped layers, the active region emitting light in response to an electrical signal applied to the oppositely doped layer. A dielectric reflective layer is included at one of the oppositely doped layers and extends beyond the edge of the active region. A reflective metal layer is also included at the first dielectric reflective layer.

[0013] One embodiment of a method for forming LED chips comprises depositing epitaxial layers with an active structure onto a wafer. The method also comprises etching different portions of the active structure in a single etching step, wherein the different portions can be etched at different rates and wherein at least one of the portions is self-limiting with respect to the etching.

[0014] Another embodiment of a method for forming LED chips comprises forming an active structure of epitaxial layers and forming a plurality of reflective layers on the active structure. The method further comprises performing a single etching step to form a self-aligned via through the reflective layers to the active structure.

[0015] Yet another embodiment of an LED chip according to the present invention comprises an active LED structure including an active region between two oppositely doped layers. A dielectric reflective layer is sandwiched adjacent to one of the oppositely doped layers. A reflective metal layer is disposed on the dielectric reflective layer, with the dielectric and reflective metal layers extending beyond the edge of the active region.

[0016] These and other aspects and advantages of the invention will become more apparent from the following detailed description and the accompanying drawings, which illustrate by way of example the features of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a sectional view of an embodiment of a prior art LED lamp; Fig. 2 is a sectional view of another embodiment of a prior art LED lamp; Fig. 3 is a sectional view of another embodiment of a prior art LED chip; Fig. 4 is a sectional view of an embodiment of an LED chip according to the present invention; Fig. 5 is a plan view of an embodiment of an LED chip according to the present invention; Fig. 6 is a flowchart illustrating steps in an LED chip manufacturing method according to the present invention; Fig. 7 is a sectional view of another embodiment of an LED chip according to the present invention; Fig. 8 is a flowchart showing steps in another LED chip manufacturing process according to the present invention; Fig. 9 is a sectional view of another embodiment of an LED chip according to the present invention; Fig. 10 is a sectional view of layers in an LED chip according to the present invention; Fig. 11 is a sectional view of other layers in an LED chip according to the present invention; Fig. 12 is a sectional view of another LED chip according to the present invention; and Fig. 13 is a sectional view of yet another embodiment of an LED chip according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0017] The present invention relates to simplified LED chip structures / configurations that can be manufactured using fewer steps while simultaneously providing LED chips with efficient light emission. The present invention relates to LED chips with internal or integrally reflective surfaces / layers arranged to increase the emission efficiency of the emitters. The present invention can be used as a reflector in combination with one or more contacts or as a reflector separate from the contacts.

[0018] The LED chips according to the present invention may comprise an active LED structure. A dielectric reflective layer is enclosed adjacent to one of the oppositely doped layers. A reflective metal layer is disposed on top of the reflective dielectric layer, with the dielectric layer and the reflective metal layer extending beyond the edge of the active region. By increasing the dielectric layer, the LED chips can emit light with greater efficiency by reflecting more LED light to direct it in the desired direction. By increasing the reflective metal layer beyond the edge of the active region, it can serve as a current distribution layer and barrier, as well as reflecting LED light to direct it in the desired direction.The LED chips may also include self-aligning and self-limiting features that simplify etching processes during manufacturing.

[0019] The dielectric reflective layer may comprise a material with a different refractive index (IR) than the active LED structure. In most embodiments, the dielectric reflective layer may comprise a layer with an IR that is inherently lower at or near its interface with the active LED structure. Some embodiments of LED chips according to the present invention may also comprise a second reflective layer, a metal layer, or a mirror stack, which may be used on top of and in combination with the dielectric reflective layer, so that light that passes through the dielectric reflective layer (and does not experience TIR, for example) may be reflected by the second reflective layer.

[0020] These internal or integral reflective layers can reduce optical emission losses that can result from light being emitted in an undesirable direction where it can be absorbed. Light emitted from the active LED structure of the emitter in a direction away from useful light emission, such as toward the substrate, submount, or metal reflector, can be reflected by the first reflective layer. The reflective surfaces can be positioned to reflect this light so that it is emitted from the LED chip in a desired direction.

[0021] The dielectric reflective layer can comprise numerous different materials, with some embodiments comprising a dielectric material such as SiO2. It is understood that many other materials with higher or lower refractive indices can be used, with preferred materials having an IR up to about 50% lower than the material of the active structure of the LED. In other embodiments, the IR of the reflective dielectric layer can be up to about 40% lower than that of the active structure material, while in other embodiments, it can be up to about 30% lower.

[0022] Many conventional LEDs rely primarily on a metal reflector layer, which can be made of various materials, such as Ag or Au. As described above, losses can occur with each reflection by metal reflectors, and these losses can be particularly significant for light that passes through the LED and is reflected multiple times. There are no optical losses for light reflected by TIR, so if more light is reflected by TIR instead of by a metal material, the emission efficiency of the LED can be increased.

[0023] Various embodiments of emitters according to the present invention may also utilize other structures, layers, or features that enable efficient and reliable operation of the LED. In some embodiments, a current distribution layer may be included adjacent to the reflective layer to enable current distribution into the one or more layers of the active LED structures. In other embodiments, materials may be included to enable reliable adhesion between different layers, for example, between the lower IR layer and the reflective metal layer. Various embodiments of the invention also provide conductive via or pathway arrangements that provide conductive paths through insulating layers, such as the reflective / dielectric layer.Some of these components allow an electrical signal to pass through the dielectric reflective layer along the vias, allowing the dielectric material layer to be used as an internal layer.

[0024] Conventional LED chips may have relatively complex structures that enable these internal reflector arrangements and, at the same time, allow the active structure to be contacted with various contact and via arrangements. These complex structures can also result in relatively complex manufacturing processes. The LEDs according to the present invention comprise simplified LED structures that enable simplified manufacturing processes. As described in more detail below, some embodiments may comprise a dielectric reflective layer and a single layer that can serve as a mirror / barrier / current distribution layer. The LED structure may also comprise a thin contact layer in contact with the p-side of the active structure (for example, GaN). The thin contact layer may comprise numerous materials, such as ITO, and have a thickness of less than 1000 Å.

[0025] In some embodiments, the LED structure can be further simplified by having a plurality of front-side layers that are self-aligned with the mesa edges of the active area (all etched in one etch step). This results in fewer etch steps for forming features such as vias. Fabrication of the LED structure can be further simplified by forming the back-side mesas (or paths) and light extraction features in one etch step, as described below. This is particularly useful for structures that require different etch times for the mesas and the light extraction features. In some embodiments, a feature requiring less etch time can be self-limiting to free up additional etch time for the other features.

[0026] In some embodiments, the aforementioned dielectric layer can comprise a variety of materials, with some embodiments including SiO2. Hybrid dielectric mirror LED structures consisting of a SiO2 layer with a single mirror / barrier / current distribution layer and a thin ITO p-contact (<1000A) can be self-aligned with the active area mesas. The SiO2 layer can serve as both a reflective element and an interconnect passivation layer.

[0027] In some embodiments, the external p-type contact can then be formed on the mirror stack by etching through the layers to the mirror stack. In these embodiments, extending the mirror layer beyond the mesa for the purpose of p-type contact, instead of the light-absorbing barrier layer used in conventional structures, can reduce light absorption.

[0028] The present invention is described herein with reference to particular embodiments, but it should be understood that it may be embodied in many different ways and should not be construed as limited to the embodiments set forth herein. In particular, the dielectric reflective layer may comprise many different layers of material and have many different thicknesses besides those described herein. The dielectric layer is described herein as a layer of one material, such as a particular dielectric, but it should be understood that it may comprise many different materials and, in some embodiments, may comprise more than one layer. The dielectric layer may also be located in many different locations on various LED chips besides those described herein, and it may also be employed on devices other than solid-state emitters.Furthermore, the first reflective layer can be provided with or without conductive structures to allow electrical signals to pass through. It is understood that LED chips according to the present invention can also utilize single-layer dielectric stacks in combination with other reflectors, such as reflective metal layers or DBR layers. The first reflective layer is arranged to maximize the amount of light reflected by the TIR while maintaining a simple, efficient, and cost-effective reflection system.

[0029] It should also be understood that when an element, such as a layer, region, or substrate, is referred to as being "on," "adjacent," or "near" another element, it may be directly on top of the other element, or intervening elements may also be present. Further, relational terms such as "inner," "outer," "upper," "over," "lower," and "beneath," and similar terms may be used herein to describe a relationship of a layer or other region. It should be understood that these terms are intended to encompass various orientations of the device in addition to the orientation illustrated in the figures.

[0030] Although the terms "first," "second," etc., may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections are not to be understood as limited by these terms. These terms are used only to distinguish one element, component, region, layer, or section from another region of a layer or section. Thus, a first element, component, region, layer, or section discussed below could also be referred to as a second element, component, region, layer, or section without departing from the teachings of the present invention.

[0031] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic representations of embodiments of the invention. Therefore, the actual thickness of the layers may vary, and deviations from the shapes of the illustrations, for example, due to manufacturing techniques and / or tolerances, are to be expected. Embodiments of the invention are not to be understood as limited to the particular shapes of the regions illustrated herein, but are intended to include variations in the shapes resulting, for example, from the nature of the manufacturing. A region illustrated or described as square or rectangular typically also has rounded or curved features due to normal manufacturing tolerances.Therefore, the regions shown in the figures are schematic in nature and their shapes are not intended to represent the exact shape of a region of a device, nor are they intended to limit the scope of the invention.

[0032] The present invention is described herein with reference to light-emitting diodes (LEDs) or LED chips, but it is understood that it is equally applicable to other solid-state emitters. It is further understood that the present invention may be used in many different LED chips besides those described herein. The components may have different shapes and sizes besides those illustrated herein, and a different number of LEDs may be included.

[0033] The Fig. 4 and Fig. 5 show an embodiment of an LED chip 50 according to the present invention arranged with a simplified structure that enables simplified manufacturing. Although the present invention is described with reference to the fabrication of a single LED chip, it should be understood that the invention can also be applied to the fabrication of wafer-level LEDs, the fabrication of groups of LEDs, or the production of packaged LED chips. The wafer or group of LEDs can then be divided into individual LED chips using known singulation or dicing techniques. The present invention can also be used in other LEDs with different geometries, such as lateral geometry or vertical geometry. The present invention can also be used in LEDs suitable for flip-chip mounting, as well as those configured for non-flip-chip mounting.The various embodiments of the present invention are particularly applicable to production devices that have many of the same features as the LED chips from Cree, Inc. under their product family designations EZ, WZ and / or DA.

[0034] The LED chip 50 may include an active LED region or structure 52 upon which many different semiconductor layers may be arranged in a variety of ways. The fabrication and operation of LEDs and their active structure are well known in the art and are only briefly described herein. The layers of the active structure 52 may be fabricated using known methods, one suitable method being MOCVD. The LED chip 50 includes an active structure 52 having a p-type layer 54, an n-type layer 56, and an active region between the two. It should be understood that additional layers and elements may also be included in the active structure 52, including but not limited to buffer, nucleation, contact, and current distribution layers, as well as light extraction layers and elements.The active layer can comprise a single quantum well (SQW), a multiple quantum well (MQW), a double heterostructure or supercrystal lattice structures.

[0035] The active structure 52 can be fabricated from various material systems, with preferred material systems being those based on Group III nitrides. Group III nitrides are those semiconductor compounds formed between nitrogen and the elements in Group III of the periodic table, typically aluminum (Al), gallium (Ga), and indium (In). The term also refers to ternary and quaternary compounds, such as aluminum gallium nitride (AlGaN) and aluminum indium gallium nitride (AlInGaN). In one embodiment, the n- and p-type layers are made of gallium nitride (GaN), and the active layer comprises InGaN. In alternative embodiments, the n- and p-type layers may be made of AlGaN, aluminum gallium arsenide (AlGaAs), or aluminum gallium indium arsenide phosphide (AlGaInAsP), and related compounds.

[0036] The active structure 52 can be formed on a growth substrate (not shown), and the growth substrate can be made of many materials, such as sapphire, silicon carbide, aluminum nitride (AlN), GaN. A suitable substrate is a 4H polytype of silicon carbide, although other silicon carbide polytypes can also be used, including 3C, 6H, and 15R polytypes. Silicon carbide has certain advantages, such as a crystal lattice structure that matches Group III nitrides better than sapphire and results in higher-quality Group III nitride layers. Silicon carbide also has very high thermal conductivity, so the overall output power of Group III nitride-on-silicon carbide devices is not limited by heat loss from the substrate (as may be the case with some devices formed on sapphire). SiC substrates are available from Cree Research, Inc., of Durham, North Carolina, and methods for their fabrication are set forth in the scientific literature, as well as in U.S. Patent Nos. 34,861; 4,946,547; and 5,200,022. In the embodiment shown, the growth substrate has been removed, but in other embodiments, all or part of the substrate may remain, with some of these embodiments having textured sections to improve light output.

[0037] Different embodiments of the active structure can emit different wavelengths of light, depending on the composition of the active layer and the n- and p-type layers. In some embodiments, the active structure emits blue light in the wavelength range of approximately 450 to 460 nm. The LED chip 50 can also be covered with one or more conversion materials, such as phosphors, so that at least a portion of the light from the LED passes through the one or more phosphors and is converted into one or more different wavelengths of light. In one embodiment, the LED chip emits a white light combination of light from the active structure of the LED and light from the one or more phosphors. In other embodiments, a remote phosphor can be provided, located in the path emitted by the LED chip 50, to convert the light remote from the LED chip 50.

[0038] The "front-side fabrication" mentioned herein refers to the fabrication of those layers adjacent to the p-type layer 54, which in the illustrated embodiment would be the layers located beneath the active structure 50. In this embodiment, "front-side" also refers to the side opposite the primary emission surface of the LED chips. "Back-side fabrication" then generally refers to the fabrication on the side opposite the front-side fabrication.

[0039] As mentioned above, the LED chip 50 may include a simplified / hybrid mirror arrangement, which allows for simplified production of the LED chip 50. In some embodiments, the hybrid mirror may include a current distribution layer 58 on the p-GaN, a dielectric reflective layer (e.g., SiO2) 60, and a mirror stack (single mirror / barrier / current distribution layer) 62 on the dielectric layer 60. However, it should be understood that other embodiments may include many different simplified / hybrid mirrors arranged in various ways. In some embodiments, these front-side layers may be self-aligned with the mesa edges of the active region. In other words, as described in more detail below, these layers (in addition to others) may be etched to a level of the epitaxial material, which may simplify the overall manufacturing process.

[0040] The distribution layer 58 may be located on the active structure 52 at a location to assist in current distribution into the p-type layer. In the illustrated embodiment, the current distribution layer 58 may cover all or part of the p-type layer, and in some embodiments, the current distribution layer 58 helps distribute current from a p-type contact 64 across the surface of the p-type layer. This helps provide improved current distribution across the p-type layer, thereby also improving current injection from the p-type layer into the active region.

[0041] The current distribution layer 58 can comprise many different materials and is typically a transparent conductive oxide, such as indium tin oxide (ITO), or a metal, such as platinum (Pt), although other materials can also be used. The current distribution layer 58 can have many different thicknesses, with the present invention having a thickness thin enough to minimize the absorption of light from the active structure that passes through the current distribution layer. In some embodiments, the current distribution layer 58 comprises ITO and can have thicknesses of less than 1000 angstroms (Å). In still other embodiments, it can have a thickness of less than 700 Å, and in other embodiments, a thickness of less than 500 Å. Other embodiments can have a thickness in the range of 50 to 300 Å, with some of these embodiments having a current distribution layer with a thickness of approximately 200 Å.The current distribution layer 58, as well as the reflective layers described below, can be applied using known methods. It should be understood that in embodiments where current distribution is not required, the LED chips can be provided without a current distribution layer.

[0042] The dielectric reflective layer 60 in the embodiment shown is formed on the current distribution layer 58, with the current distribution layer located between the dielectric layer 60 and the active structure 52. However, it should be understood that in other embodiments, the dielectric reflective layer 60 may be formed directly on the active structure 52, while in other embodiments, other layers may be located between the active structure 52 and the dielectric layer 60. The dielectric layer 60 may comprise many different materials and preferably comprises a material that has a refractive index (IR) step between the material comprising the active structure 52. In other words, the dielectric layer 60 may have an IR that is lower than the active structure to promote total internal reflection (TIR).Light undergoing TIR is reflected without absorption or loss, and TIR enables the efficient reflection of light from the active structure so that it can contribute to useful or desired LED chip emission.

[0043] The dielectric reflective layer 60 may comprise a material with an IR of less than 2.3, while other embodiments may have an IR of less than 2.15. In still other embodiments, the IR may be less than 2.0. Many different materials may be used, and in some embodiments, the dielectric layer 60 may comprise SiO2. It is understood that other dielectric materials may be used, such as SiN, Si, Ge, MgOx, MgNx, ZnO, SiNx, SiOx, AlN, and alloys, or combinations thereof. The dielectric layer 60 may also comprise a variety of different layers. In some embodiments, the dielectric layer may comprise an SiO2 layer with one or more layers of different materials. In some embodiments, a TiO2 layer may be combined with an SiO2 layer.In still other embodiments, the dielectric layer may comprise multiple layers in the form of a distributed Bragg reflector (DBR).

[0044] Some Group III nitride materials, such as GaN, may have an IR of approximately 2.4, and SiO2 has an IR of approximately 1.46. Embodiments with an active LED structure 52 comprising GaN as well as a SiO2 dielectric layer may have a sufficiently large IR step between the two to enable efficient TIR of light at the junction between the two. The GaN material of the active structure 52 has an IR of 2.4, and the SiO2 material of the dielectric reflective layer 60 has an IR of 1.46. This represents a difference between the IRs of the two of approximately 39%. The dielectric reflective layer 60 may have various thicknesses depending on the type of material, with some embodiments having a thickness of at least 0.2 µm. In some of these embodiments, it may have a thickness in the range of 0.2 to 0.7 µm, and in some of these embodiments, it may be approximately 0.5 µm thick.

[0045] As mentioned above, the LED chips 50 according to the present invention may also utilize a second reflective layer, referred to above as a mirror stack 62, to reflect light that does not experience TIR at the junction with the dielectric reflective layer 60 and that penetrates the dielectric reflective layer 60. The mirror stack 62 may comprise many different materials, such as Ag, Au, Al, or combinations thereof, and may comprise multiple layers. In the embodiment shown, the mirror stack 62 may at least partially comprise Ag, with other embodiments comprising a layer consisting essentially only of Ag. Other embodiments according to the present invention may also comprise an adhesion layer (not shown) between the dielectric reflective layer 60 and the mirror stack 62 to enable adhesion between the two.Numerous different materials can be used for the adhesion layer, such as TiO, TiON, TiO2, TaO, TaON, Ta2O5, AlO, or combinations thereof, with a preferred material being TiON. The adhesion layer can have a wide variety of thicknesses, from a few Å to thousands of Å. The thickness of the adhesion layer and the material used should minimize the absorption of light passing through it to minimize light loss due to reflection from the metal layer 62.

[0046] The LED chip 50 further includes vias 64 (p-type vias) in the dielectric layer, which can penetrate the dielectric reflective layer 60 all the way to the current distribution layer 58. The vias 64 can be filled when the mirror stack 62 is deposited, and the metal layer material can form vias 66 in the dielectric layer to the current distribution layer 58. As described in more detail below, the vias 66 form a conductive path through the reflective layer 60, with the electrical signal originating from the p-type contact, passing through the mirror stack 62, passing through the vias 66, and being conducted all the way to the current distribution layer 58.

[0047] The holes 64 can be formed using numerous known methods, such as conventional etching processes or mechanical processes such as micro-drilling. The holes 64 can have many different shapes and sizes, with the holes 64 in the illustrated embodiment having a circular cross-section with a diameter of less than 20 µm. In some embodiments, the holes can have a diameter of approximately 8 µm, and others have a diameter as small as 1 µm. Adjacent holes 64 can be spaced less than 100 µm apart, with the illustrated embodiment having an edge-to-edge spacing of 30 µm. In other embodiments, the vias can have a spacing of as little as 10 µm or less.It will be appreciated that the holes 64 (and the resulting vias 100) may have cross-sections of various shapes, such as square, rectangular, oval, hexagonal, pentagonal, etc. In other embodiments, the holes do not have a uniform size or shape, and there may be different or non-uniform spacing between adjacent holes.

[0048] In other embodiments, other structures may be used to form a conductive path between the p-contact and the current distribution layer. Instead of vias, a meshed grid may be formed through the dielectric reflective layer 60, after which a conductive material is introduced into the grid to form the conductive path through the composite layer. The grid may have many different shapes, with portions of the grid being connected at different angles in various embodiments. An electrical signal applied to the grid may propagate through and along the connected portions. It should be further understood that in other embodiments, a grid may be used in combination with vias, while other embodiments may provide other conductive paths.In some embodiments, one or more conductive paths may extend outside the active layer of the LED chip, for example, along a side surface of the LED chip.

[0049] An n-type via 68 may be formed through the mirror stack 62, the dielectric reflective layer 60, the current distribution layer 58, the p-type layer 54, and down to the n-type layer 56. In the embodiment shown, the formation of the via 68 may take place in a single etch step. This means that the layers are "self-aligned." A passivation layer 70 on the front side may then be incorporated into the inner surface of the via 66 and may extend to cover the exposed bottom surface of the mirror stack 62. The passivation layer 70 may protect layers and provide electrical insulation between them, and it may comprise many different materials, such as a dielectric material. A contact hole 72 may be formed through the passivation layer 70 to the n-type layer 56.

[0050] A conductive layer may be included that forms a via 74 through the n-type layer, which may be on the surface of the via hole 68 and on the passivation layer 70. The via 74 penetrates the mirror stack 62, the dielectric reflective layer 60, the current distribution layer 58, the p-type layer 54, and the passivation hole 72, then contacts the n-type layer 56. In this arrangement, an electrical signal applied to the via 74 is conducted to the n-type layer 56. The via 74 may also be made of many different conductive materials, such as a metal. Some embodiments of the via include a layer of metal, such as Al, covering the passivation layer in the hole 66, extending further onto the passivation layer, and covering the mirror stack 62.A bonding layer 76 may then be deposited onto the via metal layer 74.

[0051] As mentioned above, "backside processing" refers to the processing of the LED chip 50 on the side opposite the dielectric reflective layer 60 and the mirror stack 62. When LED chips are produced at the wafer level, the epitaxial layers are continuous. Mesas, or pathways, are then formed through the epitaxial layers to form the active structures for the individual LEDs. Many different formation techniques can be used, for example, etching.

[0052] During wafer-level LED chip fabrication, a first "path" 78 is formed between adjacent LED chips. In the illustrated embodiment, the front-side passivation layer 70 and the conductive layer 74 extend beyond the edge of the LED structure 52 and cover the first path 78. An interconnect contact region (i.e., a second path) 80 is also formed between the LED chips 50 in a position for the p-type contact 82. In some embodiments, the interconnect contact region 80 may be formed in one or more corners of the LED chip 50. In this embodiment, the current distribution layer 58, the dielectric reflective layer 60, and the mirror stack 62 extend into the interconnect contact region 80 (not the first path 78). A p-type contact via 84 is formed through the current distribution layer 58 and the dielectric reflective layer 60, exposing the mirror stack 62.The p-contact is enclosed in the p-contact hole 80 and is in contact with the mirror stack 62 and the current distribution layer 58.

[0053] During operation, an electrical signal applied to the p-type contact propagates primarily to metal layer 62 through vias 66 and to current distribution layer 58, where it propagates into p-type layer 54. An electrical signal applied to conductive layer 68 is conducted to n-type layer 56.

[0054] One or more layers of the surfaces of the active structure 52 can also be patterned using various methods, such as known etching or grinding processes. In conventional LED manufacturing processes, path formation and patterning can take place in separate manufacturing steps. In embodiments according to the present invention, the path formation and patterning processes can take place in the same step, simplifying the overall manufacturing process.

[0055] In one embodiment according to the present invention, backside processing may include forming a first backside passivation layer 86 on the top surface of the n-type layer. Portions of the first backside passivation layer 86 may then be formed as an array of features that help determine the texturing pattern in the n-type layer 56. In some embodiments, the first passivation layer 86 may be etched to form a pattern, such as an array of features (e.g., circles or dots), where the dots serve as a mask for etching the textured features. The dots may be arranged in a predefined pattern, resulting in textured features 87 (i.e., truncated cones) that are substantially the same size, or they may be in a random pattern, resulting in textured features that vary in size.

[0056] In embodiments according to the present invention, the n-type layer 56 may be etched between the features of the patterned passivation layer 82, with some embodiments using a wet chemical etch. This allows etching along a crystal plane of the semiconductor layer comprising the n-type layer 56. As shown, this etching continues until the bottoms of each of the frustoconical features intersect with adjacent frustoconical features. In this way, no more material is removed from the n-type layer by the etching process, as this cutting is "self-limiting" to the depth of the features. This arrangement and method for forming the textured features 87 are fully described in U.S. Patent Application Serial No. 13 / 868,361 by Donofrio, assigned to Cree Inc., the contents of which are incorporated herein.

[0057] During the etching of the n-type layer 56, the first path 78 and the via contact region 80 may also be etched. The textured features of the n-type layer are self-limiting, and once the bottoms of the features intersect, the etching process for those features ends, even if the etch feature remains. This allows additional etch time to further remove epitaxial material in the paths 78, 80, while epitaxial material at the textured features is no longer removed. This allows one etching step to be used to etch different features that require different etch times. Because a feature is self-limiting, additional time can be used to etch one or more other features, such as the paths.

[0058] Following this etching process, a second backside passivation layer 88 may be enclosed over the active structure 52 and across the paths 78, 80 between the active structures. The first and second backside passivation layers 86, 88 may comprise many different materials, and in some embodiments, they may comprise the same material or different materials. The first backside passivation layer 86 primarily serves as a mask for forming the textured features, while the second backside passivation layer 88 primarily serves to protect the layers beneath it. Like the frontside passivation layer 70 described above, the first and second backside passivation layers may also comprise many different materials, such as dielectric materials.

[0059] The opening can then be formed in the second passivation layer 88, along with the current distribution layer 58 and the dielectric reflective layer 60, to form the p-type contact hole 84. The p-type contact 80 is formed in the hole 84 and directly on the metal layer 62 to supply an electrical signal to the p-type layer 54, as described above. The openings are preferably formed by an etching process that leaves a relatively clean surface on the metal layer 62, and the p-type contact 82 should be provided with good sidewall coverage by the current distribution layer 58, the dielectric reflective layer 60, and the second passivation layer 84 to prevent metal migration between the layers.

[0060] The LED chip 50 has a simplified structure that can be manufactured with fewer steps than those used in the production of conventional LED chips. Fig. 6 is a flowchart 90 illustrating some of the steps employed in one embodiment of a manufacturing method according to the present invention, with various steps focusing primarily on etching processes. In step one 91, the holes in the p-type reflective layer (or p-type via holes) 64 may be etched through the dielectric layer 60 to the current distribution layer 58. The holes 64 may be filled when the metal layer 62 is deposited, and the metal layer material may form vias 66 to the current distribution layer 58.

[0061] After depositing the mirror stack 62, in step 92, the mirror stack 62, the dielectric reflective layer 60, the current distribution layer, and a portion of the p-type epitaxial GaN material 54 may be etched to form a via hole. As mentioned above, the layers being etched are "self-aligned" and are etched in a single step. In some conventional LED chips, these layers may be etched in different steps, which can result in a more complicated manufacturing process.

[0062] After applying the passivation layer 70, in step three 93, the passivation layer 70 can be etched to form the passivation layer hole 72, which leads to the n-type layer 56. The conductive via layer 74 fills the passivation layer hole and forms a contact with the n-type layer 56.

[0063] The first backside passivation layer 86 may be applied and then formed into the pattern of features that control the formation of the textured features of the epitaxial materials. In step four 94, the first path 78, the interconnect contact region 80, and the textured features 87 may be formed in the same etching step. As described above, the etching of the textured features 87 may be self-limiting, resulting in the etching of the textured features 87 being halted while the additional texturing of the paths 78, 80 continues. This self-limiting nature of the textured features enables the etching of the textured features 87 and the paths 78, 80 in one etching step.

[0064] The second backside passivation layer 88 can then be applied. In step five 95, the p-type contact hole 84 can be etched through the second backside passivation layer 88, the current distribution layer 58, and the dielectric reflective layer 60 to the mirror stack 62. The p-type contact 82 can then be inserted into the hole 84 and into contact with the mirror stack 62. By extending the mirror stack beyond the mesa, instead of a light absorption barrier like some conventional LED chips, light absorption can be reduced.

[0065] LED chips according to the present invention can be arranged in many different ways and can include numerous different layer structures manufactured using different methods. Fig. Figure 7 shows another embodiment of an LED chip 100 which is similar to the LED chip 50 shown in Fig. 4 and Fig. 5 and described above. The same reference numerals are used for the same or similar features or elements as in the description of the LED chip 50 above, it being understood that the above description refers to this embodiment.

[0066] The LED chip 100 includes an active structure 52 comprising a p-type layer 54 and an n-type layer 56, with an active region between the two. The front side of the LED chip 100 includes a current distribution layer 58 on the p-type layer 54 and a dielectric reflective layer 60 on the current distribution layer 58, with adhesion layers included between additional layers if desired. A mirror stack 62 is included on the dielectric layer 60, with reflective layer vias 66 formed through the dielectric reflective layer 60 and extending from the mirror stack 62 to the current distribution layer 58.

[0067] Also on the front side of LED chip 100, an n-type via 68 is formed through dielectric reflective layer 60, current distribution layer 58, and p-type layer 54 to n-type layer 56. Mirror stack 62 is offset from the via, and the via is not formed in the layers in the self-aligned manner described above. Furthermore, dielectric reflective layer 60 is arranged differently than the dielectric reflective layer described above and extends inside via 68 over the surfaces of p-type and n-type layers 54, 56 exposed in via 68.The passivation layer hole 72 extends through the dielectric reflective layer 60 at the top of the via hole 68 to expose a surface of the n-type layer 56, which is thereby in contact with the conductive via layer 74. The dielectric reflective layer 60 may also extend into the first path 78 and into the interconnect contact region 80. The front-side passivation layer 70 extends into the first path 78 on the reflective layer 60.

[0068] This covering of the dielectric reflective layer 60 enables a reflective cup arrangement that helps reflect laterally emitted or collected light so that it can contribute to usable emission from the LED chip. This can include light emitted directly laterally from the active region or light collected in the active structure by total internal reflection (TIR). As shown by the first light path 102, light emitted along the active region toward the edge of the active structure 52 can be reflected by the upwardly extending portion of the dielectric reflective layer 60 at the edge of the active structure. Similarly, and as shown by the second light path 104, light emitted toward the via can be reflected by the upwardly extending portion of the dielectric reflective layer 60 in the via hole 68.This reflective cup arrangement may enable improved overall emission efficiency for the LED chip 100.

[0069] There are further differences in the LED device / package 100. Unlike the LED device 50, the current distribution layer 58 does not extend into the first path 78 or into the interconnect contact region 80. Instead, it terminates at or near the edge of the active structure 52. Additionally, the dielectric reflective layer 60 does not terminate at the edge of the active structure 52 in the interconnect contact region 80, but continues to the edge surface of the current distribution layer 58, the edge of the p-type layer 54, and a portion of the edge of the n-type layer, and then extends into the interconnect contact region 80.

[0070] The LED package also includes first and second backside passivation layers 86, 88, with the first passivation layer 86 being arranged to form the pattern to determine the shape and size of the n-type structural features, as described above. As previously mentioned, the self-limiting etching of the textured features allows the same etching step to be used for the formation of the textured features and the first path 78 and the interconnect contact region 80. The second backside passivation layer 88 is applied as protection over the textured features, the first path 78, and the interconnect contact region 80. A p-type contact via 84 may be formed in the interconnect contact region 80 through the second backside passivation step 88 and the dielectric reflective layer 60 to expose the top surface of the mirror stack 62. A p-type contact 82 may be formed in the via 84 and in contact with the mirror stack.As discussed above, an electrical signal applied to p-type contact 82 propagates into mirror stack 62 and is conducted through vias 66 into current distribution layer 58, from where the signal propagates into p-type layer 54. An electrical signal applied to conductive layer 74 is conducted to n-type layer 56, as described above.

[0071] In LED 100, the dielectric reflective layer 60 may terminate at specific points after etching the active mesa. In some embodiments, the dielectric reflective layer may extend beyond the edge of the n-GaN into the first path 78 and the interconnect contact region 80, as shown, while in other embodiments, it may terminate between the active mesa step and the edge of the n-GaN. In most embodiments, it may be important for the dielectric reflective layer 60 to extend beyond the active region step to form the reflective cups, as described above. There may be other considerations for how far the layer should extend, such as the difference in moisture permeability between SiO2 and SiN, in which case it may be preferable for the SiO2 to be continuous across the path.Another SiN layer (back passivation) is included, which would cover the SiO2 in the paths, but upon dicing, the edge of the SiO2 could be exposed. If a portion of the SiO2 of the dielectric reflective layer in the path is removed, it would be encapsulated by SiN on both sides.

[0072] The LED chip 100 also has a simplified structure that can be manufactured with fewer steps than those used in the production of conventional LED chips. The LED chip 100 has layers arranged as described above to enable improved light output. Fig. Figure 8 is a flowchart 120 illustrating some of the steps employed in one embodiment of a manufacturing method according to the present invention, with various steps focusing primarily on etching processes. After deposition of current distribution layer 58, in step 121, the n-type mesa is etched through current distribution layer 58, through p-type layer 54, and down to n-type layer 56.

[0073] The dielectric layer 60 may then be deposited over the current distribution layer 58 and over the n-type mesa. In some embodiments, the dielectric reflective layer 60 may form a cup, as described above, and extend into the first path 78 and / or the interconnect contact region 80. In step two 122, vias 64 may be formed in the dielectric layer using known etching techniques through the dielectric layer.

[0074] In step three 123, the mirror stack may be deposited onto the dielectric reflective layer 60, filling the holes in the dielectric layer to form vias 66. Then, the passivation layer 70 may be deposited, and in step four 124, the passivation layer may be etched to form the n-type via 68. Then, the conductive layer 74 may be formed over the passivation layer and in contact with the n-type layer 56.

[0075] The first back passivation layer 86 can then be applied and etched into its pattern of features. In step five 125, the textured features 87, the first path 78, and the interconnect contact region 80 can be etched in the same step. As described above, the etching of the textured features 87 can be self-limiting, allowing the etching of the textured features and paths, although the etching of the paths may take longer.

[0076] Then, the second back layer 88 and, in step six 126, the second back passivation layer 88 may be deposited, the dielectric reflective layer 60 may be etched down to the mirror stack 62, and the p-contact 82 may be deposited on the mirror stack 62.

[0077] It should be understood that other embodiments may include layers arranged in many different ways, in addition to those shown in the above-mentioned embodiments, and that they may cover different portions of adjacent layers. For example, in the above-mentioned embodiments, the mirror stack 62 extends into the interconnect contact region 80, but it does not extend beyond the edge of the active region 52 in the first path 78, nor does it extend beyond the edge of the n-type via 68. However, in other embodiments, these and other layers may cover other portions and extend beyond the regions shown.

[0078] Fig. Figure 9 shows another embodiment of an LED chip 130 according to the present invention, which is similar to the LED chip 100 shown in Fig. 6 and described above. The LED chip 130 includes an active structure 52 having a p-type layer 54 and an n-type layer 56, with an active region between the two. The front side of the LED chip 130 includes a current distribution layer 58 and a dielectric reflective layer 60 on the current distribution layer 58, with adhesion layers included between additional layers if desired. A mirror stack 62 is included on the dielectric layer 60, with reflective layer vias 66 formed through the dielectric reflective layer 60 and leading from the mirror stack 62 to the current distribution layer 58.

[0079] As in the above embodiments, an n-type via 68 is formed through the dielectric reflective layer 60, the current distribution layer 58, and the p-type layer 54 to the n-type layer 56. Also similar to the above embodiments, the dielectric reflective layer 60 and the mirror stack 62 extend beyond the edge of the active structure 52 into the interconnect contact region 80, and the dielectric reflective layer extends into the first path 78. However, in this embodiment, the mirror stack 62 may extend beyond the edge of the active structure 52 on the dielectric reflective layer 60 and at least partially into the first path 78. The mirror stack 62 may also extend with the dielectric layer beyond the edge of the active structure, and it may also at least partially cover the inner surface of the n-type via 68.It should be understood that in some embodiments, the mirror stack 62 should not extend into the n-type GaN layer 56 and should not extend to the edge of the path 80. The mirror stack 62 should also not extend into the n-type vias in order to completely cover the dielectric reflective layer 60 in the n-type vias 68. This allows for efficient and reliable device singulation and etching of the passivation layer via 72 without touching the mirror stack 62 when the conductive layer 74 is deposited over the passivation layer 70.

[0080] This arrangement can provide advantages, such as a more efficient cup-like reflector than in the embodiment described above. Both the dielectric layer 60 and the mirror stack 62 can contribute to the reflection of light emitted directly laterally from the active region or of light collected by total internal reflection (TIR) in the active structure. It should also be understood that the mirror stack, as described herein, can extend into embodiments that do not include the reflective cup arrangement, such as in the embodiment described above.

[0081] GaN texturing using SiN dots formed by the first backside passivation layer and a self-limiting crystallographic wet etch is described above. Some crystallographic etching is known to etch through the n-type GaN layer quickly but is slow for the p-type GaN layer. LED chip 100 may have an advantage in that the p-type GaN layer was removed during frontside processing (n-mesa etching), so the backside etch is completed in a relatively short time. In some prior art devices, such as LED chip 50, the backside etch must penetrate the p-type GaN layer, and therefore the etching can take longer and sometimes leaves p-type GaN residues that can reduce product yield.

[0082] With further reference to the LED chip 50, which is used in the Fig. 4 and Fig. 5 and described above, the self-aligned mirror stack 62, the dielectric reflective layer 60, the current spreading layer (ITO), the p-type layer, and a portion of the n-type (GaN) layer, the hole through these layers can be etched by reactive ion etching (RIE) techniques, although it is preferred to wet etch the Ag mirror stack due to the known difficulties in performing a clean dry etch of Ag. If an adhesion layer is included, it can be wet or dry etched, depending on the nature of the adhesion layer. Wet etching the Ag mirror stack layer will etch the Ag laterally as well as vertically, resulting in an undercut. If the adhesion layer is a light-absorbing metal, the silver undercut can create an absorbing edge around the silver periphery as viewed from the dielectric layer side.This is undesirable because it can affect light output. It is also undesirable to have an overhanging adhesion layer when the passivation layer is applied on top, as the overhang can prevent conformal deposition and leave gaps in the passivation layer, which can compromise reliability.

[0083] With reference to Fig. 10, to solve this problem, the present invention provides a method for performing a second wet etch after the etching of the Ag mirror stack 62 is complete, wherein the second etch comprises a chemical that etches the adhesion layer 130 but not the Ag mirror stack 62. If the timing of this etching process is correct, the second etch will etch the adhesion layer 130 laterally beyond the mirror stack 62, thereby eliminating the absorption edge around the mirror stack 62. This method also maintains the alignment of the dielectric reflective layer 60 and the current distribution layer 58 within the via hole 68. Many different wet etchants can be used to etch silver, such as the commercially available silver etchant TFS, Seiver Ethcant 9044 (both from Transese Company, Inc.), and commercially available nitric acid (concentrated or diluted).An example of an adhesion layer material may include Ti, which is compatible with Ag. In some embodiments, the Ti layer may be etched with HCl (concentrated or diluted in water).

[0084] For the building structures according to the present invention and as described above with reference to the embodiments shown in the Fig. 4 and Fig. 6, the p-contact 82 may be located on and connected to the mirror stack 62, with some embodiments having a p-contact on the Ag side of the mirror stack. Before the p-contact 82 is formed, a via must be drilled through as many as three or more layers. In some embodiments, these layers may include the second backside passivation layer 88, the power distribution layer (ITO) 58, and the dielectric layer 60. Typical RIE chemistries for etching dielectrics can tarnish exposed Ag, which can result in poor electrical contact or an inconsistent appearance that hinders the operation of automated visual inspection tools. One solution to the problem is to remove the tarnish layer by immersing it in a chemical or by subjecting the tarnished surface to a plasma cleaning process, for example, with N2 plasma.

[0085] In some embodiments according to the present invention, the exposed mirror stack (Ag) should be encapsulated during the deposition of the p-contact 82 to prevent migration of metal (Ag) during operation. All exposed surfaces of the metal (Ag) should be sealed during the deposition of the p-contact. There are two aspects to this. First, no polymer or contaminant should be deposited on the sidewalls during the RIE etch that precedes the deposition of the p-contact. Second, the p-contact should comprise metals known to be good barrier metals, and the deposition of the metals should cover the sidewalls as well as the bottom of the p-contact hole. Examples of suitable RIE etch chemistries include CF4 / O2 and SF6 / O2. With reference to Fig. 11 illustrates a p-type contact structure 140 that may comprise more than one material, where the p-type contact 140 comprises a barrier layer 142 of one material and a base material 144 of another material. Examples of suitable materials include p-type contact barrier layer 142 materials including, but not limited to, sputtered Ti / Pt, followed by a base material 144 comprising evaporated Au. Other embodiments may comprise a sputtered Ti / Ni barrier layer 142 and a base material 144 of evaporated Ti / Au. Further embodiments may comprise various combinations of these materials.

[0086] With renewed reference to the embodiments in the Fig. 4 and Fig. 6. When the structures are subjected to a wafer bonding process, there is a possibility of gaps in the interconnect layer if the structure topology is too large. For example, the gaps under the via hole 68 or the first path 78 may be too large and lead to gaps in the interconnect layer. One solution to this problem may be to flatten the structure prior to wafer bonding. This can be achieved by enclosing a polymer or spin-on glass on the wafer. Fig. Figure 12 shows an embodiment of an LED chip 160 that is similar to the LED chip 50 shown in Fig. 5 and described above. In this embodiment, a polymer 162 may be included in the gaps, with the polymer 162 being spin-coated, cured, and etched back in the shallow areas immediately prior to deposition onto the interconnect layer 164. Alternatively, planarization may be performed between the passivation layer and the Al layer, between the mirror stack and the passivation layer, or the planarizing polymer may replace the passivation. In these embodiments, the polymer may be left intact after curing or etched back in the shallow areas, leaving polymer only at the step edges.

[0087] Fig.13 shows another embodiment of an LED chip 150 according to the present invention with a further simplified construction. The LED chip 170 may include layers and structures similar to those of the LED chip 50, including but not limited to the active structure 52 and front-side layers such as the current distribution layer 58, the mirror stack 62, the passivation layer 70, the conductive layer 74, and the interconnect layer 76. The backside may also include the first path 78, the interconnect contact region 80, the p-contact 82, first and second backside passivation layers 86, 88, and textured features 87. However, the LED chip 170 is simplified by removing the dielectric reflective layer and omitting the step of forming vias through the reflective layer.This can result in a simplified construction process involving fewer steps, with some embodiments being fabricated in a 4-stage or 4-level construction. In some embodiments, removing the reflective layer may result in some reduction in emission efficiency due to the removal of the dielectric reflective layer, but in some applications, these losses may be acceptable.

[0088] In still other embodiments, the path and texturing features may be etched in two different etch steps than in prior art devices. However, this may add another step to the manufacturing process for LED die 50 and LED die 100. In still other embodiments, the current distribution layer may be removed, allowing the mirror stack to be in direct contact with p-GaN and used instead of the current distribution layer to distribute current from the p-contact.

Claims

[1] A light-emitting diode (LED) chip (50) comprising: an active LED structure (52) comprising an active region between two oppositely doped layers (54, 56), the active region emitting light in response to an electrical signal applied to the oppositely doped layer (54, 56); a first reflective layer (60) adjacent to one of the oppositely doped layers (54, 56); a second reflective layer (62) on the first reflective layer, the second reflective layer (62) reflecting light not reflected by the first reflective layer, wherein the second reflective layer extends beyond an edge of the active LED structure (52) into a connection contact region (80) formed on the LED chip (50) to hold a contact (82) in the connection region (80) on the second reflective layer (62) that extends through the first reflective layer (60) and is in contact with the second reflective layer (62). [2] The LED chip (50) of claim 1, wherein the first reflective layer (60) extends beyond the edge of the active LED structure (52). [3] The LED chip (50) of claim 1, wherein the first reflective layer (60) comprises a dielectric material. [4] The LED chip (50) according to claim 1, wherein the first reflective layer (60) comprises one or more of the following materials: SiO2, SiN, Si, Ge, MgOx, MgNx, ZnO, SiNx, SiOx, AlN and alloys or combinations thereof. [5] The LED chip (50) of claim 1, wherein the second reflective layer (62) comprises a metal. [6] The LED chip (50) of claim 1, wherein the second reflective layer (62) comprises a mirror stack. [7] The LED chip (50) of claim 1, further comprising a current distribution layer (58) between the first reflective layer (60) and the active LED structure (52). [8] The LED chip (50) of claim 1, wherein the contact (82) is a p-contact located on the second reflective layer (62). [9] The LED chip (50) according to claim 1 or 8, wherein the contact is arranged in a hole through the first reflective layer (60). [10] The LED chip (50) according to claim 1, wherein the first reflective layer (60) ends before an edge of the LED chip. [11] The LED chip (50) according to claim 1, wherein the first reflective layer (60) terminates at an edge of the LED chip. [12] The LED chip (50) of claim 1, wherein the first reflective layer (60) terminates between an edge of the active region and an edge of an n-type layer of the active LED structure (52). [13] The LED chip (50) according to claim 1, wherein the first (60) and / or the second reflective layer (62) form a reflective cup. [14] The LED chip (50) of claim 13, wherein the reflective cup includes an upwardly extending portion that reflects light emitted laterally in the active structure. [15] The LED chip (50) of claim 1, comprising a self-aligned via through the first (60) and second reflective layers (62) to the active LED structure (52). [16] The LED chip (50) of claim 1, further comprising textured features (87) on the active LED structure (52). [17] The LED chip (50) of claim 16, wherein the textured features (87) are self-limiting upon etching. [18] The LED chip (50) of claim 1, comprising the current distribution layer (58) disposed between the first reflective layer (60) and the active LED structure (52), wherein the current distribution layer (58) completely covers an adjacent one of the oppositely doped layers (54, 56). [19] The LED chip (50) according to claim 18, wherein the current distribution layer (58), the first reflective layer (60) and the second reflective layer (62) extend into the connection region (80), wherein a contact hole (84) is formed through the current distribution layer (58) and the first reflective layer (60) and thereby exposes the second reflective layer (62), wherein the contact (82) lies in the contact hole (84) and is in contact with the second reflective layer (62) and the current distribution layer (58). [20] The LED chip (50) according to claim 18 or 19, wherein the contact (80) is a p-contact and wherein the one adjacent layer of the oppositely doped layers (54, 56) is a p-type layer.

Images