Semiconductor device and method for manufacturing a semiconductor device

Abstract

Semiconductor device comprising the following: - an insulating plate (21); - an electrode (22) which is arranged on the insulating plate (21) and has a concave area; - a compound layer (3) made from a sintered body of metal crystal grains arranged at the electrode (22); and - a semiconductor element (4, 5) connected to the electrode (22), wherein the interconnect layer (3) is located between them, the concave region not reaching an end region of an interconnect surface between the electrode (22) and the interconnect layer (3).

Description

TECHNICAL AREA

[0001] The present invention relates to a semiconductor device in which a semiconductor element and a circuit substrate are electrically connected. STATE OF THE ART

[0002] A semiconductor device for energy conversion, used for inverter control of a motor, comprises a vertical semiconductor element, such as an insulated-gate bipolar transistor (IGBT) or a metal-oxide-semiconductor field-effect transistor (MOSFET), and a diode. A metallized electrode is formed on a front and a back surface of the semiconductor element. In the case of a typical semiconductor device, a back electrode located on the rear surface of the semiconductor element and a circuit substrate are connected by a solder joint.

[0003] Since the amount of heat generated in semiconductor devices tends to increase, high heat resistance is desirable for a bonding material used in the semiconductor energy conversion device. However, a lead-free solder material with high heat resistance is not currently available; therefore, the use of a sintered bonding technique, which utilizes a sintering phenomenon of metal grains, is being considered as a method for joining materials in a semiconductor energy conversion device, replacing the solder connection.

[0004] A sintered bonding material, used in the sintered bonding technique, consists of metal grains and an organic component. The sintered bonding technique is a method in which a bond is created with a component to be joined using a porous bonding layer formed by the sintering process of the metal grains contained in the sintered bonding material.

[0005] In a conventional semiconductor device, the rear electrode of the semiconductor element is connected to the circuit substrate using a sintered bonding material containing silver (Ag) nanoparticles (see, for example, patent document 1).

[0006] In another conventional semiconductor device, particles of high hardness, consisting of copper (Cu) or nickel (Ni) or of both Cu and Ni and containing Ag nanoparticles as a major component, are distributed in the sintered bonding material to improve the strength of the bonding layer at the time of joining the back electrode of the semiconductor element to the circuit substrate (see, for example, patent document 2).

[0007] Patent document 3 describes a bonding method in which a first silver metal region of a semiconductor device is bonded to a second copper metal region on a ceramic insulating substrate with a copper circuit. A metal nanopaste consisting of fine silver particles in an organic solvent is used. The bond is formed by heating. Additionally, indentations are created on the bonding surface of the second metal region, extending to the edge of the bonded area.

[0008] Patent document 4 describes a method for joining a semiconductor element to a substrate by the following steps: coating a circuit pattern with corrosion protection, applying a sinterable bonding material, dehydration to form an organic protective film and anchoring effect, and sintering under pressure. The process includes a preliminary joining at a lower temperature and a final joining at a higher temperature for diffusion bonding.

[0009] Patent document 5 discloses a semiconductor module comprising: a semiconductor element with front and back electrodes, a metal plate connected to the back electrode via a sintered material containing metal nanoparticles, and a plate-shaped conductor connected to the front electrode via the same material. The metal plate and conductor contain grooves that connect the connection zone to the external environment. DOCUMENTS OF THE STATE OF TECHNOLOGY Patent documents Patent document 1: JP 2007- 214 340 A Patent document 2: JP 2012- 124 497 A Patent document 3: JP 2006- 202 586 A Patent document 4: JP 2015- 106 677 A Patent document 5: US 2015 / 0 130 076 A1 SHORT DESCRIPTION Problem to be solved by the invention

[0010] Such a conventional semiconductor device, as described in patent document 1 or patent document 2, has a problem in that when the semiconductor device is used in a high-temperature environment of, for example, 175 °C to 300 °C, thermal stress on the electrode and the interconnect layer of the circuit substrate, which occurs during repeated operation at low and high temperatures, causes cracking in the interconnect layer, thus an advantageous interconnect reliability cannot be achieved in some cases.

[0011] The present invention was designed to solve these problems as described above, and the object of the present invention is to provide a semiconductor device and a method for producing such a semiconductor device with advantageous reliability of a compound layer, even when the semiconductor device, which has a compound layer formed from a sintered bonding material, is used in a high-temperature environment. Means to solve the problem

[0012] The problem underlying the invention is solved by a semiconductor device having the features of independent claim 1. The problem underlying the invention is further solved by a method for manufacturing a semiconductor device according to claim 12. Advantageous embodiments of the semiconductor device according to the invention are specified in dependent claims 2 to 11. Effects of the invention

[0013] The semiconductor device according to the present invention can be a semiconductor device which exhibits the advantageous reliability of the interconnect layer even when the semiconductor device is used in an environment with a high temperature.

[0014] Furthermore, a semiconductor device which exhibits the advantageous reliability of the interconnect layer even when the semiconductor device is used in a high-temperature environment can be manufactured using the method for manufacturing the semiconductor device according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The figures show: Fig. 1 a schematic cross-sectional view representing an essential area of ​​a semiconductor device according to embodiment 1 of the present invention; Fig. 2 a top view showing a circuit substrate of the semiconductor device according to embodiment 1 of the present invention; Fig. 3 a diagram representing an experimental result of a strain test of a sintered specimen according to embodiment 1 of the present invention; Fig. 4 a diagram representing an experimental result of a strain test of a sintered specimen according to embodiment 1 of the present invention; Fig. 5 a cross-sectional view schematically representing an aspect of a connection layer of the semiconductor device according to embodiment 1 of the present invention; Fig. 6 a cross-sectional view schematically representing an aspect of a compound layer of a conventional semiconductor device; Fig. 7 a cross-sectional view schematically representing an aspect of a compound layer after a temperature cycle test of the semiconductor device according to embodiment 1 of the present invention; Fig. 8 A cross-sectional view schematically representing an aspect of a compound layer after a temperature cycle test of a conventional semiconductor device; Fig. Diagrams 9A to 9E, illustrating a method for manufacturing the semiconductor device according to embodiment 1 of the present invention; Fig. 10 to 10E diagrams, which represent a further method for manufacturing the semiconductor device according to embodiment 1 of the present invention; Fig. 11 a cross-sectional view schematically representing a structure near a connection layer of a semiconductor device according to embodiment 2 of the present invention; Fig. 12A to 12D Top views and side cross-sectional views showing a circuit substrate of a semiconductor device according to embodiment 3 of the present invention; Fig. 13 a cross-sectional view schematically representing a structure near a connection layer of a semiconductor device according to embodiment 4 of the present invention. DESCRIPTION OF EXECUTION FORMS Execution form 1

[0016] First, the configuration of a semiconductor device according to embodiment 1 of the present invention is described. Fig. Figure 1 is a schematic cross-sectional view representing an essential area of ​​the semiconductor device according to embodiment 1 of the present invention. Fig. Figure 2 is a top view showing a circuit substrate of the semiconductor device according to embodiment 1 of the present invention.

[0017] A semiconductor device 1 comprises: a circuit substrate 2 on which an electrode 22 and an electrode 23, formed from a metal such as copper (Cu) or nickel (Ni), are arranged on both surfaces of an insulating plate 21, formed, for example, from a silicon nitride ceramic plate, and a first semiconductor element 4 and a second semiconductor element 5, which are connected to a surface of the electrode 22 of the circuit substrate 2 by means of a bonding layer 3, which is made from a sintered body of metal crystal grains, such as Ag.

[0018] As in Fig. As shown in Figure 2, a concavely shaped area 6, which is formed, for example, by mechanical processing, printing or etching, is arranged in each area by a connection area 22a, which is in contact with the first semiconductor element 4, and a connection area 22b, which is in contact with the second semiconductor element 5, on one side of the surface of the electrode 22 of the circuit substrate 2.

[0019] In Fig. 1. The concavely shaped region 6 is formed such that it extends from the surface of the electrode 22 in a depth direction of the electrode 22, with the electrode 22 being located in a lower region of the concavely shaped region 6. However, the concavely shaped region 6 can also be arranged such that it passes through the electrode 22, in which case the insulating plate 21 can be a lower region of the concavely shaped region 6. The remaining region, which does not form the concavely shaped region 6 in the connection regions 22a and 22b in the electrode 22, forms a flat surface of the electrode 22 and thus constitutes a flat region.

[0020] The interconnect layer 3 is located on the surface of interconnect region 22a and interconnect region 22b in the electrode 22, and the first semiconductor element 4 and the second semiconductor element 5 are connected to the electrode 22 via the interconnect layer 3. In fact, interconnect regions 22a and 22b are not explicitly shown as a dashed line extending into the electrode 22 according to Fig. 2 is shown, but the connection areas 22a and 22b are completely covered with the connection layer 3, so that the area covered with the connection layer 3 can also be referred to as a connection area at electrode 22.

[0021] As in Fig. As shown in Figure 1, the bonding layer 3 is arranged to embed an inside of the concave shaped region 6, and the bonding layer 3 has a first region 3a which is in contact with the concave shaped region 6 and a second region 3b which is not in contact with the concave shaped region 6.

[0022] In Fig. 1 appears to be an area of ​​the region in which the concavely shaped region 6 is arranged on the surface of the electrode 22 equal to an area of ​​the region in which the concavely shaped region 6 is not arranged; however, the width of the concavely shaped region 6 is several hundred micrometers (µm), so that the surface of the electrode 22 is mostly occupied by a flat region in which the concavely shaped region 6 is not arranged.

[0023] In the first region 3a of the interconnect layer 3, the layer thickness is defined as the distance between the lower region of the concave region 6 and the rear electrodes 4d and 5c of the first and second semiconductor elements. Similarly, in the second region 3b of the interconnect layer 3, the layer thickness is defined as the distance between the surface of the electrode 22, where the concave region 6 is not located, and the rear electrodes 4d and 5c of the first and second semiconductor elements. Accordingly, the concave region 6 is located on the surface of the electrode 22, and therefore the layer thickness of the first region 3a is greater than that of the second region 3b.

[0024] If, for example, the lower part of the concavely shaped area 6 has a concave surface shape that differs from the case according to Fig. 1 distinguishes, a region which has the greatest distance to the rear electrodes 4d and 5c of the first and second semiconductor element can be defined as the lower region of the concave shaped region 6, and the distance between this lower region and the rear electrodes 4d and 5c can be defined as the layer thickness of the first region 3a.

[0025] The third layer is a sintered body containing a plurality of metal crystal grains and exhibits an organizational structure such that a large number of very small pores in the submicrometer range, characteristic of sintered bodies, are uniformly distributed. Thus, the filling rate of the metal crystal grains in the third layer is less than 100%, and the filling rate decreases with an increasing number of pores.

[0026] In the semiconductor device 1 according to embodiment 1 of the present invention, the fill rate of the metal crystal grains in the first region 3a of the compound layer 3 is lower than the fill rate of the metal crystal grains in the second region 3b. The fill rate of the metal crystal grains in the compound layer 3 is preferably equal to or greater than 80% and less than 100% in the second region 3b in order to increase the bond strength of the compound layer 3. The fill rate of the metal crystal grains in the first region 3a must be lower than the fill rate of the metal crystal grains in the second region 3b, and it is particularly preferred that the fill rate in the first region 3a is equal to or greater than 20% and less than 80%.

[0027] The layer thickness of the electrode 22 can, for example, be between 200 µm and 1000 µm. The width of the concavely shaped region 6 formed in the electrode 22, that is, the width of the groove shape formed by the cross-section in Fig. As shown in Figure 1, the depth in a horizontal direction of a drawing sheet can, for example, be 100 to 300 µm. Although the depth of the concavely shaped area 6 can be deep enough to pass through the electrode 22, as described above, it is preferably 20 µm to 100 µm for ease of processing.

[0028] The width of the concavely shaped region 6 is preferably greater than its depth in order to form the compound layer 3 within the concavely shaped region 6, and it is particularly preferred that the ratio between the width and the depth, i.e., width / depth, is between 2 and 8. The distance between the compound layer 3 and the electrode 22, i.e., the layer thickness of the second region 3b in the compound layer 3, can, for example, be between 20 µm and 100 µm.

[0029] For the insulating plate 21 of the circuit substrate 2, a ceramic plate made of aluminum oxide or aluminum nitride, as well as silicon nitride, can be used. Since the semiconductor device 1 generates a large amount of heat due to its use for power generation, the insulating plate 21 is preferably made of a material having a thermal conductivity equal to or greater than 20 W / m·K to improve heat dissipation from the semiconductor device; a material having a thermal conductivity equal to or greater than 70 W / m·K is further preferred.

[0030] The first semiconductor element 4 and the second semiconductor element 5 are made of a large-bandgap semiconductor material, such as silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), or diamond (C), which have a bandgap larger than that of silicon (Si). One or both of the first semiconductor element 4 and the second semiconductor element 5 may be silicon (Si).

[0031] At semiconductor facility 1 in Fig. In example 1, the first semiconductor element 4 is a MOSFET, and the second semiconductor element 5 is a Schottky barrier diode (SBD). However, each of the first semiconductor element 4 and the second semiconductor element 5 can also be a different type of semiconductor element, such as an IBGT. The number of semiconductor elements is not limited to two; one semiconductor element, three, or more semiconductor elements can also be used.

[0032] The drain electrode 4d, which is the back electrode, is located on the back surface of the MOSFET, which is the first semiconductor element 4, and a source electrode 4s and a gate electrode 4g, which are front electrodes, are located on the front surface of the same.

[0033] The cathode electrode 5c, which is the rear electrode, is located on the rear surface of the SBD, which is the second semiconductor element 5, and an anode electrode 5a, which is a front electrode, is located on the front surface of the same.

[0034] A wiring element is connected to electrode 22, to which drain electrode 4d and cathode electrode 5c (not shown) are connected, which are the back electrodes of each semiconductor element; another wiring element is also connected to source electrode 4s and gate electrode 4g, which are the front electrodes, and anode electrode 5a of the SBD (not shown); and the semiconductor device 1 is electrically connected to an external circuit by means of these wiring elements.

[0035] In a similar manner to the general semiconductor device, the first semiconductor element 4 and the second semiconductor element 5 are covered, for example, with a sealing body or housing, and a heat dissipation element, such as a heat spreader, is arranged at the electrode 23 of the circuit substrate 2 (not shown). The heat dissipation element can also be connected directly to the circuit substrate 2, away from which the electrode 23 is located, instead of being connected to the electrode 23.

[0036] The semiconductor device 1 according to embodiment 1 of the present invention is configured as described above. When the semiconductor device 1, which has the configuration described above, is used in a high-temperature environment, for example, from 175 °C to 300 °C, a stress is applied to the interconnect layer 3. However, cracking preferably occurs in the first region 3a, which has a low fill rate of metal crystal grains, and this cracking reduces the stress on the interconnect layer 3, consequently preventing cracking in the second region 3b. As a result, the adhesive force between the electrode 22 and the first and second semiconductor elements 4 and 5 is not reduced, so that a semiconductor device 1 with high interconnect reliability can be achieved.

[0037] As described above, the semiconductor device 1 according to embodiment 1 of the present invention has a feature in that the concavely shaped area 6 is formed in a predetermined pattern in the electrode 22 and the filling rate of the metal crystal grains of the compound layer 3 is controlled according to the formation pattern so that the area in which cracking occurs and the area in which the occurrence of cracking is prevented can be controlled.

[0038] Next, a basic concept is described regarding how the occurrence and prevention of crack formation in the interconnection layer 3 can be controlled, after a method for producing the interconnection layer 3 of the semiconductor device 1 has been described.

[0039] The bonding layer 3 is formed by the following measures: supplying a sintered bonding material in which metal nanoparticles, such as silver nanoparticles, coated with an organic protective layer, are dispersed in an organic component, such that this material is present in the form of a paste or a sheet-like structure between the electrode 22 and the first semiconductor element 4 and the second semiconductor element 5, and heating the sintered bonding material at a transition temperature (250 °C in the case of silver nanoparticles) while applying pressure to bond the majority of the metal nanoparticles by sintering. If the electrode 22 is made of copper or nickel, which are easily oxidized, it is preferred to use a sintered bonding material that can remove an oxide layer and contains a reducing agent that can evaporate at the transition temperature or a lower temperature.

[0040] The sintered bonding material is a bonding material that utilizes a phenomenon whereby a metal is sintered at a temperature lower than a melting point in the volume due to the reactivity of the metal nanoparticles (the fine metal particles) in the nanometer range.

[0041] For the sintered bond material described in the present invention, metal nanoparticles made from a single metal classified as a precious metal, such as gold (Au), copper (Cu), palladium (Pd) and platinum (Pt), as well as metal nanoparticles made from an alloy containing the precious metal, such as Ag-Pd, Au-Si, AuGe and Au-Cu, can be used, as well as the Ag nanoparticles described above.

[0042] Of the aforementioned metal nanoparticles, the Ag nanoparticles, which consist of a metal that is hardly oxidized, so that the sintering process is not adversely affected, and which can be used at comparatively low cost, are preferred because the semiconductor device 1 can be manufactured at low cost. The electrode 22 of the circuit substrate 2, which is made of Cu, is particularly preferred because of its advantageous interconnect performance.

[0043] Since the metal nanoparticles exhibit high reactivity, sintering proceeds easily even at normal temperature through contact between the metal nanoparticles. Therefore, the metal nanoparticles used for the sinter bond material are coated with an organic protective layer to prevent clumping and the progression of the sintering reaction, and are kept dispersed in a state where each metal nanoparticle is separated from the others. It is preferred to use a material that, with respect to the organic protective layer and the organic component that disperses the metal nanoparticles, volatilizes or degrades and can be removed at the transition temperature or a lower temperature.

[0044] Since the organic component in the sintered bonding material degrades and the metal nanoparticles are bonded by sintering during the formation of bonding layer 3 using heat, the volume of the bonded area after bonding is reduced to 1 / 2 or 1 / 4 of the volume of sintered bonding material applied to the bonded area before heat application. Thus, heat is applied under additional pressure during the formation of bonding layer 3 to achieve a bonded area with fewer voids and therefore high reliability.

[0045] The compound layer 3, formed in the manner described above, has an organizational form such that the large number of very small pores in the submicrometer range, characteristic of the sintered body, are uniformly distributed. As described above, the compound layer 3 has a large number of pores, and the advantageous compound reliability can be achieved by specifying a crystalline grain fill rate of 80% or higher. The fill rate mentioned here refers to the fill rate of the second region 3b in a region of the compound layer 3 that is not in contact with the concave region 6.

[0046] A sintered bonding material comprising metal nanoparticles with a mean grain size of 50 nm or less is particularly preferred. This is because, when the mean grain size of the metal nanoparticles is 50 nm or less, the mean grain size of the crystal grains contained in the bonding layer 3, which is a sintered body produced by feeding the sintered bonding material to the bonding area and applying pressure and heat, can be kept at 150 nm or less, thus enabling the formation of the bonding layer 3, which exhibits advantageous deformability, as described below.

[0047] The metal nanoparticles in the sintered bond material, which have a small mean grain size, are also preferred because the filling rate of the second region 3b in the bonding layer 3 is increased to 80% or more, and the metal nanoparticles which have a mean grain size of 50 nm or less are particularly preferred.

[0048] After the sintered bond material has been supplied to each connection area in the electrode 22, from connection area 22a, which is in contact with the first semiconductor element 4, to connection area 22b, which is in contact with the second semiconductor element 5, the first semiconductor element 4 and the second semiconductor element 5 are arranged on the supplied sintered bond material, and then pressure and heat are applied to bond the first semiconductor element 4 and the second semiconductor element 5 to the electrode 22.

[0049] Even if the bonding layer 3 is formed in the manner described above, the concavely shaped area 6 is arranged in the electrode 22, so that when the first and second semiconductor elements 4 and 5 are joined by applying pressure, the compressibility of the sintered bond material caused by the application of pressure differs between the first area 3a, which is in contact with the concavely shaped area 6, and the second area 3b, which is not in contact with the concavely shaped area 6, in the bonding layer 3.

[0050] Consequently, the filling rate of the metal crystal grains in the first region 3a is lower than the filling rate of the metal crystal grains in the second region 3b of the compound layer 3, so that it can easily be caused that a crack forms in the first region 3a in the compound layer 3.

[0051] As described above, the area in the semiconductor device 1 of the present invention in which cracking in the interconnect layer 3 is caused can be controlled by arranging the concavely shaped area 6 in the predetermined area of ​​the electrode 22, so that cracking can be caused to occur in the predetermined area in order to reduce the stress on the entire interconnect layer 3, and furthermore, it can be caused that the occurrence of cracking in the interconnect layer 3 remains local, so that the interconnect reliability of the interconnect layer 3 can be improved.

[0052] Since the filling rate of the second area 3b in the bonding layer 3 is specified as 80% or higher, and the filling rate of the first area 3a is specified as being lower than that of the second area 3b or equal to or higher than 20% and lower than 80%, the occurrence of cracking in the first area 3a and the prevention of cracking in the second area 3b can be reliably carried out, and the bonding reliability of the bonding layer 3 can be further improved.

[0053] Since the bonding layer 3, as described above, is the sintered body of metal crystal grains which has a large number of pores, the filling rate of the second region 3b cannot be specified at 100%, but the adhesion force increases with increasing filling rate of the second region 3b, so that the filling rate of the second region is preferably specified as equal to or higher than 80% and less than 100%.

[0054] The hardness of electrode 22 of the circuit substrate 2 is preferably lower than that of the compound layer 3, in order to ensure that crack formation occurs more reliably in the first region 3a in the compound layer 3. The hardness of the compound layer 3 mentioned here refers to the hardness of the second region 3b, which is not in contact with the concave region 6. The hardness of electrode 22 and the second region 3b in the compound layer 3 can be compared, for example, using the Vickers hardness test.

[0055] Even if the hardness of electrode 22 is equal to that of the second region 3b of the interconnect layer 3, or even if the hardness of the electrode is higher, the first region 3a, which is in contact with the concave region 6, exhibits a low fill rate of metal crystal grains, resulting in a structure in which cracking readily occurs. Thus, cracking in the first region 3a is caused by stress when the semiconductor device is used in a high-temperature environment, and the stress on the interconnect layer 3 is reduced. However, the hardness of electrode 22 of the circuit substrate 2 is preferably lower than that of the interconnect layer 3, in order to ensure that cracking occurs more reliably in the first region 3a.

[0056] The hardness of electrode 22 can be reduced by softening it through a tempering process involving the application of heat at the time it is joined to the insulating plate 21 by soldering or casting, for example, to produce the circuit substrate 2. When electrode 22 is tempered, the grain size of the crystal particles in the electrode 22 becomes coarser. Therefore, it is preferred to specify the average grain size of the crystal particles in electrode 22 as approximately 100 µm and to soften the electrode 22 so that it has, for example, a Vickers hardness of 50 HV or less. The dimensions of the crystal particles can be evaluated by an electron backscatter diffraction (EBSD) method.

[0057] The crystal orientation at a grain boundary is defined as 5° or more, and a sample is evaluated, with a shape measured and displayed as an image to determine the dimensions of the crystal grains. The dimensions of the crystal grains of a sintered body, described below, which forms the compound layer 3, can be evaluated in a comparable manner.

[0058] Next, an experimental result is described, whereby the experiment was conducted to investigate properties of the compound layer 3. First, a procedure for preparing a sample used for the experiment is described.

[0059] A sintered bonding material containing silver nanoparticles with a mean grain size of 50 nm is printed and deposited onto a glass substrate to a thickness of 100 µm to 200 µm. A solution component is then dried. The sintered bonding material is sandwiched between two glass plates, and heat and pressure are applied under bonding conditions at a temperature of 260 °C to 350 °C, a welding pressure of 10 to 30 MPa, and a holding time of 90 to 300 seconds to produce a sintered specimen A. The mean crystal grain size of the sintered specimen A is 150 nm.

[0060] Next, the sintered body produced by the preceding method is heated without pressure for 60 minutes at a temperature of 350°C in a manner similar to that used for sintered specimen A, in order to produce a sintered body B with coarser crystal grains. The mean crystal grain size of sintered specimen B is 300 nm. The Vickers hardness of sintered specimen A and sintered specimen B is equal to or greater than 70 HV, and the Vickers hardness of electrode 22 of the circuit substrate 2 in the semiconductor device 1 is equal to or less than 50 HV, so that sintered specimen A and sintered specimen B have a Vickers hardness greater than that of electrode 22.

[0061] The sintered specimen A and the sintered specimen B, which were produced by the above method, were evaluated by a strain test in which the ambient temperature is changed. Fig. Figure 3 is a drawing that represents an experimental result of the strain test of the sintered specimen. Fig. Figure 3 represents a relationship between the ambient temperature and the strain percentage of sintered specimens A and B. The strain percentage is the percentage of the strain experienced by the sintered specimen during the strain test until it fractured, and it indicates that a material exhibits higher deformability as the strain percentage increases.

[0062] As in Fig. Figure 3 shows that the strain percentage of the sintered body, in the case of the sintered body formed by bonding the Ag nanoparticles through sintering, increases with increasing ambient temperature, thus increasing the deformability.

[0063] Fig. Figure 4 shows a diagram representing an experimental result of the strain test of the sintered specimen. Fig. Figure 4 represents a relationship between the mean grain size of the crystal grains and the strain percentage of the sintered specimen, using the ambient temperature as a parameter. As in Fig. Figure 4 shows that the strain percentage of the sintered body, in the case of the sintered body formed by bonding the Ag nanoparticles through sintering, increases with a reduction in the mean grain size of the crystal grains; thus, the deformability increases.

[0064] Even if Fig. 3 and Fig. 4. Considering a case where the metal nanoparticles in the sintered bond material are Ag nanoparticles, the strain percentage also increases with increasing ambient temperature in the case of a sintered body formed from other metal nanoparticles, and the strain percentage increases with a decrease in the mean grain size of the crystal grains in the sintered body.

[0065] Since the semiconductor element formed from a large bandgap semiconductor material, such as silicon carbide, has a transition operating temperature limit that is higher than that of the silicon-based semiconductor element, it is used in some cases in a high-temperature environment.

[0066] Although the semiconductor device using the silicon-based semiconductor element can only be used in a state where the junction area 3 has a temperature of substantially 150 °C or lower, the semiconductor device using the silicon carbide-based semiconductor element is in some cases used in a state where the junction area 3 has a high temperature, such as 250 °C.

[0067] It is preferred to use the compound layer 3 with a high deformability in the semiconductor device 1, which can be used at normal temperature or in an environment where the temperature changes from a range below zero to a high temperature, such as 250 °C; thus, the mean grain size of the crystal grains in the sintered body of the compound layer 3 is preferably small.

[0068] As in Fig. As shown in Figure 3, a strain percentage of 7% can be achieved at an ambient temperature of 175 °C if the mean grain size of the crystal grains in the sintered body of the compound layer is 150 nm; thus, the advantageous compound reliability can also be achieved with a semiconductor device formed from a wide-bandgap semiconductor material. That is, the mean grain size of the crystal grains in the sintered body of the compound layer 3 is preferably 1 to 150 nm when the sintered body of the compound layer 3 is used for the semiconductor device formed from a wide-bandgap semiconductor material.

[0069] While it is preferable to reduce the mean grain size of the crystal grains in the sintered body of the bonding layer 3 due to increased deformability, the mean grain size of the metal nanoparticles contained in the pre-sintering sinter-bond material used to form the sintered body must be small to achieve this reduction, and such a sinter-bond material is expensive. Furthermore, the heating temperature and pressure applied during the fabrication of the sintered body must be controlled with a high degree of accuracy, making such a production facility also costly.

[0070] When the semiconductor device 1, which is formed from the wide bandgap semiconductor material, is used in a condition in which the compound layer 3 has a temperature of 300 °C or a lower temperature, the mean grain size of the crystal grains in the sintered body of the compound layer 3 is preferably equal to 10 to 150 nm in order to reduce the cost of manufacturing a semiconductor device 1.

[0071] Next, an experimental result of a comparison of the semiconductor device according to embodiment 1 of the present invention with a conventional semiconductor device by means of a temperature cycle test is described. The semiconductor device 1 according to embodiment 1 of the present invention is a semiconductor device in which the concavely shaped region 6 is arranged in the electrode 22 of the circuit substrate 2, as described above, and the conventional semiconductor device is a semiconductor device in which a concavely shaped region is not arranged in an electrode of a circuit substrate. That is, the only difference is whether the concavely shaped region is arranged in the electrode of the interconnection area or not.

[0072] In the semiconductor device 1 according to embodiment 1, the sintered bond material, which contains the Ag nanoparticles with a mean grain size of 50 nm as metal nanoparticles, is printed and fed to the electrode 22 of the circuit substrate 2 such that it has a thickness of 100 µm to 200 µm, and the solvent component is dried.

[0073] Subsequently, the first semiconductor element 4 and the second semiconductor element 5 are arranged, and heat and pressure are applied under the joining condition at a temperature of 260 °C to 350 °C, a welding pressure of 10 to 30 MPa and a holding time of 90 to 300 seconds to form and join the compound layer 3, which is the sintered body.

[0074] The compound layer 3 that has been formed has a mean grain size of the crystal grains of 150 nm or less and a Vickers hardness of 70 HV or more, and the electrode 22 of the circuit substrate 2 has a crystal grain size of approximately 100 µm and a Vickers hardness of 50 HV or less.

[0075] The conventional semiconductor device is also fabricated using the same steps as those for the semiconductor device according to embodiment 1, as described above. Furthermore, in the conventional semiconductor device, the compound layer formed has a mean grain size of 150 nm or less and a Vickers hardness of 70 HV or more, and the electrode 22 of the circuit substrate 2 has a grain size of approximately 100 µm and a Vickers hardness of 50 HV or less.

[0076] Fig. Figure 5 is a cross-sectional view that schematically represents an aspect of the interconnect layer of the semiconductor device according to embodiment 1, which has been produced by the method described above. Fig. Figure 6 is a cross-sectional view that schematically represents one aspect of the interconnect layer of the conventional semiconductor device fabricated by the method described above. Each of Fig. 5 and Fig. Figure 6 represents an aspect of the interconnect layer of the semiconductor device prior to the temperature cycle test.

[0077] As in Fig. As shown in Figure 5, the interconnect layer 3 of the semiconductor device according to embodiment 1 has an organizational form such that the large number of very small pores 31 in the submicrometer range, which are characteristic of the sintered body, are distributed. However, the density of the pores 31 differs between the first region 3a, which is in contact with the concave region 6 formed in the electrode 22, and the second region 3b, which is not in contact with the concave region 6. That is, the density of the pores 31 in the first region 3a is greater than that of the pores 31 in the second region 3b.

[0078] This indicates that the first region 3a in the interconnect layer 3 has a lower metal crystal grain filling rate than the second region 3b. In the semiconductor device 1 produced according to embodiment 1 of the present invention, the metal crystal grain filling rate in the first region 3a in the interconnect layer 3 is 30% to 60%, and the metal crystal grain filling rate in the second region 3b is 80% or higher.

[0079] Meanwhile, the conventional semiconductor device, as in Fig. Figure 6 shows an organizational form such that the large number of very small pores 31 in the submicrometer range, which are characteristic of the sintered body, are distributed in the compound layer 3 in a similar manner to the semiconductor device 1 according to embodiment 1; however, the density of the pores 31 is almost uniform throughout the entire area of ​​the compound layer 3. The conventional semiconductor device produced exhibits a nearly uniform fill rate of the metal crystal grains in the compound layer 3 throughout its entire area, which is equal to 80% or higher.

[0080] The semiconductor device 1 according to embodiment 1 and the conventional semiconductor device manufactured as described above are compared by means of a temperature cycle test. In the temperature cycle test, the following pattern is defined as one cycle: increasing the temperature from 100 °C to 250 °C in one minute, holding the temperature at 250 °C for five seconds, decreasing the temperature from 250 °C to 100 °C in one minute, and then holding the temperature at 100 °C for five seconds, and this cycle is performed 8000 times.

[0081] Fig. Figure 7 is a cross-sectional view that schematically represents an aspect of the interconnect layer after the temperature cycle test of the semiconductor device according to embodiment 1. Fig. Figure 8 is a cross-sectional view that schematically represents an aspect of the interconnect layer after the temperature cycle test of the conventional semiconductor facility.

[0082] As in Fig. As shown in Figure 7, the region in the semiconductor device according to embodiment 1, in which the concavely shaped region 6 is formed, is deformed to have a wave-like shape, while the region away from the concavely shaped region 6 in the electrode 22 of the circuit substrate 2 is hardly deformed. This is because, when a low-temperature condition and a high-temperature condition are repeated in the temperature cycle test, each crystal grain forming the electrode 22 of the circuit substrate 2 is deformed in each preferred sliding direction, and the region in which the concavely shaped region 6 is formed in the electrode 22 is slightly deformed, preferably to have the wave-like shape.

[0083] Since the first region 3a of the bonding layer has a metal crystal grain filling rate that is lower than that of the second region 3b, crack formation 32 preferentially occurs in the first region 3a of the bonding layer 3. Consequently, the stress on the bonding layer 3 is reduced, and no significant deterioration is observed from this point; thus, the advantageous bonding performance is achieved.

[0084] Since the concavely shaped area 6 in the electrode 22 is formed, as described above, to form the first area 3a and the second area 3b, which have the different metal filling rates in the compound layer 3, the occurrence of cracking 32 in the compound layer 3 in a localized area can be prevented, and cracking 32 can be caused to occur by the design used.

[0085] Since the cracking 32 is caused by the configuration through the design used, the stress on the entire bonding layer 3 can be reduced, the cracking 32 that occurs in the bonding layer 3 can be caused to remain locally within the first area 3a, and the occurrence of the cracking in the second area 3b, which is a different area than the first area 3a in the bonding layer 3, can be prevented.

[0086] Meanwhile, the surface of electrode 22 of the circuit substrate 2 in the conventional semiconductor device, as in Fig. Figure 8 shows that the electrode is deformed across its entire area, and cracking 32 occurs throughout the entire area in the connection layer 3. Since the electrode 22 of the circuit substrate 2 is attached to the insulating plate 21 by soldering or casting, the electrode is tempered by a thermal history at the time of manufacture, and its crystal grain size increases to approximately 100 µm, and its hardness therefore decreases.

[0087] However, since heat of 260 to 350 °C, which is comparatively low, and pressure are applied to the metal nanoparticles to sinter the metal nanoparticles in the compound layer 3, the compound layer 3 is not tempered and therefore has a comparatively high hardness.

[0088] Since the electrode 22 of the circuit substrate 2 has a hardness that is less than that of the compound layer 3 and is therefore soft, as described above, each crystal grain forming the electrode 22 of the circuit substrate is deformed in each preferred sliding direction by the thermal stress due to a repetition of the low-temperature and high-temperature conditions in the temperature cycle test, and the electrode 22 is deformed such that, because the concave-shaped region is not arranged in the electrode 22, unlike in the semiconductor device 1 according to embodiment 1, it has a wavy shape over the entire region.

[0089] Consequently, it is considered that a high thermal stress occurs in the compound layer 3, and that the compound layer 3 cannot follow the deformation of the electrode 22, so that the cracking 32 occurs over the entire area of ​​the compound layer 3.

[0090] An adhesion force is measured to evaluate the connection reliability of the semiconductor device according to embodiment 1 and the conventional semiconductor device after the temperature cycle test. To measure the adhesion force, a load is applied to the semiconductor element (the chip), and the force with which the semiconductor element is detached from the electrode 22 of the circuit substrate 2 (unit: MPa) is measured using a shear force measuring device (manufactured by Dage Corporation: HS4000 shear force measuring device).

[0091] As a result, the adhesion force of the semiconductor device 1 according to embodiment 1 is 1 to 40 MPa, and the adhesion force of the conventional semiconductor device is 20 MPa. As described above, the semiconductor device 1 according to embodiment 1 can cause the crack formation 32 to remain within the first region 3a, which is in contact with the concavely shaped region 6 in the interconnect layer 3, so that excellent interconnect reliability can be achieved. In contrast, with the conventional semiconductor device, the crack formation 32 occurs throughout the entire area of ​​the interconnect layer 3, so that sufficient interconnect reliability cannot be achieved.

[0092] As described above, the concavely shaped region 6 in the semiconductor device according to embodiment 1 of the present invention is arranged in the region of the connection surface of the electrode 22 of the circuit substrate 2, such that the first region 3a, which is in contact with the concavely formed region 6, has a filling rate of the metal crystal grains that is lower than that of the second region 3b, which is a different region than the first region 3a in the connection layer 3, which is the sintered body.

[0093] Accordingly, the area in which the electrode 22 is deformed in a high-temperature environment and cracking 32 occurs in the connection layer 3 can be easily limited. Consequently, the above configuration exhibits a constellation in which the localized cracking 32 is caused by design, thus reducing the stress on the entire connection layer 3, and the occurrence of the localized cracking 32 therefore enables a significant improvement in connection reliability.

[0094] The mean grain size of the crystal grains in the compound layer 3 is specified as 1 nm to 150 nm, preferably 10 to 150 nm, so that the compound layer 3 can be obtained which also exhibits excellent deformability in the environment with a high temperature, and the occurrence of crack formation 32 in the second region 3b, which is not in contact with the concavely shaped region 6 of the compound layer 3, can be prevented, so that in the above configuration the effect occurs in which the advantageous compound reliability can also be achieved in the semiconductor device which has the semiconductor element formed from the wide bandgap semiconductor material, which is used in an environment with a higher temperature than the semiconductor element with the conventional silicon semiconductor.

[0095] Next, a method for manufacturing the semiconductor device according to embodiment 1 of the present invention is described. Fig. Diagrams 9A to 9E illustrate the method for manufacturing the semiconductor device according to embodiment 1 of the present invention.

[0096] First, the electrodes 22 and 23, which are made of a metal such as Cu, Al and Ni, are prepared as shown in Fig. Figure 9A shows the two surfaces of the insulating plate 21, which is formed, for example, from a silicon nitride ceramic plate, being joined by soldering or casting to form the circuit substrate 2. The metal forming the electrodes 22 and 23 can be a single metal, but an alloy containing, for example, Cu, Al, or Ni is also suitable.

[0097] The electrodes 22 and 23 are tempered by means of the applied heat. Accordingly, soldering or casting is carried out to join the electrodes 22 and 23 to the insulating plate 23 while the metal forming the electrodes 22 and 23 is tempered.

[0098] Although the conditions for tempering vary depending on the type of metal, softening begins at a temperature of 200 to 300 °C when, for example, copper or a copper alloy is used. As the heating temperature and duration increase, the softening process continues and the hardness decreases. That is, the heating temperature at the time of tempering is equal to or higher than the temperature at which softening begins, and it is lower than the melting point of the metal.

[0099] In the semiconductor device of the present invention, the electrode 22 preferably has a Vickers hardness of 50 HV or less, so that the tempering process is carried out by combining the heating temperature and the heating time period in such a way that the electrode 22 has a Vickers hardness of 50 HV or less.

[0100] Next, the concave-shaped area 6, as shown in Fig. 9B is shown, for example, by means of a removal process sequence through mechanical processing, by compression molding using a pressing process or a chemical removal process sequence through an etching process in the electrode 22.

[0101] As in Fig. 9C is shown, which corresponds to the connection area at electrode 22 of the circuit substrate 2 (see Fig. 2) a sintered bonding material 33 containing the metal nanoparticles, such as Ag, is supplied to bond the circuit substrate 2, in which the concave shaped region 6 is formed in the manner described above, to the first and second semiconductor elements 4 and 5.

[0102] The sintered bond material 33 can be supplied by printing it in paste form or by applying it in planar form. If the sintered bond material 33 is in paste form, it can also be printed or supplied to the back electrode on the surface of the rear side of the first and second semiconductor elements 4 and 5.

[0103] Subsequently, the first and second semiconductor elements 4 and 5 are connected, as shown in Fig. Figure 9D shows the sintered bond material 33 being arranged at the connection area in the electrode 22 of the circuit substrate 2. As described above, the sintered bond material 33 is supplied to the electrode 22 of the circuit substrate 2 or to the back electrode of the first and second semiconductor elements 4 and 5; thus, the sintered bond material 33 has a configuration in which it is sandwiched between the first and second semiconductor elements 4 and 5 and the circuit substrate 2.

[0104] Subsequently, the sintered bond material 33, which is arranged in a sandwich-like manner between the first and second semiconductor elements 4 and 5 and the circuit substrate 2, is applied as shown in Fig. Figure 9E shows that the metal nanoparticles are heated to a temperature of 260 to 350 °C while a pressure of 20 to 30 MPa is applied. As a result, the metal nanoparticles in the sintered bond material 33 are bonded by sintering, the bonding layer 3, which is the sintered body, is formed, and the electrode 22 of the circuit substrate 2 and the first and second semiconductor elements 4 and 5 are connected to each other, so that the semiconductor device 1 can be manufactured.

[0105] The Fig. Figures 10A to 10E are diagrams illustrating a further method for manufacturing the semiconductor device according to embodiment 1 of the present invention. The method for manufacturing the semiconductor device, which is described in the Fig. The process shown in 10A to 10E differs from the method for manufacturing the semiconductor device described in the Fig. Figures 9A to 9E illustrate the procedure for producing the circuit substrate 2, and they exhibit the same subsequent steps. That is to say, the steps shown in the Fig. The steps shown in sections 10C to 10E are the same as those in the Fig. The steps shown in sections 9C to 9E are described above; therefore, a detailed description is omitted here.

[0106] The process for manufacturing the semiconductor device, which is described in the Fig. As shown in Figures 10A to 10E, the concave-shaped area 6 in the electrode 22 is pre-formed, and the electrode 22 is subsequently connected to the insulating plate 21 to create the circuit substrate 2. As shown in Fig. As shown in Figure 10A, the concavely shaped area 6 is formed, for example, by means of a removal process through mechanical processing, a compression molding process through a printing process, or a chemical removal process through an etching process.

[0107] As in Fig. As shown in Figure 10B, the electrode 22, in which the concave region 6 is formed, is subsequently connected to one surface of the insulating plate 21, which is formed, for example, from a silicon nitride ceramic plate, and the electrode 23, in which the concave region 6 is not formed, is connected to the other surface. The electrodes 22 and 23 are joined to the insulating plate 21 by soldering or casting and are tempered by the applied heat.

[0108] That is, electrodes 22 and 23 are annealed and connected to the insulating plate 21. According to the preceding steps, the circuit substrate 2, which has the concavely shaped region 6 formed in electrode 22, is prepared as shown in Fig. 10B is shown. The steps are then carried out according to the Fig. 10C to 10E were carried out, which involved the same steps as the steps described above in the Fig. 9C to 9E; thus, semiconductor element 1 can be manufactured.

[0109] Since the concave-shaped region 6 in the electrode 22 is pre-formed as described above, the electrode 22 can be processed separately, and the cycle time required to perform the steps can be reduced, for example, by processing the majority of electrodes 22 together. As a result, the manufacturing costs for the semiconductor device 1 can be reduced. Design 2

[0110] Fig. Figure 11 is a cross-sectional view schematically representing a structure near a junction layer of a semiconductor device according to embodiment 2 of the present invention. Fig. 11. The same reference symbols are assigned to the same or a corresponding single element as those in Fig. 5 as described in embodiment 1, and the description thereof is omitted. Embodiment 2 of the present invention differs from embodiment 1 in that a metallized layer 24 is arranged on the surface of the electrode 22 of the circuit substrate 2, and an advantageous transition is achieved using a sintered bonding material containing the metal nanoparticles, irrespective of the material of the electrode 22.

[0111] The metallized layer 24 is formed by laminating a metal material that differs from that of the electrode 22, for example by means of a process such as plating, evaporation coating and sputtering, onto the surface of the electrode 22 after the concave shaped area 6 has been formed in the electrode 22 of the circuit substrate 2.

[0112] Since the metallized layer 24 only needs to be formed thinly on the surface of the electrode 22 to be bonded to the bonding layer 3, the metallized layer can have a thickness of approximately 10 nm to 10 µm. The metallized layer 24 improves a favorable transition with the bonding layer 3, which is formed from the sintered bonding material containing the metal nanoparticles. The metallized layer 24 is formed from a single metal selected from Au, Pt, Pd, Ag, or Cu, or from a metal material consisting of an alloy containing one of these metals.

[0113] The metallized layer 24 is applied to the surface of the electrode 22 as described above; thus, the material for the electrode 22 can be selected without regard to its bonding performance with the bonding layer 3, which is formed from the sintered bonding material containing the metal nanoparticles. That is, the electrode 22 material only needs to have excellent conductivity, and copper, aluminum (Al), or an alloy containing these materials as a major component, for example, can be applied to the material. This increases the degree of freedom in selecting the electrode 22 material.

[0114] Although Al is particularly suitable for the material of the electrode 22 because it has excellent machinability, it does not possess the advantageous bonding performance with the bonding layer 3 formed from the sintered bonding material; thus, an electrode 22 which has excellent machinability and excellent bonding performance can be obtained by applying the metallized layer 24 to the surface of the electrode 22 formed from Al.

[0115] A metallized layer 24, which has a lower hardness than the compound layer 3, can be used. Accordingly, the metallized layer 24 can follow the deformation of the electrode 22, even if the electrode 22 of the circuit substrate 2 is deformed to have a wavy shape when used in a high-temperature environment. Thus, the detachment of the metallized layer 24 from the electrode 22 can be prevented, and the advantageous connection reliability can be achieved in a manner similar to that of the semiconductor device described in embodiment 1.

[0116] As described above, embodiment 2 of the present invention has the effect that the material of the electrode 22 of the circuit substrate 2 can be selected regardless of the compatibility of the connection performance with the interconnection layer 3, which is formed from the sintered bond material containing the metal nanoparticles, and the advantageous connection reliability with the interconnection layer 3 can be ensured by the metallized layer 24. Thus, a semiconductor device exhibiting excellent connection reliability can also be achieved in a high-temperature environment. embodiment 3

[0117] The Fig. Figures 12A to 12D are top and side cross-sectional views depicting a circuit substrate of a semiconductor device according to embodiment 3 of the present invention. Fig. 12A to 12D are assigned the same reference symbols to the same or corresponding individual elements as those used in connection with Fig. 2 are described in embodiment 1, and the description thereof is omitted. Embodiment 3 differs from embodiment 1 of the present invention with respect to the formation of a pattern of the concavely shaped area 6 formed in the electrode 22.

[0118] Fig. Figure 12A is a top view of the circuit substrate 2, in which the concave shaped area 6 is formed such that it is distributed over the entire area in the connection areas 22a and 22b in a state in which the electrode 22 is viewed from the top surface, and Fig. Figure 12B is a cross-sectional view of the circuit substrate 2 along a dashed line AB in Fig. 12A.

[0119] In Fig. 2 In embodiment 1, the concavely shaped area 6 is configured such that it has the grid-like groove shape in the connection areas 22a and 22b in the state in which the electrode 22 is viewed from the upper surface. However, the formation pattern of the concavely shaped area 6 is not limited to this; the concavely shaped area 6 can also be configured such that it has the hole-like shape that is visible when viewed from the upper surface, as in Fig. 12A, is distributed across the entire area in connection areas 22a and 22b.

[0120] Furthermore, the concavely shaped area 6 does not necessarily have to be uniformly arranged throughout the entire area in the connection areas 22a and 22b in the electrode 22, but can be arranged in an area that has a low influence even in a state in which crack formation is caused by design or by design in the connection layer. Fig. Figure 12C is a top view of the circuit substrate 2, in which the concave shaped area 6 is formed only in an outer peripheral area of ​​the connection areas 22a and 22b in the electrode 22, and Fig. 12D is a cross-sectional view of the circuit substrate 2 along a dashed line CD in Fig. 12C.

[0121] For the interconnect layer 3, a function is required by which the heat of the first semiconductor element 4 and the second semiconductor element 5 is radiated to the circuit substrate 2, and a heat-generating region in the first semiconductor element 4 and the second semiconductor element 5 is in many cases located in a central region of the semiconductor element.

[0122] Accordingly, the configuration according to embodiment 3 has the effect that the area in which crack formation is caused by design or by construction in the compound layer 3 is located in an area other than the heat-generating area, such as the central area of ​​the semiconductor element, thus the semiconductor device 1, which has the advantageous compound reliability, can be achieved without adversely affecting the function as a heat dissipation path required for the compound layer 3.

[0123] The formation pattern of the concavely shaped area 6 is not limited to those shown in embodiment 1 and the present embodiment 3; however, the formation patterns shown in those embodiments can be combined with one another. For example, a formation pattern is also applicable such that the concavely shaped area 6 is distributed over the outer peripheral area of ​​the connecting areas 22a and 22b, as shown in Fig. 12A, and the grid pattern in the central area of ​​the connecting areas 22a and 22b is as shown in Fig. 2 shown in embodiment 1.

[0124] To achieve the advantageous connection reliability, a further formation pattern, which is not described in the respective embodiments of the present invention, is also applicable, as long as it causes the crack formation to occur selectively in the first area 3a, which is in contact with the concavely shaped area 6 in the connection layer 3, and causes the crack formation not to occur in the second area 3b, which is not in contact with the concavely shaped area 6.

[0125] If the formation pattern of the concavely shaped region 6 has a symmetrical shape with line symmetry or point symmetry, the unevenness of crack formation that occurs in the first region 3a in the connection layer 3 can be prevented. In the case of the line-symmetric formation pattern, the formation patterns on both sides overlap when the first region 3a is folded along a specific straight line, and this specific straight line can be a straight line passing through the center of connection regions 22a and 22b. In the case of the point-symmetric formation pattern, the formation pattern coincides with the initial formation pattern before a rotation when the first region 3a is rotated 180 degrees around a specific point, and this specific point can be the center of connection regions 22a and 22b.

[0126] Cracking occurs in the first region 3a of the compound layer 3, and this region has a metal crystal grain filling rate that is lower than that of the second region 3b. Consequently, the first region 3a exhibits electrical and thermal conductivity that are lower than those of the second region 3a in the compound layer 3. Accordingly, an excessively large ratio of the total area of ​​the first region 3a to the area of ​​the compound region 22a or 22b in the electrode 22 results in an increase in electrical or thermal resistance in the compound layer 3, potentially causing problems in some cases. Therefore, the ratio of the total area of ​​the concave region 6 in each compound region to the area of ​​the compound region 22a or 22b in the electrode 22 is preferably 1% to 50% and more preferably 1% to 20%.

[0127] The reduction in electrical and thermal conductivity is determined in a linear functional form by the ratio of the total area of ​​the concave region 6 to the area of ​​the connection region. However, in a case where the connection layer 3 is thin, there is little effect on the reduction in electrical and thermal conductivity compared to the case where the connection layer 3 is thick.

[0128] In a case where the thickness of the compound layer 3 is approximately 100 µm, the ratio of the total area of ​​the concavely shaped region 6 is preferably 1 to 20%, but in the case where the thickness of the compound layer 3 is approximately 25 µm, the electrical conductivity and the thermal conductivity can be kept at a level similar to that in the case where the thickness of the compound layer 3 is approximately 100 µm, even if the ratio of the total area of ​​the concavely shaped region 6 is 1 to 80%.

[0129] However, if the ratio of the total area of ​​the concave shaped region 6 is greater than 50%, the strength of the interconnect layer 3 decreases, and the semiconductor element easily detaches from the electrode 22 of the circuit substrate; thus, the ratio of the total area of ​​the concave shaped region 6 is preferably equal to 50% or less.

[0130] Furthermore, if the ratio of the total area of ​​the concavely shaped region 6 to the area of ​​the connection area in the electrode 22 is equal to 1%, it can be caused that the cracking occurs directly above the concavely shaped region 6 of the connection layer 3, and the stress can be reduced as described in embodiment 1, and the effect of an improvement in connection reliability can be achieved.

[0131] If the ratio of the total area of ​​the concavely shaped region 6 is small, such as 1%, the reduction in electrical conductivity and thermal conductivity may cause a small problem; therefore, the ratio of the total area of ​​the concavely shaped region 6 to the area of ​​the connection region in the electrode 22 must be at least equal to 1%, regardless of the thickness of the connection layer 3. Design 4

[0132] Fig. Figure 13 is a cross-sectional view schematically representing a structure near a junction layer of a semiconductor device according to embodiment 4 of the present invention. Fig. 13. The same reference symbols are assigned to the same or corresponding individual elements as those assigned in Fig. 5 are described in embodiment 1, and the description thereof is omitted. In embodiment 1 of the present invention, a concavely shaped region 6 is arranged in the electrode 22; however, embodiment 4 differs from embodiment 1 in that a convexly shaped region 7 is arranged in the electrode 22.

[0133] The convexly shaped region 7 can be formed by removing an area in the electrode 22, excluding the convexly shaped region 7, for example, by mechanical machining or etching. The shape of the convexly shaped region 7 can be trapezoidal, as shown in Fig. 11 shown, can be a rectangular shape or a hemispherical shape, or it can also be a shape such as a circular cone or a pyramid.

[0134] A convexly shaped region 7 can be arranged linearly such that it exhibits a grid formation pattern similar to those described in embodiment 1 and embodiment 3, or it can be distributed in point form throughout the entire area within the connection region. That is, the formation pattern of the convexly shaped region 7 is not limited to a specific formation pattern as described in embodiment 3.

[0135] When the convexly shaped region 7 is arranged in the electrode 22, the region between the convexly shaped region 7 of the interconnect layer 3 and the back electrode 4d of the semiconductor element 4 serves as the first region 3a, and the other region serves as the second region 3b. When the convexly shaped region 7 is arranged in the electrode 22, the first region 3a has a layer thickness that is less than that of the second region 3b, and the first region 3a has a metal crystal grain filling rate that is higher than that of the second region 3b.

[0136] In such a case, too, the filling rate of the metal crystal grains in the second region 3b is preferably 80% or higher and less than 100%. The layer thickness of the first region 3a can also be defined by a distance between an upper region of the convexly shaped region 7, that is, a region that has the smallest distance to the rear electrode 4d of the semiconductor element 4, and the rear electrode 4d.

[0137] As shown in embodiment 4, the thermal stress occurring in the compound layer 3 at the time when the semiconductor device is used in a high-temperature environment is concentrated in the convex-shaped region 7 when the convex-shaped region 7 is formed in the electrode 22, and the stress increases locally in the first region 3a which is in contact with the convex-shaped region 7 of the compound layer 3.

[0138] Thus, the occurrence of cracking in the first region 3a or at an interface between the first region 3a and the second region 3b can be induced by a suitable design. Accordingly, the occurrence of cracking in the second region 3b, which is not in contact with the convexly shaped region 7 of the bonding layer 3, can be prevented, and the bond reliability of the bonding layer 3 can be improved.

[0139] The semiconductor device in which the convexly shaped region 7 is formed in the electrode, as described in the present embodiment 4, can also be manufactured using the manufacturing process described in embodiment 1. That is, the convexly shaped region 7 can be formed by removing the area in the electrode 22, with the exception of the convexly shaped region 7, for example, by means of a removal process such as mechanical processing or a chemical removal process such as etching, in a manner similar to the formation of the concavely shaped region 6 in the electrode 22, as described in the description of Fig. 9B and Fig. 10A is described. The subsequent steps are the same as described in embodiment 1.

[0140] As described above, the convexly shaped region 7, according to embodiment 4 of the present invention, is formed in the electrode 22 in the predetermined pattern to cause cracking to occur in the first region 3a, which is in contact with the convexly shaped region 7 of the compound layer 3, and to prevent cracking in the second region 3b, which is not in contact with the convexly shaped region 7. Thus, an effect similar to that described in embodiment 1 can be achieved, and a semiconductor device with advantageous connection reliability can be obtained.

[0141] As described above, the concave-shaped region can be arranged in the electrode 22 as described in embodiment 1, or the convex-shaped region can be arranged as described in embodiment 4. It is not only possible for one of the concave-shaped region and the convex-shaped region to be arranged separately, but also for both the concave-shaped region and the convex-shaped region to be arranged in the electrode 22 in a mixed configuration. EXPLANATION OF REFERENCE MARKS 1 Semiconductor device 2 Circuit substrate 21 insulating plate 22 electrode 22a Connection area 22b Connection area 3. Bonding layer 3a first area 3b second area 33 Sintered Bond Material 4 first semiconductor element 5 second semiconductor element 6 concave shaped area 7 convex shaped area

Claims

[1] Semiconductor device comprising the following: - an insulating plate (21); - an electrode (22) which is arranged on the insulating plate (21) and has a concave area; - a compound layer (3) made from a sintered body of metal crystal grains arranged at the electrode (22); and - a semiconductor element (4, 5) connected to the electrode (22), wherein the interconnect layer (3) is located between them, the concave region not reaching an end region of an interconnect surface between the electrode (22) and the interconnect layer (3). [2] Semiconductor device according to claim 1, wherein the concave region is formed in the surface of the electrode (22). [3] Semiconductor device according to claim 1 or 2, wherein a pattern of the concave region in a planar view is symmetrical with respect to the center of the semiconductor element (4, 5). [4] Semiconductor device according to any one of claims 1 to 3, wherein the total area of ​​the concave region in a planar view is equal to 1% to 20% of the total area of ​​the interconnect layer (3). [5] Semiconductor device according to any one of claims 1 to 4, wherein the mean grain size of the metal crystal grains is equal to or greater than 10 nm and equal to or less than 150 nm. [6] Semiconductor device according to any one of claims 1 to 5, wherein the material of the metal crystal grains is Ag. [7] Semiconductor device according to any one of claims 1 to 6, wherein the material of the electrode (22) is Cu or Al. [8] Semiconductor device according to any one of claims 1 to 7, wherein a metal layer (24) made of a metal material that differs from a metal material of the electrode (22) is arranged between the electrode (22) and the interconnect layer (3). [9] Semiconductor device according to claim 8, wherein the material of the metal layer (24) is a metal made of one of Au, Pt, Pd, Ag and Cu or an alloy containing a substance of Au, Pt, Pd, Ag and Cu. [10] Semiconductor device according to any one of claims 1 to 9, wherein the semiconductor element (4, 5) is formed from a large band gap semiconductor material having a band gap larger than that of silicon. [11] Semiconductor device according to claim 10, wherein the large band gap semiconductor material is one of silicon carbide, gallium nitride, gallium arsenide and diamond. [12] Method for manufacturing a semiconductor device comprising the following steps: - Arranging a semiconductor element (4, 5) by means of a sintered bonding material containing metal nanoparticles on an electrode (22) which is connected to an insulating plate (21); and - Connecting the electrode (22) and the semiconductor element (4, 5) by heating the insulating plate (21) and the semiconductor element (4, 5) while applying pressure, bonding the sinter-bond material by sintering and forming a bonding layer (3) that is in contact with the electrode (22), wherein: - the electrode (22) is tempered in order to be connected to the insulating plate (21); - the electrode (22) has a concave area; and - the concave area does not reach an end area of ​​a connection surface between the electrode (22) and the connection layer (3).

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