Systems and procedures for command authorization

Abstract

A device (102) comprising: a memory (104) and a control unit (130) coupled to the memory, wherein the control device (130), while in a first mode, is configured to receive, by means of a first command (162), a signal (164) authorizing the execution of a second command, which is classified as an unauthorized command by data available to the control unit (130), and wherein the control device (130) is further configured to modify the data authorizing the execution of the second command in response to the specification (164) while the control device (130) is in the first mode.

Description

Territory of Revelation

[0001] This revelation generally refers to an authorization to issue commands. background

[0002] Non-volatile data storage devices, such as embedded storage devices and removable storage devices (for example, removable USB (Universal Serial Bus) flash memory devices and other removable memory cards), have been approved for increased portability of data and software applications. Users of non-volatile data storage devices are increasingly relying on them to store large amounts of data and ensure fast access to it.

[0003] Many data storage devices can operate in a multitude of different modes. For example, certain data storage devices can operate in a command queue module if a command queue is released and not empty. Each mode of operation can have a set of operations that are authorized (for example, permitted) to be executed by the data storage device. The set of authorized commands can include all commands recognized by the data storage device. This means that some commands may not be authorized to execute during operation in particular modes. In order to execute an unauthorized command, the data storage device must exit the operating mode.While operating in command queue mode, a data storage device may need to exit command queue mode to execute a command that is not authorized for execution in command queue mode. This can be done, for example, by clearing the command queue of all pending commands (without executing the pending commands) or by executing each of the pending commands in the command queue to clear the queue. After the command queue is cleared, the device may be able to change modes and execute commands that are not authorized in command queue mode. Clearing the command queue of pending commands or executing all pending commands in the command queue delays the execution of a command that is not authorized in command queue mode.

[0004] US 2012 / 0 203 986 A1 concerns the management of operations for data storage media, wherein an adaptation module interrupts or otherwise modifies the execution of an operation performed on the data storage medium. US 2011 / 0 055 453 A1 concerns a NAND flash memory with a control circuit that processes instructions and allows program and / or erase instructions to be interrupted by read instructions.

[0005] The task is to enable the execution of commands not authorized for a given mode without changing the mode. Brief description of the drawings Fig. Figure 1 is a block diagram of a special illustrative example of a system which includes a data storage device that can be operated to authorise the execution of an unauthorized instruction; Fig.Figure 2 is a special illustrative example of the operation of the data storage device of Fig. 1; Fig. Figure 3 is a flowchart of a special illustrative example of a procedure for authorizing the execution of an unauthorized command; and Fig. Figure 4 is a flowchart of the special illustrative example of a procedure for sending a notification that the execution of an unauthorized command is authorized. Detailed description

[0006] This disclosure describes systems and methods for authorizing the execution of special instructions while a data storage device is in a first mode, such as an instruction queue mode. While operating in first mode (for example, while an instruction queue is released and occupied), the data storage device can receive a prompt from an accessing device, such as a host device, to authorize (for example, allow) the execution of a specific or special instruction that is not authorized during operation in first mode (for example, an unauthorized or unauthorized instruction). Upon receiving the prompt, the data storage device can temporarily authorize the execution of the special instruction while it is in first mode. For illustration, the data storage device can maintain an array of bits, each bit corresponding to a different instruction.The value of a specific bit can indicate whether a corresponding instruction is categorized as authorized or unauthorized during operation in first mode. To (temporarily) authorize the execution of the instruction, the data storage device can change the bit value corresponding to the instruction from a first value (e.g., a logical zero) to a second value (e.g., a logical one). After the instruction has been executed while operating in first mode, the data storage device can change the bit value corresponding to the instruction from the second value (e.g., a logical one) back to the first value (e.g., a logical zero) to categorize the instruction as unauthorized (i.e., forbidden).Thus, the present disclosure enables a device configured in the first mode (for example, the command queue mode) to temporarily authorize the execution of an otherwise unauthorized command without switching from the first mode to the second mode (for example, by emptying the command queue).

[0007] Fig. Figure 1 presents a simplified example of a system 100. The system 100 includes a data storage device 102 and an access device 170. The data storage device 102 includes a control unit 130 and a storage device 103 coupled to the control unit 130. The storage device 103 can contain one or more memory chips.

[0008] The data storage device 102 and the access device 170 can be coupled by means of a connection (for example, a communication path 180), such as a bus or a wireless connection. The data storage device 102 can include a first interface 110 (for example, an eMMC (embedded multimedia card) interface) which allows communication via the communication path (180) to the data storage device 102 and the access device 170.

[0009] In some implementations, the data storage device 102 can be attached to or embedded within one or more access devices, such as within an enclosure of the access device 170. For example, the data storage device 102 can be embedded within the access device 170, as per a Joint Electron Devices Engineering Council (JEDEC) - Solid State Technology Association Universal Flash Storage (UFS) configuration. As illustrative examples, the data storage device 102 can also be configured to be coupled or embedded with the access device 170 as embedded storage, such as eMMC® (trademark of JEDEC - Solid State Technology Association, Arlington, Virginia) and eSD.For illustration, the data storage device 102 can correspond to an eMMC (embedded multimedia card) device. As another example, the data storage device 102 can correspond to a memory card, such as a secure digital (SDO) card, a micro-SDO card, a mini-SD™ card (trademark of SD-3C LLC, Wilmington, Delaware), a MultiMediaCard™ (MMC™) card (trademark of JEDEC-Solid State Technology Association, Arlington, Virginia), or a CompactFlash® (CF) card (trademark of SanDisk Corporation, Milpitas, California).For further illustration, the data storage device 102 can be integrated into a device such as a mobile phone, computer, laptop, tablet or notebook computer, music player, video player, gaming device or console, electronic book reader, personal digital assistant (PDA), portable navigation device, vehicle electronic system or other device that uses non-volatile memory.

[0010] In other implementations, the data storage device 102 can be implemented in a portable device designed to be selectively coupled to one or more external access devices. For example, the data storage device 102 can be removable from the access device 170 (that is, it is "removably" coupled" to the access device 170). As an example, the data storage device 102 can be coupled to the access device 170 according to a removable USB (Universal Serial Bus) configuration. In still other implementations, the data storage device 102 can be a component (for example, a solid-state drive (SSD)) of a network-accessible data storage system, such as a corporate data system, a network-attached storage system, a cloud data storage system, etc.

[0011] In some implementations, the data storage device 102 may contain or be equivalent to a solid-state drive (SSD) that is contained in or different from (and accessible to) the access device 170. As illustrative, non-limiting examples, the data storage device 102 may, for instance, contain or be equivalent to a solid-state drive (SSD) that can be used as an embedded storage drive (e.g., a mobile embedded storage drive), an enterprise storage drive (ESD), a client storage device, or a cloud storage device. In some implementations, the data storage device 102 may be indirectly coupled to the access device 170, for example, via a network.The network may include, for example, a data center storage system network, an enterprise storage system network, a storage area network, a cloud storage network, a local area network (LAN), a wide area network (WAN), the internet, and / or another network. In some implementations, the data storage device 102 may be a network-attached storage (NAS) device or a component (for example, a solid-state drive (SSD) device) of a data center storage system, an enterprise storage system, or a storage area network.

[0012] The data storage device 102 can operate in accordance with a JEDEC industry specification. For example, the data storage device 102 can operate in accordance with a JEDEC eMMC specification, a JEDEC Universal Flash Storage (UFS) specification, one or more other specifications, or a combination thereof. In some implementations, the data storage device 102 and the access device 170 can be designed as illustrative, non-limiting examples to communicate using one or more protocols, such as an eMMC protocol, a Universal Flash Storage (UFS) protocol, a Universal Serial Bus (USB) protocol, a SATA Serial Advanced Technology Port protocol, and / or another protocol.

[0013] The access device 170 may include a third interface 172 (an eMMC interface), and it may be designed or configured to communicate with the data storage device 102 via the third interface 172 to read data from and write data to the storage device 103 of the data storage device 102. The access device 170 may, for example, operate in accordance with a JEDEC Interconnect Engineering Council of Electronic Devices - Industry Specification, such as a UFS Universal Flash Memory Access Control Device Interface Specification. As other examples, the access device 170 may operate in accordance with one or more other specifications, such as a Secure Digital (SD) Access Control Device Specification, as an illustrative, non-limiting example.

[0014] The access device 170 can communicate with the storage device 103 according to any other suitable communication protocol.

[0015] The access device 170 can contain a processor 174 and a memory 176. The memory 176 can be configured to store data and / or instructions that can be executed by the processor 174. The memory 176 can be a single memory or it can contain multiple memories, such as one or more non-volatile memories, one or more volatile memories, or a combination thereof. The access device 170 can issue one or more instructions to the data storage device 102, such as one or more requests to delete data, to read data from, or to write data to the data storage device 103. For example, the access device 170 can be configured to provide data, such as user data 160, to be stored in the data storage device 103 or to request data to be read from the data storage device 103.The access device 170 can, by way of illustrative, non-limiting examples, correspond to a mobile phone, a computer (for example, a laptop, tablet or notebook computer), a music player, a video player, a gaming device or console, an electronic book reader, a personal digital assistant (PDA), a portable navigation device, a computer such as a laptop computer or notebook computer, a network computer, a server, a traffic electronics system or any other electronic device or a combination thereof.

[0016] The storage device 103 of the data storage device 102 can contain one or more memory chips (for example, one memory chip, two memory chips, eight memory chips, or any other number of memory chips). The storage device 103 contains a memory 104, such as non-volatile memory consisting of memory elements contained within a memory chip. As an illustrative, non-limiting example, the memory 104 can, for instance, contain flash memory, such as NAND flash memory. The memory 104 can have a three-dimensional (3D) memory configuration. For example, the memory 104 can have a vertical 3D bit-line (VBL) configuration. In a particular implementation, the memory 104 contains non-volatile memory with a 3D memory configuration arranged in one or more physical layers of rows of memory elements (e.g.,The memory cells are monolithically formed, with an active area arranged above a silicon substrate. Alternatively, the memory 104 can have a different configuration, such as a two-dimensional (2D) memory configuration or a non-monolithic 3D memory configuration (e.g., a stacked chip 3D memory configuration).

[0017] The storage device 103 (and / or the memory 104) may contain a circuit arrangement associated with the operation of the memory elements of the memory 104. For example, the storage device 103 (and / or the memory 104) may contain a support circuit arrangement, such as a read / write circuit arrangement 113, to support the operation of one or more memory chips of the storage device 103. Although the read / write circuit arrangement 113 is shown as a single component, it may be divided into separate components of the storage device 103, such as a read circuit arrangement and a write circuit arrangement. The read / write circuit arrangement or circuit 113 may be located outside of the one or more memory chips of the storage device 103.Alternatively, one or more individual memory chips of the storage device 103 can contain the read / write circuitry that is operable to read and / or write data from and / or to the memory element(s) within the individual memory chip independently of any other read and / or write operations to any other memory chips.

[0018] Memory 104 can contain multiple groups of memory elements. For example, memory 104 can contain a representative group of memory elements 106 (e.g., a group of memory cells). As an illustrative, non-restrictive example, the group of memory elements 106 can contain a representative memory element 108 (e.g., a memory cell). The memory element 108 can be configured to function as a single-level cell (SLC), a multi-level cell (MLC), or a three-level cell (TLC). Each of the groups of memory elements, such as the group of memory elements 106 of memory 104, can correspond to one or more word lines, blocks, levels, or any other definable group of memory elements.

[0019] The control unit 130 is coupled to the storage device 103 via a bus 121, a memory interface (e.g., an interface circuit such as a second interface 132), another structure, or a combination thereof. The bus 121 can, for example, contain one or more channels to allow the control unit 130 to communicate with a single memory chip of the storage device 103. Alternatively, the bus 121 can contain multiple individual channels to allow the control unit 130 to communicate with each memory chip of the storage device 103 in parallel and independently of communication with other memory chips of the storage device 103.

[0020] The control unit 130 is configured to receive data and commands from the access device 170 and to send data to the access device 170. For example, the control unit 130 can send data to the access device 170 via the first interface 110, and the control unit 130 can receive data from the access device 170 via the first interface 110. The control unit 130 is configured to send data and commands to the memory 104 and to receive data from the memory 104. For example, the control unit 130 is configured to send data and a write command so that the memory 104 is instructed to store data in memory elements according to a specified address of the memory 104. The write command can specify a physical address of a part of the memory 104 (for example, a physical address of a word line of the memory 104) that is to store the data.The control unit 130 can also be configured, as an illustrative, non-limiting example, to send data and commands to memory 104 in association with background sampling operations, waste collection operations, and / or wear compensation operations, etc. The control unit 130 is designed to send a read command to memory 104 to access data from memory elements corresponding to a specified address of memory 104. The read command can specify the physical address of a portion of memory 104 (for example, a physical address of a word line of memory 104).

[0021] The control device 130 contains a set of registers 133, an instruction module 138, and a memory 150. The set of registers 133 can contain an array or array of bits 136. For each instruction of a plurality of instructions that can be executed by the data storage device 102, the array or array of bits 136 can contain a corresponding bit. For example, a first bit of the array of bits 136 can correspond to a first instruction (CMD1); a second bit of the array of bits 136 can correspond to a second instruction (CMD2); a third bit of the array of bits 136 can correspond to a third instruction (CMD3); a fourth bit of the array of bits 136 can correspond to a fourth instruction (CMD4); and a fifth bit of the array of bits 136 can correspond to a fifth instruction (CMD5).Although the arrangement of bits 136 is described as containing five bits, the arrangement of bits 136 can contain more or less than five bits in other realizations.

[0022] Each instruction from the multitude of instructions can be categorized (or marked) as authorized or unauthorized for execution based on a corresponding bit value in the array of bits 136. Thus, as an illustrative, non-limiting example, a bit value of "0" can indicate that a particular instruction is categorized as unauthorized, and a bit value of "1" can indicate that a particular instruction is categorized as authorized. For illustration, as in Fig.Figure 1 shows the arrangement of bits 136 indicating that the third command (CMD3) is authorized to be executed, and that the fifth command (CMD5) is not authorized to be executed.

[0023] The memory 150 can contain a first authorization scheme or system 152. The first authorization scheme 152 can contain data that categorizes instructions (from the multitude of instructions executable by the data storage device 102) as authorized or unauthorized to be executed for a particular mode, such as the first mode. For illustration, the first mode can correspond to an instruction queue mode in which an instruction queue 134 is released and occupied (for example, containing one or more authorized instructions awaiting execution). The first authorization scheme 152 can contain or be associated with data that categorizes (or marks) a set of authorized instructions 146 and a set of unauthorized instructions for the particular mode.The first authorization scheme 152 can, for example, contain or be associated with an arrangement of bits 136 (e.g., a bit mapping) which are loaded into registers 133 configured in the specific mode by the control unit 130 (e.g., the instruction module 138). In this example, each bit of the arrangement of bits 136 can correspond to an instruction recognized by the instruction module 138. Thus, the arrangement of bits 136 together corresponds to a set of recognized instructions. Furthermore, in this example, a first set of bits in the arrangement of bits 136, which have a first value, corresponds to instructions authorized for execution in the specific mode (e.g., the set of authorized instructions 146), and a second set of bits in the arrangement of bits 136, which have a second value, corresponds to instructions not authorized for execution in the specific mode (e.g.,the set of unauthorized commands 148). In other implementations, the first authorization scheme 152 may contain or be associated with a list(s) of authorized / or unauthorized commands.

[0024] Examples of recognized commands are defined in the eMMC specification. Table 1 below lists various examples of recognized commands and their respective command indices. Table 1 is not intended to list all commands that the 130 control unit can recognize. The eMMC specification also lists, for example, various reserved command indices that are not listed in Table 1. Table 1 CMD index abbreviation brief command description CMD0 GO_IDLE_STATE Resetting an EMMC chip to idle state CMD1 SEND_OP_COND Requirements of operating conditions, registry contents CMD2 ALL SEND CID Requesting a CID number via CMD line CMD3 SET RELATIVE ADDR Assigning a relative address CMD6 SWITCH Switching the operation mode or modifying the EXT CSD registers CMD7 SELECT / DESELCT CARD Selecting a device by its relative address CMD8 SEND_EXT_CSD Requesting the EXT_CSD register as a block of data CMD9 SEND CSD Requesting map-specific data (CSD) CMD10 SEND CID Requesting card identification (CID) CMD12 STOP_TRANSMISSION Forcing an EMMC chip to stop transmission CMD13 SEND STATUS Requesting the status register CMD14 BUSTEST_R Reading the reverse bus test data pattern from an EMMC chip CMD15 GO_INACTIVE_STATE Putting an EMMC chip into an inactive state CMD16 SET_BLOCKLEN Setting a block length (in bytes) for a length following block commands (e.g., read and write) CMD17 READ_SINGLE_BLOCK Reading a block of a size selected by the SET BLOCKLEN command CMD18 READ MULTIPLE BLOCK Reading multiple blocks CMD19 BUSTEST_W A host sends a bus test data pattern to an EMMC chip. CMD23 SET_BLOCK_COUNT Specifies the number of blocks to be transferred in an immediately subsequent multi-block read or write command. CMD24 WRITE_BLOCK Write a block of a size selected by the SET BLOCKLEN command CMD25 WRITE_MULTIPLE_BLOCK Continues writing blocks of data until a STOP_TRANSMISSION is received or a requested block count is received. CMD27 PROGRAM CSD Programs programmable bits of the CSD CMD28 SET_WRITE_PROT Sets a write-protect bit for an addressed group CMD29 CLR_WRITE_PROT Deletes a write-protection bit of an addressed group CMD30 SEND WRITE PROT Requesting a status of write-protection bits CMD35 ERASE_GROUP_START Specifying an address for an initial deletion group within a range to be selected for deletion. CDMD36 ERASE GROUP END Setting an address for a last deletion group within a segment to be selected for deletion and which is interrupted CMD38 ERASE Deletes all previously selected writing pads CMD39 FAST_IO Writes and reads 8-bit (register) data fields CMD40 GO IRQ STATE Sets a system to interrupt mode CMD42 LOCK_UNLOCK To set / reset a password or to lock / unlock an EMMC chip

[0025] The instruction module 138 can contain an execution unit 135, the instruction queue 134, a parser or analyzer module 140, and a mode indicator 142. In some implementations, the execution unit 135 is a component of the control unit 130, and the instruction module 138 is executed by or implemented by the execution unit 135. The execution unit 135 can, for example, contain or be equivalent to a processor, an application-specific integrated circuit (ASIC), or any other circuit containing logic that enables the execution of software or firmware code. In this example, the instruction module 138 can contain or be equivalent to software or firmware code that is executed by the execution unit 135. The execution unit 135 can also execute or implement instructions that are recognized and authorized (for example, instructions from the set of authorized instructions 146).

[0026] The mode indicator 142 can show whether the control device 130 (for example, the command module 138) is configured for operation in a first mode or whether it is configured for operation in a different mode (for example, a second mode). In some implementations, the first authorization scheme 152 can correspond to the first mode. For illustration, the first mode can contain a command queue mode, and the second mode can contain a non-command queue mode, such as a transfer mode. The mode indicator 142 can have a first value if the control device 130 is configured for operation in the first mode.The first mode (for example, when command queue 134 is enabled and occupied) is defined, and it can have a second value if the control unit 130 is designed for operation in the second mode (for example, when command queue 134 is neither enabled nor occupied). The first mode (for example, the command queue mode) and the second mode (for example, the non-command queue mode) can be associated with an eMMC protocol.

[0027] If the mode indicator 142 indicates that the control unit 130 is configured for operation in the first mode, the control unit 130 may be configured to execute any command from a first set of commands (for example, one or more commands from the set of authorized commands 146) if such a command is received or is placed in the command queue 134. Furthermore, if the mode indicator 142 indicates that the control unit 130 is configured for operation in the first mode, the control unit 130 may be configured to discard, ignore, or otherwise not execute second commands from any commands of a second set of commands, such as the set of unauthorized commands (for example, one or more commands from the set of unauthorized commands 148), if such a command is received or is placed in the command queue 134.If the mode indicator 142 indicates that the control unit 130 is configured to operate in the second mode, the control unit 130 may be configured to execute a different set of commands, to exclude different commands, or both, to ignore them, or not execute them in any other way. In some implementations, if the mode indicator 142 indicates that the control unit 130 is configured to operate in the second mode, then all commands in the set of recognized commands may be authorized for execution by the control unit 130, and no recognized command may be unauthorized for execution.

[0028] Commands, such as command 162 received by access device 170, can be queued in command queue 134 for subsequent execution (for example, by execution unit 135). Although command queue 134 is described as the only queue, in other implementations, as an illustrative, non-limiting example, command queue 134 can contain multiple queues, such as separate queues for read and write operations.

[0029] The analyzer module 140 can be configured to receive one or more instructions, such as instruction 162, from the access device 170. Upon receiving instruction 162, the analyzer module 140 can analyze it to identify an instruction index value 166 (e.g., CMD2) of instruction 162. Based on the instruction index value 166 of instruction 162, the instruction module 138 can determine whether instruction 162 (e.g., CMD2) is authorized to be executed or not. For illustration, the instruction module 138 can determine a bit value of the arrangement of bits 136 that corresponds to the instruction index value 166. If the bit value indicates that instruction 162 is categorized as not authorized for execution, instruction module 138 may reject, ignore, or otherwise not execute instruction 162.Alternatively, if the bit value indicates that instruction 162 is categorized as authorized for execution, instruction module 138 can provide instruction 162 (for example, instruction index value 166) to instruction queue 134.

[0030] Additionally or alternatively, the analyzer module 140 can analyze the instruction to determine whether instruction 162 contains a specification 164 to modify the authorization / authorization of a specific instruction. In some implementations, the specification 164 may be contained in reserved bits of an argument of instruction 162. For example, instruction 162 may contain an argument indicating that an instruction belonging to a different instruction index (e.g., CMD4) needs to be authorized for execution. Based on the specification 164, instruction module 138 may be configured to authorize the execution of the fourth instruction (CMD4). To configure instruction module 138 to authorize the execution of the fourth instruction (CMD4), the analyzer module 140 can send data 168 to registers 133 to modify a bit value corresponding to the fourth instruction (CMD4) for categorizing the fourth instruction (CMD4) as authorized.To illustrate, the analyzer module 140 can send data 168 to registers 133 to change the bit value corresponding to the fourth instruction (CMD4) from a 0 (indicating that the execution of the fourth instruction (CMD4) is not authorized) to a 1 (indicating that the execution of the fourth instruction (CMD4) is authorized). Therefore, if the access device 170 wishes to execute an instruction that is not normally authorized for execution while operating in first mode, the access device 170 can send the signal 164 to temporarily authorize the instruction without exiting first mode.

[0031] While the mode indicator device 142 indicates that the control device 130 is configured for operation in first mode, the control device 130 can, for illustrative purposes, execute a specific instruction that results in an exception. To determine the reason for the exception, the access device 170 could issue an instruction associated with instruction index CMD8 (e.g., an instruction to request the contents of one or more card-specific data registers). During operation in an instruction queue mode (e.g., first mode), the CMD8 may not be authorized. According to a particular implementation, the access device 170 can issue an instruction associated with instruction index CMD13 (e.g., to request the status of registers), which is authorized for execution in first mode. An argument (or reserved bits) of the CMD13 instruction can indicate that the CMD8 needs to be authorized for execution.Based on the argument (or the reserved bits), the value of a bit in the bit set 136 can be changed to categorize the CMD8 instruction as authorized. Thus, an instruction authorized for execution in first mode (for example, CMD13) can be used to induce an unauthorized instruction (e.g., CMD8) to become authorized by changing the value of a bit in the bit set 136. After inducing the authorization and execution of the CMD8 instruction, the access device 170 can issue another instruction to cause the value of the bit in the bit set 136 to be changed again, thus categorizing the CMD8 instruction as unauthorized once more.

[0032] In some implementations, the mode indicator device 142 can specify one mode from a variety of modes. For example, the mode indicator device 142 can be set to indicate an operation in the first mode (e.g., a command queue mode) or in the second mode (e.g., a non-command queue mode). As described above, the first mode can correspond to the first authorization scheme 152, which contains the set of authorized commands 146 and the set of unauthorized commands 148. Additionally or alternatively, the first mode can correspond to a second set of unauthorized commands.If the first mode corresponds to both the first authorization scheme 152 and the second authorization scheme, the first authorization scheme 152 can be used to set values ​​of the bit order 136 when the instruction queue 134 is not empty, and the second authorization scheme can be used to set values ​​of the bit order 136 when the instruction queue 134 is empty. In some implementations, the first authorization scheme 152 can be more restrictive than the second authorization scheme, so that fewer instructions are authorized for execution under the first authorization scheme 152 compared to the second authorization scheme. Additionally, the second mode (for example, the non-instruction queue mode) can correspond to a third authorization scheme.In some implementations, the third authorization scheme may be less restrictive than the first authorization scheme 152, the second authorization scheme, or both.

[0033] After the data storage device 102 turns on or is powered on, or exits a standby period, the command module 138, in some implementations, can set the mode indicator 142 to specify an operation in the second mode (for example, non-command-squeue mode). The access device 170 can send an entry command-squeue mode command to cause the command module to change the mode indicator 142 from the second mode (for example, non-command-squeue mode) to the first mode (for example, command-squeue mode). While the mode indicator 142 is set to the first mode, the access device 170 can send one or more initial commands (contained in the set of authorized commands 146) to the data storage device 102 for execution.

[0034] In an illustrative, non-limiting example, the access device 170 and the data storage device 102 can communicate using an eMMC protocol. To send the value 164 to the data storage device 102, the access device 170 can include the value 164 in a specific instruction, such as instruction 13 (CMD13), which is used by the eMMC protocol. For example, the access device 170 can include the value 164 in an argument or in reserved bits of instruction 13 (CMD13). For illustration, an argument of instruction 13 (CMD13) of the eMMC protocol can contain 32 bits, such as the bits [31:0].A format of command 13 (CMD13) can specify that bits [31:16] indicate a relative map address (RCA), that bit

[15] indicates a send queue status (SQS), that bits [14:1] are reserved bits (for example, stuffing bits, such as all zeros or all ones), and that bit [0] is a high priority interrupt indicator (HPI). Access device 170 can include the specification 164 in reserved bits [14:1].

[0035] As an illustrative, non-limiting example, the specification 164 can contain a bit which, at bit [7] of the argument, represents an instruction authorization / non-authorization indicator, and at bits [6:1] of the argument, represents an instruction index value (e.g., an operation code of an instruction). The instruction authorization / non-authorization value at bit [7] can indicate whether the execution of an instruction corresponding to the instruction index value at bits [6:1] should be authorized or not. For example, if bit [7] has a value of 1, the instruction corresponding to the instruction index value should be authorized for execution. For illustration, the instruction index value could correspond to instruction 16 (CMD6) or instruction 8 (CMD8) of the eMMC protocol. If bit [7] has a value of 0, the instruction corresponding to the instruction index value should alternatively not be authorized for execution.As a further illustrative, non-restrictive example, the specification 164 can contain a bit that is an instruction authorization / non-authorization indicator at bit

[14] , an instruction index value (e.g., an operation code of an instruction) at bits [13:7], and bits [6:1] that can specify a frequency to allow the execution of the instruction. After the instruction has been executed at the frequency specified by bits [6:1], the instruction can be categorized as not authorized for execution. As an additional illustrative, non-restrictive example, the specification 164 can contain in the reserved bits [14:1] a bit that is an instruction authorization / non-authorization indicator at bit

[14] , a first instruction index value (e.g., an operation code of an instruction) at bits [13:7], and a second instruction index value (e.g., an operation code of another instruction) at bits [6:1].By including two instruction index values, the specification 164 can authorize / disauthorize the execution of two different instructions.

[0036] In some implementations, command module 138 can be configured to temporarily authorize the execution of a specific command, such as the fourth command (CMD4), upon a request from module 164. After a single execution or multiple executions of the specific command, command module 138 can automatically disauthorize its execution (for example, the data associated with the specific command can be modified to indicate that the specific command is categorized as unauthorized). Additionally or alternatively, command module 138 can block the execution of the specific command upon a second request received from access module 170, indicating that the specific command should not be authorized. In some implementations, command module 138 cannot authorize the specific command after it has already been executed.In other implementations, instruction module 138 cannot authorize the specific instruction after it has been made available to instruction queue 134. If the specific instruction is contained in instruction queue 134, it can be executed in such implementations regardless of the arrangement of bits 136.

[0037] In some implementations, the data storage device 102 may contain an (not shown) ECC machine. The ECC machine may be configured to receive data, such as the data 160, and to generate one or more ECC codewords (for example, containing a data part and a parity part) based on the data. For example, the ECC machine may receive the data 160 and generate a codeword. For illustration, the ECC machine may contain an encoder configured to encode data using an ECC encoding scheme. As an illustrative, non-limiting example, the ECC machine may contain a Reed-Solomon encoder, a Bose-Chaudhuri-Hocquenghem (BCH) encoder, a low-density LDPC parity-checking encoder, a turbo encoder, an encoder configured to encode the data according to one or more other ECC schemes, or a combination thereof.

[0038] The ECC machine may include a decoder configured to decode data read from memory and to detect and correct any bit errors that may be present in the data. For example, the ECC machine may correct a certain number of bit errors up to the error correction capability of an ECC method used by the ECC machine. In some implementations, the ECC machine may be configured to determine and / or track a failed bit count (FBC), a bit error rate, or both, based on the data decoded by the ECC machine.

[0039] In some implementations, the instruction queue 134, the mode specification 142, and / or the first authorization scheme 152 can be stored in memory 104. In other implementations, the control unit 130 can contain or be coupled to a specific memory (for example, memory 150), such as random access memory (RAM), designed to store the instruction queue 134, the mode specification, and / or the first authorization scheme 152. A portion of memory 150, for example, can be configured to be used as the instruction queue 134. Alternatively or additionally, the control unit 130 can contain or be coupled to another (not shown) memory, such as non-volatile memory, RAM, or read-only memory (ROM).The other memory can be a single memory component, a plurality of different memory components, and / or a plurality of different types (e.g., volatile and / or non-volatile memory) of memory components. In some implementations, the other memory can be contained within the access device 170.

[0040] Although one or more components of the data storage device 102 have been described with regard to the control unit 130, in other implementations certain components may be contained in the storage device 103 (for example, in memory 104). For example, one or more of the registers 133, the instruction module 138, and / or memory 150 may be contained in the storage device 103. Alternatively or additionally, one or more functions, as described above with reference to the control unit 130, may be executed at or by the storage device 103. For example, one or more functions of the registers 133, the instruction module 138, and / or memory 150 may be executed by components and / or a circuit arrangement that are contained in the storage device 103.Alternatively or additionally, one or more components of the data storage device 102 may be contained in the access device 170. Alternatively or additionally, one or more of the functions described above with reference to the control device 130 may be performed in, on, or by the access device 170.

[0041] By configuring command module 138 to authorize the execution of a specific command (for example, an unauthorized command) while remaining in first mode, the specific command can be received and executed while command module 138 is in first mode. The specific command can then be executed, for example, without emptying command queue 134.

[0042] Referring to Fig.Figure 2 is a special illustrative example of the stages of operation of a data storage device. The data storage device can, for example, be the data storage device 102 of Fig. 1 contain or correspond to it. Each level of the in Fig. Figure 2 of the operating diagram shows the corresponding state of the instruction queue 134, the mode specification 142 and the arrangement of bits 136 after one or more functions / operations have been performed.

[0043] A first stage of operation of the data storage device is illustrated and generally designated by 200. As shown in the first stage of operation or operation 200, the mode specification 142 is set in a first instruction queue mode 202 (for example, an instruction queue mode when the instruction queue 134 is empty), and the arrangement of the bits 136 is set in a first authorization bit sequence, which corresponds to the first instruction queue mode 202.

[0044] A second stage of operation of the data storage device is shown and generally designated 210. As shown in the second stage of operation 210, the second instruction (CMD2) 212 is received and added to the instruction queue 134 upon determination that the second instruction (CMD2) 212 is authorized for execution. The second instruction (CMD2) 212 may, for example, have been determined to be authorized for execution according to the arrangement of bits 136, as shown in the first stage of operation 200. Following the addition of the second instruction (CMD2) 212 to the instruction queue 134, the mode indication 142 may be updated to a second instruction queue mode 214 (for example, to an instruction queue mode when the instruction queue 134 contains one or more instructions).The arrangement of bits 136 can be set to a second authorization bit sequence corresponding to the second instruction queue mode 214. The second authorization bit sequence can be different from the first authorization bit sequence. For example, the fourth instruction (CMD4) can be authorized to execute according to the first authorization bit sequence, and it can be not authorized to execute according to the second authorization bit sequence.

[0045] A third stage of operation of the data storage device is shown and generally designated 220. As shown in the third stage of operation 220, the third instruction (CMD3) 224 has been received and added to the instruction queue 134 upon a determination that the third instruction (CMD3) 224 is authorized for execution. The third instruction (CMD3) 224 may, for example, have been determined to be authorized for execution according to the bit arrangement 136, as shown in the second stage of operation 210. The third instruction (CMD3) 224 may have contained a declaration authorizing the fourth instruction (CMD4) for execution. Upon this declaration, a bit value of the bit arrangement 136 corresponding to the fourth instruction (CMD4) (as shown in the second stage of operation 210) may have been modified from a 0 value to a 1 value.Accordingly, the arrangement of bits 136, as shown in the third stage of operation 220, categorizes the fourth instruction (CDM4) as authorized for execution, while the mode indication 142 is the second instruction queue mode 214 (for example, while the instruction queue 134 contains at least one instruction).

[0046] A fourth stage of operation of the data storage device is shown and generally designated 230. As shown in the fourth stage of operation 230, the second instruction (CMD2) 212 has been received and added to the instruction queue 134, with a determination that the fourth instruction (CMD4) 236 is authorized for execution. The fourth instruction (CMD4) 236 may, for example, have been determined to be authorized for execution according to the arrangement of bits 136, as shown in the third stage of operation 220.

[0047] A fifth stage of the operation of the data storage device is shown and generally designated 240. As shown in the fifth stage of operation 240, the first instruction (CMD1) 242 has been received and added to the instruction queue 134, based on a determination that the first instruction (CMD1) 242 is authorized for execution. The first instruction (CMD1) 242 may, for example, have been determined to be authorized for execution according to the arrangement of bits 136, as shown in the fourth stage of operation 230. Additionally, the third instruction (CMD3) 224 and the fourth instruction (CMD4) 236 have each been executed. After the execution of the fourth instruction (CMD4), the bit value of the arrangement of bits 136 may have been modified from a 1 to a 0 according to the fourth instruction (CMD4) (as shown in the fourth stage of operation 230).Accordingly, the arrangement of bits 136, as shown in the fifth stage of operation 240, categorizes the fourth instruction (CMD4) as not authorized for execution, while the mode indication 142 is in the second instruction queue mode 214 (for example, the instruction queue 134 contains at least one instruction). The arrangement of bits 136 can, for example, correspond to the second authorization bit sequence, as shown in the fifth stage of operation 240.

[0048] A sixth stage of operation of the data storage device is shown and generally designated 250. As shown in the sixth stage of operation 250, the first instruction (CMD1) 424 has been executed. After execution of the first instruction (CMD1), the instruction queue 134 is empty. Since the instruction queue 134 is empty, the mode specification 142 can be set in the first instruction queue mode 202, and the arrangement of bits 136 can be set in the first authorization bit sequence.

[0049] A seventh stage of operation of the data storage device is shown and generally designated 260. As shown in the seventh stage of operation 260, a mode change instruction has been received, and the mode specification 142 has been changed from the first command queue mode 202 to a non-command queue mode 254, such as a transfer mode. With the mode specification 142 now in non-command queue mode 154, the arrangement of bits 136 has been set to a third authorization bit sequence, which corresponds to non-command queue mode 254. The third authorization bit sequence can be different from the first authorization bit sequence, the second authorization bit sequence, or both.

[0050] The reference to Fig.The two described examples of the different stages of operation thus illustrate how the arrangement of bits 136 can be modified to temporarily authorize the execution of a specific instruction during an instruction queue mode, such as the first instruction queue mode 202 or the second instruction queue mode 214. The specific instruction can, for example, be temporarily authorized without emptying the instruction queue 134 and without executing all appended instructions in the instruction queue 134.

[0051] Referring to Fig. Figure 3 is a specific illustrative example of a method for authorizing the execution of an unauthorized command and is generally designated as 300. Method 300 can be implemented in the data storage device 102, such as the control device 130, and / or the access device 170. Fig.1 or a combination thereof as illustrative, non-restrictive examples.

[0052] Method 300, at 302, while the data storage device is in a first mode, includes, by means of a first command, the receipt of an indication to authorize the execution of a second command, which is categorized as an unauthorized command by data available to the control device. The indication can, for example, be the indication 164 of Fig.1, or corresponding to it, which is received in the control unit 130 by instruction 162. To identify that the instruction has been received, bits of received instructions can be analyzed to determine if any of the received instructions contain the instruction. The instruction can contain an instruction index and an enable bit. The instruction index is associated with the instruction. For illustration, the instruction index can contain an identifier of the instruction, such as a bit value corresponding to an operation code of the instruction. The enable bit can have a value indicating whether the instruction is to be categorized as authorized or unauthorized. The first mode can contain an instruction queue mode, such as an instruction queue mode of an (eMMC) protocol.

[0053] In some implementations, the information can be provided by a data storage device, such as the data storage device 102 from Fig.1. The information can be received, for example, in a control unit, such as the control unit 130 of Fig. 1. The data storage device receives the information via an interface, such as an eMMC interface. The control unit can be configured to operate in a first mode when the information is received. While the device is in first mode, the control unit can be configured to execute first commands from one or more authorized commands and to reject (or otherwise not execute) second commands from one or more unauthorized commands.

[0054] Procedure 300 also includes, as specified in 304, modifying the data to authorize the execution of the second instruction while the control device is in first mode. The data accessible to the control device may, for example, be the arrangement of bits 136 of Fig. 1 and Fig. 2. In this example, modifying the data to authorize the execution of the second instruction may involve changing the value of one or more of the bits in the array of bits 136.

[0055] In some implementations, the instruction can be received, and the second instruction can contain the specification. If the specification is included in the second instruction, the second instruction can be executed after the data for categorizing the second instruction as authorized has been modified. In other implementations, a second instruction can be received that contains the specification. The specification can, for example, be contained in reserved bits of the second instruction.

[0056] In some implementations, after modifying the data to categorize the second instruction as authorized, procedure 300 may include receiving and executing the second instruction. For illustration, the data storage device may receive the second instruction while the data storage device (e.g., the control device) is configured in first mode. An instruction index value of the second instruction can be identified, and based on the instruction index value, a bit of an array of bits can be identified. Each bit of the array of bits corresponds to a different instruction index value. The array of bits may, for example, contain or correspond to the array of bits 136. The identified bit of the array of bits can be assigned the instruction index value (e.g.,The second instruction corresponds to the command, and the value of the bit indicates whether the execution of the second instruction is authorized (allowed) or unauthorized (blocked). Based on the determination that the execution of the second instruction is authorized according to the bit's value, the second instruction can be made available to a command queue.

[0057] After the second command has been executed (or after the second command has been made available to the command queue), the command module can be configured to reject (for example, drop) the second command while the device is in first mode. After the second command has been executed (or after the second command has been made available to the command queue), the control module can, for example, automatically modify the data to categorize the second command as not authorized for execution in first mode.As another example, after the execution of the second command (or after the second command has been provided to the command queue), a second specification of the second command may be received (for example, by a third command), and the command module may categorize the data for categorizing the second command as not authorized for execution in the first mode based on the second specification.

[0058] By releasing the command module to authorize the execution of the second command while remaining in first mode, the second command can be received and executed while the command module is in first mode without emptying command queue 134.

[0059] Referring to Fig.4 is a specific illustrative example of a method for sending a statement that the execution of an unauthorized command is authorized, and is generally referred to as 400. Method 400 can be described as illustrative, non-limiting examples in the data storage device 102, such as the control device 130, and / or the access device 170. Fig. 1 or a combination thereof.

[0060] Method 400 includes, at 402, determining that a device is configured in a first mode. Method 400 also includes, at 404, sending to the device, while it is in first mode, a statement that the execution of an unauthorized command associated with first mode is authorized. The statement may, as an illustrative, non-limiting example, be the statement 164 of Fig. The information can be contained in or correspond to 1. This information can be sent via an interface, such as the third interface 172, which is configured to send the information to the device. The interface can include an eMMC interface.

[0061] In some implementations, procedure 400 may include sending the unauthorized command to the device. The specification may be included in the unauthorized command itself. Alternatively, the specification may be included in another command sent to the device before the unauthorized command. This other command may be an authorized command or another unauthorized command.

[0062] In some implementations, an instruction (for example, the unauthorized instruction or another instruction) can be generated that includes the specification. A processor, such as the Processor 174, can be configured, for example, to generate the specification, which is included as part of the instruction. The specification can be contained, for example, in a set of reserved bits of the instruction. In addition to specifying the authorization for the execution of the unauthorized instruction, the specification can also indicate that the execution of a second unauthorized instruction belonging to the first mode is authorized while the device is in the first mode.For illustration, the specification can include a first command index associated with the unauthorized command (which, for example, identifies the unauthorized command) and a second command index associated with the second unauthorized command (which, for example, identifies the second unauthorized command).

[0063] By generating the instruction, the access device can instruct the device to temporarily authorize the execution of an unauthorized command while the device is in first mode. Once authorized, the command can be executed, for example, while the device is in first mode, without clearing the device's command queue or executing all pending commands in the queue. By sending the instruction to the device, the access device therefore does not need to wait for the command queue to clear or for all pending commands in the queue to be executed before the unauthorized command is executed.

[0064] The procedure 300 of Fig. 3 and / or the procedure 400 of Fig.4 can be initiated or controlled by an application-specific integrated circuit (ASIC), a processing unit such as a central processing unit (CPU), a control device, another hardware device, a firmware device, a field-programmable gate array (FPGA) device, or any combination thereof. For example, the procedure 300 of Fig. 3 and / or the procedure 400 of Fig. 4 by one or more processors, such as one or more processors contained in or coupled to a control device, or a memory of the data storage device 102 or the access device 170 of Fig. 1. Initiated or controlled. A control device configured to execute procedure 300 of Fig. 3 and / or the procedure 400 of Fig.4. It may be able to authorize the execution of an unauthorized command. For example, one or more of the procedures of Fig. 3-4 individually or in combination by the control unit 130 of Fig. 1. To illustrate, part of one of the procedures of Fig. 3-4 with a second part of one of the procedures of Fig. 3-4 can be combined. In addition, one or more operations relating to Fig. 3-4 described above are optional, and they can be executed at least partially simultaneously and / or they can be executed in a different order than shown or described.

[0065] Although various components of the data storage device 102, such as the control device 130 or the access device 170 of Fig.1. Herein represented as block components and described in general terms, such components may contain one or more physical components, such as hardware control devices, one or more microprocessors, state machines, logic circuits, one or more other structures or circuits, or a combination thereof, which are configured to enable the various components to perform operations described herein.

[0066] The components described here can be operationally coupled using one or more nodes, one or more buses or bus lines (for example, data buses and / or control buses), one or more other structures, or a combination thereof. One or more aspects of the various components can be implemented using a microprocessor or microcontroller programmed to execute operations described here, such as one or more operations of Procedure 300 of Fig. 3 and / or of procedure 400 of Fig. 4.

[0067] Alternatively or additionally, one or more aspects of the data storage device 102, such as the control device 130 or the access device 170, can be Fig.1. be implemented using the microprocessor or microcontroller, which is programmed (for example, by executing instructions) to perform operations described herein, such as one or more operations of Procedure 300 of Fig. 3 and / or one or more operations of procedure 400 of Fig. 4, as further described here. As an illustrative, non-limiting example, the data storage device 102 contains a processor that executes instructions (for example, firmware) retrieved from memory 104. Alternatively or additionally, instructions executed by the processor can be retrieved from a separate memory location that is not part of memory 104, such as a read-only or ROM (reset memory).

[0068] In some implementations, the control unit 130, the storage device 103 and / or the access device 170 can be used by Fig.1 each contain a processor for executing instructions stored in a memory, such as a non-volatile memory of the data storage device 102 or the access device 170 of Fig. 1 are stored. Alternatively or additionally, executable instructions that are executed by the processor can be stored in a separate memory location that is not part of the non-volatile memory, such as a read-only or ROM of the data storage device 102 or the access device 170. Fig. 1 is.

[0069] Memory 104 can contain random-access resistance memory (ReRAM), three-dimensional (3D) memory, flash memory (for example, NAND flash memory, NOR flash memory, single-level cell (SLC) flash memory, multi-level cell (MLC) flash memory, divided bit-line NOR (DINOR) flash memory, AND flash memory, high-capacitance coupling (HiCR) device, asymmetric clockless transistor (ACT) device, or other flash memory, erasable programmable read / write memory (EPROM), electrically erasable programmable read / write memory (EEPROM), read / write memory (ROM), one-time programmable memory (OTP), or a combination thereof. Alternatively or additionally, Memory 104 can contain any other type of memory. Memory 104 can contain a semiconductor memory device.

[0070] Semiconductor memory devices include volatile memory devices, such as dynamic random-access read / write memory ("DRAM") devices or static random-access read / write memory ("SRAM") devices; non-volatile memory devices, such as magnetoresitive random-access memory ("MRAM"), resistive random-access memory ("ReRAM"), electrically erasable programmable read-only memory ("EEPROM"), flash memory (which can also be considered a subset of EEPROM), ferroelectric random-access read / write memory ("FRAM"), and other semiconductor elements capable of storing information. Each type of memory device can have various configurations. Flash memory devices, for example, can be configured in a NAND or NOR configuration.

[0071] The memory devices can be composed of passive and / or active elements in any combination. By a non-limiting example, passive semiconductor memory devices include ReRAM device elements, which in some implementations contain a resistive switching memory element, such as an anti-fuse, a phase-change material, etc., and optionally a control element, such as a diode, etc. By a non-limiting example, active semiconductor memory devices further include EEPROM and flash memory device elements, which in some implementations contain elements that include a charge storage region, such as a floating gate, conductive nanoparticles, or a dielectric charge storage material.

[0072] Multiple memory elements can be configured to be connected in series or in such a way that each element is individually accessible. By non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND memory array can be configured to consist of multiple memory chains, where each chain comprises multiple memory elements sharing a single bit line and being accessed as a group. Alternatively, memory elements can be configured so that each element is individually accessible, such as in a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be designed or configured in other ways.

[0073] Semiconductor memory elements located in and / or above a substrate can be arranged in two or three dimensions, as a two-dimensional or three-dimensional memory structure. In a two-dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device plane. Typically, in a two-dimensional memory structure, memory elements are arranged in a plane (for example, in a plane along the xz direction) that extends substantially parallel to a major face of a substrate that supports the memory elements. The substrate can be a wafer over which or in which the layer of memory elements is formed, or it can be a support substrate that is attached to the memory elements after they have been formed. As a non-limiting example, the substrate can contain a semiconductor, such as silicon.

[0074] The memory elements can be arranged in an ordered sequence within a single memory device plane, such as in multiple rows and / or columns. However, the memory elements can also be arranged in irregular or non-orthogonal configurations. Each memory element can have two or more electrodes or contact lines, such as bit lines and word lines.

[0075] A three-dimensional storage array is arranged such that storage elements occupy a plurality of planes or a plurality of storage device planes, forming a structure in three dimensions (that is, in the x, y, and z directions, with the y-direction being substantially perpendicular and the x and z directions being substantially parallel to the main surface of the substrate). As a non-restrictive example, a three-dimensional storage structure can be arranged vertically as a stack of a plurality of two-dimensional storage device planes. As another non-restrictive example, a three-dimensional storage array can be arranged as a plurality of vertical columns (for example, as columns that are substantially perpendicular to the main surface of the substrate, that is, in the y-direction), with each column containing a plurality of storage elements.The columns can be arranged in a two-dimensional configuration, for example in an xz plane, resulting in a three-dimensional array of memory elements where the elements reside in a plurality of vertically stacked memory levels. Other three-dimensional configurations of memory elements can also form a three-dimensional memory array.

[0076] In a non-restrictive example of a three-dimensional NAND memory array, the memory elements can be coupled to form a NAND chain within a single horizontal (e.g., xz) memory device layer. Alternatively, the memory elements can be coupled to form a vertical NAND chain spanning multiple horizontal memory device layers. Other three-dimensional configurations are possible, where some NAND chains contain memory elements within a single memory layer, while other chains contain memory elements spanning multiple memory layers. Three-dimensional memory arrays can also be designed in a NOR configuration and a ReRAM configuration.

[0077] Typically, in a monolithic three-dimensional storage array, one or more storage device layers are formed above a single substrate. Optionally, the monolithic three-dimensional storage array can also have one or more storage layers at least partially within the single substrate. As a non-limiting example, the substrate can contain a semiconductor material such as silicon. In a monolithic three-dimensional array, the layers forming each storage device layer of the array are typically formed on top of the layers of the underlying storage device layers of the array. However, the layers of adjacent storage device layers of a monolithic three-dimensional storage array can share or contain layers inserted between the storage device layers.

[0078] Alternatively, two-dimensional arrays can be fabricated separately and then packed together to form a non-monolithic storage device with multiple memory layers. Non-monolithic stacked memories can be constructed, for example, by fabricating memory layers on separate substrates and then stacking these layers on top of each other. The substrates may be thinned or removed from the memory device layers prior to stacking, but the memory device layers are still initially fabricated on separate substrates; the resulting memory arrays are not monolithic three-dimensional memory arrays. Furthermore, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) can be fabricated on separate chips and then packed together to form a single-chip stacked memory device.

[0079] An associated circuitry is typically used for operating the memory elements and for communicating with them. As non-limiting examples, memory devices may include a circuitry used to control and drive memory elements to perform functions such as programming and reading. This associated circuitry may be located on the same substrate as the memory elements and / or on a separate substrate. For example, a control device for memory read / write operations may be located on a separate control device chip and / or on the same substrate as the memory elements.

Claims

[1] A device (102) comprising: a memory (104) and a control unit (130) coupled to the memory, wherein the control device (130), while in a first mode, is configured to receive, by means of a first command (162), a signal (164) to authorise the execution of a second command, which is classified as an unauthorized command by data available to the control device (130), and wherein the control device (130) is further configured to modify the data for authorizing the execution of the second command in response to the specification (164) while the control device (130) is in the first mode. [2] The device of claim 1, wherein the first mode comprises a command queue mode. [3] The device of claim 1, wherein the control device (130), while the device is in the first mode, is configured to execute one or more authorized commands based on the data and to reject one or more unauthorized commands. [4] The device of claim 1, wherein specification (164) includes an instruction index and an enable bit, wherein the instruction index is associated with the instruction and wherein the enable bit indicates authorizing the execution of the second instruction. [5] The device of claim 1, further comprising a set of registers (133) containing an arrangement of bits (136), wherein the arrangement of bits (136) contains a corresponding bit of data for each instruction of a plurality of instructions, and wherein each instruction of the plurality of instructions is classified as authorized or unauthorized on the basis of a bit value of the corresponding bit. [6] The device of claim 5, wherein a specific bit of the arrangement of bits (136) corresponds to the second instruction and wherein the control device (130) is configured to change a value of the specific bit from a first value to a second value in order to modify the data for authorizing the execution of the second instruction. [7] The device of claim 6, wherein the control device (130) is configured to change the value of the specified bit from the second value to the first value in order to block the execution of the second instruction while the device (102) is in first mode. [8] The device of claim 1, wherein the memory (104) comprises a non-volatile memory containing a three-dimensional (3D) memory configuration monolithically formed in one or more physical planes of arrays of memory elements (108) having an active area arranged above a silicon substrate, and further comprising a circuit arrangement pertaining to the operation of the memory elements (108). [9] A procedure comprising (300): in a data storage device (102) which includes a memory (104) and a control device (130), the following are performed: While operating in a first mode, a first command (302) is received containing information (164) to authorize the execution of a second command, while the second command is classified as an unauthorized command in the first mode by data available to the control device (130). and modify (304) the data to the specification (164) to authorize the execution of the second command while the control device (130) is in the first mode. [10] The method of claim 9, wherein received commands are parsed to determine whether any of the received commands contains the specification. [11] The method of claim 9, wherein the specification (164) is contained in reserved bits of the first instruction. [12] The method of claim 9, wherein the first command is classified by the data as an authorized command in the first mode. [13] The method of claim 9, further comprising receiving the second instruction after modifying (304) the data and executing the second instruction during the first mode. [14] The method of claim 9, further comprising receiving the second instruction after modifying (304) the data, executing the second instruction during the first mode and modifying the data after executing the second instruction to classify the second instruction as not authorized for execution in the first mode. [15] The method of claim 14, wherein the data are modified to automatically classify the second instruction as unauthorized for execution in the first mode after the second instruction has been executed. [16] The method according to claim 14, wherein the data are modified to classify the second command as unauthorized for execution in the first mode upon receipt of a third command. [17] The method of claim 9, further comprising receiving the second instruction while the data storage device (102) is configured in the first mode, identifying an instruction index value of the second instruction, identifying a bit of an arrangement of bits based on the instruction index value, wherein a value of the bit indicates whether execution of the second instruction is authorized or unauthorized, and making the second instruction available to an instruction queue upon a determination that execution of the second instruction is authorized based on the value of the bit. [18] The method of claim 17, wherein each bit of the arrangement of bits corresponds to a different instruction index value. [19] An access device (170) comprising: a memory (176) configured to store commands, and a processor (174) coupled to the memory (176), wherein the processor (174) is configured to execute the instructions to cause the processor (174) to determine that a device (102) is configured in a first mode, and to send to the device, while the device (102) is in the first mode, a notification (164) that the execution of an unauthorized instruction pertaining to the first mode is authorized, while the device (102) is in the first mode. [20] The access device according to claim 19, further comprising an interface (172) for sending the information (164) to the device (102). [21] The access device according to claim 19, wherein the processor (174) is configured to generate the indication (164). [22] A procedure (400), comprising: The following are executed in an access device (170) coupled with a data storage device (102): Determine (402) that the data storage device (102) is configured in a first mode, and sending (404) a statement (164) to the data storage device (102) while the data storage device (102) is in a first mode, that the execution of an unauthorized command associated with the first mode is authorized while the data storage device (102) is in the first mode. [23] The method according to claim 22, further comprising generating an instruction (162) containing a specification (164), wherein the instruction (162) is an authorized instruction belonging to the first mode. [24] The method of claim 22, wherein the specification (164) is contained in a set of reserved bits of the instruction. [25] The method of claim 22, wherein the specification (164) further specifies that an execution of a second unauthorized instruction belonging to the first mode is authorized while the data storage device (102) is in the first mode, and wherein the specification (164) includes a first instruction index belonging to the unauthorized instruction and a second instruction index belonging to the second unauthorized instruction. [26] The method of claim 22, further comprising sending the unauthorized command to the data storage device (102).

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