Epitaxial silicon carbide substrate, use of the silicon carbide substrate and method for manufacturing a silicon carbide semiconductor device

Abstract

Epitaxial silicon carbide substrate (100), comprising: a single-crystal silicon carbide substrate (10) with a first main surface (11); and a silicon carbide layer (20) on the first main surface (11), wherein the silicon carbide layer (20) comprises a second main surface (30) opposite a surface in contact with the single-crystal silicon carbide substrate (10), wherein the second principal surface (30) corresponds to a plane inclined relative to a {0001} plane in a direction of deviation, wherein the second main surface (30) has a maximum diameter of not less than 100 mm, wherein the second main surface (30) has an outer circumferential region (52) and a central region (53), wherein the outer circumferential region (52) lies within 3 mm of an outer edge (54) of the second main surface (30), wherein the central region (53) is surrounded by the outer circumferential region (52), wherein the central region (53) is provided with a first dislocation arrangement (2) of first half-loops (1) along a straight line perpendicular to the direction of deviation, wherein the area density of the first dislocation arrangement (2) at the central region (53) is not more than 10 / cm² 2 amounts, wherein each of the first half-loops (1) includes a pair of penetration edge dislocations exposed at the second main surface (30), the central area (53) is provided with a second dislocation arrangement (5) of second half-loops (4) along a straight line which is inclined relative to the direction of deviation, wherein each of the second half-loops (4) has a pair of penetration edge dislocations exposed at the second main surface (30), and where the area density of the first dislocation arrangement (2) is lower than the area density of the second dislocation arrangement (5) in the central region (53).

Description

Technical field

[0001] The present invention relates to an epitaxial silicon carbide substrate, a use of the silicon carbide substrate, and a method for fabricating a silicon carbide semiconductor device. Background

[0002] WO 2009 / 035 095 A1 discloses an epitaxial substrate with a dislocation arrangement generated during epitaxial growth. Summary of the invention

[0003] An epitaxial silicon carbide substrate according to the present invention comprises a single-crystal silicon carbide substrate and a silicon carbide layer. The single-crystal silicon carbide substrate has a first primary surface. The silicon carbide layer is located on the first primary surface. The silicon carbide layer comprises a second primary surface opposite a surface that is in contact with the single-crystal silicon carbide substrate. The second primary surface corresponds to a plane that is inclined relative to a {0001} plane in a direction of deviation. The second primary surface has a maximum diameter of at least 100 mm. The second primary surface has an outer circumferential region and a central region, the outer circumferential region being located within 3 mm of an outer edge of the second primary surface, and the central region being surrounded by the outer circumferential region.The central region is provided by a first dislocation array consisting of first half-loops along a straight line perpendicular to the deviation direction. Each of the first half-loops comprises a pair of threading-edge dislocations exposed at the second main surface. The areal density of the first dislocation array in the central region is no greater than 10 / cm. 2Each of the first half-loops comprises a pair of penetration-edge dislocations exposed at the second main surface. The central region comprises a second dislocation array consisting of second half-loops along a straight line inclined relative to the deviation direction. Each of the second half-loops has a pair of penetration-edge dislocations exposed at the second main surface. The areal density of the first dislocation array is lower than the areal density of the second dislocation array in the central region.

[0004] A method for manufacturing a silicon carbide semiconductor device, wherein the method comprises the following steps: an epitaxial substrate preparation step of preparing the epitaxial silicon carbide substrate according to any one of claims 1 to 6; and a substrate processing step of processing the epitaxial silicon carbide substrate, wherein the substrate processing step comprises at least one of the following steps: ion implantation of impurities into the second main surface, heating the epitaxial silicon carbide substrate in an oxygen-containing atmosphere to form an oxide film on the second main surface, forming an electrode on the oxide film, forming an interlayer insulating film to cover the electrode, etching the oxide film and the interlayer insulating film to expose the second main surface, and cutting the epitaxial silicon carbide substrate.

[0005] Use of the epitaxial silicon carbide substrate according to any one of claims 1 to 6 for the manufacture of a silicon carbide semiconductor device. Brief description of the characters Fig. Figure 1 shows a schematic planar view representing a configuration of an epitaxial silicon carbide substrate according to the present embodiment. Fig. Figure 2 shows a schematic cross-sectional view along a line II-II in Fig. 1. Fig. Figure 3 shows a schematic perspective view of area III in Fig. 1. Fig. Figure 4 shows a schematic planar view in area III. Fig. 1 Fig. Figure 5 shows a schematic cross-sectional view in area III. Fig. 1 Fig. Figure 6 shows a schematic perspective view of area VI from Fig. 1. Fig. Figure 7 shows a schematic planar view in area VI. Fig. 1. Fig. Figure 8 shows a schematic cross-sectional view in area VI. Fig. 1. Fig. Figure 9 shows a partially schematic sectional view representing a configuration of a manufacturing device for the epitaxial silicon carbide substrate according to the present embodiment. Fig. Figure 10 shows a schematic planar view representing a first step of a method for producing the epitaxial silicon carbide substrate according to the present embodiment. Fig. Figure 11 shows a schematic cross-sectional view along a line XI-XI in Fig. 10. Fig. Figure 12 shows a relationship between temperature and time in the process for producing the single-crystal silicon carbide substrate according to the present embodiment. Fig. Figure 13 shows a schematic perspective view illustrating a configuration of a basal plane dislocation on area XIII. Fig. 10 represents a growth step at a zero time. Fig. Figure 14 shows a schematic perspective view illustrating the configuration of the basal plane dislocation on region XIII. Fig. 10 represents a first stage in the growth phase. Fig. Figure 15 shows a schematic perspective view illustrating the configuration of the basal plane dislocation on region XIII. Fig. 10 represents a third time in the growth step. Fig. Figure 16 shows a schematic perspective view illustrating the configurations of the basal plane dislocations and first half-loops on region XIII. Fig. 10 represents the cooling step. Fig. Figure 17 shows a schematic perspective view illustrating a configuration of a basal plane dislocation on area XVII. Fig. 10 represents the zeroth time in the growth step. Fig. Figure 18 shows a schematic perspective view illustrating the configurations of the basal plane dislocation and a second half-loop on area XVII. Fig. 10 represents the first stage of growth. Fig. Figure 19 shows a schematic perspective view illustrating the configurations of the basal plane dislocation and the second half-loops on area XVII. Fig. 10 represents the second time in the growth phase. Fig. Figure 20 shows a relationship between pressure and time in a method for producing the epitaxial silicon carbide substrate according to the present embodiment. Fig. Figure 21 shows a flowchart illustrating the process for manufacturing the silicon carbide semiconductor device according to the present embodiment. Fig. Figure 22 shows a schematic cross-sectional view representing a first step of the method for manufacturing the silicon carbide semiconductor device according to the present embodiment. Fig. Figure 23 shows a schematic cross-sectional view representing a second step of the method for manufacturing the silicon carbide semiconductor device according to the present embodiment. Fig. Figure 24 shows a schematic cross-sectional view representing a third step of the method for manufacturing the silicon carbide semiconductor device according to the present embodiment. Description of embodiments [Technical problem]

[0006] One object of the present invention is to provide an epitaxial silicon carbide substrate and a method for producing a silicon carbide semiconductor device, each of which can reduce a dislocation arrangement of half-loops along a straight line perpendicular to a direction of deviation. [Advantageous effect of the present invention]

[0007] According to the present invention, an epitaxial silicon carbide substrate and a method for producing a silicon carbide semiconductor device can be provided, each of which can reduce a dislocation arrangement of half-loops along a straight line perpendicular to a direction of deviation. [Overview of an embodiment of the present invention]

[0008] (1) An epitaxial silicon carbide substrate 100 according to the present invention comprises a single-crystal silicon carbide substrate 10 and a silicon carbide layer 20. The single-crystal silicon carbide substrate 10 has a first main surface 11. The silicon carbide layer 20 is located on the first main surface 11. The silicon carbide layer 20 comprises a second main surface 30 opposite a surface 14 that is in contact with the single-crystal silicon carbide substrate 10. The second main surface 30 corresponds to a plane that is inclined relative to a {0001} plane in a direction of deviation. The second main surface 30 has a maximum diameter 111 of not less than 100 mm.The second main surface 30 has an outer periphery region 52 and a central region 53, the outer periphery region 52 being within 3 mm of an outer edge 54 of the second main surface 30, and the central region 53 being surrounded by the outer periphery region 52. The central region 53 is provided by a first dislocation arrangement 2 of half-loops 1 along a straight line perpendicular to the deviation direction. Each of the first half-loops 1 comprises a pair of penetration-edge dislocations exposed at the second main surface 30. The areal density of the first dislocation arrangement 2 at the central region 53 is not more than 10 / cm². 2A central region 53 is provided with a second dislocation arrangement 5 consisting of second half-loops 4 along a straight line inclined relative to the direction of deviation. Each of the second half-loops has a pair of penetration-edge dislocations exposed at a second principal surface 30. The areal density of the first dislocation arrangement 2 is lower than the areal density of the second dislocation arrangement 5 in the central region 53.

[0009] A dislocation arrangement consisting of penetration edge dislocations is typically found in an epitaxial silicon carbide substrate. Such a dislocation arrangement leads to a decrease in the breakdown voltage of a semiconductor device, increased current loss, reduced reliability of the semiconductor device, and the like. Therefore, it is necessary to reduce the dislocation arrangement. As a result of a thorough study of a method for reducing penetration edge dislocation arrangements, the inventors obtained the following insights and arrived at an embodiment of the invention.

[0010] It is assumed that the dislocation arrangements of penetration edge dislocations are mainly classified into the following three types. A first type of dislocation arrangement is one transferred from a single-crystal silicon carbide substrate to a silicon carbide layer formed by epitaxial growth. A second type of dislocation arrangement is one generated by epitaxial growth of the silicon carbide layer. The depth of each of a plurality of half-loops in the dislocation arrangement is determined by the thickness of the silicon carbide layer at the time the half-loops are formed. Accordingly, the plurality of half-loops in the dislocation arrangement have different depths.Furthermore, the direction in which each of the plurality of half-loops is arranged (particularly the longitudinal direction of the dislocation arrangement) has a component in a stepwise growth direction (deviation direction). Specifically, the longitudinal direction of the dislocation arrangements is not perpendicular to the deviation direction. A third type of dislocation arrangement is one that is generated after the end of epitaxial growth of the silicon carbide layer. This dislocation arrangement is thought to be generated due to a basal plane dislocation in the silicon carbide layer that slips in a direction perpendicular to the deviation direction after the end of epitaxial growth. Consequently, the longitudinal direction of the dislocation arrangement is perpendicular to the deviation direction. Moreover, the corresponding depths of the plurality of half-loops in the dislocation arrangement are essentially equal.

[0011] In particular, the inventors took care to suppress the generation of the third type of dislocation arrangement. It is assumed that the basal plane dislocation slips in the direction perpendicular to the deviation direction to relieve stress in the silicon carbide layer, thereby forming half-loops in the silicon carbide material. Furthermore, it is assumed that stress in the silicon carbide layer is primarily generated during the cooling step of the epitaxial silicon carbide substrate. Based on the above findings, the inventors realized that stress in the epitaxial silicon carbide substrate can be relieved to prevent the generation of the third type of dislocation arrangement by controlling the cooling rate of the epitaxial silicon carbide substrate in a manner described below.Accordingly, the area density of the first dislocation arrangement of the first half-loops along the straight line perpendicular to the direction of deviation can be reduced. [Details of the embodiment of the present invention]

[0012] The following describes in more detail one embodiment (hereinafter referred to as "the present embodiment") of the present invention. The present embodiment is not limited to this embodiment. (epitaxial silicon carbide substrate)

[0013] According to the presentation in the Fig. 1 and Fig. In the present embodiment, an epitaxial silicon carbide substrate 100 comprises a single-crystal silicon carbide substrate 10 and a silicon carbide layer 20. The single-crystal silicon carbide substrate 10 includes a first main surface 11 and a third main surface 13 opposite the first main surface 11. The silicon carbide layer 20 comprises: a fourth main surface 14 in contact with the single-crystal silicon carbide substrate 10; and a second main surface 30 opposite the fourth main surface 14. The epitaxial silicon carbide substrate 100 may have: a first flat (not shown) extending in a first direction 101; and a second flat (not shown) extending in a second direction 102. The first direction is, for example, an <11-20> direction. The second direction 102 is, for example, a <1-100> direction.

[0014] The single-crystal silicon carbide substrate 10 (hereinafter referred to simply as the "single-crystal substrate") is formed from a single-crystal silicon carbide substrate. The single-crystal silicon carbide exhibits, for example, a polytype of 4H-SiC. 4H-SiC is superior to other polytypes with respect to electron mobility, dielectric strength, and the like. The single-crystal silicon carbide substrate 10 includes an n-type impurity, such as nitrogen (N). The single-crystal silicon carbide substrate 10 exhibits, for example, n-type conductivity. The first principal surface 11 corresponds to a plane that is inclined, for example, by no more than 4° relative to a <11-20> plane. If the first principal surface 11 is inclined relative to the <1-100> plane, then, for example, B. represents a direction in which the normal line of the first main surface 11 is inclined, the <11-20> direction.

[0015] According to the representation in Fig. In Figure 2, the silicon carbide layer 20 is an epitaxial layer formed on the single-crystal silicon carbide substrate 10. The silicon carbide layer 20 is located on a first main surface 11 and is in contact with it. The silicon carbide layer 20 contains an n-type impurity, such as nitrogen. The silicon carbide layer 20 exhibits, for example, an n-type conductivity. The concentration of the n-type impurity in the silicon carbide layer 20 can be lower than the concentration of the n-type impurity in the single-crystal silicon carbide substrate 10. As shown in Figure 2, the silicon carbide layer 20 is located on a first main surface 11 and is in contact with the first main surface 11. The silicon carbide layer 20 contains an n-type impurity, such as nitrogen. The silicon carbide layer 20 has, for example, an n-type conductivity. The concentration of the n-type impurity in the silicon carbide layer 20 can be lower than the concentration of the n-type impurity in the single-crystal silicon carbide substrate 10. Fig. In the second main surface 30, a maximum diameter 111 of not less than 100 mm is observed. The maximum diameter 111 of the epitaxial silicon carbide substrate 100 according to the present embodiment is 150 mm. The maximum diameter 111 can be at least 150 mm, at least 200 mm, or at least 250 mm. The upper limit of the maximum diameter 111 is not specifically restricted. For example, the upper limit of the maximum diameter 111 can be 300 mm.

[0016] The second principal surface 30 corresponds to a plane inclined relative to a {0001} plane in a deviation direction. The deviation direction can be the <11-20> direction, the <1-100> direction, or a direction between the <11-20> and <1-100> directions. In particular, the deviation direction can be, for example, an [11-20] direction, a [1-100] direction, or a direction between the [11-20] and [1-100] directions. The second principal surface 30 can correspond to a plane inclined by no more than 4° relative to the (0001) plane. The second principal surface 30 can correspond to a plane inclined by no more than 4° relative to the (000-1) plane. The angle of inclination (angle of deviation) relative to the {0001} plane cannot be less than 1° or less than 2°. The angle of deviation cannot be more than 3°.

[0017] According to the representation in Fig. 1 The second main surface 30 has an outer circumferential region 52 and a central region 53, which is surrounded by the outer circumferential region 52. The outer circumferential region 52 represents a region within 3 mm of an outer edge 54 of the second main surface 30. In other words, a distance 112 between the outer edge 54 and an interface between the outer circumferential region 52 and the central region 54 in a radial direction of the second main surface 30 is 3 mm. (Dislocation arrangement of half-loops along a straight line perpendicular to the direction of deviation)

[0018] According to the presentation of Fig. 1 and Fig. 3 The central region 53 is provided with a first dislocation arrangement 2 consisting of first half-loops 1 along a straight line perpendicular to the deviation direction. The first dislocation arrangement 2 comprises the majority of first half-loops 1. If the deviation direction is equal to the first direction 101, a direction perpendicular to the deviation direction is equal to the second direction 102. Each of the first loops 1 comprises a pair of penetration-edge dislocations exposed at the second main surface 30. The areal density of the first dislocation arrangement in the central region 53 is not more than 10 / cm². 2 Preferably, the areal density of the first dislocation arrangement 2 in the central region 53 is not more than 8 / cm². 2 , preferably no more than 5 / cm 2 .

[0019] Next, a procedure for measuring the areal density of the dislocation arrangement is described below.

[0020] First, the central region 53 is etched with molten KOH (potassium hydroxide) to form etch pits. The molten KOH has a temperature of, for example, 515°C. Etching with the molten KOH is carried out for, for example, 8 minutes. Next, the etch pits formed in the central region 53 are examined using an optical microscope. The central region 53 is divided, for example, into 1 cm × 1 cm square sections in the form of a grid. The areal densities of the dislocation arrangements are measured in all square sections. The expression "area density of the first dislocation arrangement 2 in the central region 53 is no more than 10 / cm²" is given. 2 “ is intended to indicate that the areal density of the first dislocation arrangement 2 in each of the square areas is no more than 10 / cm² 2Since a section of the central region 53 has a circular shape around its outer circumference, the section cannot be subdivided into a square segment. For the calculation of the area density of the dislocation arrangement, the area density of the first dislocation arrangement 2 in such a section, which cannot be subdivided into a square segment, is not considered.

[0021] According to the representation in Fig. The first half-loop 1 has a substantially U-shaped form. The first half-loop 1 has a curved section provided in the silicon carbide layer 20. End regions 3 of the pair of penetration edge dislocations are exposed at the second main surface 30. The curved section of the first half-loop 1 can be a dislocation distinct from the penetration edge dislocation. The single-crystal silicon carbide substrate 100 includes a basal plane dislocation 34. The basal plane dislocation 34 comprises a first section 31, a second section 32, and a third section 33. The first section 31 represents a basal plane dislocation present in the single-crystal silicon carbide substrate 10. The second section 32 represents an interfacial dislocation that is present at an interface between the single-crystal silicon carbide substrate 10 and the silicon carbide layer 20.The third section 33 represents a basal plane dislocation present in the silicon carbide layer 20. The first section 31 extends through to the second section 32. The second section 32 extends through to the third section 33. The first section 31 is exposed at the third major surface 13 of the single-crystal silicon carbide substrate 10. The third section 33 is exposed at the second major surface 30 of the silicon carbide layer 20. In other words, the basal plane dislocation 34 has a first end section 35 exposed at the second major surface 30 and another end section exposed at the third major surface 13.

[0022] According to the representation in Fig. 3 The first dislocation arrangement 2 can be arranged between a terminal section 35 of the basal plane dislocation 34 and a point 36 where an imaginary line 37 is exposed on the second principal surface 30. The imaginary line 37 is obtained by extending the first section 31 to the silicon carbide layer 20 along a direction in which the first section 31 extends. In other words, any of the plurality of first half-loops 1 formed in the first dislocation arrangement 2 can be arranged between the point 36 and the terminal section 35. In particular, the first dislocation arrangement 2 can be arranged in a view along the direction perpendicular to the second principal surface 30 between the imaginary line 37 and the third section 33.

[0023] According to the representation in Fig. 4 is a length 123 of the first dislocation arrangement 2 in a second direction 102 not less than 0.1 mm and, for example, not more than 50 mm. For example, a distance 122 between one end section 3 and the other end section 3 in the first direction 102 is not less than 1 µm and not greater than 10 µm. For example, a distance between two adjacent first half-loops 1 in the second direction 102 is not less than 1 µm and not greater than 100 µm. The distance 121 can be longer than the distance 122. The two end sections 3 can be arranged along the first direction 101. Distances between two adjacent first half-loops can be the same or different.

[0024] In a view along the direction perpendicular to the second main surface 30, each of the plurality of half-loops 1 overlaps with a straight line parallel to the second direction 102. The longitudinal direction of the first dislocation arrangement 2 represents the second direction 102. The longitudinal direction of the first dislocation arrangement 2 can be parallel to a direction in which the interface dislocation extends.

[0025] According to the representation in Fig. 5 Each of the plurality of half-loops 1 can have substantially the same depth in the direction perpendicular to the second main surface 30. The depth of the first half-loop 1 refers to the length of the half-loop in the direction perpendicular to the second main surface 30. The depth of the first half-loop 1 can be less than the thickness of the silicon carbide layer 20. The first half-loop 1 can be spaced apart from the single-crystal silicon carbide substrate 10. (Dislocation arrangement of half-loops along a straight line that is inclined relative to the direction of deviation)

[0026] According to the presentation in the Fig. 1 and Fig. 6 The central region 53 can be provided with a second dislocation arrangement 5 consisting of second half-loops 4 along a straight line inclined relative to the deviation direction. The second dislocation arrangement 5 comprises the majority of second half-loops 4. The second half-loops 4 are parallel to a straight line inclined relative to the first direction 101 and the second direction 102 along a third direction 103. The second half-loop 4 includes a pair of penetration-edge dislocations exposed at the second main surface 30. In the central region 53, the areal density of the first dislocation arrangement 2 can be less than the areal density of the second dislocation arrangement 5. The areal density of the second dislocation arrangement 5 in the central region 53 can be greater than 10 / cm². 2. A multiplicity of the first dislocation arrangements 2 tends to be located near the outer perimeter region 52, whereas a multiplicity of the second dislocation arrangements 5 tends to be located near the center of the central region 53.

[0027] According to the representation in Fig. Each of the second half-loops 4 has a substantially U-shaped form. The second half-loop 4 has a curved section provided in the silicon carbide layer 20, and end sections 6 of the pair of penetration edge dislocations are exposed at the second main surface 30. The curved section of the second half-loop 4 can be a dislocation distinct from the penetration edge dislocation. The epitaxial silicon carbide substrate 100 includes a basal plane dislocation 44. The basal plane dislocation 44 comprises a fourth section 41, a fifth section 42, and a sixth section 43. The fourth section 41 is a basal plane dislocation present in the single-crystal silicon carbide substrate 10. The fifth section 42 represents an interfacial dislocation that is present at the interface between the single-crystal silicon carbide substrate 10 and the silicon carbide layer 20.The sixth section 43 represents a basal plane dislocation present in the silicon carbide layer 20. The fourth section 41 extends through to the fifth section 42. The fifth section 42 extends through to the sixth section 43. The fourth section 43 is exposed at the third major surface 13 of the single-crystal silicon carbide substrate 10. The sixth section 43 is exposed at the second major surface 30 of the silicon carbide layer 20. In other words, the basal plane dislocation 41 has one end section 45 exposed at the second major surface 30 and the other end section exposed at the third major surface 13.Viewed along the direction perpendicular to the second main surface 30, the second dislocation arrangement 5 can be located between the sixth section 43 and an imaginary line 47 obtained by extending the fourth section 42 to the silicon carbide layer 20 along the direction in which the fourth section 41 extends. In other words, the second dislocation arrangement 5 can be located between a terminal section 45 of a basal plane dislocation 44 and a point 46 where the imaginary line 47 is exposed on the second main surface 30.

[0028] According to the representation in Fig. For example, a length 126 of the second dislocation arrangement 5 in the third direction 103 is not less than 0.1 mm and not greater than 50 mm. In the direction perpendicular to the third direction 103, for example, a distance 125 between one end section 6 and the other end section 6 is not less than 1 µm and not more than 10 µm. A distance 124 between two adjacent half-loops 14 in the third direction 103 is, for example, not less than 1 µm and not greater than 100 µm. The distance 124 can be longer than the distance 125. Two end sections 6 can be arranged on a straight line perpendicular to the third direction 103. In a view along the direction perpendicular to the second main surface 30, each of the plurality of second half-loops 4 overlaps a straight line parallel to the third direction 103. Distances between adjacent second half-loops can be the same or different.

[0029] According to the representation in Fig. 8 The majority of second half-loops 4 in the direction perpendicular to the second main surface 30 can have different depths. The depth of the second half-loop 4 refers to the length of the half-loop in the direction perpendicular to the second main surface 30. In particular, the depths of the second half-loops 4 can decrease in the direction of deviation. In other words, the depth of the second half-loop 4 near the fourth section 41, viewed along the direction perpendicular to the second main surface 30, is greater than the depth of the second half-loop 4 near the sixth section 43. The depth of the second half-loop 4 can be less than the thickness of the silicon carbide layer 20. The second half-loop 4 can be spaced apart from the single-crystal silicon carbide substrate 10. (Film forming device)

[0030] Next, the following describes an embodiment of a manufacturing device 200 which is used in the method for producing the epitaxial silicon carbide substrate 100 according to the present embodiment.

[0031] According to the representation in Fig. 9 The manufacturing device 200 is, for example, a hot-wall CVD (chemical vapor deposition) device. The manufacturing device 200 mainly comprises heating elements 203, a quartz tube 204, a thermal insulator 205, an induction heating coil 206, and a preheating structure 211. A hollow space surrounded by the heating elements 203 constitutes a reaction chamber 201. A susceptor plate 210, designed to hold the single-crystal silicon carbide substrate 10, is provided in the reaction chamber 201. The susceptor plate 210 is rotatable. The single-crystal silicon carbide substrate 10 is arranged on the susceptor plate 210 with its first main surface 11 facing upwards.

[0032] The heating element 203 is made of graphite, for example. The induction heating coil 206 is wound around the outer circumference of the quartz tube 204. Next, a predetermined alternating current is applied to the induction heating coil 206, thereby inductively heating the heating elements 203. The reaction chamber 201 is heated accordingly.

[0033] The manufacturing device 200 further comprises a gas inlet 207 and a gas outlet 208. The gas outlet 208 is connected to an exhaust gas pump (not shown). An arrow in Fig. Figure 9 represents a gas flow. Carrier gas, source material gas, and dopant gas are introduced into reaction chamber 201 through gas inlet 207 and discharged through gas outlet 208. The pressure in reaction chamber 201 can be adjusted according to an equilibrium between the amount of gas supplied and the amount of gas discharged.

[0034] Normally, the susceptor plate 210 and the single-crystal substrate 10 are arranged in the axial direction essentially at the center of the reaction chamber 201. According to the illustration in Fig. 9. In the present embodiment, the susceptor plate 210 and the single-crystal substrate 10 can be arranged on a downstream side relative to the center of the reaction chamber 201, in particular on the side of the gas outlet 208, in order to sufficiently support a decomposition reaction of the source material gas until the source material gas reaches the single-crystal substrate 10. Accordingly, it is assumed that a uniform distribution of a C / Si ratio in the plane of the single-crystal substrate 10 is achieved.

[0035] Ammonia gas, acting as a dopant gas, is preferably pre-decomposed by sufficient heating before being fed into reaction chamber 201. Accordingly, it can be expected that the uniformity of nitrogen (dopant) density in the silicon carbide layer 20 will be improved. As shown in Fig. 9. The preheating structure 211 can be provided on the upstream side of the reaction chamber 201. The ammonia gas can be preheated in the preheating structure 211. The preheating structure 211 comprises a chamber that is heated, for example, to at least 1300°C. As it passes through the preheating structure 211, the ammonia gas is sufficiently thermally decomposed and then fed into the reaction chamber 201. With this configuration, the ammonia gas can be thermally decomposed without generating excessive turbulence in the gas stream. (Method for producing the epitaxial silicon carbide substrate)

[0036] Next, the following describes a method for producing the epitaxial silicon carbide substrate according to the present embodiment.

[0037] First, a single-crystal silicon carbide substrate of polytype 4H is produced by a sublimation process. Next, the single-crystal silicon carbide substrate is sawn, e.g., using a wire saw, thereby preparing the single-crystal silicon carbide substrate 10 (see Figure 10). Fig. 10 and Fig. 11). The single-crystal silicon carbide substrate 10 has a first main surface 11 and a third main surface 13 opposite the first main surface 11. According to the representation in Fig. 11 corresponds to the first main surface 11 of a plane that is inclined relative to the {0001} plane in the direction of deviation.

[0038] In particular, the first principal surface 11 corresponds to a plane inclined by no more than 4° relative to the {0001} plane. The first principal surface 11 can correspond to a plane inclined by no more than 4° relative to the (0001) plane, or it can correspond to a plane inclined by no more than 4° relative to the (000-1) plane. An angle of inclination (angle of deviation) relative to the {0001} plane can be at least 1° and at least 2°. The angle of deviation can be at most 3°. The direction of deviation can be the <11-20> direction, the <1-100> direction, or the direction between the <11-20> direction and the <1-100> direction.

[0039] Next, the single-crystal silicon carbide substrate 10 is arranged in the aforementioned manufacturing apparatus 200. Specifically, the single-crystal silicon carbide substrate 10 is positioned in a recess of the susceptor plate 210, such that the first main surface 11 is exposed with respect to the susceptor plate 210. The silicon carbide layer 20 is then formed on the single-crystal silicon carbide substrate 10 by epitaxial growth. For example, after the pressure of the reaction chamber 201 is reduced from atmospheric pressure to approximately 1 × 10⁻⁶ -6 Once the Pa value has decreased, the single-crystal silicon carbide substrate 10 begins to be heated. During heating, hydrogen (H2) gas is introduced into the reaction chamber 201, with the hydrogen gas serving as a carrier gas.

[0040] Once the temperature in reaction chamber 201 reaches approximately 1600°C, the source material gas and the dopant gas are introduced into the chamber. The source material gas comprises, for example, a silicon source gas and a carbon source gas. Silane (SiH₄) gas can be used as the silicon source gas, for example. Propane (C₃H₈) gas can be used as the carbon source gas. The flow rates of the silane gas and the propane gas are, for example, 46 sccm and 14 sccm, respectively. The volume ratio of silane gas to hydrogen is, for example, 0.04%. The C / Si ratio of the source material gas is, for example, 0.9.

[0041] For example, ammonia (NH3) gas is used as a dopant gas. Ammonia gas decomposes more readily than nitrogen gas with a triple bond. Using ammonia gas improves the in-plane uniformity of the charge carrier concentration. For example, the ratio of ammonia gas concentration to hydrogen gas concentration is 1 ppm. The ammonia gas is preferably pre-decomposed by the preheating structure 211 before being introduced into the reaction chamber 201. For example, the ammonia gas is heated to at least 1300°C by the preheating structure 211.

[0042] The carrier gas, the source gas, and the dopant gas are introduced into the reaction chamber 201 containing the single-crystal silicon carbide substrate 10, which is preheated to approximately 1600°C. This causes the silicon carbide layer 20 to form on the single-crystal silicon carbide substrate 10 by epitaxial growth. During the epitaxial growth of the silicon carbide layer 20, the susceptor plate 210 rotates about an axis of rotation 212 (see Figure 1). Fig. 9) The average rotational speed of the susceptor plate 210 is, for example, 20 rpm. In this way, the silicon carbide layer 20 is formed on the single-crystal silicon carbide substrate 10 by epitaxial growth.

[0043] According to the representation in Fig. In the growth step of the silicon carbide layer 20, the temperature of the single-crystal silicon carbide substrate 10 is maintained at a first temperature (A1) for a duration from a zero time (T0) to a third time (T3). The first temperature (A1) is, for example, 1600°C. The zero time (T0) represents the time at which the source material gas and the dopant gas begin to be introduced into the reaction chamber 201. At the zero time (T0), the formation of the silicon carbide layer 20 on the single-crystal silicon carbide substrate 10 essentially begins. The third time (T3) represents the time at which the introduction of the source material gas and the dopant gas into the reaction chamber 201 is stopped. At the third time (T3), the formation of the silicon carbide layer 20 on the single-crystal silicon carbide substrate 10 is essentially completed.Preferably, the temperature of the single-crystal silicon carbide substrate 10 is maintained uniformly in the in-plane direction during the growth step of the silicon carbide layer 20. More precisely, the difference between the maximum temperature and the minimum temperature at the first main surface 11 of the single-crystal silicon carbide substrate 10 is kept at no more than 10°C during the time from time zero (T0) to time three (T3).

[0044] Next, the following fully describes a growth step of a section of the silicon carbide layer 20 on a region XIII of the single-crystal silicon carbide substrate 10.

[0045] According to the presentation in the Fig. 10 and Fig. At time zero (T0), a basal plane dislocation 34 extends along the {0001} plane in the single-crystal silicon carbide substrate 10 in a specific region XIII. The basal plane dislocation 34 has one end section exposed at the first major surface 11 and the other end section exposed at the third major surface 13. The basal plane dislocation 34 extends along the first direction 101, which represents the direction of deviation.

[0046] According to the representation in Fig. At time 14, a section of the silicon carbide layer 20 is formed on the single-crystal silicon carbide substrate 10. The basal plane dislocation 34 propagates from the single-crystal silicon carbide substrate 10 to the silicon carbide layer 20. The basal plane dislocation 34 extends in the silicon carbide layer 20 along the first direction 101. One end segment of the basal plane dislocation 34 is exposed at the surface of the silicon carbide layer 20, and the other end segment is exposed at the third main surface 13.

[0047] According to the representation in Fig. As the silicon carbide layer 20 grows, the basal plane dislocation 34 extends further into the silicon carbide layer 20. At the third time point (T3) after the first time point (T1), one end segment of the basal plane dislocation 34 is exposed at the second main surface 30 of the silicon carbide layer 20, and the other end segment is exposed at the third main surface 13 of the single-crystal silicon carbide substrate 10. Accordingly, the formation of the silicon carbide layer 20 is essentially complete.

[0048] Next, the following describes a step in the cooling of the epitaxial silicon carbide substrate 100.

[0049] According to the representation in Fig. 12. The cooling step is performed after the end of the growth step. The cooling step is defined as the time interval from the third time point (T3) to the seventh time point (T7). In the cooling step, an epitaxial silicon carbide substrate 100, consisting of the single-crystal silicon carbide substrate 10 and the silicon carbide layer 20, is cooled. For example, the temperature of the epitaxial silicon carbide substrate 100 is reduced from the first temperature (A1) to the second temperature (A2) during the time interval from the third time point (T3) to the sixth time point (T6). The time interval from the third time point (T3) to the sixth time point (T6) is, for example, 60 minutes. The first temperature (A1) is, for example, 1600°C and the second temperature (A2) is, for example, 1600°C. B. 100° C. Therefore, for example, the cooling rate of the epitaxial silicon carbide substrate is 100 (1600-100)° C / 1h = 1500° C / h.The cooling rate from the first temperature (A1) to the second temperature (A2) cannot exceed 1500°C / h, 1300°C / h, or 1000°C / h.

[0050] According to the representation in Fig. 16 The first dislocation arrangement 2 with the first half-loops 1 can be formed in the silicon carbide layer 20 during the cooling step. It is assumed that the first dislocation arrangement 2 is generated due to the third segment 33 of the basal plane dislocation in the silicon carbide layer 20, which slips in the second direction 102 perpendicular to the direction of deviation. The basal plane dislocation 34 (cf. Fig. 15) In the growth step, in the cooling step, the basal plane dislocation 34 ( Fig. 16) with the first section 31, the second section 32 and the third section 33 modified and forms the majority of first half-loops 1. In other words, the correspondingly formed first half-loops 1 arise from the basal plane dislocation 34.

[0051] Preferably, the temperature of the epitaxial silicon carbide substrate 100 is kept uniform in the in-plane direction during the cooling step. In particular, the difference between the maximum and minimum temperatures on the second main surface 30 of the epitaxial silicon carbide substrate 100 is kept to no more than 10°C during the time from the third time (T3) to the sixth time (T6). By reducing the cooling rate of the epitaxial silicon carbide substrate 100 in the cooling step described above, the uniformity of the temperature in the in-plane direction can be improved. As a result, strain in the epitaxial silicon carbide substrate 100 is relieved, thereby suppressing the generation of the first dislocation arrangement 2 of the first half-loops 1 along the straight line perpendicular to the direction of deviation.

[0052] During the period from the fifth time (T5) to the sixth time (T6), the temperature of the epitaxial silicon carbide substrate 100 is reduced from the second temperature (A2) to the third temperature (A3). The third temperature (A3) represents, for example, room temperature. After the temperature of the epitaxial silicon carbide substrate 100 has reached approximately room temperature, it is removed from the reaction chamber 201. In this way, the epitaxial silicon carbide substrate 100 is completed (see Figure 1). Fig. 1).

[0053] According to the representation in Fig. 20. The pressure in reaction chamber 201 can be reduced during the cooling step. For example, the pressure in reaction chamber 201 is reduced from a first pressure (B1) to a second pressure (B2) during the time interval from the third time interval (T3) to the fourth time interval (T4). For example, the first pressure (B1) is 100 mbar (10 kPa) and the second pressure (B2) is 10 mbar (1 kPa). For example, the time interval from the third time interval (T3) to the fourth time interval (T4) is 10 minutes. Specifically, the rate of pressure reduction in reaction chamber 201 is (10 - 1) kPa / 10 min = 0.9 kPa / min. The rate of pressure reduction in reaction chamber 201 cannot be less than 0.9 kPa / min, less than 1.2 kPa / min, or less than 1.5 kPa / min.By rapidly reducing the pressure of the reaction chamber 201 during the cooling step, the interior of the reaction chamber 201 is thermally insulated from the outside, thereby reducing the cooling rate of the epitaxial silicon carbide substrate 100.

[0054] The pressure in reaction chamber 201 can be reduced, for example, by decreasing the flow rate of the carrier gas. For instance, the flow rate of the carrier gas can be 120 slm during the growth step and 12 slm during the cooling step. During the growth step, the carrier gas, the dopant gas, and the source material gas are supplied to reaction chamber 201. During the cooling step, only the carrier gas can be supplied to reaction chamber 201. The flow rate of the carrier gas can be reduced immediately after the end of the growth step or after maintaining a constant flow rate for a certain period of time during the cooling step.

[0055] Next, the following fully describes the growth step of a section of the silicon carbide layer 20 on a specific area XVI of the single-crystal silicon carbide substrate 10.

[0056] According to the representation in Fig. 10 and Fig. 17 At time zero (T0), a basal plane dislocation 44 may be present in the {0001} plane in a specific region XVII within the single-crystal silicon carbide substrate 10. The basal plane dislocation 44 has one end segment exposed at the first major surface 11 and the other end segment exposed at the third major surface 13. The basal plane dislocation extends along the first direction 101, which represents the direction of deviation.

[0057] According to the representation in Fig. 18. The second half-loops 4 arise from the basal plane dislocation 44 at the first time (T1). The two end segments of the second half-loop 4 are exposed at the surface of the silicon carbide layer 20. The sixth segment 43 of the basal plane dislocation, which extends into the silicon carbide layer 20, becomes the second direction (one direction of the arrow in Fig. 18) is displaced. As a result, the basal plane dislocation 44 is transformed into: a fourth section 41, which is located in the single-crystal silicon carbide substrate 10; a fifth section 42, which is located at the interface between the single-crystal silicon carbide substrate 10 and the silicon carbide layer 20 and extends in the second direction; and a sixth section 43, which is located in the silicon carbide layer 20. Accordingly, the second half-loop 4 is generated. One end section of the basal plane dislocation 44 is exposed at the surface of the silicon carbide layer 20, and the other end section is exposed at the third main surface 13.

[0058] According to the representation in Fig. At time 19, another second half-loop 4 arises from the basal plane dislocation 44 at the second time (T2). This second second half-loop 4 is generated on the side of the first direction 101 and the side of the second direction 102 relative to the previously generated second half-loop 4. The depth of the previously generated second half-loop 4 is greater than the depth of the subsequently generated second half-loop 4. At time 1, the sixth segment 43 of the basal plane dislocation present in the silicon carbide layer 20 is further extended in the second direction (one direction of the arrow in Fig. 19) displaced. The sixth section 43 is exposed at the surface of the silicon carbide layer 20. In the manner described above, the majority of second half-loops 4 are formed along the straight line inclined relative to the direction of deviation. The number of second half-loops 4 increases over time. At the third time (T3), the second dislocation arrangement 5 of the second half-loops 4 is formed along the straight line inclined to the direction of deviation (cf. Fig. 6) According to the description above, the second dislocation arrangement 5 is formed during the silicon carbide layer formation step (specifically, the growth step). In other words, it is assumed that the second dislocation arrangement 5 is neither generated nor eliminated during the cooling step of the epitaxial silicon carbide substrate 100. (Method for manufacturing the silicon carbide semiconductor device)

[0059] The following describes a method for manufacturing a silicon carbide semiconductor device 300 according to the present embodiment.

[0060] The method for manufacturing the silicon carbide semiconductor device according to the present embodiment mainly comprises an epitaxial substrate preparation step (S10: Fig. 21) and a substrate processing step (S20: Fig. 21).

[0061] The first step is the epitaxy substrate preparation step (S10: Fig. 21) carried out. In particular, the epitaxial silicon carbide substrate 100 is prepared by the method for producing the epitaxial silicon carbide substrate as described above ( Fig. 1) The epitaxy substrate preparation step (S10: Fig. 21) can include a step of forming a buffer layer 21 on the epitaxial silicon carbide substrate 10.

[0062] Next comes the substrate processing step (S20: Fig. 21) carried out. In particular, the silicon carbide semiconductor device is fabricated by processing the epitaxial silicon carbide substrate. The term "process" includes various types of processes, e.g., ion implantation, heat treatment, etching, oxide film formation, electrode formation, and cutting. In particular, the substrate processing step may include at least one of the processes, e.g., ion implantation, heat treatment, etching, oxide film formation, electrode formation, and cutting.

[0063] The following describes a method for fabricating a MOSFET (metal oxide semiconductor field-effect transistor) as an example of a silicon carbide semiconductor device. The substrate processing step (S20: Fig. 21) includes an ion implantation step (S21: Fig. 21), an oxide film formation step (S22: Fig. 21), an electrode formation step (S23: Fig. 21) and a cutting step (S24: Fig. 21).

[0064] The first step is the ion implantation step (S21: Fig. 21) is carried out. For example, a p-type impurity, such as aluminum (Al), is implanted into the second main surface 30, on which a mask provided with an opening (not shown) is formed. Accordingly, a body region 132 with p-type conductivity is formed. Next, an n-type impurity, such as phosphorus (P), is implanted into a predetermined location in the body region 132. Accordingly, a source region 133 with n-type conductivity is formed. Next, a p-type impurity, such as aluminum, is implanted into a predetermined location in the source region 133. Accordingly, a contact region 134 with a p-type impurity is formed (see Figure 21). Fig. 22).

[0065] A section of the silicon carbide layer 20, distinct from the body region 132, the source region 133, and the contact region 134, serves as a drift region 131. The source region 133 is separated from the drift region 131 by the body region 132. Ion implantation can be performed by heating the epitaxial silicon carbide substrate 100 to a temperature of not less than 300°C and not more than 600°C. After ion implantation, the epitaxial silicon carbide substrate is subjected to an activation heat treatment. This activation heat treatment activates the impurities implanted in the silicon carbide layer 20, thereby generating charge carriers in each region. An atmosphere for the activation heat treatment can be, for example, an argon (Ar) atmosphere. The temperature of the activation heat treatment can be, for example, approximately 1800°C.The activation heat treatment time can be approximately 30 minutes.

[0066] Next, an oxide film formation step (S22: Fig. 21) carried out. For example, the epitaxial silicon carbide substrate 100 is heated in an oxygen-containing atmosphere, causing an oxide film 136 to form on the second main surface 30 (see Fig. 23) is formed. The oxide film 136 is formed, for example, from silicon dioxide (SiO2) or the like. The oxide film 136 functions as a gate insulating film. The temperature of the thermal oxidation treatment can be, for example, approximately 1300°C. The time for the thermal oxidation treatment can be, for example, approximately 30 minutes.

[0067] After the formation of oxide film 136, the heat treatment can continue in a nitrogen atmosphere. For example, the heat treatment can be carried out at approximately 1100°C for about 1 hour in an atmosphere such as nitric oxide (NO) or nitrogen oxide (N₂O). The heat treatment can then be further carried out in an argon atmosphere. For example, the heat treatment in the argon atmosphere can be carried out at approximately 1100°C to 1500°C for about 1 hour.

[0068] Next, the electrode formation step (S23: Fig. 21) is carried out. A first electrode 141 is formed on the oxide film 136. The first electrode 141 functions as a gate electrode. The first electrode 141 is formed, for example, by CVD. The first electrode 141 comprises, for example, an impurity and is formed from polysilicon, which has conductivity, or the like. The first electrode 141 is formed at a location that is oriented towards the source region 133 and the body region 132.

[0069] Next, an intermediate insulating film 137 is formed to cover the first electrode 141. The intermediate insulating film 137 is formed, for example, by CVD. The intermediate insulating film 137 is formed, for example, from silicon dioxide or the like. The intermediate insulating film 137 is formed in contact with the first electrode 141 and the oxide film 136. Next, the oxide film 136 and the intermediate insulating film 137 are removed at a predetermined location by etching. Accordingly, the source region 133 and the contact region 134 are exposed through the oxide film 136.

[0070] For example, a second electrode 142 is formed on the exposed section by sputtering. The second electrode 142 acts as a source electrode. The second electrode 142 is formed, for example, from titanium, aluminum, silicon, or similar materials. After the formation of the second electrode 142, the second electrode 142 and the epitaxial silicon carbide substrate 100 are heated to, for example, a temperature of approximately 900°C to, for example, 1100°C. Accordingly, the second electrode 142 and the epitaxial silicon carbide substrate 100 are brought into ohmic contact with each other. Next, an intermediate compound layer 138 is formed in contact with the second electrode 142. The intermediate compound layer 138 is formed from a material that includes, for example, aluminum.

[0071] Next, the third electrode 143 is formed on the third main surface 13. The third electrode 143 acts as a drain electrode. The third electrode 143 is made of an alloy containing nickel and, for example, silicon (e.g., NiSi or the like).

[0072] Next comes the cutting step (p. 24: Fig. 21) is carried out. For example, the epitaxial silicon carbide substrate 100 is cut along a dividing line, thereby dividing the epitaxial silicon carbide substrate 100 into a plurality of semiconductor chips. In this way, the silicon carbide semiconductor device 300 is produced (see Figure 21). Fig. 24).

[0073] In the above description, the method for fabricating the silicon carbide semiconductor device according to the present invention was described with reference to the MOSFET as an example; however, the fabrication method according to the present invention is not limited to this. The fabrication method according to the present invention is applicable to various types of silicon carbide semiconductor devices, such as IGBTs (isolated gate bipolar transistors), SBDs (Schottky barrier diodes), thyristors, GTOs (gate turn-off thyristors), and PiN diodes.

[0074] The embodiments disclosed herein are illustrative and in no way limiting. The essence of the invention is defined by the expressions of the claims and not by the embodiments described above, and it is intended to include any modifications that signify the scope and meaning of equivalents to the expressions of the claims. Reference symbol list

[0075] 1: first half-loop; 2: first dislocation arrangement; 3, 6, 35, 45: end section; 4: second half-loop; 5: second dislocation arrangement; 10: single-crystal silicon carbide substrate; 11: first main surface; 13: third main surface; 14: fourth main surface (plane); 20: silicon carbide layer; 21: buffer layer; 30: second main surface; 31: first section; 32: second section; 33: third section; 34, 44: basal plane dislocation; 37, 47: imaginary line; 41: fourth section; 42: fifth section; 53: sixth section; 52: outer circumferential region; 53: central region; 54: outer edge; 100: epitaxial silicon carbide substrate; 101: first direction; 102: second direction; 103: third direction; 111: maximum diameter; 131: drift area; 132: body area; 133: source area; 134: contact area; 136: oxide film; 137: intermediate layer insulation film; 138: intermediate compound layer; 141: first electrode; 142: second electrode;143: Third electrode; 200: Manufacturing device; 201: Reaction chamber; 203: Heating element; 204: Quartz tube; 205: Heating insulator; 206: Induction heating coil; 207: Gas inlet; 208: Gas outlet; 210: Susceptor plate; 211: Preheating structure; 212: Rotation axis; 300: Silicon carbide semiconductor device.

Claims

[1] Epitaxial silicon carbide substrate (100), comprising: a single-crystal silicon carbide substrate (10) with a first main surface (11); and a silicon carbide layer (20) on the first main surface (11), wherein the silicon carbide layer (20) comprises a second main surface (30) opposite a surface in contact with the single-crystal silicon carbide substrate (10), wherein the second principal surface (30) corresponds to a plane inclined relative to a {0001} plane in a direction of deviation, wherein the second main surface (30) has a maximum diameter of not less than 100 mm, wherein the second main surface (30) has an outer circumferential region (52) and a central region (53), wherein the outer circumferential region (52) lies within 3 mm of an outer edge (54) of the second main surface (30), wherein the central region (53) is surrounded by the outer circumferential region (52), wherein the central region (53) is provided with a first dislocation arrangement (2) of first half-loops (1) along a straight line perpendicular to the direction of deviation, wherein the area density of the first dislocation arrangement (2) at the central region (53) is not more than 10 / cm² 2 amounts, wherein each of the first half-loops (1) includes a pair of penetration edge dislocations exposed at the second main surface (30), the central area (53) is provided with a second dislocation arrangement (5) of second half-loops (4) along a straight line which is inclined relative to the direction of deviation, wherein each of the second half-loops (4) has a pair of penetration edge dislocations exposed at the second main surface (30), and where the area density of the first dislocation arrangement (2) is lower than the area density of the second dislocation arrangement (5) in the central region (53). [2] Epitaxial silicon carbide substrate (100) according to claim 1, wherein an areal density of the second dislocation arrangement in the central region is higher than 10 / cm² 2 is. [3] Epitaxial silicon carbide substrate (100) according to claim 1 or 2, wherein the maximum diameter is not less than 150 mm. [4] Epitaxial silicon carbide substrate (100) according to any one of claims 1 to 3, wherein the direction of deviation is a <11-20> direction. [5] Epitaxial silicon carbide substrate (100) according to any one of claims 1 to 4, wherein the second main surface (30) corresponds to a plane inclined by no more than 4° relative to a (0001) plane. [6] Epitaxial silicon carbide substrate (100) according to any one of claims 1 to 4, wherein the second main surface (30) corresponds to a plane inclined by no more than 4° relative to a (000-1) plane. [7] Method for manufacturing a silicon carbide semiconductor device, the method comprising the following steps: an epitaxial substrate preparation step (S10) of preparing the epitaxial silicon carbide substrate (100) according to any one of claims 1 to 6; and a substrate processing step (S20) of the processing of the epitaxial silicon carbide substrate (100), wherein the substrate processing step (S20) comprises at least one of the following steps: Ion implantation (S21) of impurities into the second main surface (30), Heating (S22) the epitaxial silicon carbide substrate (100) in an oxygen-containing atmosphere to form an oxide film (136) on the second main surface, Formation (S23) of an electrode (141) on the oxide film (136), Forming an intermediate layer insulating film (137) to cover the electrode (141), Etching of the oxide film (136) and the intermediate layer insulation film (137) to expose the second main surface (30), and Cutting (S24) of the epitaxial silicon carbide substrate (100). [8] Use of the epitaxial silicon carbide substrate (100) according to any one of claims 1 to 6 for the manufacture of a silicon carbide semiconductor device.

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