Semiconductor component and power converter

Abstract

Semiconductor component (1) with: a semiconductor chip (72) having a semiconductor layer (2) having a first surface (4) on a chip bond side, having a second surface (3) on the side opposite the first surface, and having an end surface (5) extending in a direction intersecting the first surface and the second surface, wherein the semiconductor chip (72) has a first electrode (24) formed on the first surface (4) and having a circumferential edge located inward from the end surface (5), and having a second electrode (18) formed on the second surface (3), wherein a transistor (8) is formed on the side of the second surface (3) of the semiconductor layer; a conductive substrate (73) onto which the semiconductor chip (72) is chip-bonded; a conductive spacer element (74) which has a flat surface that is smaller than that of the first electrode (18) and which places the semiconductor chip (72) on the conductive substrate above the first electrode; a resin housing (75) that seals at least the semiconductor chip (72) and the conductive spacer (74); and a bond material (82) provided between the conductive spacer element (74) and the first electrode (24) of the semiconductor chip, and having a projecting section that extends beyond the conductive spacer element (74) and is fitted into the interior of the first electrode (24), wherein the resin housing (75) has a side surface extending in a direction that intersects the first surface (4) and the second surface (3) of the semiconductor chip (72), wherein a part of the conductive substrate (73) is exposed opposite the side surface of the resin housing (75) as a connection section (81), wherein a part of the resin housing (75) enters a space between a section of the semiconductor chip (72) on an outer side of the conductive spacer element (74) and the conductive substrate (73), and where a resistance voltage of the semiconductor component V B1 (V) is a resistance voltage of the resin housing (75) per unit length V B2 (V / mm) and a height distance between the semiconductor chip (72) and the conductive substrate (73) H is, the height H having a value of V B1 / V B2 exceeds.

Description

Technical area

[0001] The present invention relates to a semiconductor device. State of the art

[0002] A bidirectional switch using MOSFETs and / or IGBTs is known as a bidirectional high-voltage AC switch for use in an electrical power system or power generation system. The bidirectional switch is used, for example, in a matrix converter circuit and a neutral point clamp.

[0003] Normally and as it is in Fig. 23, a bidirectional switch 101 includes a combination of two transistors 102A and 102B and two diodes 103A and 103B. In the Fig. In the configuration shown in Fig. 23, the two transistors 102A and 102B are connected in series, and a conduction loss is determined by the sum of the conduction losses of the two transistors 102A and 102B, so that there remains room for improvement in a power loss in the on-state of a bidirectional switch.

[0004] For this reason, a component has been proposed in recent years that has reliability in terms of forward withstand voltage or forward breakdown strength as well as reverse withstand voltage, whereby the component is also referred to as reverse blocking IGBT (RB-IGBT). As it is described in Fig. As shown in Fig. 24, a bidirectional switch 105 whose conduction loss can be calculated on the basis of a single element can be constructed by connecting reverse blocking IGBTs 104A and 104B in parallel.

[0005] For example, as described in Patent Literature 1, a metal film on an inner surface of a trench functions as a Schottky electrode, forming a Schottky junction with an n-type SiC layer. In the device described in Patent Literature 1, when a reverse voltage is applied to induce a negative potential on a drain electrode side between the drain electrode and a source electrode, the Schottky junction is caused to bear the reverse voltage. Literature listPatent literature

[0006] Patent literature 1: JP 2012- 174 831 A Further semiconductor components are known from DE 10 2004 055 908 A1, DE 10 2005 001 151 A1, DE 10 2004 064 235 B3, DE 10 2005 002 767 A1, WO 2015 / 186 305 A1, DE 10 2006 015 447 A1, JP 2012- 256 662 A, US 2009 / 0 134 405 A1, WO 2015 / 166 608 A1, JP 2009-111 187 A and EP 2 851 964 A1. OVERVIEW OF THE INVENTIONTechnical Problem

[0007] In a reverse-blocking device, a semiconductor surface (semiconductor region) of a semiconductor layer constituting a semiconductor chip is sometimes exposed to the outside of a back metal on a chip bonding side. In this case, when a high voltage that makes the surface side positive is applied between a surface metal and the back metal near an end surface on the chip bonding side of the semiconductor layer, a potential distribution is generated that has the same potential as that on the surface side.

[0008] Therefore, when a semiconductor component is mounted on a conductive substrate using a bonding material such as solder, the semiconductor layer and the conductive substrate may be short-circuited via the bonding material. Even if the bonding material is thinned to prevent contact between the semiconductor layer and the conductive substrate, the distance between the semiconductor layer and the conductive substrate or the bonding material is short, and a discharge may occur between them. As a result, a sufficiently large withstand voltage for use as a reverse-blocking component cannot be guaranteed.

[0009] It is therefore an object of the present invention to provide a semiconductor device capable of preventing short-circuiting between a semiconductor layer and a conductive substrate when a first electrode is bonded to a chip bonding side and mounted on the conductive substrate. Solution to the problem

[0010] The above object is achieved by a semiconductor device having the features of claim 1, by a semiconductor device having the features of claim 2, by a semiconductor device having the features of claim 9 and by a semiconductor device having the features of claim 10. The semiconductor devices according to claims 1 and 2 include a semiconductor chip having a semiconductor layer having a first surface on a chip bonding side, a second surface on the opposite side of the first surface, and an end surface extending in a direction crossing the first surface and the second surface, a first electrode formed on the first surface and having a peripheral edge separated inwardly at a position thereof.spaced from the end surface, and having a second electrode formed on the second surface, wherein the semiconductor device further includes a conductive substrate to which the semiconductor chip is chip-bonded, wherein the semiconductor device further includes a conductive spacer having a planar area smaller than that of the first electrode and supporting the semiconductor chip on the conductive substrate, and wherein the semiconductor device includes a resin package sealing at least the semiconductor chip and the conductive spacer.

[0011] With this configuration, even if a high-potential distribution is generated on a semiconductor surface (semiconductor region) on the bonding side when a reverse voltage is applied between the first electrode and the second electrode, an insulating distance between the potential distribution and the conductive substrate can be ensured due to the presence of the conductive spacer. As a result, discharge between the semiconductor layer and the conductive substrate can be prevented.

[0012] In addition, the conductive spacer has a planar surface smaller than that of the first electrode of the semiconductor chip. Therefore, when bonding the semiconductor chip and the conductive spacer, pre-providing an appropriate amount of bonding material to a portion of an upper surface of the conductive spacer can prevent excess bonding material from spreading excessively horizontally and coming into contact with the semiconductor layer after bonding. As a result, the semiconductor layer and the conductive spacer can be prevented from being short-circuited via the bonding material.

[0013] In a semiconductor device according to a preferred embodiment of the present invention, the conductive spacer may be a columnar spacer formed integrally with the conductive substrate.

[0014] In a semiconductor device according to a preferred embodiment of the present invention, the columnar spacer may be formed in a rectangular parallelepiped shape having a side surface perpendicular to a surface of the conductive substrate.

[0015] In a semiconductor device according to a preferred embodiment of the present invention, the columnar spacer may be formed in a shape having a tapered side surface inclined with respect to the surface of the conductive substrate.

[0016] In a semiconductor device according to a preferred embodiment of the present invention, the columnar spacer may be formed into a shape having a side surface having a curved surface concave inward with respect to the columnar spacer.

[0017] In a semiconductor device according to a preferred embodiment of the present invention, the conductive spacer element can be bonded to the conductive substrate via a second bonding material.

[0018] In a semiconductor device according to a preferred embodiment of the present invention, the conductive spacer and the conductive substrate may be formed of materials different from each other.

[0019] In the semiconductor components according to claims 9 and 10, a semiconductor chip includes a semiconductor layer having a first surface on a chip-bonding side, a second surface on the side opposite the first surface, and an end surface extending in a direction crossing the first surface and the second surface, a first electrode formed on the first surface and having a peripheral edge at a position spaced inward from the end surface, a second electrode formed on the second surface, a conductive substrate to which the semiconductor chip is chip-bonded, a conductive spacer, which is a hollow conductive spacer formed by selectively protruding a part of the conductive substrate and having a flat surface area smaller than that of the first electrode, and a resin package,which seals at least the semiconductor chip and the conductive spacer element.,

[0020] In a semiconductor device according to a preferred embodiment of the present invention, the semiconductor chip may have, in a surface portion of the semiconductor layer on the first surface side, a first doping region of a first conductivity type electrically connected to the first electrode, and may have a second doping region of a second conductivity type exposed on the outer side of the first electrode, wherein the second doping region may have a portion that may be at the same potential as that of the second electrode when a reverse voltage is applied between the first electrode and the second electrode.

[0021] A semiconductor device according to a preferred embodiment of the present invention may include a bonding material provided between the conductive spacer and the first electrode of the semiconductor chip, and has a protruding portion protruding from the conductive spacer and fitted within the first electrode.

[0022] A semiconductor device according to a preferred embodiment of the present invention may further include a protective insulating film formed in contact with at least a peripheral edge portion of the first electrode and covering an area from the peripheral edge of the first electrode to the end surface of the semiconductor layer.

[0023] In the semiconductor devices according to claim 1 and 9, a part of the resin package can penetrate into a space between a portion of the semiconductor chip on an outer side of the conductive spacer and the conductive substrate, and when a withstand voltage of the semiconductor device V B1 (V) is a resistance voltage of the resin package per unit length V B2 (V / mm), and a height distance between the semiconductor chip and the conductive substrate is H, then the height H can have a value of V B1 / V B2 exceed.

[0024] In the semiconductor devices according to claim 2 and 10, a part of the resin package can penetrate into a space between a portion of the semiconductor chip on an outer side of the conductive spacer and the conductive substrate, and when a withstand voltage of the semiconductor device V B1(V) is a resistance voltage of the resin package per unit length V B2 (V / mm), and a distance between a peripheral surface of the conductive spacer element and a peripheral surface of a termination structure, in particular in the form of a second doping region, is L, then the distance L can have a value of V B1 / V B2 exceed.

[0025] In a semiconductor device according to a preferred embodiment of the present invention, the conductive spacer may be made of Cu or an alloy including Cu, or of a metal whose surface is plated or coated with Cu.

[0026] In a semiconductor device according to a preferred embodiment of the present invention, the conductive substrate may include a substrate terminal having an island portion on which the semiconductor chip is arranged and the terminal portion extending from the island portion.

[0027] In a semiconductor device according to a preferred embodiment of the present invention, the semiconductor chip may include an active region within which a plurality of transistors are formed in a surface portion of the semiconductor layer, and may include an outer peripheral region within which a protective element is formed to surround the active region.

[0028] In a semiconductor device according to a preferred embodiment of the present invention, the semiconductor layer may be a wide band gap type semiconductor layer.

[0029] A power converter according to a preferred embodiment of the present invention uses the semiconductor device as a bidirectional switching circuit. SHORT DESCRIPTION OF THE DRAWING Fig. 1 is a schematic plan view of a semiconductor device according to an example. Fig. 2 is a schematic bottom view of the semiconductor device according to the example. Fig. 3 is a schematic sectional view of the semiconductor device according to the example. Fig. 4A is a view showing part of a manufacturing process of the semiconductor device of the Fig. 3 shows. Fig. 4B is a view that takes you to the Fig. 4A shows the following step. Fig. 4C is a view that takes you to the Fig. 4B shows the following step. Fig. 4D is a view that allows you to Fig. 4C shows the following step. Fig. 4E is a view that takes you to Fig. 4D shows the following step. Fig. 4F is a view that takes you to Fig. 4E shows the following step. Fig. 4G is a view that Fig. 4F shows the following step. Fig. 4H is a view that takes you to Fig. 4G shows the following step. Fig. 5A is a schematic sectional view of a semiconductor device, the view being used to show an effect of a reverse leakage characteristic. Fig. Figure 5B is a schematic sectional view of a semiconductor device and is used to show an effect of a reverse leakage characteristic. Fig. Figure 5C is a schematic cross-sectional view of a semiconductor device and is used to show an effect of a reverse leakage characteristic. Fig. Figure 6 is a diagram showing reverse leakage characteristics of the semiconductor devices used in the Fig. 5A to Fig. 5C are shown. Fig. Figure 7 is a diagram showing an Id-Vd forward characteristic of the semiconductor device used in Fig. 5C is shown. Fig. Figure 8 is a diagram showing a forward Schottky characteristic of the semiconductor device used in Fig. 5C is shown. Fig. 9 is a diagram showing a resistance-voltage characteristic of the semiconductor device used in Fig. 5C is shown. Fig. Figure 10 is a circuit diagram of a bidirectional switch using reverse-blocking SiC MISFETs. Fig. 11 is a view of another embodiment of a rear termination structure shown in Fig. 3 is shown. Fig. 12 is a view of another embodiment of a rear termination structure, the Fig. 3 is shown. Fig. 13 is a schematic cross-sectional view of a semiconductor device including field stop layers. Fig. 14 is a schematic cross-sectional view of a semiconductor device including field stop layers. Fig. Figure 15 is a view for describing field relaxation regions formed at a Schottky interface. Fig. Figure 16 is a view for describing field relaxation regions formed at a Schottky interface. Fig. 17 is a view for describing a variation of a planar pattern on the back end structure. Fig. 18 is a view for describing a variation of a planar pattern of the back end structure. Fig. 19 is a view for describing a variation of a planar pattern of the back end structure. Fig. 20 is a view of an example of a combination pattern of a back termination structure and field relaxation regions. Fig. 21 is a view showing an example of a combination pattern of a back termination structure and field relaxation regions. Fig. 22 is a view showing an example of a combination pattern of a back termination structure and field relaxation regions. Fig. Figure 23 is a circuit diagram of a bidirectional switch configured by connecting conventional MOSFETs in series. Fig. Figure 24 is a circuit diagram of a bidirectional switch using reverse blocking IGBTs. Fig. Fig. 25 is a view for describing a short-circuit fault that may occur when a semiconductor device is mounted on a metal substrate. Fig. Fig. 26 is a view for describing a short-circuit fault that may occur when a semiconductor device is mounted on a metal substrate. Fig. 27 is a schematic sectional view of a semiconductor device according to another example. Fig. 28A is a view showing a part of a manufacturing process of the semiconductor device used in Fig. 27 is shown. Fig. 28B is a view showing one of the Fig. 28A shows the following step. Fig. 28C is a view showing one of the Fig. 28B shows the following step. Fig. 28D is a view showing one of the Fig. 28C shows the following step. Fig. 28E is a view showing one of the Fig. 28D shows the following step. Fig. 28F is a view showing one of the Fig. 28E shows the following step. Fig. Fig. 29 is a view showing another embodiment of a protective insulating film used in Fig. 27 is shown. Fig. 30 is a view showing still another embodiment of a protective insulating film used in Fig. 27 is shown. Fig. 31 is a view for describing a variation of an element structure of the semiconductor device shown in Fig. 27 is shown. Fig. 32 is a view for describing a variation of the element structure of the semiconductor device shown in Fig. 27 is shown. Fig. 33 is a view for describing a variation of the element structure of the semiconductor device shown in Fig. 27 is shown. Fig. 34 is a view for describing a variation of the element structure of the semiconductor device shown in Fig. 27 is shown. Fig. 35 is a view for describing a short-circuit fault that may occur when a semiconductor device is mounted on a metal substrate. Fig. Fig. 36 is a view for describing a short-circuit fault that may occur when a semiconductor device is mounted on a metal substrate. Fig. Fig. 37 is a view for describing a discharge defect that may occur when a semiconductor device is mounted on a metal substrate. Fig. 38 is a schematic perspective view of a semiconductor device according to an embodiment of the present invention. Fig. 39 is a partial sectional view of the semiconductor device shown in Fig. 38 is shown. Fig. 40 is a view for describing a variation of a spacer used in Fig. 38 and Fig. 39 is shown. Fig. 41 is a view for describing a variation of the spacer used in Fig. 38 and in Fig. 39 is shown. Fig. 42 is a view for describing a variation of the spacer used in Fig. 38 and in Fig. 39 is shown. Fig. 43 is a view for describing a variation of the spacer used in Fig. 38 and in Fig. 39 is shown. Fig. 44 is a view showing a modification of a semiconductor chip used in Fig. 38 and in Fig. 39 is shown. Fig. 45 is a view showing a modification of the semiconductor chip used in Fig. 38 and in Fig. 39 is shown. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] Examples and preferred embodiments of the invention will now be described in detail with reference to the accompanying drawings.

[0031] The Fig. 1 and Fig. 2 are a top view and a bottom view of a semiconductor device 1 according to an example.

[0032] The semiconductor component 1 has a source electrode 18 and a gate pad 47 on the side of its surface 3, and has a drain electrode 24 on the side of its rear surface 4.

[0033] The source electrode 18 is formed in a substantially quadrilateral shape on substantially the entire surface 3 and has a peripheral edge 48 in a position spaced inward from an end surface 5 of the semiconductor device 1. A surface termination structure such as a guard ring, which will be described later, is provided on the peripheral edge. Accordingly, on the surface 3 of the semiconductor device 1, a semiconductor region 49 is exposed around the source electrode 18. In this preferred embodiment, the semiconductor region 49 surrounding the source electrode 18 is exposed. The gate pad 47 is provided in a corner portion of the source electrode 18 at a distance from the source electrode 18.

[0034] As described in the following description, the drain electrode 24 is formed in a substantially quadrilateral shape on substantially the entire surface 4 and has a peripheral edge 25 in a position spaced inward from the end surface 5 of the semiconductor device 1. Accordingly, on the rear surface 4 of the semiconductor device 1, a semiconductor region 26 is exposed around the drain electrode 24. In this preferred embodiment, the semiconductor region 26 surrounding the drain electrode 24 is exposed.

[0035] Fig. 3 is a schematic sectional view of the semiconductor device 1 according to an example.

[0036] The semiconductor component 1 includes a semiconductor layer 2 made of n-type SiC --type. The semiconductor substrate 2 has the surface 3 and the back surface 4 on the side opposite to the surface 3, and has the end surface 5 extending in a direction crossing the surface 3 (a direction extending in Fig. 3 extends in a vertical direction). The surface 3 may be a Si surface of SiC, and the back surface 4 may be a C surface of the SiC.

[0037] The semiconductor layer 2 has a thickness of 10 µm to 100 µm. The semiconductor layer 2 has an overall substantially uniform doping concentration, wherein the doping concentration is, for example, in a range of 1 × 10 14 cm -3 up to 1 × 10 17 cm -3An overall substantially uniform doping concentration here means that the semiconductor layer 2 does not have an n-type portion (for example, an n + -type) with a comparatively high doping concentration (for example, a region starting from the rear surface 4 up to a certain distance in the thickness direction).

[0038] The semiconductor device 1 has an outer peripheral region 6 set or formed at its peripheral edge portion (portion near the end face 5) and has an active region 7 surrounded by the outer peripheral region 6.

[0039] An MIS transistor structure 8 is formed in a surface portion of the semiconductor layer 2 in the active region 7. The MIS transistor structure 8 includes p-type body regions 9, n-type source regions 10, and +-type, a gate insulation film 11, gate electrodes 12 and body contact regions 13 of the p + -Type.

[0040] In detail, a plurality of p-type body regions 9 are formed in the surface portion of the semiconductor layer 2. Each p-type body region forms a minimal unit (unit cell) in which a current flows in the active region 7. The n-type source region 10 + -type is formed in an inner region of each p-type body region 9 such that it is exposed at the surface 3 of the semiconductor layer 2. In the p-type body region 9, a region on the outer side of the n-type source region 10 defines + -Type (region that contains the source region 10 from the n + -type) surrounds a channel region 14. The gate electrode 12 extends over adjacent unit cells and faces the channel regions 14 via the gate insulation film 11. The body contact region 13 of the p +-type penetrates the source region 10 of the n + -type and is electrically connected to the p-type body region 9.

[0041] Each section of the MID transistor structure 8 is described additionally. For example, a doping concentration of the p-type body region 9 is in the range of 1 × 10 16 cm -3 up to 1 × 10 19 cm -3 , a doping concentration of the source region 10 of n + -Type, for example, is in a range of 1 × 10 19 cm -3 up to 1 × 10 21 cm -3 , and a doping concentration of the body contact region of p + -Type, for example, is in a range of 1 × 10 19 cm -3 up to 1 × 10 21 cm -3The gate insulation film 11 is made of, for example, silicon oxide (SiO2), and its thickness is in a range of 20 nm to 100 nm. The gate electrode 12 is made of, for example, polysilicon.

[0042] In the semiconductor layer 2 there is a region of n - -type on the side of the rear surface 4 with respect to the MIS transistor structure 8 a drift region 15 of the n - -type, and it is exposed on the back surface 4 of the semiconductor layer 2.

[0043] A dielectric interlayer film 16 is formed on the semiconductor layer 2, extending over both the active region 7 and the outer peripheral region 6. The dielectric interlayer film 16 is made of silicon oxide (SiO2), for example, and has a thickness in the range of 0.5 µm to 3.0 µm. Contact holes 17 are formed in the dielectric interlayer film 16 to connect the source regions 10 from the n-type. +-Type and the body contact regions 13 from the p + -type of each unit cell.

[0044] A source electrode 18 is formed on the interlayer dielectric film 16. The source electrode 18 penetrates into the respective contact holes 17 and comes into ohmic contact with the source regions 10 of the n + -Type and the body contact regions 13 from the p + -type. The source electrode 18 has an overlap portion 19 that extends from the active region 7 toward the outer peripheral region 6 and that rests on the interlayer dielectric film 16 in the outer peripheral region 6.

[0045] A surface termination structure 20 is formed in the surface portion of the semiconductor layer 2 in the outer peripheral region 6. The surface termination structure 20 may include a plurality of portions including at least one portion overlapping a peripheral edge portion of the source electrode 18 (a peripheral edge portion of a junction portion joined to the semiconductor layer 2). Fig. 3, the surface termination structure includes a RESURF (Reduced Surface Field) layer 21 at the innermost side, and includes a plurality of guard ring layers 22 surrounding the RESURF layer 21. The RESURF layer 21 is formed to extend across the inside and outside of an opening 23 of the interlayer dielectric film 16 and is in contact with the peripheral edge portion of the source electrode 18 within the opening 23. The plurality of guard ring layers 22 are formed at intervals. The surface termination structure 20 may be formed from a p-type doping region.

[0046] A drain electrode 24 is formed on the back surface 4 of the semiconductor layer 2. The drain electrode 24 is an electrode common to a plurality of unit cells. The drain electrode 24 is formed of a metal (e.g., a lamination structure of Ti / Al, etc.) that can form a Schottky junction with the semiconductor layer 2. Specifically, it is required that a layer (e.g., a Ti layer) in contact with the semiconductor layer 2 in the drain electrode 24 can form a Schottky junction with the semiconductor layer 2.

[0047] The drain electrode 24 is formed to have a peripheral edge 25 in a position spaced inward from the end surface 5 of the semiconductor layer 2. Accordingly, on the rear surface 4 of the semiconductor layer 2, the semiconductor region 26 around the drain electrode 24 is exposed. In this preferred embodiment, a semiconductor region 26 surrounding the drain electrode 24 is exposed (see Fig. 17 to Fig. 22). The peripheral edge portion of the drain electrode 24 faces the peripheral edge portion of the source electrode 18, across the semiconductor layer 2 or, in a view through the semiconductor layer 2. In detail, the drain electrode 24 has a peripheral edge portion that extends from the active region 7 toward the outer peripheral region 6 and is arranged in the outer peripheral region 6 directly below the surface termination structure 20 (in this preferred embodiment, the RESURF layer 21). The drain electrode 24 can be formed to have the same size as the source electrode 18, as shown in Fig. 3 is shown.

[0048] In the outer peripheral region 6, a back termination structure 27 is formed in a portion on the back surface of the semiconductor layer 2. The back termination structure 27 includes an inner peripheral edge 28 on the inner side of the peripheral edge 25 of the drain electrode 24, and an outer peripheral edge 29 positioned on the outer side of the peripheral edge 25 of the drain electrode 24 and spaced inward from the end surface 5 of the semiconductor layer 2. In this preferred embodiment, the formation area of ​​the back termination structure 27 is substantially the same as that of the surface termination structure 20. Therefore, the outer peripheral edge 29 of the back termination structure 27 can coincide with the outer peripheral edge 30 of the outermost guard ring layer 22.

[0049] The rear connection structure 27 may be a high-resistivity region having a higher resistance than the drift region 15 of the n - -type, or may be a p-type doping region. If it is a high-resistivity region, the backside termination structure 27 may have a crystal defect concentration of 1 × 10 14 cm -3 up to 1 × 10 21 cm -3 On the other hand, in the case of a p-type doping region, the rear termination structure 27 can have a doping concentration in a range of 1 × 10 16 cm -3 up to 1 × 10 19 cm -3 have.

[0050] Next, reference is made to the Fig. 4A to Fig. 4H, which describe a method for manufacturing the semiconductor device 1.

[0051] The Fig. 4A to Fig. 4H are views showing a manufacturing process of the semiconductor device 1 in the order of steps. Fig. 4A to Fig. 4H, only points or times of the method of manufacturing the semiconductor device 1 are described, so that the configuration of the semiconductor device 1 is simpler than in the Fig. 3 shown configuration.

[0052] To produce the semiconductor component 1, as shown in Fig. 4A, first on a base substrate 31 (wafer) made of SiC of n + -type (with a doping concentration of e.g. 1 × 10 18 cm -3 up to 1 × 10 20 cm - 3), a semiconductor layer 2 having a lower concentration than the base substrate 31 is formed by epitaxial growth. A thickness of the base substrate 31 may, for example, be in a range of 250 µm to 450 µm. Next, the above-described MIS transistor structure 8 is formed in the surface portion of the semiconductor layer 2 by conventional semiconductor manufacturing technology. Thereafter, the interlayer dielectric film 16 (not shown) and the source electrode 18 are formed.

[0053] Next, as it is in Fig. 4B, the entire back surface 4 of the semiconductor layer 2 is exposed by removing the base substrate 31. In this step, after the base substrate 31 has been substantially completely removed by grinding from the back surface 4 side, a polishing step (e.g., CMP) may be performed for finishing purposes. In the polishing step, the semiconductor layer 5 exposed after grinding may be further thinned. In detail, it is possible that the base substrate 31 having a thickness of 350 µm is removed by grinding on the back surface, and that the semiconductor layer 2 is thereafter ground to a thickness of 40 µm from a thickness of 50 µm.Finally, by applying the polishing step, the surface state of the exposed back surface 4 of the semiconductor layer 2 can be smoothed so that the drain electrode 24 can be Schottky-joined in a satisfactory manner.

[0054] Next, as it is in Fig. 4C, a resist film 33 selectively having openings 32 is formed on the back surface 4 of the semiconductor layer 2, and p-type dopant ions (e.g., aluminum (Al)) are injected into the back surface 4 of the semiconductor layer 2 via the resist film 33. At this time, alignment (back surface alignment) may be performed to form the pattern of the resist film 33 based on a pattern on the surface 3 seen through the semiconductor layer 2. For example, based on the source electrode 18 seen through the semiconductor layer 2, the openings 32 may be formed in the resist film 33 so as to overlap the source electrodes 18. Thereafter, the p-type dopant is activated by laser annealing, and the back termination structure 27 is formed.

[0055] When the back-end termination structure 27 is formed as a high-resistivity region after forming the resist film 33, boron ions (B), p-type dopant ions, protons, or electron beams are irradiated, and then, by laser annealing or heat treatment at 500°C or less, the back-end termination structure 27 is transformed into a high-resistivity region with a higher resistance value than the semiconductor layer 2. By adopting laser annealing or heat treatment at 500°C or less, the MIS transistor structure 8 already formed on the surface 3 side of the semiconductor layer 2 can also be protected. For example, the source electrodes 18 can be prevented from melting.

[0056] Next, as it is in Fig. 4D, the resist film 33 is removed.

[0057] Next, as it is in Fig. 4E, a metal film 34 (e.g., Ti / Al) is formed on the entire back surface 4 of the semiconductor layer 2, for example, by sputtering.

[0058] The following explains how it is Fig. 4F, a resist film 35 is formed on the metal film 34, selectively covering regions in which drain electrodes 24 are to be formed.

[0059] Next, as it is in Fig. 4G, the metal film 34 is selectively removed by etching over the resist film 35. Accordingly, the drain electrodes 24 are formed. By performing alignment to form the pattern of the resist film 35 based on the source electrodes 18, as shown in Fig. As shown in Figure 3, the drain electrodes 24 and the source electrodes 18 can be formed to have the same size. After the drain electrodes 24 are formed, the resist film 35 is removed.

[0060] Next, the semiconductor layer 2 is cut along cutting lines 36 set at positions away from the peripheral edges 25 of the drain electrodes 24. Consequently, customized semiconductor devices 1 are obtained.

[0061] According to the method described above, a Schottky junction surface (back surface 4) in the semiconductor layer 2 can be easily exposed by removing the base substrate 31, unlike trench formation by etching as disclosed in Patent Literature 1. By forming the drain electrode 24 in a desired size on this Schottky junction surface, a Schottky junction area can be adjusted. For example, as shown in Fig. 4E to Fig. 4G, the metal film 34 is formed on the entire back surface 4 of the semiconductor layer 2, and drain electrodes 24 having desired sizes can be easily obtained by patterning the metal film 34.

[0062] Next, effects of the semiconductor device 1 according to the present preferred embodiment will be described.

[0063] The Fig. 5A to Fig. 5C are schematic cross-sectional views of semiconductor devices A, B, and C, the cross-sectional views being used to show effects of reverse leakage characteristics.

[0064] First of all, the Fig. 5A to Fig. 5C that in Fig. 5C, the semiconductor device C is a semiconductor device having the same configuration as that of the semiconductor device 1 shown in Fig. 3 and described above. On the other hand, in the semiconductor device A shown in Fig. 5A, so that the base substrate 31 made of SiC of n + -type remains on the back surface 4 of the semiconductor layer 2, and the drain electrode 24 is in ohmic contact with the base substrate 31. The semiconductor component B, which is in Fig. 5B is consistent with the semiconductor device C shown in Fig. 5C, in that the base substrate 31 is not provided and the entire rear surface 4 of the semiconductor layer 2 is exposed, wherein the drain electrode 24 forms a Schottky junction with the semiconductor layer 2, but the drain electrode 24 is formed such that it reaches the end surface 5 of the semiconductor layer 2 and the rear termination structure 27 is not provided. Fig. 5B and Fig. 5C, reference numeral 38 denotes a depletion layer when a reverse voltage is applied.

[0065] The reverse leakage characteristics of these semiconductor devices A, B and C are shown in Fig. 6 shown.

[0066] With reference to Fig. 6 flows into the Fig. 5A and Fig. 5B, a reverse leakage current occurs when a reverse voltage is applied between the source and drain. In the configuration shown in Fig. 5A, it is assumed that a current flows to the back side in an ohmic manner (drain electrode 24) via the body diode of the MIS transistor structure 8.

[0067] The configuration shown in Fig. 5B, it is assumed that electron-hole pairs are generated in a defect region 37 (cutting defect) of the end face 5 of the semiconductor layer 2, although a body diode current is blocked by a Schottky barrier of the drain electrode 24, and a current flows by being drifted by an electric field in the depletion layer 38 extending from the Schottky interface (back face 4) to the end face 5.

[0068] On the other hand, it was found that in Fig. 5C, hardly any leakage current flows before the reverse voltage reaches about -3 kV, and when -3 kV is applied, punchthrough occurs. This is because a body diode current is blocked by the Schottky barrier at the drain electrode 24, and the back termination structure 27 is formed to overlap the peripheral edge portion of the drain electrode 24, so that when a reverse voltage is applied, the depletion layer 38 is prevented from reaching the end surface 5 (chip end surface 5) of the semiconductor layer 2. Even if a defect region 37 exists at the end surface 5 of the semiconductor layer 2 due to a dicing process, leakage current can be prevented from flowing due to the generation of electron-hole pairs in the defect region 37. Accordingly, in the semiconductor device C shown in Fig. 5C, a reverse resistance voltage of at least about 3 kV is realized.

[0069] Regarding the semiconductor component C, which is Fig. 5C, forward characteristics were also measured. The semiconductor device C had as a measurement sample a semiconductor layer 2 with a thickness of 40 µm (chip size: 1.6 mm 2 edge length), and an area of ​​the active region 7 was 1.3 mm 2 . Fig. Figure 7 is a diagram showing Id-Vd forward characteristics of the semiconductor device C used in Fig. 5C is shown. Fig. Figure 8 is a diagram showing forward Schottky characteristics of the semiconductor device C used in Fig. 5C is shown.

[0070] With reference to Fig. 7, it was confirmed that the drain current flowed sufficiently when the gate voltage Vgs was increased in steps of 0.5 V, 10 V, 15 V and 20 V. Referring to Fig. 8, an ideal factor at the Schottky interface between the drain electrode 24 and the semiconductor layer 2 had a value of 1.04, showing excellent forward Schottky characteristics.

[0071] From the results described above, the withstand voltage characteristics of the semiconductor device C used in Fig. 5C, as shown in Fig. 9. That is, by adapting the configuration of the semiconductor device 1 according to the present preferred embodiment as shown in Fig. As shown in Figure 9, breakdown did not occur until the voltage reached about 3 kV in both the reverse direction (negative drain-source voltage side) and the forward direction (positive drain-source voltage side), and a withstand voltage of 3 kV or more could be realized.

[0072] Accordingly, the semiconductor device 1 according to the present preferred embodiment can realize a bidirectional withstand voltage of 3 kV or more, and therefore, as shown in Fig. 10, two parallel-connected semiconductor devices 1 can be sufficiently used as a bidirectional switch 39. In detail, in the resistance voltage state shown in Fig. 10, a reverse voltage is applied to the upper transistor 1A (left to right) and the lower transistor 1B (right to left), and a forward voltage is applied to the lower transistor 1B (left to right) and the upper transistor 1A (right to left), and due to sufficient withstand voltage characteristics in both directions, both ends of the transistors can be prevented from becoming conductive.

[0073] Furthermore, when a current is supplied, a conduction loss can be calculated based on a single element of the upper or lower transistor 1A or 1B, so that an on-state loss can be suppressed or reduced to a low level. In addition, by configuring transistors 1A and 1B of the bidirectional switch 39 to achieve a MISFET configuration, a high-speed, low-power bidirectional switch can be realized compared to the case where an IGBT is used.

[0074] A modification of the semiconductor device 1 according to the present preferred embodiment will be described below with reference to the drawings. <Variationen der rückseitigen Abschlussstruktur 27>

[0075] The Fig. 11 and Fig. 12 are views showing further forms of the rear closure structure 27, which in Fig. 3 is shown.

[0076] As it is in Fig. 11, the rear termination structure 27 may have a plurality of sections, with at least one section overlapping a peripheral edge portion of the drain electrode 24. In Fig. 11, the back-side termination structure includes a RESURF (Reduced Surface Field) layer 40 at the innermost side, and a plurality of guard rings 41 surrounding the RESURF layer 40. The RESURF layer 40 is formed to extend across the inside and outside of the drain electrode 24 and is in contact with the peripheral edge portion of the drain electrode 24. The plurality of guard ring layers 41 are formed at intervals. The RESURF layer 40 and the guard ring layers 41 may be positioned one-to-one opposite the RESURF layer 21 and the guard ring layers 22 of the surface termination structure 20.

[0077] As it is in Fig. 12, when the back termination structure 27 is a high-resistivity region as described above, it may be formed to reach the end face 5 of the semiconductor layer 2 from the peripheral edge portion of the drain electrode 24. That is, the outer peripheral edge 29 of the back termination structure 27 may coincide with the end face 5 of the semiconductor layer 2. <Struktur zum Verhindern eines Durchschlages>

[0078] Fig. 13 and Fig. 14 are schematic sectional views of a semiconductor device 1 including field stop layers 42 and 43.

[0079] By forming field stop layers 42 and 43, when a voltage is applied between the source and drain, a depletion layer extending from a low-voltage side can be prevented from reaching a conductive pattern (e.g., MIS transistor structure 8) on a high-voltage side. Consequently, leakage current due to a breakdown phenomenon can be prevented.

[0080] These field stop layers 42 and 43 need only be n-type field stop layers formed on at least the surface 3 side and the back surface 4 side of the semiconductor layer 2, and they may have a higher doping concentration than the n-type drift region 15. - -Type. In the Fig. 13 and Fig. 14, both the surface-side field-stop layer 42 and the back-surface-side field-stop layer 43 are shown.

[0081] The field stop layers 42 and 43 can be arranged, for example, in depth positions away from the surface 3 or the back surface 4 of the semiconductor layer 2, as shown in Fig. 13 is shown.

[0082] In detail, the surface-side field stop layer 42 may be arranged below the MIS transistor structure 8, separated or spaced from the p-type body regions 9 in the direction toward the side of the rear surface 4.

[0083] On the other hand, the rear surface field stop layer 43 may be arranged on an upper side, separated or spaced from the rear termination structure 27 in the direction toward the side of the surface 3.

[0084] It is also permissible that the field stop layers 42 and 43 are formed so that they reach the surface 3 or the back surface 4 of the semiconductor layer 2, as shown in Fig. 14 is shown.

[0085] In detail, the surface-side field-stopping layer 42 may be formed in an entire region from the surface 3 to a certain depth position so that it comes into contact with the p-type body regions 9 and the surface-side termination structure 20. In this case, the depth of the surface-side field-stopping layer 42 may be deeper than the p-type body regions 9 (solid line A in Fig. 14), or the depth can be set to the center of the p-type body regions 9 (dashed line A' in Fig. 14). That is, in the latter case, the p-type body regions 9 are selectively exposed toward the rear surface 4, starting from the surface-side field-stop layer 42.

[0086] On the other hand, the back surface field stop layer 43 may be formed in an entire region from the back surface 4 to a certain depth position so that it comes into contact with the back termination structure 27. In this case, the depth of the back surface field stop layer 43 may be deeper than the back surface termination structure 27 (solid line B in Fig. 14), or can be set to the center of the rear surface-side closure structure 27 (dashed line B' in Fig. 14). That is, in the latter case, the rear surface-side termination structure 27 is selectively exposed toward the side of the surface 3, starting from the rear surface-side field-stop layer 43.

[0087] Doping concentrations in the field stop layers 42 and 43 may have profiles that are uniform in the depth direction of the semiconductor layer 2, or may have profiles that reach peaks at specific depth positions. If the doping concentration has a peak, the concentration at this peak merely needs to be higher than a concentration of the drift region 15 of the n - -Type.

[0088] The field stop layers 42 and 43 in the Fig. 13 and Fig. 14 can be combined with each other as appropriate. For example, it is also permissible for the rear-surface field-stop layer 43 to be formed so that it reaches the rear surface 4 of the semiconductor layer 2, whereas the surface-side field-stop layer 42 is arranged in a position separated or spaced from the surface 3 of the semiconductor layer 2. <Reduktion der rückflächenseitigen Schottky-Leckage>

[0089] Fig. 15 and Fig. 16 are views for describing field relaxation regions 44 formed at the Schottky interface. Fig. 15 and Fig. 16 correspond to enlarged views of a region A, which in Fig. 3 is enclosed by a dashed line.

[0090] That is, the semiconductor device 1 may include field relaxation regions 44 formed in a back surface side portion of the semiconductor layer 2, specifically in a region on the inner side of the back surface side termination structure 27, the field relaxation regions 44 being in contact with the drain electrode 24.

[0091] By forming the field relaxation regions 44, an electric field can be generated at the Schottky interface between the drift region 15 of the n --type and the drain electrode 24. Accordingly, even when a metal having a comparatively low work function is used as the drain electrode 24, a reverse leakage current can be reduced, so that a low on-resistance can be ensured by using this metal. In detail, although it is also possible to reduce a reverse leakage current at the expense of a low on-resistance, in this configuration, a reverse leakage current can be reduced through the field relaxation regions 44, so that a low on-resistance value can be realized by using a metal having a lower work function than a metal to be used when the field relaxation regions 44 are not provided.

[0092] The field relaxation regions 44 can, similar to the rear surface termination structure 27, be highly resistive regions with a higher resistance value than the drift region 15 of the n - -type, or may be p-type doping regions. In the case of the high-resistivity regions, the rear surface termination structure 27 may have a crystal defect concentration of 1 × 10 14 cm -3 up to 1 × 10 21 cm -3 On the other hand, in the case of p-type doping regions, the rear surface termination structure 27 may have a doping concentration of 1 × 10 16 cm -3 up to 1 × 10 19 cm -3 If the configurations of the field relaxation regions 44 and the back surface termination structure 27 are aligned, they can be formed together in the same step (e.g., in the Fig. 4C).

[0093] As it is in Fig. 15, when the back surface 4 of the semiconductor layer 2 has a substantially uniform flat portion 45 in a region on the inner side of the back surface termination structure 27, the field relaxation regions 44 can be formed on the flat portion 45.

[0094] As it is in Fig. 16, when the back surface 4 of the semiconductor layer 2 selectively has trenches 46 in a region on the inner side of the back surface termination structure 27, the field relaxation regions 44 can be formed along inner surfaces of the trenches 46 in the drift region 15 of the n - -type. In this case, the drain electrode 24 can be embedded in the trenches 46 and can be connected to the field relaxation regions 44 in the trenches 46. <Ebene Muster der rückflächenseitigen Abschlussstruktur 27 und der Feldrelaxationsregionen 44>

[0095] The Fig. 17 to 19 are views for describing variations of the planar pattern of the back surface termination structure 27. The Fig. 20 to Fig. 22 are views for describing examples of a combination pattern of the back termination structure 27 and the field relaxation regions 44.

[0096] First, as it is in Fig. 17, the rear surface termination structure 27 may be formed into an annular shape surrounding the active region 7.

[0097] If the rear surface-side termination structure 27 is formed from a plurality of layers, as shown in Fig. 11, as shown in Fig. 18, in the rear termination structure 27, a RESURF layer 40 and a guard ring layer 41 assume annular shapes that spread or extend concentrically.

[0098] As it is in Fig. 19, when the rear termination structure 27 is a high-resistivity region as described above, it may assume a ring-shaped form reaching the end surface 5 of the semiconductor layer 2 from the peripheral edge portion of the drain electrode 24. This configuration corresponds to the configuration shown in Fig. 12 is shown.

[0099] Different patterns of field relaxation regions 44 can be combined with any planar pattern of the rear termination structure 27 shown above. Fig. 20 to 22 are exemplary combinations with the rear end structure 27, which in Fig. 17 is shown.

[0100] For example, as in Fig. 20, the field relaxation regions 44 are arranged discretely in the active region 7, which is surrounded by the rear termination structure 27 in a plan view. In Fig. 20, the field relaxation regions are arranged in a matrix within a region spaced from the rear termination structure 27.

[0101] As it is in Fig. 21, the field relaxation regions 44 in the active region 7, which is surrounded by the backside termination structure 27 in a plan view, may be arranged in a striped pattern. The field relaxation regions 44 in a striped pattern may be connected to the backside termination structure 27 at both end portions, as shown in Fig. 21, or may be separated or spaced apart from the rear termination structure 27 at least at one end portion. The strip direction does not necessarily have to be parallel to the end surface 5 of the semiconductor layer 2, as shown in Fig. 21, and may extend in a direction (direction of arrow D) crossing the end face 5 of the semiconductor layer 2.

[0102] As it is in Fig. 22, the field relaxation regions 44 may be arranged in a lattice pattern in the active region 7, which is surrounded by the backside termination structure 27. The field relaxation regions 44 in the lattice pattern may be connected to the backside termination structure 27 at each end portion, as shown in Fig. 22, or may be separated from the rear end structure 27 at least at one end portion.

[0103] The patterns of field relaxation regions 44, which in Fig. 20 to Fig. 22 can of course be combined with the patterns of the rear end structure 27 shown in the Fig. 18 and Fig. 19 are shown.

[0104] The Fig. 25 and Fig. 26 are views for describing short-circuit faults that may occur when the semiconductor device 1 is mounted on a metal substrate 50. The metal substrate 50 may include a member for supporting the semiconductor device 1 at the time of mounting, such as an island portion 80 ( Fig. 38, Fig. 39) of a drain terminal 77, which is described below.

[0105] As it is in Fig. As shown in Figure 10, when the semiconductor devices 1 are used as the bidirectional switch 39 and a forward voltage is applied to one transistor, a reverse voltage is applied to the other transistor. For the case of "when powered, left to right" in the upper left cell in Fig. 10, for example, a reverse voltage is applied to the transistor 1A, whereas a forward voltage is applied to the transistor 1B. That is, between the source electrode 18 and the drain electrode 24 of the transistor 1A (semiconductor device 1, shown in Fig. 25), as in Fig. 25, a high voltage (e.g. 1000 V) is applied, which makes the source side positive.

[0106] At this point, as it is in Fig. 5C, in the configuration of the semiconductor device 1, the depletion layer 38 is prevented from reaching the end surface 5 (chip end surface 5) of the semiconductor layer 2. As shown in Fig. 25, however, in the region between an end portion of the depletion layer 38 and the chip end face 5, a potential distribution having the same potential (e.g., 1000 V) as that of the surface side is generated via the semiconductor layer 2.

[0107] Therefore, if, as it is in Fig. 26, the side of the drain electrode 24 is set as a bonding side, and when the semiconductor device 1 is mounted on the metal substrate 50 through a bonding material 51 such as solder, the semiconductor layer 2 and the metal substrate 50 can be short-circuited via the bonding material 51.

[0108] Therefore, the Fig. 27, the semiconductor device 52 has a protective insulating film 53 which is in contact with the peripheral edge portion of the drain electrode 24 and which covers the semiconductor region 26 from the peripheral edge 25 of the drain electrode 24 to the end surface 5 of the semiconductor layer 2.

[0109] The protective insulating film 53 in this preferred embodiment has a structure in which a first film 54 and a second film 55 are laminated one on top of the other in this order starting from the back surface 4 of the semiconductor layer 2.

[0110] The first film 54 is sandwiched between the peripheral edge portion of the drain electrode 24 and the semiconductor layer 2, and the second film 55 has an overlap portion 56 that sits on the peripheral edge portion of the drain electrode 24. The overlap portion 56 may have an inner peripheral edge 57 that is arranged on the inner side or on the inside of an inner peripheral edge 58 of the first film 54, as shown in Fig. 27, and the inner peripheral edge 57 may further be disposed on an inner side of an inner peripheral edge 28 of the rear end structure 27.

[0111] The protective insulating film 53 can be made of various insulating materials. Applicable materials include, for example, SiO2, SiN, and polyimide, etc. Among them, SiO2 or SiN is preferably used for the first film 54, and polyimide is used for the second film 55. Film formability is unsatisfactory when SiO2 and SiN are formed on a metal film of the drain electrode 24, etc., compared to a resin film made of polyimide, etc., so by using this material for the first film 54, the adhesiveness of the protective insulating film 53 can be improved.

[0112] The protective insulating film 53 may have a thickness t that satisfies the following equation based on the back surface 4 of the semiconductor layer 2. This thickness t is a thickness of a portion from the chip end surface 5 to the peripheral edge portion 25 of the drain electrode 24 in the protective insulating film 53 (portion at the semiconductor region 26). When the protective insulating film 53 is a lamination film including the first film 54 and the second film 55, as shown in Fig. 27, the thickness t may be the sum of the thicknesses of the first film 54 and the second film 55. t>V / (3MV / cm)

[0113] (In equation (1), V is a voltage to be applied in a reverse direction between the source electrode 18 and the drain electrode 24.)

[0114] For example, when the protective insulating film 53 is SiO2, a relationship between an applied voltage V between source and drain and the thickness t of the protective insulating film 53 may be as follows. Applied voltage V = 650 V: Thickness t > 2.2 µm Applied voltage V = 1200 V: Thickness t > 4.0 µm Applied voltage V = 1700 V: Thickness t > 5.7 µm Applied voltage V = 3000 V: Thickness t > 10.0 µm

[0115] According to this semiconductor device 52, the semiconductor region 26 is covered by the protective insulating film 53 from the peripheral edge 25 of the drain electrode 24 on a side to be bonded to the metal substrate 50 to the end surface 5 of the semiconductor layer 2. Accordingly, when the drain electrode 24 is bonded to the metal substrate 50 and then mounted, the semiconductor region 26 of the semiconductor layer 2 can be prevented from coming into contact with the bonding material 51 and the metal substrate 50, so that a short circuit between the semiconductor layer 2 and the metal substrate 50 can be prevented.

[0116] Next, a method of manufacturing the semiconductor device 52 will be described with reference to FIG. Fig. 28A to Fig. 28F described.

[0117] The Fig. 28A to 28F are views showing a manufacturing process of the semiconductor device 52 used in Fig. 27, in the sequence of steps. In Fig. 28A to Fig. 28F, only points or times of the process of manufacturing the semiconductor device 52 are described, so that the configuration of the semiconductor device 52 is shown more simply than that in Fig. Configuration shown in 27.

[0118] In order to manufacture the semiconductor component 52, first, as shown in Fig. 28A, on a base substrate 31 (wafer) made of n-type SiC + -type (with a doping concentration of, for example, in the range of 1 × 10 18 cm -3 up to 1 × 10 20 cm -3), a semiconductor layer 2 having a lower concentration than the base substrate 31 is formed by epitaxial growth. Next, the above-described MIS transistor structure 8 is formed in the surface portion of the semiconductor layer 2 by a known semiconductor manufacturing technology. Thereafter, the interlayer dielectric film 16 and the source electrode 18 are formed.

[0119] Next, as it is in Fig. 28B, by removing the base substrate 31, the entire rear surface 4 of the semiconductor layer 2 is exposed.

[0120] Next, as it is in Fig. 28C, a resist film (not shown) selectively having openings is formed on the back surface 4 of the semiconductor layer 2, and p-type dopant ions (e.g., aluminum (Al)) are injected into the back surface 4 of the semiconductor layer 2 via the resist film. Thereafter, the p-type dopant is activated by laser annealing, and the back termination structure 27 is formed.

[0121] Next, as it is in Fig. 28D, an insulating film of SiO2, SiN, etc. is formed, for example, by a CVD method, on the entire back surface 4 of the semiconductor layer 2, and is selectively etched to form the first film 54.

[0122] Next, as it is in Fig. 28E, for example, by sputtering, a metal film is formed on the entire back surface 4 of the semiconductor layer 2, and then selectively etched to form the drain electrode 24.

[0123] Next, as it is in Fig. 28F, a resin film of polyimide, etc., is applied to the entire back surface 4 of the semiconductor layer 2 and patterned by selective exposure and development to form the second film 55. Accordingly, the protective insulating film 53 including the first film 54 and the second film 55 is formed.

[0124] Thereafter, the semiconductor layer 2 is cut along cutting lines (not shown) set at positions away from the peripheral edge 25 of the drain electrode 24. Accordingly, individualized semiconductor devices 52 are obtained. <Variationen des Schutzisolationsfilms 53>

[0125] The Fig. 29 and Fig. 30 are views showing other forms of the protective insulation film 53 used in Fig. 27 is shown.

[0126] The protective insulation film 53 may be a single-layer film of the above-described first film 54, as shown in Fig. 29, or may be a single-layer film of the second film 55 described above, as shown in Fig. 30. In the case of Fig. 30, the protective insulation film 53 (second film 55) is formed in contact with the semiconductor region 26, starting from the peripheral edge 25 of the drain electrode 24 toward the end surface 5 of the semiconductor layer 2. <Variationen der Elementstruktur>

[0127] Fig. 31 to Fig. 34 are views for describing variations of the element structure of the semiconductor device 52 shown in Fig. 27. In the Fig. 31 to 34 are the same components as in Fig. 27 are designated by the same or common reference numerals, and their description is omitted here.

[0128] The semiconductor device 52 has the MIS transistor structure 8 in the surface portion of the semiconductor layer 2 as an element structure in Fig. 27, however, the semiconductor device may have an IGBT structure 59 in the surface portion of the semiconductor layer 2, as shown, for example, in Fig. 31. The IGBT structure 59 may, as a configuration different from that of the MIS transistor structure 8, have p-type base regions 60 instead of the p-type body regions 9, n-type emitter regions 61 + -type instead of the source regions 10 of the n + -Type, base contact regions 62 from p + -Type instead of the body contact regions 13 from the p + -type, an emitter electrode 63 instead of the source electrode 18, and a collector electrode 64 instead of the drain electrode 24.

[0129] A p-type collector region 65 is formed in the rear surface portion of semiconductor layer 2. The collector electrode 64 is in ohmic contact with the p-type collector region 65. The rear termination structure 27 is formed such that it partially overlaps the p-type collector region 65.

[0130] The semiconductor component 52 can, as shown in Fig. 32, for example, may have a JFET structure 66 in the surface portion of the semiconductor layer 2. The JFET structure 66 includes, as a configuration different from that of the MIS transistor structure 8, p-type gate regions 67 instead of the gate insulation films 11.

[0131] The semiconductor component 52 can, for example, as shown in Fig. 33, may be configured as an MIS-type bidirectional switch having MIS transistor structures 8 formed in both surface portions on both the surface 3 side and the back surface 4 side of the semiconductor layer 2. In this case, the drain electrode 24 functions as a source electrode of the MIS transistor structure 8 on the back surface 4 side. That is, when a forward voltage is applied to one of the MIS transistor structures 8 on the surface 3 side and the back surface 4 side, a reverse voltage is applied to the other MIS transistor structure 8. Such an MIS-type bidirectional switch can be manufactured by bonding together the back surfaces of semiconductor wafers each having an MIS transistor structure 8 on one surface side.

[0132] Furthermore, the semiconductor component 52 can, for example, as shown in Fig. 34, may be configured as a JFET-type bidirectional switch, with JFET structures 66 formed in surface portions of both the surface 3 side and the back surface 4 side of the semiconductor layer 2. The semiconductor device 2 may be a trench-gate type MIS transistor structure, or an IGBT, which is not shown in the drawings. <Andere bevorzugte Ausführungsformen, die in der Lage sind, einen Kurzschluss zwischen Halbleiterschicht und Metallsubstrat zu verhindern>

[0133] The Fig. 27 to 34 show examples of the preferred embodiment capable of preventing a short circuit between the semiconductor layer and the metal substrate, and this effect can also be obtained by other preferred embodiments.

[0134] That is, as it is in Fig.35 is shown, in a configuration in which a part of the semiconductor layer 2 is formed as a semiconductor region 26 towards the outside of a back metal 68 (e.g., the drain electrode 24 shown in Fig. 27) is exposed, in the case where a high voltage (e.g., 1000 V) making the surface side positive is applied to a surface metal 69 and the back metal 68, a potential distribution having the same potential (e.g., 1000 V) as that on the surface side is generated in the region between an end portion of the depletion layer 38 and the chip end face 5, via the semiconductor layer 2.

[0135] Therefore, as stated in Fig. 36, in the case where the back metal side 68 is set as a bonding side and the semiconductor device is mounted on the metal substrate 50 by a bonding material 51 such as solder, the semiconductor layer 2 and the metal substrate 50 are short-circuited via the bonding material 51. In addition to this, as shown in Fig. As shown in Fig. 37, even if the bonding material 51 is thinned and contact between the semiconductor layer 2 and the metal substrate 50 is prevented, the distance from the semiconductor layer 2 to the metal substrate 50 or to the bonding material 51 is short, and discharge may occur between them. Therefore, when the transistor is used as a reverse-blocking device, a withstand voltage is not high unless the above-described protective insulating film 53 is formed.

[0136] Therefore, as a further preferred embodiment for solving this type of problem, a preferred embodiment can be proposed, for example, which is shown in the Fig. 38 and Fig. 39 is shown.

[0137] Fig. 38 is a schematic perspective view of a semiconductor package 71 according to a preferred embodiment of the present invention. Fig. 39 is a partial sectional view of the semiconductor package 71 shown in Fig. 38 is shown. In the Fig. 38 and Fig. 39 are the same components as in the Fig. 1 to 37 are designated by the same or common reference numerals, and their description is omitted here. Fig. 38, the interior of the resin housing 75 is shown transparently for the sake of clarity.

[0138] The semiconductor package 71, as an example of the semiconductor device of the present invention, includes a semiconductor chip 72, a substrate terminal 73, a spacer 74, and a resin package 75.

[0139] The semiconductor chip 72 may have the same configuration as that of the semiconductor device 1 shown in the Fig. 1 to 3. That is, the semiconductor chip 72 has on a surface on the bonding side (in the semiconductor chip 72 on the back surface 4 on the drain side) a doping region pattern 76 like the back termination structure 27. An element structure of the semiconductor chip 72 is not limited to the MIS transistor structure 8, and may be an IGBT structure 59 ( Fig. 31), a JFET structure 66 ( Fig. 32), MIS transistor structures can be provided on both surfaces ( Fig. 33), or JFET structures 66 may be provided on both surfaces ( Fig. 34).

[0140] A substrate terminal 73 is a plate or a plate-shaped member (metal substrate) made of a metal material, for example, Cu, etc., and includes a drain terminal 77, a source terminal 78, and a gate terminal 79.

[0141] The drain terminal 77 includes an island portion 80 having a quadrilateral shape in plan view, and includes a linear terminal portion 81 extending from one side of the island portion 80. The source terminal 78 and the gate terminal 79 are formed linearly, parallel to the terminal portion 81 of the drain electrode 77, and are arranged on the right and left sides in the paper plane, respectively, so as to sandwich the central drain terminal 77 (terminal portion 81) from both sides in the width direction.

[0142] The island portion 80 is intended to support the semiconductor chip 72 and has a larger surface area than the semiconductor chip 72. Accordingly, the island portion 80 includes an outer peripheral portion 88, which is a portion on the outer side of the semiconductor chip 72 and surrounds the semiconductor chip 72 in a state when the semiconductor chip 72 is mounted (the state shown in the Fig. 38 and Fig. 39 is shown).

[0143] The spacer 74 is made of a metal material such as Cu (Cu, an alloy containing Cu, a metal whose surface is plated with Cu, etc.) and is provided integrally with the island portion 80. The integrated structure of the island portion 80 and the spacer 74 can be manufactured, for example, by preparing a metal substrate and by etching and machining the metal substrate according to the shape of the spacer 74.

[0144] The spacer 74, in the present preferred embodiment, is formed into a rectangular parallelepiped shape, with a side surface (peripheral surface 83) perpendicular to the surface of the island portion 80, and has a planar area smaller than that of the back metal (drain electrode 24) of the semiconductor chip 72. The spacer 74 is disposed between the semiconductor chip 72 and the island portion 80 so as to be completely fitted within an inner region of the semiconductor chip 72. The semiconductor chip 72 is bonded to the spacer 74 by means of a bonding material 82 (solder, silver paste, etc.) provided on the upper surface of the spacer 74.Accordingly, the semiconductor chip 72 is supported by the island portion 80 via the columnar spacer 74, which has a planar area smaller than that of the drain electrode 24, in a state where the semiconductor region 26 floats on the outer side of the peripheral surface 83 of the spacer 74. Consequently, a space 84 with a height H substantially equal to a height of the spacer 74 is formed between the semiconductor region 26 of the semiconductor chip 72 and the island portion 80, and a material of the resin package 75 enters this space 84.

[0145] Here, the size (width and height) of the spacer 74 is preferably designed taking into account a withstand voltage required for the semiconductor chip 72. When a high reverse voltage is applied to the semiconductor chip 72, which is in Fig. 38 and Fig. 39, the island portion 80, the spacer 74, the bonding material 82, and the drain electrode 24 are all given the same potential of 0 V. At this time, the semiconductor region 26 is pulled to a high potential (for example, 1000 V), so that withstand voltages in the vertical direction and in the horizontal direction from the semiconductor region 26 must be considered. In the vertical direction, a distance (height H of the space 84) between the semiconductor region 26 receiving a high potential and the island portion 80 must be considered, and in the horizontal direction, a distance L between the semiconductor region 26 and the bonding material 82 must be considered.

[0146] For example, in the semiconductor chip 72 required to have a reverse withstand voltage of 1000 V, when the resin material (e.g., epoxy resin, etc.) of the resin package 75 has a withstand voltage of 10 kV to 30 kV per 1 mm, the size of the spacer 74 must be designed so that the height H and the distance L exceed 100 µm.

[0147] The drain electrode 24 of the semiconductor chip 72 is electrically connected to the island portion 80 via the spacer 74. On the other hand, the source electrode 18 and the gate pad 47 of the semiconductor chip 72 are electrically connected to the source terminal 78 and the gate terminal 79, respectively, via bond wires 85 and 86.

[0148] The resin package 75 seals the semiconductor chip 72 etc. so that portions of the terminal portion 81 of the drain terminal 77, the source terminal 78 and the gate terminal 79 are exposed.

[0149] As described above, in this semiconductor package 71, even if a high potential distribution (e.g., 1000 V) is generated in the bond-side semiconductor region 26, when a reverse voltage is applied, an insulating distance can be ensured between this potential distribution and the island portion 80 due to the presence of the spacer 74. As a result, discharge between the semiconductor layer 2 and the island portion 80 can be prevented.

[0150] In addition, the spacer 74 has a smaller flat surface area than the back metal (drain electrode 24) of the semiconductor chip 72. Therefore, when the semiconductor chip 72 and the spacer 74 are bonded together, by providing an appropriate amount of the bonding material 82 for an area of ​​an upper surface of the spacer 74 after bonding, it is possible to prevent excess bonding material 82 from excessively spreading in the horizontal direction and coming into contact with the semiconductor layer 2. As a result, the semiconductor layer 2 and the spacer 74 can be prevented from being short-circuited via the bonding material 82.

[0151] The shape of the spacer 74 is not limited to the rectangular parallelepiped shape integrated with the island portion 80 as described above, and may be any other shape.

[0152] For example, as in Fig. 40, it is also possible for the spacer 74 to have a rectangular parallelepiped shape formed independently from the island portion 80 and bonded to the island portion 80 via a bonding material 87 such as solder. This case is advantageous in that the spacer 74 and the island portion 80 can be made of different materials, but a thermal resistance value of solder to be used as the bonding material 87 is not low, so that from the viewpoint of efficient heat dissipation, it is better to integrate the spacer 74 and the island portion 80 with each other.

[0153] As it is in Fig. 41, the peripheral surface 83 of the spacer element 74 may be a surface that is inclined with respect to the surface of the island portion 80. For example, the spacer element 74 may have a conical peripheral surface 83 such that its diameter decreases toward an upper portion.

[0154] As it is in Fig. 42, the peripheral surface 83 of the spacer element 74 may be a concave surface that is concave toward the interior of the spacer element 74. This concave peripheral surface 83 may be formed by manufacturing the spacer element 74, for example, by isotropic wet etching.

[0155] The spacer element 74 does not have to be formed into a columnar shape (block shape) on the island section 80 as shown in Fig. 38 to Fig. 42, as long as it can be ensured that a distance is established between the island portion 80 and the semiconductor layer 2. For example, the spacer 74 may be a hollow convex portion formed by selectively protruding a part of the island portion 80. This hollow spacer 74 may be formed, for example, by pressing or press-forming a metal substrate that forms the drain terminal 77.

[0156] In the semiconductor chip 72, Fig. 39, just like in Fig. 1, a doping region pattern (the MIS transistor structure 8, the surface termination structure 20, etc.) also on one side (side of the surface 3 of the semiconductor layer 2 in Fig. 39) opposite to the bond side. However, this doping region pattern must not be formed on a side opposite to the bond side, e.g., like the flip-chip bond form of the diode as shown in Fig. 44. As an example, it is also possible that the side opposite the bond side completely contains a cathode region 90 of the n + -type, while on the bond side of the semiconductor layer 2 an anode region 89 of the p + -type. In this case, a cathode electrode 91 that comes into contact with the cathode region 90 of the n + -type, are formed on the entire surface 3 of the semiconductor layer 2, and an anode electrode 92 which comes into contact with the anode region 89 of the p + -type, can be selectively formed on a part of the back surface 4 of the semiconductor layer 2.

[0157] Furthermore, as stated in Fig. 45, in the semiconductor chip 72, the semiconductor region 26 may also be covered by the protective insulation film 53, which in Fig. 27, etc. Accordingly, a reverse withstand voltage of the semiconductor chip 72 can be further improved.

[0158] Preferred embodiments of the present invention are described above, but the present invention may also be embodied in preferred embodiments different from the preferred embodiments described above.

[0159] For example, the preferred embodiments described above only show the case where the semiconductor layer 2 is made of SiC, but the material of the semiconductor layer 2 may be any other material of a so-called wide band gap type, such as GaN, and the semiconductor layer 2 may also be made of Si. By using the semiconductor device of the preferred embodiment of the present invention as a bidirectional switch of a power supply unit, a power supply unit can be easily obtained that is improved in withstand voltage reliability and has a small on-state loss.

[0160] In addition, various design changes may be made within the scope of the subject matter described in the claims.

[0161] The following problem can be represented as a “technical problem” described above.

[0162] For example, in the configuration described in Patent Literature 1, in order to form a Schottky junction on the back surface of the n-type SiC layer, trenches must be formed in the p-type SiC substrate. + -type SiC layers can be formed by etching. It is difficult to finely control the depths of the trenches by etching, and the trenches may not reach the n-type SiC layer, or the n-type SiC may be over-etched. In addition, etching propagates not only in the thickness direction but also in the transverse direction of the substrate, making it difficult to form trenches with a predetermined width in the planar direction of the substrate.

[0163] Accordingly, a second object of the present invention is to provide a SIC semiconductor device capable of realizing a satisfactory reverse withstand voltage through a Schottky junction between a drift region and a drain electrode, wherein the Schottky junction is accurately formed, and to provide a method for manufacturing such a device.

[0164] A third object of the present invention is to provide a semiconductor device that can realize a satisfactory reverse withstand voltage between the first electrode and the second electrode by a potential barrier formed when a reverse voltage is applied, and that can prevent short-circuiting between a semiconductor layer and a metal substrate when the first electrode is bonded to and mounted on the metal substrate.

[0165] In order to achieve the second and third objects described above, the following features can be extracted from the preferred embodiments described above.

[0166] For example, a semiconductor device includes a semiconductor layer having a surface and an end surface extending in a direction transverse to the surface, a body region of a second conductivity type formed in a surface portion of the semiconductor layer, a source region of a first conductivity type formed in a surface portion of the body region, a drift region of a first conductivity type formed so as to be exposed on a back surface of the semiconductor layer and separated from the source region by the body region.a gate electrode facing the body region via an insulation film, a drain electrode Schottky-connected to the drift region on the back surface of the semiconductor layer and having a peripheral edge at a position inwardly separated from the end surface of the semiconductor layer, and a back termination structure formed in a back surface portion of the semiconductor layer and arranged to overlap the peripheral edge portion of the drain electrode.

[0167] This semiconductor device can be obtained by the following method for manufacturing a semiconductor device.The method for manufacturing a semiconductor device includes, on a semiconductor wafer having a semiconductor layer of a first conductivity type, a step of forming a transistor structure in a surface portion of the semiconductor layer, a step of selectively forming a back termination structure for improving a reverse withstand voltage of the transistor in a peripheral portion of the back surface of the semiconductor layer, a step of selectively forming a back electrode on the back surface of the semiconductor layer such that at least a part of its peripheral edge portion overlaps the back termination structure, and Schottky-connecting a back electrode to the semiconductor layer, and a step of cutting the semiconductor layer along cutting lines set at positions spaced from a peripheral edge of the back electrode.

[0168] According to this method, a Schottky junction area can be adjusted by forming a back electrode of a desired size at a Schottky junction surface (back surface) in the semiconductor layer. For example, an electrode film is formed over the entire back surface of the semiconductor layer, and by patterning this electrode film, a back electrode of a desired size can be easily obtained.

[0169] In the thus-obtained semiconductor device, for example, when a reverse bias is applied between the source and drain, a current flowing in a thickness direction within the semiconductor layer via a body diode formed by a pn junction between a body region and a drift region can be blocked by a Schottky barrier of the Schottky junction. Furthermore, a back termination structure is formed to overlap the peripheral edge portion of the drain electrode (back electrode), so that when a reverse bias is applied, a depletion layer can be prevented from reaching an end surface (chip end surface) of the semiconductor layer.Thus, even if a defect region exists at the end surface of the semiconductor layer due to a dicing process, leakage current can be prevented from flowing due to the generation of electron-hole pairs in this defect region. As a result, the semiconductor device ensures a satisfactory reverse withstand voltage and can therefore be satisfactorily used as a reverse-blocking MISFET for a bidirectional switch.

[0170] In the semiconductor device, the backside termination structure may include a first high-resistance region or a first high-resistance region with a higher resistance value than the drift region. In this case, it is possible for the semiconductor layer to be SiC, and for the first high-resistance region to have a crystal defect concentration of 1 × 10 14 cm -3 up to 1 × 10 21 cm -3 has.

[0171] In the semiconductor device, the rear termination structure may include a first doping region of a second conductivity type. In this case, it is possible for the semiconductor layer to be SiC, and for the first doping region to have a doping concentration of 1 × 10 16 cm -3 up to 1 × 10 19 cm -3 has.

[0172] In the semiconductor device, the back termination structure may have an inner peripheral edge on the inner side of a peripheral edge of the drain electrode, and an outer peripheral edge at a position separated from the peripheral edge of the drain electrode and inward from the end surface of the semiconductor layer.

[0173] In the semiconductor device, a distance of the outer peripheral edge from the end surface of the semiconductor layer may be a distance for preventing a depletion layer formed in the back termination structure from reaching the end surface of the semiconductor layer.

[0174] In the semiconductor device, the outer peripheral edge of the back termination structure may be arranged at a position closer to the drain electrode than a region in which the depletion layer formed in the back termination structure spreads.

[0175] In the semiconductor device, the back termination structure may include a plurality of portions, with at least one portion overlapping the peripheral edge portion of the drain electrode.

[0176] In the semiconductor device, the back termination structure may be a high resistance region having a higher resistance value than the drift region, and may be formed to reach the end surface of the semiconductor layer.

[0177] The semiconductor device may include a field stop layer of a first conductivity type formed on the surface side and / or the back surface side of the semiconductor layer, and having a higher doping concentration than the drift region. In this case, the field stop layer may be arranged at a depth position separated from the surface or the back surface of the semiconductor layer, or may be formed to reach the surface or the back surface of the semiconductor layer.

[0178] With this configuration, when a voltage is applied between the source and drain, a depletion layer extending from or emanating from a low-voltage side can be prevented from reaching a conductive pattern (e.g., an MIS transistor structure) on a high-voltage side. Accordingly, leakage current due to a breakdown phenomenon can be prevented.

[0179] The semiconductor device may include field relaxation regions formed in the back surface portion of the semiconductor layer, in a region on the inner side of the back termination structure, and in contact with the drain electrode.

[0180] In this configuration, an electric field at the Schottky interface between the drift region and the drain electrode can be relaxed. Even if a metal with a comparatively small work function is used as the drain electrode, reverse leakage current can be reduced, ensuring a low on-state resistance by using this metal.

[0181] In the semiconductor device, the field relaxation region may include a second high-resistance region having a higher resistance than the drift region. In this case, the second high-resistance region may have a crystal defect concentration of 1 × 10 14 cm -3 up to 1 × 10 21 cm -3 have.

[0182] In the semiconductor device, the field relaxation region may include a second doping region of a second conductivity type. In this case, the second doping region may have a doping concentration of 1 × 10 16 cm - 3 up to 1 × 10 19 cm -3 have.

[0183] In the semiconductor device, in a region on the inner side or within the back termination structure, the back surface of the semiconductor layer may have a substantially uniform flat portion, and the field relaxation regions may be formed on the flat portion.

[0184] In the semiconductor device, in a region on the inner side of the back termination structure, trenches may be selectively formed in the back surface of the semiconductor layer, and the field relaxation regions may be formed along the inner surfaces of the trenches within the drift region.

[0185] In the semiconductor device, the field relaxation regions may be arranged discretely in a plan view, may be arranged in a stripe pattern in a plan view, or may be arranged in a grid pattern in a plan view.

[0186] The semiconductor device may further include a source electrode formed on the surface side of the semiconductor layer and connected to the source region, and a surface termination structure arranged at a peripheral edge portion of the source electrode such that at least a part of the surface termination structure overlaps the source electrode.

[0187] In the method for manufacturing a semiconductor device, the step of forming the back termination structure may include a step of transforming the back termination structure into a high-resistance region having a higher resistance value than the semiconductor layer by laser annealing or a heat treatment at 500°C or less after irradiating the back surface of the semiconductor layer with second dopant ions, protons, or electron beams, wherein one end of the back termination structure may be flush with the cut surface.

[0188] In the method of manufacturing a semiconductor device, the step of forming the back termination structure may include a step of transforming the back termination structure into a first doping region of a second conductivity type by activating the back termination structure by laser annealing after injecting second doping ions into the back surface of the semiconductor layer, and an end of the back termination structure may have a length on a side closer to the back electrode side as a depletion layer formed when a reverse voltage is applied to the semiconductor device.

[0189] The method of manufacturing a semiconductor device may further include a step of forming a protective insulation layer partially overlapping a peripheral edge of the back electrode.

[0190] A semiconductor device according to another preferred embodiment includes a semiconductor layer having a first surface on a chip bonding side, a second surface on a side opposite to the first surface, and an end surface extending in a direction crossing the first surface and the second surface, forming an active region and an outer peripheral region surrounding the active region, a first electrode formed on the first surface of the semiconductor layer and having a peripheral edge at a position spaced inward from the end surface of the semiconductor layer, a first termination structure, and a second termination structure.A terminal structure formed in a surface portion on the first surface side of the semiconductor layer and arranged to overlap the peripheral edge portion of the first electrode, a second electrode formed on the second surface of the semiconductor layer and having a peripheral edge at a position offset inward from the end surface of the semiconductor layer.and a protective insulating film formed to come into contact with at least the peripheral edge portion of the first electrode and covering a semiconductor surface of the semiconductor layer from the peripheral edge of the first electrode to the end surface of the semiconductor layer, wherein, when a reverse voltage is applied between the first electrode and the second electrode, a current flowing in a reverse direction between the first electrode and the second electrode is reduced by a potential barrier formed on at least one of the first surface and the second surface.

[0191] With this configuration, when a reverse voltage is applied between the first electrode and the second electrode, a current flowing in a thickness direction within the semiconductor layer can be blocked by a potential barrier formed on the first surface and / or the second surface. Furthermore, a termination structure is formed on both the first surface and the second surface of the semiconductor layer, so that when a reverse voltage is applied, a depletion layer can be prevented from reaching the end surface (chip end surface) of the semiconductor layer. Accordingly, even if a defect region exists at the end surface of the semiconductor layer due to a dicing process, a leakage current due to generation of electron-hole pairs in the defect region can be prevented from flowing.As a result, a satisfactory reverse withstand voltage can be ensured in the semiconductor device, so that the semiconductor device can be satisfactorily used as a reverse blocking device for a bidirectional switch.

[0192] Furthermore, a semiconductor surface of the semiconductor layer is covered by a protective insulating film from the peripheral edge of the first electrode on the bonding side to the end surface of the semiconductor layer. Accordingly, when the first electrode is bonded to a metal substrate and then mounted, the semiconductor surface of the semiconductor layer can be prevented from coming into contact with the metal substrate, thus preventing a short circuit between the semiconductor layer and the metal substrate.

[0193] The semiconductor device according to another preferred embodiment may further include a second termination structure formed on a surface portion of the second surface side of the semiconductor layer and arranged to overlap the peripheral edge portion of the second electrode.

[0194] In the semiconductor device according to another preferred embodiment, the peripheral edge portion of the first electrode and a part of the protective insulating film may overlap.

[0195] In the semiconductor device according to another preferred embodiment, the protective insulating film may include a lamination structure including a first film sandwiched between the peripheral edge portion of the first electrode and the semiconductor layer, and a second film formed on the first film and overlapping the peripheral edge portion of the first electrode.

[0196] In the semiconductor device according to another preferred embodiment, the first film may be formed of SiO2 or SiN, and the second film may be made of polyimide.

[0197] In the semiconductor device according to another preferred embodiment, the protective insulating film may have a thickness t satisfying the following equation (1) based on the semiconductor area. t>V / (3MV / cm)

[0198] (In the equation, V is a voltage to be applied between the first electrode and the second electrode.)

[0199] The semiconductor device according to another preferred embodiment may include a MISFET structure formed in the surface portion on the side of the second surface of the semiconductor layer, and the first electrode may be Schottky-connected to the semiconductor layer at the first surface of the semiconductor layer.

[0200] The semiconductor device according to another preferred embodiment may include an IGBT structure formed in the surface portion on the side of the second surface of the semiconductor layer.

[0201] The semiconductor device according to another preferred embodiment may include a JFET structure formed in the surface portion on the second surface side of the semiconductor layer, and the first electrode may be Schottky-connected to the semiconductor layer at the first surface of the semiconductor layer.

[0202] The semiconductor device according to a further preferred embodiment may include MISFET structures formed in the surface portions on both the first surface side and the second surface side of the semiconductor layer.

[0203] The semiconductor device according to another preferred embodiment may include JFET structures formed in the surface portions on both the first surface side and the second surface side of the semiconductor layer.

[0204] In the semiconductor device according to another preferred embodiment, the semiconductor layer may be made of any material selected from Si, SiC, and GaN. List of reference symbols 1 semiconductor component 2 semiconductor layer 3 Area or surface (of semiconductor layer) 4 Rear surface or surface (of semiconductor layer) 5 End surface or surface (of semiconductor layer) 8 MIS transistor structure 9 p-type body region 10 Source region from n + -Type 11 Gate insulation film 12 Gate electrode 15 Drift region from n - -Type 18 Source electrode 20 Surface finishing structure 24 Drain electrode 25 Peripheral edge (of drain electrode) 27 Rear end structure 28 Inner peripheral edge 29 Outer peripheral edge 31 Base substrate 34 metal film 36 Cutting line 40 RESURF layer 41 Guard ring layer 42 Surface-side field stop layer 43 Back surface field stop layer 44 Field relaxation region 45 Flat section 46 Trench 50 metal substrate 51 Bond material 52 semiconductor component 53 Protective insulation film 54 First Film 55 Second Film 56 Overlap section 57 Inner peripheral edge 58 Inner peripheral edge 59 IGBT structure 66 JFET structure 71 Semiconductor housing or package 72 semiconductor chips 73 Substrate connection 74 spacer element 75 synthetic resin housing or “packing” 76 doping region patterns 77 Drain connection 78 Source connection 79 Gate connection 80 Island section 81 connecting section 82 Bond material 83 circumferential area 84 Room 85 Bond wire 86 Bond wire 87 Bond material 88 Outer peripheral section 89 Anode region of the p + -Type 90 cathode region of the n + -Type 91 Cathode electrode 92 Anode electrode

Claims

[1] Semiconductor component (1) with: a semiconductor chip (72) having a semiconductor layer (2) having a first surface (4) on a chip bonding side, a second surface (3) on the side opposite the first surface, and an end surface (5) extending in a direction crossing the first surface and the second surface, the semiconductor chip (72) having a first electrode (24) formed on the first surface (4) and having a peripheral edge at a position spaced inwardly from the end surface (5), and a second electrode (18) formed on the second surface (3), a transistor (8) being formed on the second surface (3) side of the semiconductor layer; a conductive substrate (73) to which the semiconductor chip (72) is chip-bonded; a conductive spacer (74) having a flat area smaller than that of the first electrode (18) and supporting the semiconductor chip (72) on the conductive substrate via the first electrode; a resin package (75) sealing at least the semiconductor chip (72) and the conductive spacer element (74); and a bonding material (82) provided between the conductive spacer (74) and the first electrode (24) of the semiconductor chip and having a protruding portion protruding from the conductive spacer (74) and fitted into the interior of the first electrode (24), wherein the resin package (75) has a side surface extending in a direction crossing the first surface (4) and the second surface (3) of the semiconductor chip (72), wherein a part of the conductive substrate (73) is exposed opposite the side surface of the resin housing (75) as a terminal portion (81), wherein a part of the resin package (75) enters a space between a portion of the semiconductor chip (72) on an outer side of the conductive spacer (74) and the conductive substrate (73), and where if a resistance voltage of the semiconductor component V B1 (V) is a resistance voltage of the resin case (75) per unit length V B2 (V / mm) and a height distance between the semiconductor chip (72) and the conductive substrate (73) is H, the height H has a value of V B1 / V B2 exceeds. [2] Semiconductor component (1) with: a semiconductor chip (72) having a semiconductor layer (2) having a first surface (4) on a chip bonding side, a second surface (3) on the side opposite the first surface, and an end surface (5) extending in a direction crossing the first surface and the second surface, the semiconductor chip (72) having a first electrode (24) formed on the first surface (4) and having a peripheral edge at a position spaced inwardly from the end surface (5), and a second electrode (18) formed on the second surface (3), a transistor (8) being formed on the second surface (3) side of the semiconductor layer; a conductive substrate (73) to which the semiconductor chip (72) is chip-bonded; a conductive spacer (74) having a flat area smaller than that of the first electrode (18) and supporting the semiconductor chip (72) on the conductive substrate via the first electrode; a resin package (75) sealing at least the semiconductor chip (72) and the conductive spacer element (74); and a bonding material (82) provided between the conductive spacer (74) and the first electrode (24) of the semiconductor chip and having a protruding portion protruding from the conductive spacer (74) and fitted into the interior of the first electrode (24), wherein the resin package (75) has a side surface extending in a direction crossing the first surface (4) and the second surface (3) of the semiconductor chip (72), wherein a part of the conductive substrate (73) is exposed opposite the side surface of the resin housing (75) as a terminal portion (81), wherein a part of the resin package (75) enters a space between a portion of the semiconductor chip (72) on an outer side of the conductive spacer (74) and the conductive substrate (73), and wherein when a resistance voltage of the semiconductor component (72) V B1 (V) is a resistance voltage of the resin case (75) per unit length V B2 (V / mm) and a distance between a peripheral surface of the conductive spacer element (74) and a peripheral surface of a termination structure (76) is L, the distance L has a value of V B1 / V B2 exceeds. [3] A semiconductor device according to claim 1 or 2, wherein the conductive spacer (74) includes a columnar spacer formed integrally with the conductive substrate. [4] The semiconductor device according to claim 3, wherein the columnar spacer (74) is formed into a rectangular parallelepiped shape having a side surface oriented perpendicular to a surface of the conductive substrate. [5] A semiconductor device according to claim 3, wherein the columnar spacer (74) is formed into a shape having a conical side surface inclined with respect to the surface of the conductive substrate. [6] The semiconductor device according to claim 3, wherein the columnar spacer (74) is formed into a shape having a side surface with a curved surface which is concave toward the interior of the columnar spacer. [7] A semiconductor device according to claim 1 or 2, wherein the conductive spacer (74) is bonded to the conductive substrate via a second bonding material. [8] A semiconductor device according to claim 7, wherein the conductive spacer (74) and the conductive substrate are formed of different materials from each other. [9] Semiconductor component (1) with: a semiconductor chip (72) comprising a semiconductor layer having a first surface (4) on a chip bonding side, a second surface (3) on a side opposite the first surface, and an end surface (5) extending in a direction crossing the first surface and the second surface, a first electrode (24) formed on the first surface (4) and having a peripheral edge at a position spaced inward from the end surface (5), and a second electrode (18) formed on the second surface (3), a transistor (8) being formed on the second surface (18) side of the semiconductor layer; a conductive substrate (73) to which the semiconductor chip is chip-bonded; a conductive spacer (74) which is a hollow conductive spacer formed by selectively projecting a part of the conductive substrate (73) which supports the semiconductor chip (72) over the first electrode (24) and which has a flat surface area smaller than that of the first electrode (4); a resin package (75) sealing at least the semiconductor chip and the conductive spacer; and a bonding material (82) provided between the conductive spacer (74) and the first electrode (24) of the semiconductor chip and having a protruding portion protruding from the conductive spacer and fitted into the interior of the first electrode (24), wherein the resin package (75) has a side surface extending in a direction crossing the first surface (4) and the second surface (3) of the semiconductor chip (72), wherein a part of the conductive substrate (73) is exposed opposite the side surface of the resin housing (75) as a terminal portion (81), wherein a part of the resin package (75) enters a space between a portion of the semiconductor chip (72) on an outer side of the conductive spacer (74) and the conductive substrate (73), and where if a resistance voltage of the semiconductor component V B1 (V) is a resistance voltage of the resin case (75) per unit length V B2 (V / mm) and a height distance between the semiconductor chip (72) and the conductive substrate (73) is H, the height H has a value of V B1 / V B2 exceeds. [10] Semiconductor component (1) with: a semiconductor chip (72) comprising a semiconductor layer having a first surface (4) on a chip bonding side, a second surface (3) on a side opposite the first surface, and an end surface (5) extending in a direction crossing the first surface and the second surface, a first electrode (24) formed on the first surface (4) and having a peripheral edge at a position spaced inward from the end surface (5), and a second electrode (18) formed on the second surface (3), a transistor (8) being formed on the second surface (18) side of the semiconductor layer; a conductive substrate (73) to which the semiconductor chip is chip-bonded; a conductive spacer (74) which is a hollow conductive spacer formed by selectively projecting a part of the conductive substrate (73) which supports the semiconductor chip (72) over the first electrode (24) and which has a flat surface area smaller than that of the first electrode (4); a resin package (75) sealing at least the semiconductor chip and the conductive spacer; and a bonding material (82) provided between the conductive spacer (74) and the first electrode (24) of the semiconductor chip and having a protruding portion protruding from the conductive spacer and fitted into the interior of the first electrode (24), wherein the resin package (75) has a side surface extending in a direction crossing the first surface (4) and the second surface (3) of the semiconductor chip (72), wherein a part of the conductive substrate (73) is exposed opposite the side surface of the resin housing (75) as a terminal portion (81), wherein a part of the resin package (75) enters a space between a portion of the semiconductor chip (72) on an outer side of the conductive spacer (74) and the conductive substrate (73), and wherein when a resistance voltage of the semiconductor component (72) V B1 (V) is a resistance voltage of the resin case (75) per unit length V B2 (V / mm) and a distance between a peripheral surface of the conductive spacer element (74) and a peripheral surface of a termination structure (76) is L, the distance L has a value of V B1 / V B2 exceeds. [11] Semiconductor device according to one of claims 1 to 10, wherein the semiconductor chip has, in a surface portion of the semiconductor layer on the side of the first surface (4), a termination structure (76) with a first doping region of a first conductivity type, which is electrically connected to the first electrode (24), and a second doping region of a second conductivity type, which is exposed from the outside of the first electrode (24), and the second doping region (15) has a portion which is at the same potential as the second electrode (18) when a reverse voltage is applied between the first electrode and the second electrode. [12] A semiconductor device according to any one of claims 1 to 11, further comprising: a protective insulating film (53) formed to be in contact with at least a peripheral edge portion of the first electrode, and covering an area from the peripheral edge of the first electrode toward the end surface of the semiconductor layer. [13] A semiconductor device according to any one of claims 1 to 12, wherein the conductive spacer (74) is made of Cu or an alloy including Cu or a metal whose surface is plated with Cu. [14] A semiconductor device according to any one of claims 1 to 13, wherein the conductive substrate (73) includes an island portion on which the semiconductor chip is arranged, and the terminal portion extending from the island portion. [15] A semiconductor device according to claim 11, wherein the semiconductor chip includes an active region (7) in which a plurality of the transistors are formed, and an outer peripheral region (6) in which a protective element (20) is formed so as to surround the active region. [16] A semiconductor device according to any one of claims 1 to 15, wherein the semiconductor layer is a wide band gap type semiconductor layer. [17] A power converter using the semiconductor device according to any one of claims 1 to 16 as a bidirectional switching circuit.

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