SoC fabric extensions for configurable memory images through memory area screens and selectable address flattening

Abstract

Device (800), comprising: a memory request data path (801) that is operational to transmit a memory request; first circuits (810) that are operable to identify any memory request with an address that lies between any one of one or more pairs of base address and boundary address indicators; second circuits (820) that are operable to transmit any memory request identified by the first circuits (810) to a memory interface (841), and to apply a default memory access protocol to any memory request not identified by the first circuits (810); and third circuits (830) that are operable to modify the address of a memory request when both a multiple memory interface indicator (803) and an address flattening indicator (805) are enabled.

Description

PRIORITY CLAIM

[0001] This application claims priority to U.S. patent application Serial No. 14 / 998,224, filed December 24, 2015, entitled "SOC FABRIC EXTENSIONS FOR CONFIGURABLE MEMORY MAPS THROUGH MEMORY RANGE SCREENS AND SELECTABLE ADDRESS FLATTENING." BACKGROUND

[0002] A memory map in a computer system can partition different areas of system memory based on a number of factors, such as the intended purpose for the different areas, the memory type for each area, and the system components that can access or use the different memory areas. A memory map may also imply access protocols for the different memory areas to ensure that all system elements interact appropriately with memory resources. For example, the memory map for Intel®-based personal computer (PC) systems evolved to incorporate new technologies and methodologies incorporated into system architectures while maintaining backward compatibility with previous system architectures. To be compatible with existing PC systems, new system architectures should incorporate such "legacy" PC memory maps.(Intel is a trademark of Intel Corporation in the U.S. and / or other countries.)

[0003] To provide flexibility in light of factors such as cost and development time, component training has increasingly been expanded to include SoC (System-on-Chip) training methodologies. Some SoC components can be trained to include IP (Intellectual Property) cores, as well as fabrics that interconnect the IP cores, for flexibility purposes.

[0004] Some SoC fabric developments have supported legacy PC system memory mapping, and as a result, the architecture of such systems can be tightly coupled with memory subsystems. However, this tight coupling can compromise flexibility in an SoC system architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The embodiments of the disclosure will become more fully understood from the detailed description provided below and the accompanying drawings of various embodiments of the disclosure. While the drawings are intended to aid explanation and understanding, they are only an aid and should not be considered as limiting the disclosure to the embodiments shown therein. Fig. 1 illustrates one embodiment of a legacy PC memory dump. Fig. Figure 2 illustrates an embodiment of a tightly coupled legacy PC memory map with two memory interfaces and a flattened address space. Fig. Figure 3 illustrates one embodiment of an algorithm for a fabric to process memory requests. Fig. Figure 4 illustrates one embodiment of configuration registers for a fabric. Fig. 5-7 illustrate embodiments of SoC memory maps and corresponding SoC memory architectures that incorporate a fabric to process memory requests. Fig. Figure 8 illustrates one embodiment of a portion of a fabric that implements an algorithm for processing memory requests. Fig. 9 illustrates one embodiment of a method for a fabric to process new memory requests. Fig. 10 illustrates a computing device with mechanisms to provide various SoC fabric extensions for configurable memory mapping, according to some embodiments of the disclosure.

[0006] US 2015 0 172 252 A1 generally shows the administration of a computer network and, in particular, techniques for displaying and analyzing network address translation rules or commands.

[0007] The stated object is achieved according to the invention by the features of patent claims 1 and 16. Further embodiments of the invention are presented in the subclaims. DETAILED DESCRIPTION

[0008] Some earlier SoC fabrics were trained to support a legacy PC memory image. Fig. 1 illustrates one embodiment of a legacy PC memory map. As illustrated, a memory map 100 includes a lower memory address range between 0 and a configurable lower limit, a lower MMIO address range between the configurable lower limit and 4 GB, an upper memory address range between 4 GB and a configurable upper limit, and an upper MMIO address range between the configurable upper limit and the top of physical memory. The lower memory address range may optionally include a VGA address range (which may span addresses from 0xA_0000 to 0xB_FFFF) and / or one or more DOS MMIO address ranges (which may span addresses from 0xF_0000 to 0xF_FFFF, or from 0xE_0000 to 0xE_FFFF).

[0009] Memory accesses to DRAM can have much higher latencies than accesses to local memory and can therefore impact system performance. However, in systems with multiple memory interfaces, the latency of a memory access on one memory interface can "hide" at least part of the latency of a memory access on another memory interface. If multiple memory accesses could be performed in parallel, it may be possible to increase system performance. Theoretically, this can increase memory access bandwidth by a factor of up to two.

[0010] To take advantage of such potential performance gains, other earlier SoC fabrics were designed for a legacy PC memory image using multi-channel memory striping. Fig. Figure 2 illustrates one embodiment of a tightly coupled legacy PC memory map with two memory interfaces and a flattened address space. As with memory map 100, memory map 200 includes a lower memory address range between 0 and a configurable lower bound, a lower MMIO address range between the configurable lower bound and 4 GB, an upper memory address range between 4 GB and a configurable upper bound, and an upper MMIO address range between the configurable upper bound and the top of physical memory.

[0011] However, unlike memory map 100, the lower memory and upper memory address ranges of memory map 200 are striped, and memory accesses to these address ranges are alternately mapped to two memory interfaces. More specifically, some accesses to addresses within memory map 200 may be mapped to a first memory interface 210 (e.g., "memory interface 0"), while other accesses may be mapped to a second memory interface 220 (e.g., "memory interface 1"). The selection of the memory interface may be based on a physical address bit [6] being XORed with 0 or more physical address bits.In some embodiments, striping may map alternating 64-byte memory sections to two different memory interfaces (although in other embodiments, alternating 32-byte sections may be mapped, or alternating sections of a different size). Although illustrated as supporting two memory interfaces, in other embodiments, memory map 200 may support more than two memory interfaces. Similarly, striping may support more than two memory interfaces.

[0012] A disadvantage of memory map 200 is that the memory subsystem may be tightly coupled to the fabric, and other (non-fabric) masters may not be allowed to access the memory subsystem independently. For example, the address spaces of the first memory interface 210 and second memory interface 220 are "flattened" so that non-contiguous addresses in the memory map can be mapped to a range of contiguous addresses in the physical memory devices accessed by the first memory interface 210 and second memory interface 220. However, if this flattening is not implemented in an SoC memory subsystem, other masters accessing the subsystem would not perceive the same mapping between memory addresses and memory subsystem targets that the fabric masters perceive.

[0013] Various SoC fabric extensions for configurable memory mapping are discussed below. These extensions can advantageously increase the flexibility of the SoC system architecture and can thus enable a wider array of memory maps and memory system topologies. For example, these extensions can enhance the ability to increase the number of memory interfaces on the fabric to increase bandwidth, and they can allow non-fabric masters to connect directly to the memory subsystem to perceive the same mapping between memory addresses and memory subsystem targets as fabric masters. These extensions can also accommodate memory maps that are different from legacy PC memory maps.

[0014] In the following description, numerous details are discussed to provide a more detailed explanation of embodiments of the present disclosure. However, it will be apparent to those skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the present disclosure.

[0015] It should be noted that in the corresponding drawings of the embodiments, signals are depicted with lines. Some lines may be thicker to indicate a greater number of existing signal paths and / or may have arrows at one or more ends to indicate a direction of information flow. Such depictions are not intended to be limiting. Instead, the lines are used in conjunction with one or more example embodiments to facilitate a better understanding of a circuit or logic unit. Each depicted signal, as dictated by design requirements or preferences, may in fact include one or more signals capable of traveling in any direction and may be implemented with any suitable type of signaling scheme.

[0016] Throughout the specification and claims, the term "connected" means a direct electrical, mechanical, or magnetic connection between the things being connected, without any intermediary devices. The term "coupled" means either a direct electrical, mechanical, or magnetic connection between the things being connected, or an indirect connection through one or more passive or active intermediary devices. The term "circuit" or "module" can refer to one or more passive and / or active components configured to cooperate with each other to provide a desired function. The term "signal" can refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a" and "the" include plural references. The meaning of "in" includes "in" and "on."

[0017] The terms "substantially," "close to," "approximately," "near," and "about" generally refer to being within + / - 10% of a target value. Unless otherwise specified, the use of the numerical adjectives "first," "second," and "third," etc., to describe a common object means only to designate different instances of similar objects, and is not intended to imply that objects so described must be in a given sequence, whether in time, space, rank, or any other way.

[0018] For the purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0019] In addition, the various elements of combinational logic and sequential logic discussed in the present disclosure may belong to both physical structures (such as AND gates, OR gates, or XOR gates) or to synthesized or otherwise optimized collections of devices implementing the logic structures that are Boolean equivalents of the logic being discussed.

[0020] Fig. Figure 3 illustrates one embodiment of an algorithm for a fabric to process memory requests. At a first point 305 of an algorithm 300, a new memory request arrives at the fabric. Upon receipt of the new memory request, at point 310 in the algorithm, the address of the new memory request is compared with various configuration registers to determine whether the address of the memory request is within a range of physical addresses being screened. (This comparison occurs before any legacy PC memory mapping.)

[0021] If we briefly turn away from this illustration, Fig. 4 illustrates an embodiment of configuration registers for a fabric. A set of configuration registers 400 includes sets of screening registers 401 defined for one or more screens associated with each of one or more memory interfaces. The configuration registers 400 may be configurable by firmware or BIOS and may have pre-initialized values ​​after initial power-up of the fabric.

[0022] In particular, as illustrated, the configuration registers 400 may be divided among a first memory interface 410 ("Memory Interface 0"), a second memory interface 420 ("Memory Interface 1"), and a final memory interface 490 ("Memory Interface N-1" among a total of N memory interfaces). Each of these memory interfaces may include a set of screening registers 401 defined for a first screen 415 ("Screen 0"), a second screen 425 ("Screen 1"), and a final screen 495 ("Screen X-1" among a total of X screens). Each set of screening registers 401 includes three registers for the corresponding screen of the corresponding interface: a screen enable, a physical base address, and a physical boundary address.

[0023] The configuration registers 400 also include a flatten enable register 405 and a flatten shift bit for the screen area register 407, which can be operable for all memory interfaces. (These registers are discussed further below.)

[0024] With further reference to Fig. 3, when determining whether the address of the memory request is within a range of physical addresses being screened (at point 310), the fabric can check the sets of screening registers 401 for all screens and for all memory interfaces. More specifically, for all sets of screening registers 401 in which the screen enable bit is set, the fabric can evaluate the physical address of the new memory request against the screen base address and screen boundary address. If the physical address of the new memory request is both greater than or equal to the physical base address and less than the physical boundary address, then the address of the memory request can be determined to be within a range of physical addresses being screened.

[0025] For memory requests that fall within a second address range for any memory interface, at point 315, algorithm 300 may direct the memory request to the memory interface for which that ranged address is screened. At point 320, algorithm 300 may consider whether there is more than one memory interface; if so, then at point 330, algorithm 300 additionally considers whether address flattening enable register 405 is set. If so, then address bits [M:6] of the memory request may be set to the values ​​of address bits {[M:Y],[(Y-2):6]} at point 335. Y may be a number between M and 8 (inclusive) representing a bit position within memory addresses and may be set by configuring the flattening shift bit for screen range register 407.Based on the above discussion, if algorithm 300 determines that address flatten enable register 405 is set, then the address bits [M:6] of the memory request may be set to exclude address bit Y-1 of the memory request, as configured by the flatten shift bit for screen region register 407, where M >= Y >= 8 (which may reflect screen movement) to maintain a contiguous region.

[0026] For memory requests that do not fall within any screened address range for any memory interface, algorithm 300 may apply an Alt-PC memory map to the memory request at point 345. In various embodiments, applying an Alt-PC memory map may result in the memory request being directed to memory interface 0 or memory interface 1 to conform to an Alt striping or hashing protocol. At point 350, algorithm 300 may consider whether there is more than one memory interface. If so, then at point 355, algorithm 300 may select to direct the memory request to memory interface 0 or memory interface 1 based on address bit [6], with an optional XOR with address bits [M:7]. At point 360, algorithm 300 may consider whether address flattening enable register 405 is set.If so, then address bits [M:6] of the memory request can be set to the values ​​of address bits {[M-1:7]} at point 365.

[0027] According to algorithm 300, for all memory requests—whether or not they fall within a screened address range for any memory interface—if multiple memory interfaces are not present, or if the multiple interface address flattening enable register 405 is not set, then at point 375, the memory request can use the original physical address at the memory interfaces. In other words, if only one memory interface is available, or if flattening is not enabled, the original addresses can be preserved.

[0028] Algorithm 300 may allow the identification of "screened" memory regions that are not subject to legacy PC memory mapping. As a result, such accesses cannot be subjected to legacy striping or hashing protocols. Algorithm 300 may accordingly provide a mechanism for specifying memory regions that cannot be subjected to legacy striping or hashing protocols. Algorithm 300 may therefore advantageously be used, for example, to disable striping or hashing for one or more memory regions, or to specify memory regions that can be mapped to different memory interfaces without striping or hashing.

[0029] Additionally, algorithm 300 may allow the identification of specific memory regions with specific memory channels. In other words, various memory regions may be displayed for each memory interface in the system, and algorithm 300 may direct accesses to these memory regions to the corresponding memory interfaces.

[0030] Algorithm 300 may also provide a mechanism to disable address flattening. In systems with disabled address flattening, fabric masters and non-fabric masters may have identical perceptions of system memory. This may advantageously enable a simpler architecture for an SoC memory subsystem that can serve non-fabric masters, as the memory subsystem does not have to account for potentially different perceptions of system memory between the fabric masters and the non-fabric masters. Accounting for these potentially different perceptions in the memory subsystem can be complex and can incur both system and development costs.

[0031] Based on the above discussion, the algorithm 300 may advantageously provide flexibility to support a variety of system memory maps and system topologies.

[0032] Fig. 5-7 illustrate embodiments of SoC memory maps and corresponding SoC memory architectures that include a fabric to process memory requests. Fig. Figure 5 shows a scenario with a storage interface and independent storage subsystems. Fig. 5, a memory map 500 includes a DRAM region, a lower MMIO region, and an SRAM / ROM region, all spanning between 0 and 4 GB.

[0033] A corresponding SoC memory architecture 550 includes one or more fabric masters 555, one or more subsystem masters 565 (e.g., non-fabric masters), a fabric 560, a memory interface 561, an MMIO interface 563, a memory subsystem 570, and various memory subsystem targets, such as a DRAM 581, an SRAM 583, and a ROM 584.

[0034] Fabric masters 555 can transmit memory requests to fabric 560, which can then transmit the requests either to MMIO interface 563 or through memory interface 561 to memory subsystem 570. Subsystem masters 565 can transmit memory requests directly to memory subsystem 570. Memory requests received from memory subsystem 570 can then be directed to DRAM 581, SRAM 583, or ROM 584, as appropriate.

[0035] Fabric 560 may use algorithm 300, as discussed above. New memory requests to fabric 560 with addresses that fall within a shared screen for a memory interface may be sent to memory interface 561, while a legacy PC memory map may be applied for other memory requests. However, since memory architecture 550 does not have more than one memory interface, algorithm 300 may leave memory address bits [M:6] of the memory requests unchanged.

[0036] In this embodiment, the subsystem masters 565 can access the memory subsystem 570 independently and can advantageously perceive the same mapping between memory addresses and memory subsystem targets, such as DRAM 581, SRAM 583, or ROM 584, that the fabric masters 555 perceive. The fabric 560 and memory subsystem 570 can accordingly operate to ensure that the fabric masters 555 and the subsystem masters 565 perceive the same mapping between memory addresses and the various memory subsystem targets (as in memory map 500).

[0037] Fig. Figure 6 shows a scenario with two memory interfaces with a tightly coupled memory subsystem using address flattening. Fig. 6, a memory map 600 includes a DRAM region, an SRAM / ROM region, and a lower MMIO region, all extending between 0 and 4 GB. The DRAM region of the memory map 600 is striped, and some memory accesses to this address range may be alternately mapped to a first memory interface 610 ("memory interface 0") and a second memory interface 620 ("memory interface 1"). The SRAM / ROM region may also be mapped to the second memory interface 620. Additionally, address spaces of the first memory interface 610 and second memory interface 620 may be flattened (e.g., by setting the flattening enable register 405).

[0038] A corresponding SoC memory architecture 650 includes one or more fabric masters 655, a fabric 660, a first memory interface 661 (“Memory Interface 0”), a second memory interface 662 (“Memory Interface 1”), an MMIO interface 663, a memory subsystem 670, and various memory subsystem targets, such as a first DRAM 681 (“DRAM 0”), a second DRAM 682 (“DRAM 1”), an SRAM 683, and a ROM 684.

[0039] The fabric masters 655 can transmit memory requests to the fabric 660, which can then transmit the requests either to the MMIO interface 663, or through the first memory interface 661 to the first DRAM 681, or through the second memory interface 662 to the memory subsystem 670. Many memory requests, in turn, received by the memory subsystem 670, can then be directed to the second DRAM 682, SRAM 683, or ROM 684.

[0040] Fabric 660 may use algorithm 300, as discussed above. New memory requests to fabric 660 with addresses that fall within a shared address screen for either first memory interface 661 or second memory interface 662 may be sent to the appropriate memory interface, while a legacy PC memory map may be applied for other memory requests. In various embodiments, algorithm 300 may select between first memory interface 661 or second memory interface 662 to match a legacy striping or hashing protocol. Because memory architecture 650 has more than one memory interface, and because address flattening is shared, algorithm 300 may adjust memory address bits [M:6] of the memory requests.Additionally, for memory requests without an address that falls within a shared address screen for either the first memory interface 661 or second memory interface 662 (e.g., memory accesses for which a legacy PC memory map may be applied), the algorithm 300 may select the first memory interface 661 or second memory interface 662 based on an address bit [6], with an optional XOR with address bits [M:7].

[0041] Some systems that support flattened memory maps with screens and striping may benefit from ensuring that the boundary addresses of the screened regions are naturally aligned with powers of two. For example, a user can configure a value of Y in the flatten shift bit for screen region register 407 to determine which address bit should be taken from the screened memory addresses, and algorithm 300 can then set address bits [M:6] of the memory request to the values ​​of address bits {[M:Y],[(Y-2):6]} at point 335.

[0042] While address flattening may be enabled for some SoC topologies with tightly coupled memory subsystems (as in the memory map 600 and the corresponding SoC architecture 650), it may be disabled for other SoC topologies with independent memory subsystems that have two or more memory interfaces. Fig. Figure 7 shows a scenario with two memory interfaces with an independent memory subsystem and locked address flattening. In Fig. 7, a memory map 700 includes a DRAM region, an SRAM / ROM region, and a lower MMIO region, all extending between 0 and 4 GB. The DRAM region of the memory map 700 is striped, and some memory accesses to this address range may be alternately mapped to a first memory interface 710 ("memory interface 0") and a second memory interface 720 ("memory interface 1"). The SRAM / ROM region may also be mapped to a second memory interface 720. However, unlike the memory map 600, address spaces of the first memory interface 710 and second memory interface may not remain flattened and may instead preserve their (non-contiguous) physical addresses (e.g., by zeroing the flattening enable register 405).

[0043] A corresponding SoC memory architecture 750 includes one or more fabric masters 755, a fabric 760, a first memory interface 761 (“memory interface 0”), a second memory interface 762 (“memory interface 1”), an MMIO interface 763, one or more subsystem masters 765 (e.g., non-fabric masters), a memory subsystem 770, and various memory subsystem targets, such as a first DRAM 781 (“DRAM 0”), a second DRAM 782 (“DRAM 1”), an SRAM 783, and a ROM 784.

[0044] The fabric masters 755 can transmit memory requests to the fabric 760, which can then transmit the requests to either the first memory interface 761, the second memory interface 762, or the MMIO interface 763. The subsystem masters 765 can transmit memory requests directly to the memory subsystem 770. Many memory requests, in turn, received by the memory subsystem 770, can then be directed to the first DRAM 781, the second DRAM 782, the SRAM 783, or the ROM 784.

[0045] Fabric 760 may use algorithm 300, as discussed above. New memory requests to fabric 760 with addresses that fall within an enabled screen for either first memory interface 761 or second memory interface 762 may be sent to the appropriate memory interface, while a legacy PC memory map may be applied for other memory requests. In various embodiments, algorithm 300 may select between first memory interface 761 or second memory interface 762 to match a legacy striping or hashing protocol. Because memory architecture 750 has more than one memory interface, but because address flattening is disabled, algorithm 300 may leave memory address bits [M:6] of the memory requests unchanged.For memory requests without addresses that fall within a shared address screen for either the first memory interface 761 or second memory interface 762 (e.g., memory accesses for which a legacy PC memory map may be applied), the algorithm 300 may select the first memory interface 761 or second memory interface 762 based on an address bit [6], with an optional XOR with address bits [M:7].

[0046] The memory subsystem 770 may accept memory access requests from both the first memory interface 761 and the second memory interface 762 and handle them in parallel with the first DRAM 781 and the second DRAM 782 (either to supply data to the memory or to return data from the memory). The ability to disable address flattening while supporting the first memory interface 761 and the second memory interface 762 may allow the memory map 700 and the memory architecture 750 to preserve physical addresses throughout the memory subsystem 770. The subsystem masters 765, in turn, may advantageously perceive the same mapping between memory addresses and memory subsystem targets that the fabric masters 755 perceive (which would not have been possible without the ability to disable address flattening).The fabric 760 and the storage subsystem 770 may operate accordingly to ensure that the fabric masters 755 and subsystem masters 765 perceive the same mapping between memory addresses and the various storage subsystem targets (as in the memory map 700).

[0047] Fig. Figure 8 illustrates one embodiment of a portion of a fabric implementing an algorithm for processing memory requests. In some embodiments, fabric portion 800 may include: a memory request datapath 801 operable to transmit memory requests, first circuitry 810 operable to identify memory requests, second circuitry 820 operable to transmit or apply memory access protocols to memory requests, third circuitry 830 operable to modify addresses of memory requests, a multiple memory interface indicator 803, an address flattening indicator 805, and a memory interface 841.

[0048] More specifically, the first circuitry 810 may be operable to identify any memory request having an address that lies between any one or more pairs of base address and boundary address indicators. For example, the first circuitry 810 may compare addresses of memory requests, as in algorithm 300.

[0049] Some embodiments of the fabric section 800 may include pairs of base address and boundary address registers 815, each driving the pairs of base address and boundary address indicators through a register bus 817. For example, pairs of base address and boundary address registers 815 may be physical base address and physical boundary address registers of the screening registers 401. In some embodiments, at least one of the pairs of base address and boundary address indicators may have a corresponding screen enable register that drives a screen enable indicator. For example, the screen enable register may be a screen enable register of the screening registers 401. In some such embodiments, the first circuitry 810 may also be operable to identify a memory request when the corresponding screen enable indicator is enabled.Additionally, some embodiments of the fabric portion 800 may include a plurality of memory interfaces, wherein at least one memory interface of the plurality of memory interfaces includes one or more of the pairs of base address and boundary address indicators.

[0050] The second circuitry 820 may be operable to transfer any memory request identified by the first circuitry 810 to the memory interface 841. The second circuitry 820 may also be operable to apply a default memory access protocol to any memory request not identified by the first circuitry 810 (e.g., any memory request that does not have an address between any of the one or more pairs of base address and boundary address indicators). The default memory protocol may, for example, comprise a legacy PC memory map.

[0051] The third circuitry 830 may be operable to modify an address of a memory request when both the multiple memory interface indicator 803 and the address flattening indicator 805 are enabled. In some embodiments, the third circuitry 830 may be operable to set address bits [M:6] of a memory request. When the memory request is identified by the first circuitry 810, and when both the multiple memory interface indicator 803 and the address flattening indicator 805 are enabled, the third circuitry 803 may set address bits [M:6] of the memory request to the values ​​of address bits {[M:Y],(Y-2):6]}.If the memory request is not identified by the first circuitry 810, and if both the multiple memory interface indicator 803 and the address flattening indicator 805 are enabled, the third circuitry 803 may set address bits [M:6] of the memory request to the values ​​of address bits {[M-1:7]}. If either the multiple memory interface indicator 803 or the address flattening indicator 805 is disabled, the third circuitry 830 may leave address bits [M:6] of the memory request unmodified.

[0052] Some embodiments of the fabric portion 800 may include both a memory interface 841 and a second memory interface 842. In some such embodiments, the fabric portion 800 may include fourth circuitry 840 operable to select the second memory interface 842 for a memory request on the memory request data path based on an alternative memory interface indicator 807 indicating the use of one of a striping protocol and a hashing protocol.

[0053] Fig. 8 also shows embodiments of the fabric section 800, which includes: a memory request data path 801 operable to transmit a memory request, a first memory interface 841, a second memory interface 842, a first set of logic devices 810 operable to identify memory requests, configuration circuitry 855, and a second set of logic devices 820 operable to transmit or apply memory access protocols to memory requests.

[0054] More specifically, the first set of logic devices 810 may be operable to identify any memory request having an address that is either between a screen base address and a screen boundary address for any one of one or more first screens, or between a screen base address and a screen boundary address for any one of one or more second screens.

[0055] The configuration circuitry 855 may include a first set of memory interface logic devices including circuitry for the one or more first screens. The circuitry for at least one first screen may include a screen base address register operable to store a screen base address and a screen boundary address register operable to store a screen boundary address (like the physical base address and physical boundary address registers of the screening registers 401). The configuration circuitry 855 may also include a second set of memory interface logic devices including circuitry for the one or more second screens.The circuitry for at least a second screen may include a screen base address register operable to store a screen base address and a screen boundary address register operable to store a screen boundary address (like the physical base address and physical boundary address registers of the screening registers 401).

[0056] The second set of logic devices 820 may be operable to transmit to either the first memory interface 841 or the second memory interface 842 any memory requests identified by the first set of logic devices 810. The second set of logic devices 820 may also be operable to apply a default memory access protocol to any memory requests not identified by the first set of logic devices 810.

[0057] In some embodiments, the circuitry for at least a first screen and the circuitry for at least a second screen may include a corresponding screen enable register operable to store a screen enable (such as a screen enable register of screening registers 401). In some such embodiments, the first set of logic devices 810 may be operable to identify any memory request when the corresponding screen enable is enabled.

[0058] In some embodiments, the fabric section 800 may include an address flattening register operable to store an address flattening enable, and may also include a third set of logic devices 830 operable to modify an address associated with any memory request when the address flattening enable is enabled. In some such embodiments, the third set of logic devices 830 may be operable to set address bits [M:6] of a memory request. If the memory request is identified by the first set of logic devices 810, and if both a multiple memory interface indicator 803 and an address flattening indicator 805 are enabled, the third set of logic devices 830 may set address bits [M:6] of the memory request to the values ​​of address bits {[M:Y],(Y-2):6]}.If the memory request is not identified by the first set of logic devices 810, and both the multiple memory interface indicator 803 and the address flattening indicator 805 are enabled, the third set of logic devices 830 may set address bits [M:6] of the memory request to the values ​​of address bits {[M-1:7]}. If either the memory interface indicator 803 or the address flattening indicator 805 is disabled, the third set of logic devices 830 may leave address bits [M:6] of the memory request unmodified.

[0059] Some embodiments of the fabric section 800 may include a fourth set of logic devices 840 that may be operable to select the second memory interface 842 for a memory request on the memory request data path based on the alternative memory interface indicator 807 indicating the use of one of a striping protocol and a hashing protocol.

[0060] Fig. 9 illustrates one embodiment of a method for a fabric to process new memory requests. A method 900 may include identifying 910 a screened memory request, applying 900 a default memory access protocol, selecting 930 a second memory interface, modifying 940 a memory request address, transferring 950 to a memory interface, and modifying 970 a memory request address.

[0061] More specifically, identification 910 may include identifying, with a set of logic devices, any memory request on a memory request data path having an address that lies between any one or more pairs of base address and boundary address indicators. Applying 920 may include applying a default memory access protocol to any memory requests not identified by the set of logic devices. Transfer 950 may include transferring, to a memory interface, any memory requests identified by the set of logic devices. Modification 970 may include modifying an address of a memory request when multiple memory interfaces are available while an address flattening indicator is enabled.

[0062] Some embodiments of method 900 may include identifying, with the set of logic devices, a memory request when a corresponding screen enable indicator is enabled. In some embodiments, a first memory interface may include one or more first pairs of base address and boundary address indicators, and a second memory interface may include one or more second pairs of base address and boundary address indicators. Some such embodiments of method 900 may include selecting the second memory interface for a memory request on the memory request data path based on one of a striping protocol and a hashing protocol.

[0063] Some embodiments of method 900 may include modifying a memory request to set address bits [M:6] of the memory request. If the memory request is identified by the set of logical devices, if multiple memory interfaces are available and the address flattening indicator is enabled, address bits [M:6] of the memory request may be set to the values ​​of address bits {[M:Y],(Y-2):6]}. If the memory request is not identified by the set of logical devices, if multiple memory interfaces are available and the address flattening indicator is enabled, address bits [M:6] of the memory request may be set to the values ​​of address bits {[M-1:7]}. If either multiple memory interfaces are unavailable or the address flattening indicator is disabled, address bits [M:6] of the memory request may be left unmodified.

[0064] Although the actions in the flowchart are described with reference to Fig. 9 are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions can be performed in parallel. Some of the actions and / or operations shown in Fig. The actions listed in Figure 9 are optional according to certain embodiments. The numbering of the listed actions is for clarity and is not intended to dictate any order in which the various actions must occur. Additionally, operations from the various flows can be used in a variety of combinations.

[0065] Additionally, in some embodiments, a machine-readable storage medium may include executable instructions that, when executed, cause a fabric to perform an operation comprising method 900. Similarly, in some embodiments, the machine-readable storage medium may include instructions that, when executed, cause the fabric to perform an operation comprising method 900. Such machine-readable storage media may include any of various storage media, such as magnetic storage media (e.g., magnetic tape or magnetic disks), optical storage media (e.g., optical disks), electronic storage media (e.g., conventional hard disk drives, solid-state disk drives, or flash memory-based storage media), or any other tangible storage medium or non-transitory storage medium.

[0066] Fig. 10 illustrates a computing device with mechanisms to provide various SoC fabric extensions for configurable memory mapping according to some embodiments of the disclosure.

[0067] Fig. Figure 10 illustrates a computing device with mechanisms for providing various SoC fabric extensions for configurable memory mapping, according to some embodiments of the disclosure. It is emphasized that these elements of Fig. 10 having the same reference numbers (or names) as the elements of any other figure may operate or function in any manner similar to, but not limited to, that described.

[0068] Computing device 1000 may be a SoC, a computer system, a workstation, or a server with mechanisms to provide various SoC fabric extensions for configurable memory mapping according to some embodiments of the disclosure. Fig. Figure 10 illustrates a block diagram of one embodiment of a mobile device operable to utilize flat-face interface connectors. In one embodiment, computing device 1000 may be a mobile computing device, such as a computing tablet, a cellular or smartphone, a wirelessly shared e-reader, or other wireless mobile device. It should be understood that certain components are shown generically, and not all components of such a device are shown in computing device 1000.

[0069] Computing device 1000 includes a first processor 1010 with mechanisms for providing various SoC fabric extensions for configurable memory mapping according to some embodiments discussed. Other blocks of computing device 1000 may also include the mechanisms for providing various SoC fabric extensions for configurable memory mapping according to some embodiments. The various embodiments of the present disclosure may also include a network interface at 1070, such as a wireless interface, so that a system embodiment may be incorporated into a wireless device, for example, a cellular phone or a personal digital assistant.

[0070] In some embodiments, processor 1010 may include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 1010 may include executing an operating platform or operating system, upon which applications and / or device functions may then be executed. The processing operations may also include operations related to one or more of the following: I / O (input / output) with a human user or with other devices; power management; connecting computing device 1000 to another device; audio I / O; and / or display I / O.

[0071] In some embodiments, computing device 1000 includes an audio subsystem 1020 representing hardware components (e.g., audio hardware and audio circuitry) and software components (e.g., drivers and / or code) associated with providing audio functions to computing device 1000. Audio functions may include speaker and / or headphone output, as well as microphone input. Devices for such functions may be integrated into computing device 1000 or connected to computing device 1000. In one embodiment, a user interacts with computing device 1000 by providing audio commands that are received and processed by processor 1010.

[0072] In some embodiments, computing device 1000 includes a display subsystem 1030 representing hardware components (e.g., display devices) and software components (e.g., drivers) that provide a visual and / or touch display for a user to interact with computing device 1000. Display subsystem 1030 may include a display interface 1032, which may be a dedicated screen or a hardware device used to provide a display to a user. In one embodiment, display interface 1032 includes logic separate from processor 1010 to perform at least some processing related to the display. In some embodiments, display subsystem 1030 includes a touch screen (or touch pad) device that provides both output and input to a user.

[0073] In some embodiments, computing device 1000 includes an I / O controller 1040 associated with hardware devices and software components related to interaction with a user. I / O controller 1040 is operable to manage hardware that is part of audio subsystem 1020 and / or display subsystem 1030. Additionally, I / O controller 1040 may be a connection point for additional devices connected to computing device 1000 through which a user could interact with the system. For example, devices that may be attached to computing device 1000 include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I / O devices for use with specific applications, such as card readers or other devices.

[0074] As noted above, the I / O controller 1040 may interact with the audio subsystem 1020 and / or display subsystem 1030. For example, input from a microphone or other audio device may provide input or commands for one or more applications or functions of the computing device 1000. Additionally, audio output may be provided instead of or in addition to display output. In another example, if the display subsystem 1030 includes a touchscreen, the display device may also serve as an input device that may be at least partially managed by the I / O controller 1040. Additional buttons or switches may also be present on the computing device 1000 to provide I / O functions managed by the I / O controller 1040.

[0075] In some embodiments, the I / O controller 1040 manages devices such as accelerometers, cameras, light sensors, or other environmental sensors, or other hardware that may be included in the computing device 1000. The input may be part of a direct user interaction and may provide environmental input to the system to affect its operations (such as filtering for noise, setting indicators for brightness detection, triggering a flash for a camera, or other features).

[0076] In some embodiments, computing device 1000 includes a power management component 1050 that manages battery power usage, battery charging, and features related to power saving operation.

[0077] A storage subsystem 1060 includes storage devices for storing information in the computing device 1000. The storage subsystem 1060 may include non-volatile storage devices (whose state does not change when power to the storage device is interrupted) and / or volatile storage devices (whose state is indeterminate when power to the storage device is interrupted). The storage subsystem 1060 may store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) associated with the execution of the applications and functions of the computing device 1000.

[0078] Any portion of the memory subsystem 1060 may also be provided as a non-transitory machine-readable medium for storing the computer-executable instructions (e.g., instructions for implementing any of the processes discussed herein). The machine-readable medium may include, but is not limited to: flash memory, optical disks, CD-ROMs, DVD-ROMs, RAMs, EPROMs, EEPROMs S , magnetic or optical cards, phase-change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, some embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) that can be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) using data signals over a communications link (e.g., a modem or network connection).

[0079] In some embodiments, computing device 1000 includes a network interface within a connectivity component 1070, such as a cellular interface 1072 or a wireless interface 1074, so that an embodiment of computing device 1000 can be incorporated into a wireless device, such as a cellular phone or a personal digital assistant. In some embodiments, connectivity component 1070 includes hardware devices (e.g., wireless and / or wired connectors and communication hardware) and software components (e.g., drivers and / or protocol stacks) to enable computing device 1000 to communicate with external devices. Computing device 1000 could include separate devices, such as other computing devices, wireless access points or base stations, and peripheral devices, such as headsets, printers, or other devices.

[0080] In some embodiments, the connectivity component 1070 may include several different types of network interfaces, such as one or more wireless interfaces to allow the processor 1010 to communicate with another device. For generalization, the computing device 1000 is illustrated with a cellular interface 1072 and a wireless interface 1074. The cellular interface 1072 generally refers to wireless interfaces for radio mobile networks provided by cellular network carriers, such as via GSM or variations or derivatives, CDMA (Code Division Multiple Access) or variations or derivatives, TDM (Time Division Multiplexing) or variations or derivatives, or other cellular service standards. The wireless interface 1074 generally refers to non-cellular wireless interfaces and may include personal networks (such as Bluetooth, Near Field, etc.).), local area networks (such as Wi-Fi) and / or wide area networks (such as WiMax) or other wireless communications.

[0081] In some embodiments, computing device 1000 has various peripheral ports 1080, which may include hardware interfaces and connectors, as well as software components (e.g., drivers and / or protocol stacks) for establishing peripheral connections. It is understood that computing device 1000 could be both a peripheral device for other computing devices (via "to" 1082) and peripheral devices could be connected to it (via "from" 1084). Computing device 1000 may include a "docking" port for connecting to other computing devices for purposes such as managing content on computing device 1000 (e.g., downloading and / or uploading, modifying, synchronizing).Additionally, a docking port may allow the computing device 1000 to be connected to certain peripheral devices that allow the computing device 1000 to control output of content to, for example, audiovisual or other systems.

[0082] In addition to a dedicated docking connector or other dedicated connection hardware, the computing device 1000 may establish peripheral connections 1080 via common or standards-based connectors. Common types of connectors may include a Universal Serial Bus (USB) connector (which may have any of a variety of hardware interfaces), a DisplayPort or MiniDisplayPort (MDP) connector, a High Definition Multimedia Interface (HDMI) connector, a FireWire connector, or other types of connectors.

[0083] Reference in the description to "one embodiment," "a single embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "a single embodiment," or "some embodiments" do not necessarily always refer to the same embodiments. If the description states that a component, feature, structure, or characteristic "may," "could," or "would" be included, it is not required that that particular component, feature, structure, or characteristic be included.If the description or claim refers to "one" element, this does not mean that only one of the elements is present. If the description or claims refer to "an additional" element, this does not preclude the presence of more than one of the additional elements.

[0084] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment wherever the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0085] Although the disclosure has been described in connection with specific embodiments thereof, many alternatives, modifications, and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures, e.g., dynamic random access memory (DRAM), may utilize the discussed embodiments. The embodiments of the disclosure are intended to encompass all such alternatives, modifications, and variations that fall within the broad scope of the appended claims.

[0086] Additionally, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the illustrated figures for ease of illustration and discussion. Further, arrangements may be shown in block diagram form to avoid obscuring the disclosure, and also in light of the fact that specific details relating to implementation of such block diagram arrangements will depend heavily on the platform within which the present disclosure is to be implemented (i.e., such specific details should be within the purview of those skilled in the art). Where specific details (e.g., circuits) are recited to describe examples of embodiments of the disclosure, it should be apparent to those skilled in the art that the disclosure may be practiced without or with variation of these specific details. The description is thus to be considered illustrative and not restrictive.

[0087] The following examples pertain to further embodiments. Specific details in the examples may be used throughout one or more embodiments. Any optional features of the apparatus described herein may also be implemented with respect to a method or process.

[0088] In one example, an apparatus is provided that may include: a memory request data path operable to transmit a memory request; first circuitry, second circuitry, and third circuitry. The first circuitry may be operable to identify any memory request having an address that lies between any one or more pairs of base address and boundary address indicators. The second circuitry may be operable to transmit to a memory interface any memory request identified by the first circuitry and to apply a default memory access protocol to any memory request not identified by the first circuitry.The third circuits may be operable to modify an address of a memory request when both a multiple memory interface indicator and an address flattening indicator are enabled.

[0089] In some embodiments, the device may include pairs of base address and boundary address registers, each driving the pairs of base address and boundary address indicators. In some embodiments, at least one of the one or more pairs of base address and boundary address indicators has a corresponding screen enable register that drives a screen enable indicator. In some embodiments, the first circuitry may be operable to identify a memory request when the corresponding screen enable indicator is enabled. In some embodiments, the device may include a plurality of memory interfaces, wherein at least one memory interface of the plurality of memory interfaces has one or more of the pairs of base address and boundary address indicators.

[0090] In some embodiments, the third circuitry may be operable to set address bits [M:6] of a memory request to the values ​​of address bits {[M:Y],[(Y-2):6]} if the memory request is identified by the first circuitry and both the multiple memory interface indicator and the address flattening indicator are enabled, and to set address bits [M:6] of the memory request to the values ​​of address bits {[M-1:7]} if the memory request is not identified by the first circuitry and both the multiple memory interface indicator and the address flattening indicator are enabled, and to leave address bits [M:6] of the memory request unmodified if either the multiple memory interface indicator or the address flattening indicator is disabled.

[0091] In some embodiments, the device may include a first memory interface and a second memory interface. In some embodiments, the device may include fourth circuitry operable to select the second memory interface for a memory request on the memory request data path based on one of a striping protocol and a hashing protocol.

[0092] In another example, an apparatus is provided that may include: a memory request data path operable to transmit a memory request; a first memory interface; a second memory interface; a set of first memory interface logic devices; a set of second memory interface logic devices; a first set of logic devices; and a second set of logic devices. The set of first memory interface logic devices may include circuitry for one or more first screens, wherein the circuitry for at least a first screen includes a screen base register operable to store a screen base address and a screen boundary address register operable to store a screen boundary address.The set of second memory interface logic devices may include circuitry for one or more second screens, the circuitry for at least one second screen including a screen base address register operable to store a screen base address and a screen boundary address register operable to store a screen boundary address. The first set of logic devices may be operable to identify any memory request with an address that is either between the screen base address and the screen boundary address for any of the first screens or between the screen base address and the screen boundary address for any of the second screens.The second set of logic devices may be operable to transmit to a memory interface any memory requests identified by the first set of logic devices and to apply a default memory access protocol to any memory requests not identified by the first set of logic devices.

[0093] In some embodiments, the circuitry for at least a first screen and the circuitry for at least a second screen may include a respective screen enable register operable to store a screen enable. In some embodiments, the first set of logic devices may be operable to identify any memory request when the corresponding screen enable is enabled. In some embodiments, the device may include an address flatten enable register operable to store an address flatten enable and a third set of logic devices operable to modify an address associated with any memory request when the address flatten enable is enabled.

[0094] In some embodiments, the third set of logic devices may be operable to set address bits [M:6] of a memory request to the values ​​of address bits {[M:Y],[(Y-2):6]} if the memory request is identified by the first set of logic devices and both a multiple memory interface indicator and an address flattening indicator are enabled, and to set address bits [M:6] of the memory request to the values ​​of address bits {[M-1:7]} if the memory request is not identified by the first set of logic devices and both the multiple memory interface indicator and the address flattening indicator are enabled, and to leave address bits [M:6] of the memory request unmodified if either the multiple memory interface indicator or the address flattening indicator is disabled.

[0095] In some embodiments, the apparatus may include a fourth set of logic devices operable to select the second memory interface for a memory request on the memory request data path based on one of a striping protocol and a hashing protocol.

[0096] In another example, a system is provided that includes a memory, a processor coupled to the memory, and a wireless interface to enable the processor to communicate with another device, wherein the processor includes any of the examples of devices described above.

[0097] In another example, a system may include: a memory, a processor coupled to the memory, and a wireless interface to enable the processor to communicate with another device, the processor comprising: a memory request datapath operable to transmit memory requests, first circuitry, and second circuitry. The first circuitry may be operable to identify any memory request having an address that lies between any one of one or more pairs of base address and boundary address indicators. The second circuitry may be operable to transmit to a memory interface any memory requests identified by the first circuitry and to apply a default memory access protocol to any memory requests not identified by the first circuitry.The third circuits may be operable to modify an address of a memory request when both a multiple memory interface indicator and an address flattening indicator are enabled.

[0098] In some embodiments, the system may include one or more pairs of base address and boundary address registers, each driving the pairs of base address and boundary address indicators, wherein at least one of the one or more pairs of base address and boundary address indicators has a corresponding screen enable register that drives a screen enable indicator. In some embodiments, the first circuitry may be operable to identify any memory request when the corresponding screen enable indicator is enabled. In some embodiments, the system may include a first memory interface and a second memory interface, wherein both the first memory interface and the second memory interface have one or more of the pairs of base address and boundary address indicators.

[0099] In some embodiments, the third circuitry may be operable to set address bits [M:6] of a memory request to the values ​​of address bits {[M:Y],[(Y-2):6]} if the memory request is identified by the first circuitry and both the multiple memory interface indicator and the address flattening indicator are enabled, and to set address bits [M:6] of the memory request to the values ​​of address bits {[M-1:7]} if the memory request is not identified by the first circuitry and both the multiple memory interface indicator and the address flattening indicator are enabled, and to leave address bits [M:6] of the memory request unmodified if either the multiple memory interface indicator or the address flattening indicator is disabled.

[0100] In some embodiments, the system may include fourth circuitry operable to select the second memory interface for a memory request on the memory request data path based on one of a striping protocol and a hashing protocol.

[0101] In another example, a method may include: identifying, with a set of logical devices, any memory request on a memory request data path having an address that lies between any one or more pairs of base address and boundary address indicators; transferring, to a memory interface, any memory requests identified by the set of logical devices; applying a default memory access protocol to any memory requests not identified by the set of logical devices; and modifying an address of a memory request when multiple memory interfaces are available while an address flattening indicator is enabled.

[0102] In some embodiments, the method may include: identifying, with the set of logic devices, a memory request when a corresponding screen enable indicator is enabled.In some embodiments, the method may include modifying a memory request to set address bits [M:6] of the memory request to the values ​​of address bits {[M:Y],[(Y-2):6]} if the memory request is identified by the set of logical devices and multiple memory interfaces are available and the address flattening indicator is asserted, and to set address bits [M:6] of the memory request to the values ​​of address bits {[M-1:7]} if the memory request is not identified by the set of logical devices and multiple memory interfaces are available and the address flattening indicator is asserted, and to leave address bits [M:6] of the memory request unmodified if either multiple memory interfaces are not available or the address flattening indicator is deasserted.

[0103] In some embodiments, the first memory interface has one or more first pairs of base address and boundary address indicators, and a second memory interface has one or more second pairs of base address and boundary address indicators. In some embodiments, the method may include selecting the second memory interface for a memory request on the memory request data path based on one of a striping protocol and a hashing protocol.

[0104] In one example, a machine-readable storage medium is provided, the machine-readable storage medium having instructions stored thereon that, when executed, cause one or more processors to perform any of the examples of methods discussed above.

[0105] In another example, a machine-readable storage medium is provided, the machine-readable storage medium having machine-executable instructions stored thereon that, when executed, cause one or more processors to perform an operation that may include: identifying, with a set of logic devices, any memory request on a memory request data path having an address that is between any one of one or more pairs of base address and boundary address indicators; sending, to a memory interface, any memory requests identified by the set of logic devices; applying a default memory access protocol to any memory requests not identified by the set of logic devices;and modifying an address of a memory request when multiple memory interfaces are available while an address flattening indicator is enabled;

[0106] In some examples, the machine-executable instructions, when executed, cause one or more processors to perform an operation that may include: identifying, with the set of logic devices, a memory request when a corresponding screen enable indicator is enabled.

[0107] In some embodiments, the machine-executable instructions, when executed, cause one or more processors to perform an operation that may include: modifying a memory request to set address bits [M:6] of the memory request to the values ​​of address bits {[M:Y],[(Y-2):6]} if the memory request is identified by the set of logical devices and multiple memory interfaces are available and the address flattening indicator is enabled, and to set address bits [M:6] of the memory request to the values ​​of address bits {[M-1:7]} if the memory request is not identified by the set of logical devices and multiple memory interfaces are available and the address flattening indicator is enabled, and to leave address bits [M:6] of the memory request unmodified,if either multiple memory interfaces are unavailable or the address flattening indicator is disabled.

[0108] In some examples, the first memory interface may include one or more first pairs of base address and boundary address indicators, and a second memory interface may include one or more second pairs of base address and boundary address indicators. In some embodiments, the machine-executable instructions, when executed, cause one or more processors to perform an operation that may include selecting the second memory interface for a memory request on the memory request data path based on one of a striping protocol and a hashing protocol.

[0109] In another example, an apparatus may include: means for identifying, with a set of logic devices, any memory request on a memory request data path having an address that lies between any one of one or more pairs of base address and boundary address indicators; means for transmitting, to a memory interface, any memory requests identified by the set of logic devices; means for applying a default memory access protocol to any memory requests not identified by the set of logic devices; and means for modifying an address of a memory request when multiple memory interfaces are available while an address flattening indicator is enabled.

[0110] In some embodiments, the device may comprise: means for identifying, with the set of logic devices, a memory request when a corresponding screen enable indicator is enabled.

[0111] In some embodiments, the apparatus may comprise means for modifying a memory request to set address bits [M:6] of the memory request to the values ​​of address bits {[M:Y],[(Y-2):6]} if the memory request is identified by the set of logical devices and multiple memory interfaces are available and the address flattening indicator is enabled, and to set address bits [M:6] of the memory request to the values ​​of address bits {[M-1:7]} if the memory request is not identified by the set of logical devices and multiple memory interfaces are available and the address flattening indicator is enabled, and to leave address bits [M:6] of the memory request unmodified if either multiple memory interfaces are not available or the address flattening indicator is disabled.In some embodiments, a first memory interface may include one or more first pairs of base address and boundary address indicators, and a second memory interface may include one or more second pairs of base address and boundary address indicators.

[0112] In some embodiments, the apparatus may comprise: means for selecting a second memory interface for a memory request on the memory request data path based on one of a striping protocol and a hashing protocol.

Claims

[1] Device (800) comprising: a memory request data path (801) operable to transmit a memory request; first circuits (810) operable to identify any memory request having an address that lies between any one of one or more pairs of base address and boundary address indicators; second circuits (820) operable to transmit to a memory interface (841) any memory request identified by the first circuits (810) and to apply a default memory access protocol to any memory request not identified by the first circuits (810); and third circuits (830) operable to modify an address of a memory request when both a multiple memory interface indicator (803) and an address flattening indicator (805) are activated. [2] The apparatus (800) of claim 1, comprising pairs of base address and boundary address registers (815) each driving the pairs of base address and boundary address indicators. [3] The apparatus (800) of claim 1, wherein at least one of the one or more pairs of base address and boundary address indicators includes a corresponding screen enable register driving a screen enable indicator. [4] The apparatus (800) of claim 3, wherein the first circuits (810) are operable to identify a memory request when the corresponding screen enable indicator is activated. [5] The apparatus (800) of claim 1, comprising a plurality of memory interfaces, wherein at least one memory interface (841) of the plurality of memory interfaces includes one or more of the pairs of base address and boundary address indicators. [6] The apparatus (800) of claim 1, wherein the third circuits (830) are operable to set address bits [M:6] of a memory request to the values of address bits {[M:Y],[(Y-2):6]} when the memory request is identified by the first circuits (810) and both the multiple memory interface indicator and the address flattening indicator (805) are enabled, and to set address bits [M:6] of the memory request to the values of address bits {[M-1:7]} when the memory request is not identified by the first circuits (810) and both the multiple memory interface indicator and the address flattening indicator (805) are enabled, and to leave address bits [M:6] of the memory request unmodified when either the multiple memory interface indicator or the address flattening indicator (805) is disabled. [7] The device (800) of claim 1, comprising a first memory interface and a second memory interface. [8] The apparatus (800) of claim 7, comprising fourth circuitry (840) operable to select the second memory interface for a memory request on the memory request data path based on one of a striping protocol and a hashing protocol. [9] A system comprising a memory, a processor coupled to the memory, and a wireless interface to allow the processor to communicate with another device, the processor comprising the device of any one of claims 1 to 8. [10] Method (900) comprising: Identifying (910), with a set of logic devices (840), any memory request on a memory request data path having an address that is between any one of one or more pairs of base address and boundary address indicators; Transmitting, to a memory interface, any memory requests identified by the set of logic devices; applying (920) a default memory access protocol to any memory requests not identified by the set of logic devices; and Modifying an address of a memory request when multiple memory interfaces are available while asserting an address flattening indicator (805). [11] The method (900) of claim 10, comprising: Identifying, with the set of logic devices (840), a memory request when a corresponding screen enable indicator is activated. [12] The method (900) of claim 10, comprising: Modifying a memory request to set address bits [M:6] of the memory request to the values of address bits {[M:Y],[(Y-2):6]} if the memory request is identified by the set of logic devices and multiple memory interfaces are available and the address flattening indicator (805) is activated, and to set address bits [M:6] of the memory request to the values of address bits {[M-1:7]} if the memory request is not identified by the set of logic devices and multiple memory interfaces are available and the address flattening indicator (805) is activated, and to leave address bits [M:6] of the memory request unmodified if either multiple memory interfaces are not available or the address flattening indicator (805) is deactivated. [13] The method (900) of claim 10, wherein a first memory interface comprises one or more first pairs of base address and boundary address indicators, and a second memory interface comprises one or more second pairs of base address and boundary address indicators. [14] The method (900) of claim 13, comprising: Selecting the second memory interface for a memory request on the memory request data path based on one of a striping protocol and a hashing protocol. [15] A machine-readable storage medium having machine-executable instructions stored thereon which, when executed, cause one or more processors to perform a method (900) according to any one of claims 10 to 14. [16] Device comprising: Means for identifying, with a set of logic devices (810), any memory request on a memory request data path having an address that lies between any one of one or more pairs of base address and boundary address indicators; means for transmitting, to a memory interface, any memory requests identified by the set of logic devices (810); means for applying a default memory access protocol to any memory requests not identified by the set of logic devices; and Means for modifying an address of a memory request when multiple memory interfaces are available while an address flattening indicator (805) is enabled. [17] Device according to claim 16, comprising: Means for identifying, with the set of logic devices, a memory request when a corresponding screen enable indicator is activated. [18] Device according to claim 16, comprising: Means for modifying a memory request to set address bits [M:6] of the memory request to the values of address bits {[M:Y],[(Y-2):6]} if the memory request is identified by the set of logic devices and multiple memory interfaces are available and the address flattening indicator (805) is enabled, and to set address bits [M:6] of the memory request to the values of address bits {[M-1:7]} if the memory request is not identified by the set of logic devices and multiple memory interfaces are available and the address flattening indicator (805) is enabled, and to leave address bits [M:6] of the memory request unmodified if either multiple memory interfaces are not available or the address flattening indicator (805) is disabled. [19] The apparatus of claim 16, wherein a first memory interface comprises one or more first pairs of base address and boundary address indicators, and a second memory interface comprises one or more second pairs of base address and boundary address indicators. [20] Device according to claim 19, comprising: Means for selecting the second memory interface for a memory request on the memory request data path based on one of a striping protocol and a hashing protocol.

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