HYBRID REFERENCE GENERATION FOR FERROELECTRIC DIRECT ACCESS MEMORY

Abstract

A facility (200, 300) that includes: a reference generation circuit (210, 310) configured to generate a reference signal for a non-volatile memory (NVM) device (90), the reference generation circuit comprising: a first circuit (102) including at least one metal oxide semiconductor (MOS) capacitor (104), the first circuit (102) generating a first signal component of the reference signal, and a second circuit (202, 302) including at least one ferroelectric capacitor (204, 304), wherein the second circuit (202, 302) generates a second signal component of the reference signal, wherein the second signal component is temperature-dependent, wherein the first signal component generated by the first circuit (102) and the second signal component generated by the second circuit (202, 302) are programmable by a plurality of switches (106, 206, 306).

Description

PRIORITY

[0001] This application is an international application of U.S. Patent Application No. 15 / 179,070, filed June 10, 2016, claiming priority to U.S. Provisional Application No. 62 / 302,922, filed March 3, 2016. FIELD OF THE INVENTION

[0002] The present invention relates generally to a non-volatile memory (NV) device and, more particularly, to reference signal / reference voltage generation for a ferroelectric random access memory (F-RAM) device. STATE OF THE ART

[0003] Memory that retains its data even when power is unavailable is classified as non-volatile memory. Examples of non-volatile memory include nvSRAM, F-RAM, electrically erasable programmable read-only memory (EEPROM), and flash memory. This memory class can be used in applications where critical data must be retained after power is removed or when power is interrupted during operation.

[0004] The reference voltage for a memory device or cell can be interpreted as a voltage level that separates what is considered a "0" or a "1" data value, depending on the charge stored / generated in the memory device or cell. In certain embodiments, voltages on the memory bus below the reference voltage are considered a "0," and voltages above the reference voltage are considered a "1," or vice versa. In some embodiments, the reference voltage may be maintained at a constant level, programmable, or a combination thereof.

[0005] In some non-volatile memory devices, such as F-RAM devices, the charge dissipated by ferroelectric capacitors, such as the switching and non-switching terms, may be temperature-dependent. Therefore, there are advantages to making the reference voltage programmable or variable, allowing for more accurate reading in such F-RAM devices. Furthermore, the disclosures of US 2003 / 0099125 A1, US 2003 / 0058683 A1, and US 2004 / 0174750 A1 may be helpful in understanding the present invention.

[0006] US 2003 / 0099125 A1 describes a non-volatile ferroelectric memory device having a plurality of sense amplifiers and upper and lower cell array units, each arranged at an upper and a lower portion, wherein the upper and lower cell array units each contain a plurality of unit cells and are arranged symmetrically around the sense amplifiers. The non-volatile ferroelectric memory device further comprises at least one upper reference array unit, at least one lower reference array unit, a plurality of main bit lines connected to the unit cells of the upper or lower cell array unit, and a plurality of reference bit lines of the lower or upper cell array unit. The reference bit lines of the upper or lower cell array unit correspond to the main bit lines of the lower or upper cell array unit, which are arranged symmetrically around the sense amplifiers.

[0007] US 2003 / 0058683 A1 describes a ferroelectric-type non-volatile semiconductor memory device comprising a plurality of bit lines and a plurality of memory cells. Each memory cell comprises a first electrode, a ferroelectric layer formed at least on the first electrode, and a second electrode formed on the ferroelectric layer. A plurality of the memory cells belonging to one of two or more thermal history groups have different thermal histories with respect to their production processes. One-bit data is to be stored in one of the memory cells forming a pair, and other 1-bit data is to be stored in the other of the memory cells. One pair of the memory cells is connected to a pair of the bit lines, one pair of the bit lines being connected to a differential sense amplifier.When data stored in one of the memory cells forming a pair is read out, and when data stored in one of the memory cells forming a pair is read out, a reference potential is applied to the bit line connected to the other of the memory cells. When other data stored in the other of the memory cells is read out, a reference potential is applied to the bit line connected to one of the memory cells. A reference potential of the same level is applied to the bit lines connected to the memory cells belonging to the same thermal history group, and reference potentials of different levels are applied to the bit lines connected to the memory cells belonging to the different thermal history groups.

[0008] US 2004 / 0174750 A1 discloses a ferroelectric memory device comprising a logically programmable capacitance reference circuit. The circuit is configured to generate a reference voltage during a read mode of operation, wherein the reference voltage comprises a value that is a function of one or more memory states. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor connected to it for sensing, and a second bit line of the bit line pair is connected to the reference voltage. A sensing circuit is coupled to the bit line pair and configured to sense a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and the reference voltage on the second bit line.

[0009] The present invention relates to a device according to claim 1, a method according to claim 14 and a system according to claim 17. Advantageous embodiments of the invention may have features of dependent claims. BRIEF DESCRIPTION OF THE CHARACTERS

[0010] The present disclosure is illustrated by way of example and not limitation in the figures of the accompanying drawings. Fig. 1 is a schematic diagram illustrating a one-transistor-one-capacitor (1T1C) memory cell according to an embodiment of the claimed subject matter; Fig. Figure 2 is a diagram showing the ferroelectric hysteresis loop; Fig. 3 is a diagram illustrating the relationship between F-RAM switching term (P-term) and non-switching term (U-term) and bit failure count (F-RAM bit distribution); Fig. 4 is a schematic diagram illustrating a portion of an F-RAM device according to an embodiment of the claimed subject matter, including a metal oxide semiconductor capacitor (MOS capacitor) reference voltage generation group; Fig. Figure 5 is a graph illustrating the relationship between 1T1C reference voltage, P term, and U term as a function of temperature; Fig. Figure 6 is a graph illustrating the relationship between 1T1C F-RAM signal margins as a function of temperature; Fig. 7 is a schematic diagram illustrating a portion of an F-RAM device according to an embodiment of the claimed subject matter, including a hybrid reference voltage generation group; Fig. 8 is a schematic diagram illustrating a portion of an F-RAM device according to another embodiment of the claimed subject matter, including a hybrid reference voltage generation group; Fig. Figure 9 is a diagram illustrating the effect of scaling factors in ferroelectric reference signals; Fig. 10 is a graph illustrating the relationship between 1T1C signal margins using a MOS capacitor array and a hybrid reference generation array as a function of temperature; Fig. 11 is a graph illustrating the P-term signal, U-term signal, and hybrid 1T1C reference signal of hybrid F-RAM devices as a function of temperature; Fig. 12A is a schematic diagram illustrating a portion of a non-volatile memory system; and Fig. 12B is a representative flowchart including a method of operation for a hybrid 1T1C F-RAM device according to an embodiment of the claimed subject matter. DETAILED DESCRIPTION

[0011] The following description sets forth numerous specific details, such as examples of specific systems, components, methods, and so forth, in order to provide a thorough understanding of several embodiments of the claimed subject matter. However, it will be apparent to one of ordinary skill in the art that at least some embodiments may be practiced without these specific details. In other instances, well-known components or methods are not described in detail or are presented in simple block diagram format so as not to unnecessarily obscure the understanding of the techniques described herein. The specific details set forth below are therefore merely exemplary. Particular implementations may depart from these exemplary details and still be contemplated within the spirit and scope of the claimed subject matter.

[0012] It is common practice for computers and other processing devices to store information or programs developed or updated in non-volatile memory, such as flash memory, EEPROM, F-RAM, so that data can be retrieved in the event of a power failure or error. Summary of the embodiments:

[0013] A reference generation circuit configured to generate a reference signal for a non-volatile memory (NVM) device, the reference generation circuit comprising a first circuit having one or more metal-oxide-semiconductor (MOS) capacitors to generate a first signal component of the reference signal, and a second circuit having one or more ferroelectric capacitors to generate a second signal component of the reference signal. In one embodiment, the second signal component is temperature-dependent. The temperature dependence of the second signal component of the reference signal corresponds to the temperature characteristics of the NVM device. The first and second circuits may be coupled in parallel and configured to cumulatively generate the reference signal. In one embodiment, the first and second signals, respectively, are programmable by a plurality of switches.In one embodiment, the second circuit comprises a ferroelectric capacitor group, wherein the ferroelectric capacitor group has at least one ferroelectric capacitor. In one embodiment, a plurality of ferroelectric capacitors may be connected in parallel, and the second signal component is programmable by a plurality of switches. In another embodiment, the second circuit comprises a plurality of ferroelectric capacitor groups, and each of the ferroelectric capacitor groups has at least one ferroelectric capacitor. In one embodiment, a plurality of ferroelectric capacitors may be coupled in parallel, and wherein the ferroelectric capacitor groups are each coupled in parallel with one another, and the second signal component is programmable by a plurality of switches.The NVM device may be a ferroelectric random access memory (F-RAM) device comprising at least one ferroelectric storage capacitor having a one-transistor-one-capacitor (1T1C) configuration. One of the plurality of ferroelectric storage capacitors of the F-RAM device and at least one ferroelectric capacitor of the second circuit may have approximately the same size and / or similar structural features. The first signal component of the reference signal may be generated by charge sharing of the at least one MOS capacitor, and the second signal component may be generated by charge sharing of the at least one ferroelectric capacitor.In one embodiment, the second signal component of the reference signal may be configured to be approximately equal to a non-switching term (U-term) signal of the plurality of ferroelectric storage capacitors of the F-RAM device as a function of temperature, and the first signal component of the reference signal may be relatively temperature independent and configured to provide an approximately constant margin between the reference signal of the reference circuit and the U-term signal of the F-RAM device.The output of the first signal component of the reference signal may be controlled by a first pass transistor, wherein a gate of the first pass transistor may be configured to be coupled to a read wordline signal, and the output of the second signal component of the reference signal may be controlled by a second pass transistor, wherein a gate of the second pass transistor may be configured to be coupled to a wordline signal. In one embodiment, the output signal of the NVM device may be configured to be coupled as a first input of a sense amplifier, and the reference signal may be configured to be coupled as a second input of the sense amplifier.In one embodiment, the plurality of switches may be programmed to program a first set of the at least one MOS capacitor to generate the first signal component by charge sharing and a second set of the at least one ferroelectric capacitor to generate the second signal component by charge sharing.

[0014] In one embodiment, an operating method comprises the step of providing a reference generation circuit having a first circuit including at least one MOS capacitor and a second circuit including at least one ferroelectric capacitor, wherein the first and second circuits are coupled in parallel. This is followed by the steps of generating, by the first circuit, a first signal component by charge sharing, generating, by the second circuit, a second signal component by charge sharing. This is then followed by the steps of generating a reference signal by combining the first and second signal components, coupling the reference signal as a first input to a sense amplifier, and coupling a signal output of an NVM device as a second input to a sense amplifier.This is followed by the step of outputting, by the sense amplifier, a first data value of the NVM device if the reference signal is greater than the signal output of the NVM device, and a second data value if the reference signal is less than the signal output of the NVM device. In one embodiment, the NVM device comprises a ferroelectric random access memory (F-RAM) having a 1T1C configuration.The method may also include the steps of precharging the at least one MOS capacitor and the at least one ferroelectric capacitor to a precharge voltage, programming the at least one MOS capacitor and ferroelectric capacitor, using a plurality of switches such that the second signal component resembles a non-switching term (U-term) signal of the F-RAM as a function of temperature, and the first signal component provides a temperature-independent margin between the reference signal and the U-term signal, and configuring the magnitude of the precharge voltage.

[0015] In one embodiment, a memory system comprises a processing element, a memory section comprising a plurality of 1T1C F-RAM cells arranged in rows and columns, a hybrid reference generation device further comprising a MOS circuit comprising at least one MOS capacitor, the MOS circuit generating a first signal component of a reference signal that does not vary significantly as a function of temperature. The memory section further comprises a ferroelectric circuit comprising at least one ferroelectric capacitor, the ferroelectric circuit generating a second signal component of the reference signal that may be temperature dependent. The memory system further comprises a plurality of bitlines, wherein the 1T1C F-RAM cells of a same column share one of the bitlines, and a sense amplifier coupled to the 1T1C F-RAM cells via the bitlines.In one embodiment, the sense amplifier is configured to receive signal outputs of the 1T1C F-RAM cells as a first input and the reference signal from the hybrid reference generation device as a second input. In one embodiment, the ferroelectric capacitors of the ferroelectric circuit are located in a peripheral region of the memory portion, wherein the at least one ferroelectric capacitor may be similar to ferroelectric storage capacitors in the 1T1C F-RAM cells. In another embodiment, the ferroelectric capacitors of the ferroelectric circuit are located adjacent to the MOS circuit, wherein the ferroelectric capacitors replace a portion of the MOS capacitors to preserve the die area.

[0016] Embodiments of a hybrid reference voltage generation circuit for memory devices based on ferroelectric capacitors and methods for operating the same, which enable the inclusion of a temperature-dependent component in the generated reference voltage, will now be described with reference to the accompanying drawings. The described drawings are only schematic and non-limiting. In the drawings, the size of some elements may be exaggerated for illustrative purposes and not drawn to scale. The dimensions and relative dimensions may not correspond to actual reductions to be practiced within the meaning of the claimed subject matter.For the purpose of clarity, many general and specific details of input devices and methods of operation which are widely known and not relevant to the present device and method have been omitted from the following description.

[0017] Fig. Figure 1 is a schematic diagram illustrating a single-transistor-one-capacitor ferroelectric random access memory (1T1C F-RAM) cell according to one embodiment of the claimed subject matter. In one embodiment, the 1T1C F-RAM cell 90 may include a non-volatile element, such as a ferroelectric capacitor (ferroelectric F-RAM capacitor) 96, an n-channel or p-channel field-effect pass transistor (pass transistor) 98, and a bitline capacitor 92, which may be a metal-oxide-semiconductor (MOS) capacitor or a simple parasitic capacitance. The ferroelectric F-RAM capacitor 96 may comprise a structure of a ferroelectric layer sandwiched between two conductive plates, or similar embodiments known in the art.In one embodiment, one plate of the ferroelectric F-RAM capacitor 96 may be coupled to the plate line 94, and the other plate may be coupled to the bit line 99 via the source-drain path of the pass transistor 98. The gate of the pass transistor 98 may be coupled to the word line 97 and configured to be controlled by the word line signal. In one embodiment, the read and write operations of the F-RAM cell 90 are performed by programming the plate line signal, bit line signal, and word line signal. Accordingly, the polarity state representing the data value "0" or "1" of the ferroelectric F-RAM capacitor 96 may be flipped, maintained, and output according to the desired stored data value.In certain embodiments, multiple 1T1C F-RAM cells 90 may be arranged in an F-RAM group (not shown in this figure), and each 1T1C F-RAM cell 90 of a same row or column may share a common plate line 94, bit lines 99, and / or word line 97. In one embodiment, charge generated in the ferroelectric F-RAM capacitor 96 during a read operation is output to a sense amplifier (not shown in this figure) to determine whether stored data represents a "0" or "1" data. However, it should be understood that other types of transistors, such as p-channel FETs, and combinations of different types of transistors, capacitors, and resistors may be used in similar embodiments of the F-RAM cells.

[0018] Fig. Figure 2 is a diagram showing the ferroelectric hysteresis loop, which can explain the operation of the ferroelectric F-RAM capacitor 96 or similar ferroelectric devices. As shown in Fig. As shown in Figure 2, ferroelectric capacitors, such as the ferroelectric F-RAM capacitor 96, demonstrate spontaneous non-zero polarization even when the applied electric field is zero. This distinguishing feature means that the spontaneous polarization can be reversed, or flipped, by a sufficiently strong electric field applied in an opposite direction. The polarization therefore depends not only on the currently applied electric field, but also on the current polarity of the ferroelectric capacitor. The non-switching term (U-term or U-term signal) is the charge generated on the ferroelectric F-RAM capacitor 96 when no change in polarization occurs after a voltage or electric field is applied to it. The switching term (P-term or P-term signal) is the charge generated when a change in polarization occurs.In a 1T1C configuration, U term may represent data "0" and P term may represent data "1," or vice versa in some embodiments. Positive non-switch-to term (Ua term or Ua term signal) is the positive charge generated after a voltage or electric field is removed from a ferroelectric capacitor when no polarization reversal occurs, while negative non-switch-to term (Da term or Da term signal) is the negative charge generated under the same conditions. In the following subsections, the magnitude of U, P, Ua, and Da term signals can be expressed in voltage terms and compared to other signals.

[0019] The 1T1C F-RAM architecture, which may include only one ferroelectric capacitor, can use the P-term and U-term of the same ferroelectric capacitor in the 1T1C F-RAM cell to represent stored data. A 1T1C F-RAM cell can therefore be considered single-ended. In contrast, the two-transistor, two-capacitor (2T2C) F-RAM architecture (not shown), which includes two ferroelectric capacitors, can use the P-term of one ferroelectric capacitor and the U-term of the other ferroelectric capacitor in the same 2T2C F-RAM cell to represent stored data. In one embodiment, 2T2C F-RAM cells can result in a signal margin that benefits from the full ferroelectric capacitor switching charge (i.e., P-term - U-term), making the 2T2C F-RAM cell differential. However, a 1T1C F-RAM cell or array can have the advantage of a smaller cell size compared to the 2T2C design.

[0020] A reference signal or reference voltage is a voltage generated internally in an F-RAM device or externally as a reference to differentiate the P-term and U-term of ferroelectric capacitors, which in turn represent data "1" and "0," respectively. Since 1T1C F-RAM uses the P-term and U-term of the same ferroelectric capacitor, a reference voltage may be required to differentiate the two signals. In one embodiment, as shown in Fig. As illustrated in Figure 3, a reference voltage is generated within a range between the U-term signal and the P-term signal. Mgn0 is defined as the 1T1C signal margin for data "0," which may be the voltage difference between the reference voltage and the U-term signal. Mgn1 is defined as the 1T1C signal margin for data "1," which is the difference between the P-term signal and the reference voltage. It should be understood that P-term and U-term can be reversed to represent "0" and "1," respectively, in some embodiments. The 1T1C reference voltage divides the total ferroelectric switching charge into two components or parts: the signal margin for data "0" (Mgn0) and the signal margin for data "1" (Mgn1). Compared to the 2T2C design, the 1T1C design can only encompass a maximum of half the signal margin if the reference voltage is perfectly configured at a half voltage between P-term and U-term signals.The smaller cell size of the 1T1C design may therefore come at the expense of available signal margin. Referring to . Fig. 3, the U-term signal exhibits a relatively small change over the lifetime of F-RAM devices, the 1T1C reference voltage can be set across the U-term signal with a fixed offset, which can be equal to Mgn0.

[0021] Fig. 4 is a schematic diagram illustrating a portion of an F-RAM device 100 including a MOS capacitor reference voltage generation group 102. Referring to Fig. 4, the F-RAM device 100 may include a 1T1C F-RAM cell 90 having the 1T1C configuration. It should be understood that the 1T1C F-RAM device 100 may include multiple 1T1C F-RAM cells 90, where each 1T1C F-RAM cell 90 may store one bit of data ("0" or "1"). In some embodiments, the F-RAM device 100 may include at least one 2T2C F-RAM cell (not shown in this figure). In one embodiment, the ferroelectric F-RAM capacitor 96 is coupled to an input of the sense amplifier 120 and thus outputs its signal thereto via the bit line 99. Pass transistor 98 controls the output signal of ferroelectric F-RAM capacitor 96 and can be programmed by a word line (WL) signal. F-RAM device 100 further includes a MOS reference generation circuit 102, which may include a MOS capacitor array 110.In one embodiment, the MOS capacitor array 110 includes at least one reference MOS capacitor 104, with one plate of each reference MOS capacitor 104 coupled to the switch 106 and the other plate configured to receive a core voltage Vcc or other appropriate voltages. Multiple reference MOS capacitors 104 may be arranged in parallel, and their collection signal output is coupled to a second input of the sense amplifier 120. The collection signal output of the MOS array 110 is controlled by a read wordline (RWL) signal. In one embodiment, the reference MOS capacitors 104 are precharged to Vcc or other appropriate voltages. When a read operation of the F-RAM device 100 is initiated, WL and RWL signals, respectively, turn on the pass transistors 98 and 108 in the 1T1C F-RAM cell 90 and the MOS reference generation circuit 102.In the 1T1C F-RAM cell 90, if the polarity state of the ferroelectric F-RAM capacitor 96 flips, the P-term signal is output to the sense amplifier 120. The U-term signal is output if the polarity state of the ferroelectric F-RAM capacitor 96 remains unchanged. In the MOS reference generation circuit 102, the reference MOS capacitors 104 are temporarily disconnected from receiving Vcc. Charges accumulated during the precharge stage are then combined to generate the 1T1C reference voltage. The signal amplifier 120 is then configured to compare the signal output from the 1T1C F-RAM cell 90 with the 1T1C reference voltage. Data stored in the 1T1C F-RAM cell 90 is considered a "0" if the 1T1C reference voltage is greater and a "1" if the 1T1C reference voltage is less. As previously discussed, the 1T1C reference voltage is programmed to be above the U-term signal by an offset margin (Mgn0).In one embodiment, one approach to programming the magnitude of the 1T1C reference voltage is to precharge only a portion of the reference MOS capacitors 104. Another approach is to configure the 1T1C reference voltage to program the switches 106, with only a portion of the switches 106 closed during the read operation. In an alternative embodiment, a combination of the two approaches may be adopted. The 1T1C reference voltage may be generated by charge sharing among the reference MOS capacitors 104 being programmed and could be used for more than one F-RAM cell 90 by averaging the 1T1C reference voltage. In another alternative embodiment, the Vcc or voltages coupled to the reference capacitors 104 may be programmed to control the magnitude of the 1T1C reference voltage.In general, the 1T1C reference voltage can be calculated using the following formula: 1T1C reference voltage = Vcc × C. C / C T , where C C is the total capacitance of all MOS capacitors charged to Vcc, and C T is the total capacitance of the programmed MOS capacitors. In one embodiment, the 1T1C reference voltage generated by charge sharing of multiple MOS capacitors, which can be averaged for each of the multiple 17T1C F-RAM cells 90.

[0022] Generally, the reference voltage generated by the reference generation circuit consists solely of MOS capacitors, such as MOS reference generation circuit 102. In one embodiment, the reference voltage generated solely by the MOS capacitor circuit will not vary or fluctuate significantly as a function of temperature. It will be understood here and in later subsections that the reference voltage generated by MOS capacitors is considered relatively temperature-independent. After the reference generation circuit has been programmed, the reference voltage will vary or fluctuate insignificantly as a function of operating temperature.For 2T2C F-RAM devices, it may be advantageous for the reference voltage used to determine the signal margin to be relatively temperature-independent and not vary significantly as a function of temperature, since no temperature factor can be considered for the reference voltage when determining the signal margins at different temperatures. However, for 1T1C F-RAM, such as F-RAM device 100, due to the nonlinearity of the U-term and P-term of the ferroelectric F-RAM capacitors 96 in 1T1C F-RAM cell 90 as a function of temperature, a relatively temperature-independent 1T1C reference voltage can limit the switching-term signal margin Mgn1 of F-RAM device 100 as the temperature increases. The loss of Mgn1 can cause incorrect data reading and poses a major challenge for 1T1C F-RAM devices that meet the temperature requirement, such as being operational at a temperature higher than 85 °C.

[0023] Fig. Figure 5 is a graph illustrating the relationship between 1T1C reference voltage, P term, and U term as a function of temperature. Referring to Fig. 5, the 1T1C reference voltage is generated by a MOS-only capacitor generation circuit, such as the MOS reference generation circuit 102 in Fig. 4, which generates signals that may not vary significantly as a function of temperature. However, the switching-term signal (P-term signal) and non-switching-term signal (U-term signal) of the ferroelectric F-RAM capacitors 96 in the 1T1C F-RAM cell 90 may be temperature-dependent and change as a function of temperature. At temperatures higher than room temperature, the P-term signal decreases with increasing temperature, while the U-term signal follows a parabolic trend with a maximum value at or around room temperature. At temperatures higher than room temperature, the U-term signal then decreases with increasing temperature, but the decrease may occur at a slower rate than the P-term signal. As shown in Fig. 5 illustrates that when the temperature increases, Mgn1 decreases at an increasing rate, while Mgn0 remains constant or can increase. When the temperature exceeds a certain threshold, such as 125 °C, as in Fig. 5, Mgn1 may become too small for the sense amplifier to distinguish a P-term signal from a U-term signal. As a result, the sense amplifier can determine essentially all signals as being below the relatively temperature-independent 1T1C reference voltage, which is U-term (data "0"). Fig. Figure 5 shows an example of F-RAM to illustrate this phenomenon. As in the example for Fig. As shown in Figure 5, the critical or switching-term signal margin (Mgn1 = 53 mV) meets the minimum requirement of 46 mV at 90 °C, but becomes too small (Mgn1 = 19 mV) at 125 °C. The decreasing Mgn1 may be a reason why some 1T1C F-RAM devices are not suitable for applications with required temperature ranges above 85 °C, and can only be specified as operational in the industrial engine range (-45 °C to 85 °C).

[0024] Fig. Figure 6 is a diagram showing the relationship between 1T1C F-RAM signal margins (Mgn0 and Mgn1) derived from Fig. 5, as a function of temperature. As in Fig. As illustrated in Figure 6, the switching-term signal margin (Mgn1 = P-term - 1T1C reference voltage) of the MOS-capacitor-only reference generation circuit decreases rapidly with increasing temperature above 30°C. For example, at 130°C, Mgn1 is only 16 mV due to the P-term degradation of the 1T1C F-RAM at higher temperatures, while the relatively temperature-independent 1T1C reference signal determined for room temperature remains relatively stable. At 150°C, no switching margin remains on the switching side (Mgn1 = 0), which can contribute to data read errors. On the other hand, the non-switching-term signal margin (Mgn0 = 1T1C reference - U) increases with increasing temperature above 30°C due to the reduction of U-term at higher temperatures.

[0025] As previously in Fig. 3, the U-term of the F-RAM capacitors 96, such as those in the F-RAM device 100, does not change significantly during their retention period. Referring to Fig. 5, the total signal mass (Mgn0 + Mgn1) decreases as the temperature increases. Therefore, it may be preferable for the 1T1C reference voltage to follow the U-term trend of the F-RAM capacitors 96 as a function of temperature, rather than being relatively constant and not fluctuating significantly as a function of temperature. In other words, the 1T1C reference voltage may be variable according to the temperature characteristics of the ferroelectric F-RAM capacitor 96. Furthermore, this may prevent Mgn0 from increasing with temperature. The increasing Mgn0 may not add accuracy for a correct read of a U-term signal or data "0," but may contribute to an incorrect read of a P-term signal or data "1." In one embodiment, the temperature-dependent 1T1C reference voltage can maximize the switching term signal margin (Mgn1), especially at higher temperatures, such as above 85°C.

[0026] Fig. Figure 7 is a schematic diagram illustrating a portion of a hybrid F-RAM device 200, including a hybrid reference voltage generation array / matrix 210, which may be capable of generating a temperature-dependent 1T1C reference signal. The hybrid F-RAM device 200 may have a similar structure to the F-RAM device 100 in Fig. 4, which includes sense amplifier 120, 1T1C F-RAM cell 90, and 1T1C reference voltage generation matrix 210. In one embodiment, hybrid 1T1C reference voltage generation matrix 210 further includes a MOS reference generation circuit 102 and a ferroelectric reference generation circuit 202. It should be understood that hybrid F-RAM device 200 may include multiple 1T1C F-RAM cells 90, and each 1T1C F-RAM cell 90 may store one bit of data ("0" or "1"). In one embodiment, each ferroelectric F-RAM capacitor 96 is coupled to a first input of sense amplifier 120 and thus outputs its signal thereto via bit line 99. The pass transistor 98 controls the output signal of the ferroelectric F-RAM capacitor 96 and can be programmed by the word line signal (WL signal).The inclusion of the hybrid 1T1C reference voltage generation matrix 210 may provide an option for the F-RAM device 200 to utilize both the MOS reference generation circuit 102 and the ferroelectric reference generation circuit 202 to generate a hybrid 1T1C reference voltage.

[0027] Referring to Fig. 7, the MOS reference generation circuit 102 includes a MOS capacitor matrix 110. In one embodiment, the MOS capacitor matrix 110 includes at least one reference MOS capacitor 104, with one plate of each reference MOS capacitor 104 coupled to the switch 106 and the other plate configured to receive a core voltage Vcc or other appropriate voltages. In some embodiments, multiple reference MOS capacitors 104 may be programmed by the same switch 106 (not shown in this figure). Multiple reference MOS capacitors 104 may be arranged in parallel to generate a collective MOS capacitor signal by charge sharing, and their collective signal output may become the MOS component of the hybrid 1T1C reference signal. The output of the collection signal of the MOS capacitor matrix 110 can be controlled by the read word line signal (RWL signal).In one embodiment, the reference MOS capacitors 104 are precharged to Vcc or other predetermined voltages. When a read operation is initiated, the WL and RWL signals turn on the pass transistors 98 and 108 in the 1T1C F-RAM cell 90 and the MOS reference generation circuit 102, respectively. In one embodiment, the reference MOS capacitors 104 of the MOS reference generation circuit 102 are temporarily disconnected from Vcc. Charges accumulated during the precharge stage are then combined or charge-shared to generate the accumulated MOS capacitor signal, which in turn becomes the MOS component of the hybrid 1T1C reference voltage. In one embodiment, the hybrid 1T1C reference signal includes the relatively temperature-independent MOS component and the temperature-dependent ferroelectric component, which is discussed in subsequent subsections.In one embodiment, the MOS component may provide a relatively constant offset of the hybrid 1T1C reference voltage level, which may be Mgn0, over the non-switching term (U term) of the ferroelectric F-RAM capacitor 96 in the 1T1C F-RAM cell 90. The MOS reference generation circuit 102 is programmable so that the magnitude of the collection MOS capacitor signal can be adjusted to a desirable Mgn0. In one embodiment, the F-RAM device 200 is operable over a wide range of temperatures. As discussed, one embodiment for programming the magnitude of the collection MOS capacitor signal is to precharge only a portion of the reference MOS capacitors 104 in the MOS capacitor array 110. Another embodiment for programming the collective MOS capacitor signal is to program the switches 106 in which only a portion of the switches 106 are closed during the read operation.In an alternative embodiment, a combination of the two approaches may be adopted. In another alternative embodiment, the Vcc or other voltages coupled to the reference MOS capacitors 104 may be configured to control the magnitude of the pooled MOS capacitor signal. As the temperature increases, the total signal margin (P-term - U-term) of the ferroelectric F-RAM capacitor 96 decreases. There may be a point (temperature) at which the pooled MOS capacitor signal can be adjusted or reprogrammed so that the F-RAM device 200 remains operational. In one embodiment, the MOS capacitor array 110 may be required to include a full set of MOS capacitors to determine the true signal margin at different temperatures without introducing temperature-induced fluctuations into the hybrid 1T1C reference voltage.

[0028] Referring to Fig. 7, the MOS reference generation circuit 202 includes a ferroelectric capacitor array 220. In one embodiment, the ferroelectric capacitor array 220 includes at least one ferroelectric reference capacitor 204, with one plate of each ferroelectric reference capacitor 204 coupled to the switch 206 and the other plate configured to receive a core voltage Vcc or other appropriate voltages. In some embodiments, multiple ferroelectric reference capacitors 204 may be programmed by the same switch 206. Multiple ferroelectric reference capacitors 204 may be arranged in parallel to generate a ferroelectric collection capacitor signal through charge sharing, and their collection signal output as the ferroelectric component of the hybrid 1T1C reference signal.In one embodiment, the ferroelectric collection capacitor signal is combined with the collection MOS capacitor signal as previously described to generate the hybrid 1T1C reference signal and then coupled to a second input of sense amplifier 120. The output of the collection signal of ferroelectric capacitor array 220 is controlled by a ferro word line (FeRWL) signal. In one embodiment, ferroelectric reference capacitors 204 may incorporate a temperature-dependent ferroelectric component to the hybrid 1T1C reference signal, which may correspond to the temperature characteristics of ferroelectric F-RAM capacitor 96. As a result, the hybrid 1T1C reference signal varies at approximately the same rate as the U-term signal of ferroelectric F-RAM capacitors 96 as a function of temperature. Mgn0 can be kept relatively constant and the same as the MOS component of the hybrid 1T1C reference signal.As a result, Mgn1 can be maximized, especially at high temperatures, such as above 85°C. In one embodiment, the ferroelectric reference capacitors 204 can have the same structural features, including plate size, plate thickness, and construction material, as well as ferroelectric layer size, thickness, and material, as the ferroelectric F-RAM capacitors 96. In one embodiment, one plate of each ferroelectric reference capacitor 204 receives Vcc or other appropriate voltages. When Vcc is temporarily disconnected, each ferroelectric reference capacitor 204 can generate a non-switch-after-term (Ua-term) signal, or a Da-term signal if it is a negative voltage. If the ferroelectric reference capacitors 204 have a similar size and structure to the ferroelectric F-RAM capacitors 96, the generated Ua term may match the U term of the ferroelectric F-RAM capacitors 96.As a result, the ferroelectric component of the hybrid 1T1C reference signal can follow a similar curve as the U-term signal of the ferroelectric F-RAM capacitors 96 when plotted against temperature.

[0029] In one embodiment, the ferroelectric reference capacitors 204 are programmable and can be programmed in the same manner as the reference MOS capacitors 104, as discussed above using the switches 206, and / or by programming the Vcc or voltage coupled to the ferroelectric reference capacitors 204. It may be advantageous for the ferroelectric reference capacitors 204 to be programmable because their Ua or Da term may only be partially utilized to generate the ferroelectric component of the 1T1C reference signal due to charge sharing. The F-RAM device 200 may have more ferroelectric reference capacitors 204 than ferroelectric F-RAM capacitors 96 so that the ferroelectric component of the 1T1C reference signal best matches the U-term signal of ferroelectric F-RAM capacitors 96.Furthermore, the ferroelectric component of the hybrid 1T1C reference may be generated using the average of multiple ferroelectric reference capacitors 204 to ensure the reliability of the F-RAM device 200 if some of the ferroelectric reference capacitors 204 become defective over time. In one embodiment, the hybrid 1T1C reference voltage generated by charge sharing of multiple reference MOS capacitors 104 and ferroelectric reference capacitors 204 may be averaged for each of the multiple 1T1C F-RAM cells 90.

[0030] Fig. Figure 8 is a schematic diagram illustrating a portion of a hybrid F-RAM device 300, including a hybrid reference voltage generation array / matrix 310. Similar to the hybrid F-RAM device 200, the hybrid F-RAM device 300 may include a sense amplifier 120, at least one 1T1C F-RAM cell 90, and a hybrid reference voltage generation array / matrix 310. In one embodiment, the hybrid reference voltage generation array 310 includes a MOS reference generation circuit 102 and a ferroelectric reference generation circuit 302 that collectively or cumulatively generate the hybrid 1T1C reference signal. At least one ferroelectric capacitor array 320 is present in the ferroelectric reference generation circuit 302. In one embodiment, multiple ferroelectric capacitor arrays 320 may be arranged in parallel, and the output of each ferroelectric capacitor array 320 is programmed by switch 306.In one embodiment, each ferroelectric capacitor array 320 may contain at least one ferroelectric reference capacitor 304 arranged in parallel. The ferroelectric component of the hybrid 1T1C reference signal may be generated by charge sharing among the ferroelectric reference capacitors 304 in each ferroelectric capacitor array 320, and then by charge sharing among multiple ferroelectric capacitor arrays 320. As with the hybrid F-RAM device 200, both the MOS reference generation circuit 102 and the ferroelectric reference generation circuit 302 are programmable by switches 106 and 306, respectively.

[0031] Referring to Fig. 7 and Fig. 8, both the MOS reference generation circuit 102 and the ferroelectric reference generation circuit 202 or 302 are programmable. In some embodiments, the MOS component and / or the ferroelectric component of the 1T1C reference voltage, or both, may be disabled. Such embodiments may provide flexibility in configuring the hybrid F-RAM device 200 and 300.

[0032] It is understood that hybrid reference generation circuits, such as those described in Fig. 7 and Fig. 8 may also be adopted to generate hybrid reference signals for 2T2C F-RAM cells (not shown) in some alternative embodiments.

[0033] Fig. Figure 9 is a diagram illustrating the effect of scaling factors in the ferroelectric component of a hybrid 1T1C reference signal. When more ferroelectric capacitors, such as ferroelectric reference capacitors 204 and 304, share charge to generate the ferroelectric component of the 1T1C reference signal, a change in the U-term curve may occur as the temperature increases, as shown in Fig. 9. Referring to Fig. 9, for example, the ferroelectric component of the hybrid 1T1C reference signal is set to 1.4 x U-term. It is observed that the ferroelectric component can exhibit a higher scaling rate than the U-term. The change in the curve can also be more pronounced when the scaling factor is large. Therefore, it may be important that the relatively temperature-independent MOS component in the hybrid 1T1C reference signal is such that Mgn0 is kept above a minimum operating value to ensure end-of-life reliability of non-switching term data "0."

[0034] Fig. Figure 10 is a graph illustrating the relationship between Mgn1 using a MOS-only capacitor array and a hybrid reference generation array as a function of temperature. Referring to Fig. 10, the reading of Mgn1 for the P-term (data "1") is greatly improved when the temperature-dependent ferroelectric component is included in the hybrid 1T1C reference signal, especially at high temperatures. For example, at 130 °C with the proposed hybrid 1T1C reference signal, the Mgn1 is 36 mV, which is 20 mV higher than the MOS capacitor-only signal. At 150 °C, there is still a 22 mV critical 1T1C signal margin (mgn1 = 22 mV) for the hybrid 1T1C reference signal, while no signal margin remains for the MOS capacitor-only 1T1C reference signal.

[0035] Fig. Figure 11 is a graph illustrating the P-term signal, U-term signal, and hybrid 1T1C reference signal of hybrid F-RAM devices as a function of temperature. As discussed, data stored in 1T1C F-RAM cells 96 can be considered a "0" if the hybrid 1T1C reference signal is greater than the output signal of 1T1C F-RAM cells 96, and a "1" if the hybrid 1T1C reference signal is less than the output signal of 1T1C F-RAM cells 96. Referring to Fig. 11, the ferroelectric component of the hybrid 1T1C reference signal, with appropriate programming, tracks the change in the U-term signal of 1T1C F-RAM cells 90 as a function of temperature. In one embodiment, the programming may include considering the scaling factor and charge sharing factor of the ferroelectric reference generation circuitry 202 and 302. As a result, Mgn0 may be kept constant at the minimum requirement (MOS component of the hybrid 1T1C reference signal) for correctly reading data "0." In one embodiment, the remaining total signal margin contributes to maintaining an operational Mgn1 while the total signal margin continues to decrease, thus ensuring end-of-life reliability of the read non-switching term signal.

[0036] Fig. 12A is a block diagram of a semiconductor memory 400 including the memory portion 401. Within the memory portion 401, there is a memory group 402 of non-volatile memory cells (NV cells) 406 arranged in a number of rows, each sharing a common word line (WL), and a number of columns, each sharing a common bit line. In one embodiment, the NV memory cells 406 may be 1T1C F-RAM cells 90 or 2T2C F-RAM cells. In one embodiment, the reference generation group 408, which includes the MOS reference generation group, such as 102, and possibly ferroelectric reference generation groups, such as 202 and 302, may also be located within the memory portion 401. Referring to Fig. 12A, the semiconductor memory 400 further includes a processing element 410, such as a microcontroller, microprocessor, or state machine. In one embodiment, the processing element 410 may issue commands or control signals, such as WL, RWL, and FeRWL signals, to each of the NV memory cells 406 and the reference generation group 408 to perform read, erase, and program operations as described above, and to other peripheral circuitry for reading from or writing to the memory group 402. The peripheral circuitry includes a row decoder 412 to convert a memory address and apply it to the word lines of the NV memory cells 406 of the memory group 402. When a data word is read from the semiconductor memory 400, the NV memory cells 406 coupled to a selected word line (WL) are read out to a bit line, and a state of these lines is detected by a sense amplifier / driver 414.Column decoder 416 outputs the data from the bit line to sense amplifier / driver 414. In one embodiment, row and / or column decoders 412 and 416 may also convert an address and apply it to the read word lines (RWL) of the MOS reference generation group and ferro read word lines (FeRWL) of the ferroelectric reference generation group to control the output of a particular hybrid reference signal to sense amplifier / driver 414.

[0037] Possible solutions for integrating the ferroelectric reference generation group, which includes ferroelectric reference capacitors, into the semiconductor memory 400 are described in this patent. In one embodiment, ferroelectric dummy capacitors in the peripheral region 404 of the memory group 402 can be used as ferroelectric reference capacitors to generate the ferroelectric component of the hybrid reference signal. Alternatively, ferroelectric reference capacitors can use ferroelectric fill space on top of the memory group 402. These embodiments may be applicable if the path to the sense amplifier 414 is relatively direct, without excessive effects due to parasitic capacitance. In an alternative embodiment, the ferroelectric reference generation group, which includes ferroelectric reference capacitors, is located next to the MOS reference generation group in the reference generation group 408.To maintain the same die area, several reference MOS capacitors in the MOS reference generation group can be eliminated, leaving enough space to accommodate the ferroelectric reference capacitors in the ferroelectric reference generation group. There is a relatively large difference in the dielectric constant between MOS capacitors and ferroelectric capacitors (approximately 4 MOS capacitors vs. 650 ferroelectric capacitors) of the same size. Freeing up enough space to add enough ferroelectric reference capacitors to generate the hybrid reference signal component can be achieved. It should be understood that... Fig. 12A illustrates only one exemplary embodiment of the semiconductor memory 400 including the hybrid reference generation group 408. One advantage of having both MOS and ferroelectric reference generation groups is to avoid variations in the U-term signals of F-RAM cells due to the temperature difference at different locations on the die.

[0038] In an alternative embodiment (not shown), a temperature sensor can be integrated into an F-RAM system to address the temperature dependence issues of ferroelectric capacitors in F-RAM cells. The temperature sensor can be coupled to a programmable voltage regulator that generates a reference voltage for a sense amplifier. The programmable voltage regulator can then adjust the reference voltage according to the temperature change.

[0039] Fig. 12B illustrates one embodiment of a method 500 for operating a hybrid 1T1C F-RAM device, such as that described in Fig. 7 and Fig. 8 illustrated hybrid F-RAM devices 200 and 300. For illustrative purposes only, the Fig. 12B illustrated steps with reference to an example design and operational details shown in Fig. 1-12A.

[0040] In step 502, the MOS and ferroelectric reference generation groups are formed as shown in Fig. 7 and Fig.8. In step 504, both groups are precharged to Vcc and programmed using switches. In steps 506 and 508, outputs from both groups are controlled by RWL and FeRWL signals via their respective pass transistors. In step 510, when a read operation is initiated, the signal stored in the 1T1C F-RAM cells is output as the first input to a sense amplifier. The signal output of the 1T1C F-RAM cells is controlled by the WL signal applied to each pass transistor. In step 512, the MOS and ferroelectric reference generation groups are decoupled from Vcc. Outputs from both groups are then combined and coupled as the second input to the sense amplifier.In step 514, the sense amplifier may compare the two signals in its first and second inputs and determine that the stored signal of the 1T1C F-RAM cells is "1" if the first input is greater than the second input, and "0" if the second input is greater than the first input, or vice versa, depending on the system configuration.

[0041] Although the present disclosure has been described with reference to specific exemplary embodiments, it will be apparent that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the disclosure. Accordingly, the specification and drawings are to be considered as illustrative and not restrictive.

[0042] The Abstract of Disclosure is provided to comply with 37 CFR §1.72(b), which requires an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Moreover, it is apparent from this Detailed Description that, for the purpose of simplifying the disclosure, various features are grouped together in a single embodiment. This method of disclosure should not be interpreted as reflecting an intent that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims indicate, inventive subject matter resides in fewer than all of the features of a single disclosed embodiment.Therefore, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

[0043] References in the specification to "a single embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the circuit or method. The phrase "a single embodiment" in various places in this specification does not necessarily refer to the same embodiment.

[0044] In the foregoing specification, the claimed subject matter has been described with reference to specific exemplary embodiments thereof. It should be understood, however, that various changes may be made thereto without departing from the scope of the claimed subject matter as described in the appended claims. Accordingly, the specification and drawings are to be considered as illustrative and not restrictive.

Claims

[1] A device (200, 300) which includes: a reference generation circuit (210, 310) configured to generate a reference signal for a non-volatile memory (NVM) device (90), the reference generation circuit comprising: a first circuit (102) including at least one metal oxide semiconductor (MOS) capacitor (104), the first circuit (102) generating a first signal component of the reference signal, and a second circuit (202, 302) including at least one ferroelectric capacitor (204, 304), wherein the second circuit (202, 302) generates a second signal component of the reference signal, wherein the second signal component is temperature-dependent, wherein the first signal component generated by the first circuit (102) and the second signal component generated by the second circuit (202, 302) are programmable by a plurality of switches (106, 206, 306). [2] The device (200, 300) of claim 1, wherein the temperature dependence of the second signal component of the reference signal corresponds to temperature characteristics of the NVM device (90). [3] The device (200, 300) of claim 1, wherein the first (102) and second circuits (202, 302) are coupled in parallel and configured to generate the reference signal cumulatively. [4] The device (200) of claim 1, wherein the second circuit (202) comprises a ferroelectric capacitor group (220), the ferroelectric capacitor group (220) including the at least one ferroelectric capacitor (204) connected in parallel, and the second signal component is programmable by a plurality of switches (206). [5] The device (300) of claim 1, wherein the second circuit (302) comprises a plurality of ferroelectric capacitor groups (320), each of the ferroelectric capacitor groups (320) including the at least one ferroelectric capacitor (304) coupled in parallel, and wherein the ferroelectric capacitor groups (320) are each coupled in parallel with each other, and the second signal component is programmable by a plurality of switches (306). [6] The device (200, 300) of claim 1, wherein the NVM device (90) includes a ferroelectric random access memory (F-RAM) device comprising at least one ferroelectric storage capacitor (96). [7] The device (200, 300) of claim 6, wherein the F-RAM device (90) comprises a one-transistor-one-capacitor (1T-1C) configuration. [8] The device (200, 300) of claim 6, wherein one of the plurality of ferroelectric storage capacitors (96) of the F-RAM device (90) and the at least one ferroelectric capacitor (204, 304) of the second circuit (202, 302) comprise approximately the same size. [9] Device (200, 300) according to claim 1, wherein the first signal component of the reference signal is generated by charge sharing of the at least one MOS capacitor (104) and the second signal component is generated by charge sharing of the at least one ferroelectric capacitor (204, 304). [10] Device (200, 300) according to claim 6, wherein: the second signal component of the reference signal is configured to be approximately equal to a non-switching term signal (U-term signal) of the plurality of ferroelectric storage capacitors (96) of the F-RAM device (90) as a function of temperature; and the first signal component of the reference signal is configured to provide an approximately constant margin between the reference signal of the reference circuit (210, 310) and the U-term signal of the F-RAM device (96). [11] Device (200, 300) according to claim 1, wherein: an output of the first signal component of the reference signal is controlled by a first pass transistor (98), wherein a gate of the first pass transistor (98) is configured to be coupled to a read word line signal; and an output of the second signal component of the reference signal is controlled by a second pass transistor (108), wherein a gate of the second pass transistor (108) is configured to be coupled to a ferroelectric word line signal. [12] Device (200, 300) according to claim 1, wherein: an output signal of the NVM device (90) is configured to be coupled as a first input of a sense amplifier (120); and the reference signal comprises a sum of the first and second signal components and is configured to be coupled as a second input of the sense amplifier (120). [13] The device (200, 300) of claim 10, wherein the plurality of switches (106, 206, 306) are programmed to program a first set of the at least one MOS capacitor (104) to generate the first signal component by charge sharing and a second set of the at least one ferroelectric capacitor (204, 306) to generate the second signal component by charge sharing. [14] A procedure that includes: Providing a reference generation circuit (210, 310) comprising a first circuit (102) including at least one metal oxide semiconductor (MOS) capacitor (104) and a second circuit (202, 302) including at least one ferroelectric capacitor (204, 304); Parallel coupling of the first and second circuits (102, 202, 302); generating, by the first circuit (102), a first signal component by charge sharing; generating, by the second circuit (202, 302), a second signal component by charge sharing; Generating a reference signal by combining the first and second signal components, and coupling the reference signal as a first input to a sense amplifier (120); coupling a signal output of a non-volatile memory (NVM) device (90) as a second input to a sense amplifier (120); and Outputting, by the sense amplifier (120), a first data value of the NVM device (90) if the reference signal is greater than the signal output of the NVM device (90), and a second data value if the reference signal is smaller than the signal output of the NVM device (90) wherein the first signal component generated by the first circuit (102) and the second signal component generated by the second circuit (202, 302) are programmable by a plurality of switches (106, 206, 306). [15] The method of claim 14, wherein the NVM device (90) comprises a ferroelectric random access memory (F-RAM) device including a one-transistor-one-capacitor (1T-1C) configuration. [16] The method of claim 15, further comprising: Precharging the at least one MOS capacitor (104) and the at least one ferroelectric capacitor (204, 304) to a precharge voltage; Configuring, using a plurality of switches (106, 206, 306), the at least one MOS capacitor (104) and ferroelectric capacitor (204, 304) such that the second signal component is programmed to resemble a non-switching term signal (U-term signal) of the F-RAM (90) as a function of temperature, and the first signal component provides a relatively temperature-independent margin between the reference signal and the U-term signal; and Configure the precharge voltage size. [17] A system (400) comprising: a processing element (410); a memory section (402) comprising a plurality of ferroelectric one-transistor-one-capacitor (1T1C) random access memory (F-RAM) cells (406) arranged in rows and columns; a hybrid reference generating device (408) comprising: a metal oxide semiconductor (MOS) circuit (102) comprising at least one MOS capacitor (104), the MOS circuit (102) generating a first signal component of a reference signal that does not vary significantly as a function of temperature, and a ferroelectric circuit (202, 302) comprising at least one ferroelectric capacitor (204, 304), the ferroelectric circuit (202, 302) generating a second signal component of the reference signal that is temperature dependent; Bit lines, with 1T1C F-RAM cells of the same column sharing one of the bit lines; and a sense amplifier (414) coupled to the 1T1C F-RAM cells (406) via the bit lines, the sense amplifier (414) being configured to receive signal outputs of the 1T1C F-RAM cells (406) as a first input and the reference signal from the hybrid reference generation device (408) as a second input, wherein the first signal component generated by the MOS circuit (102) and the second signal component generated by the ferroelectric circuit (202, 302) are programmable by a plurality of switches (106, 206, 306). [18] The system (400) of claim 17, wherein the at least one ferroelectric capacitor (204, 304) of the ferroelectric circuit (202) is located in a peripheral region (404) of the memory section (402), and wherein the at least one ferroelectric capacitor (204, 304) is substantially identical to the ferroelectric storage capacitors (96) in the 1T1C F-RAM cells (406). [19] The system (400) of claim 17, wherein the at least one ferroelectric capacitor (204, 304) of the ferroelectric circuit (202, 302) is adjacent to the MOS circuit (102), and wherein the at least one ferroelectric capacitor (204, 304) replaces a portion of the at least one MOS capacitor (104) to preserve the die area.

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