Device for artificial neurons

Abstract

Device (1) for artificial neurons, comprising: a resistive memory cell (2) connected within an input circuit (3); wherein the input circuit (3) includes a neuron input (4) configured to receive neural input signals and a current source (5) for supplying a read current to the cell (2); wherein the input circuit (3) is further configured to be selectively configurable in response to a set of control signals defining alternating read and write phases of operation, and is further configured to supply the read current to the cell (2) during the read phase and to supply a programming current to the cell (2) to program the cell resistance upon receiving a neural input signal during the write phase, wherein the cell resistance is progressively changed from a first state to a second state in response to successive neural input signals; and an output circuit (12) having a neuron output (13) and a digital buffer (14) connected to the input circuit (3) and configured to receive a measurement signal as a function of the cell resistance, wherein the buffer (14) is configured to be functionally capable of storing, in response to the reading phase, a digital value dependent on the measurement signal such that a first value is buffered when the cell resistance has not reached the second state and a second value is buffered when the cell resistance has reached the second state, wherein the output circuit (12) is configured to provide a neural output signal at the neuron output (13) during the write phase when the second value is latched.

Description

BACKGROUND

[0001] The present invention relates generally to artificial neuron devices and, more particularly, to artificial neurons based on resistive memory cells.

[0002] Neuromorphic technology refers to computing systems inspired by biological architectures of the nervous system. Conventional computing systems rely on binary logic and sequential von Neumann architectures. While these systems are highly powerful at performing tasks such as numerical computations, the separation of external memory and processors results in energy-intensive data movement. Compared to the human brain, the conventional computational paradigm is highly inefficient in terms of energy consumption and space requirements. These problems have led to significant research efforts to understand the highly efficient computational paradigm of the human brain and to create artificial cognitive systems with unprecedented computing power.For example, the strategic intention is to develop “neuromorphic coprocessors” that can perform event-based computations in computationally intensive tasks such as “big data” analytics and real-world sensory applications.

[0003] Neurons, along with synapses, are fundamental computational units in the brain. A neuron can integrate the input signals it receives. In biological neurons, a thin lipid bilayer membrane is used to separate the electrical charge inside the cell from that outside. The membrane potential, which represents the stored neuron state, is progressively modified by the arrival of neuronal input signals. When the membrane potential exceeds a certain voltage threshold, the neuron "fires," producing an output signal known as an "action potential" or "spike," and then returning to its initial state. These spikes are transported across synapses to other neurons, which change their connection strength ("plasticity" or "synaptic weighting") as a result of neuronal activity.

[0004] The realization of efficient artificial neurons is fundamental to neuromorphic technology. Most previous proposals for artificial neurons rely on hybrid analog / digital VLSI circuits, requiring complex CMOS circuitry with a large number of transistors to emulate neural functionality. Resistive memory cells, such as phase-change memory (PCM) cells, have also been recognized as suitable candidates for the realization of neural hardware (see, for example, "The Ovonic Cognitive Computer - A new Paradigm," Ovshinsky, Proc. E / PCOS, 2004, and "Novel Applications Possibilities for Phase-Change Materials and Devices," Wright et al., Proc. E / PCOS, 2013). Resistive memory cells are programmable resistance devices based on the variable resistance characteristics of a volume of resistive material sandwiched between a pair of electrodes.These cells are memristors, meaning units that remember the history of the current that has flowed through them. A neural circuit based on Mott memristors was also proposed in "A Scalable Neuristor Built with Mott Memristors," Pickett et al., Natural Materials, 2013.

[0005] In the past, the focus of artificial neurons based on memristive units was solely on emulating the functionality of integrating and firing or emulating the shape of the biological action potential. Concrete realizations of efficient artificial neurons for operation in a neural network configuration remain challenging.

[0006] From US 2015 / 0 006 455 A1, a circuit for implementing an artificial neuron is known, comprising: an integrator for an input signal for generating a voltage signal; a signal generator connected to the output of the integrator and generating two output signals when the voltage reaches or exceeds a predetermined voltage, a first signal for an output pulse of the neuron and a second signal for a control pulse; a resistive memory having two terminals that change from a high to a low resistance state in a time following a statistical distribution specific to the memory, a first terminal being connected to the output of the integrator;a transistor connected to a zero-potential branch of a second terminal of the resistive memory and controlled by the second output signal so that, in the presence of a voltage pulse, the resistive memory changes from its high to its low resistance state to lower the voltage;

[0007] DE 11 2012 000 372 T5 discloses methods and devices for programming a phase-change memory cell (10). A bias signal (VBL) is applied to the cell. A measurement portion (m) of the bias signal has a profile that varies over time. A measurement (TM) dependent on the fulfillment of a predetermined condition is then performed. The predetermined condition depends on the cell current during the measurement portion (m) of the bias signal. A programming signal is generated depending on the measurement (TM), and the programming signal is applied to program the cell (10). SUMMARY

[0008] It is an object of the present invention to provide an improved device for artificial neurons and an improved neuromorphic system.

[0009] This problem is solved by the subject matter of main claim 1 and subordinate claim 12.

[0010] Preferred embodiments of the present invention are the subject of the subclaims.

[0011] According to at least one embodiment of the present invention, an artificial neuron device is provided. The device includes a resistive memory cell connected to an input circuit having a neuron input for receiving neural input signals, and a current source for supplying a read current to the cell. The input circuit is selectively configurable in response to a set of control signals, defining alternating read and write phases of operation, for supplying the read current to the cell during the read phase, and for supplying a programming current to the cell to program the cell resistance upon receiving a neural input signal during the write phase. The cell resistance is progressively changed from a first state to a second state in response to successive neural input signals.The device further includes an output circuit having a neuron output and a digital latch connected to the input circuit for receiving a measurement signal dependent on the cell resistance. The latch is operative to latch a digital value dependent on the measurement signal in response to the read phase. A first value is latched if the cell resistance has not reached the second state, and a second value is latched if the cell resistance has reached the second state. The output circuit is configured to provide a neural output signal at the neuron output during the write phase when the second value is latched.

[0012] The device embodying the invention provides efficient neuron implementations suitable for connectivity and operation in a neural network configuration. The neural circuitry enables a compact implementation, enabling high-density integration into neuromorphic networks. The configuration of the neural circuitry for the read and write phases of operation is controlled by one or more control signals. Such a control signal may be a simple periodic signal that can be easily generated, for example, from a system clock, and can be easily applied to multiple neural circuits for efficient global control of a multi-neural network.

[0013] In preferred embodiments of the neuron device, the input circuit is further configurable, in response to the neural output signal, to apply a reset current to the cell to reset the cell resistance to the first state. In these embodiments, the neural output signal, or "spike," is conveniently used to cause a cell reset during the write phase, so that the neuron returns to its initial state, ready for a new operating cycle.

[0014] The output circuit preferably includes a logic gate coupled between the latch and the neuron output, the logic gate being operable, in response to the write phase, to provide the neural output signal when the second value is latched. With this arrangement, the neural spike is readily synchronized to the write phase, thereby facilitating the connection between neurons in a synchronous arrangement, with the spike from one neuron providing a neural input signal synchronized to the write phase for the next neuron.

[0015] The input circuit may include at least one access unit connected between a first terminal of the cell and a reference terminal of the circuit to enable current flow through the cell in response to the read phase and the neural input signal. In preferred embodiments, the input circuit includes respective access units connected between the first terminal of the cell and the reference terminal to enable current flow, the neural input signal, and the neural output signal, through the cell in response to the read phase. The use of such access units in the neuron input circuit enables simple control of cell operation during the read and write phases.In preferred implementations, the current source is connected to a second terminal of the cell, and the input circuit includes a switch connected to the second terminal, the switch being operative to supply the programming current to the cell during the write phase. This provides a simple input circuit configuration, and simple output circuits for use with such arrangements are described below.

[0016] At least one further embodiment of the invention provides a neuromorphic system comprising a plurality of interconnected neurons, each comprising a neuron device according to an above embodiment and a control signal generator for generating the set of control signals supplied to at least a plurality of neurons in the system.

[0017] Embodiments of the invention will now be described in more detail by way of illustrative and non-limiting example with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE MULTIPLE DRAWING VIEWS Fig. Figure 1 is a schematic representation of the progressive crystallization in a phase change memory cell; Fig. 2 shows an artificial neuron device according to one or more embodiments of the invention; Fig. Figure 3 is a schematic timing diagram illustrating the operation of the device of Fig. 2 indicates; Fig. 4 shows an artificial neuron device according to one or more embodiments of the invention; Fig. Figure 5 is a schematic timing diagram illustrating the operation of the device of Fig. 4 indicates; Fig. 6 shows an implementation of a digital buffer for use in an artificial neuron device according to one or more embodiments of the invention; Fig. Figure 7 shows an implementation of a NOR gate for use in the artificial neuron device of Fig. 4; and Fig. Figure 8 is a schematic representation of a neuromorphic system based on neurons configured according to one or more embodiments of the invention. DETAILED DESCRIPTION

[0018] The embodiments to be described provide an artificial neuron device based on resistive memory cells. In the following examples, the resistive memory cell is a PCM cell. The variable resistance properties of PCM cells arise from heating a volume of chalcogenide material between the cell electrodes to change the relative proportions of a (high-resistance) amorphous phase and a (low-resistance) crystalline phase in the chalcogenide bulk. When a voltage less than a certain threshold switching voltage is applied to the cell across the electrodes, the current is so small that very few joules of heat are dissipated, and essentially no resulting phase change occurs in the cell bulk.However, when a programming (or "write") signal above the threshold voltage is applied, the cell resistance drops to a very low value during the pulse application through the phenomenon of electronic threshold switching. This allows a large current to flow, resulting in significant heat generation and a subsequent phase change. For a cell initially in the high-resistance state, applying a programming pulse of a specific input strength and duration, based on cell characteristics and circuit design, causes partial crystallization of the amorphous region, with a consequent reduction in cell resistance after programming.The cells exhibit an accumulation property, whereby by applying many such programming pulses, the resistance of the memory cell can be gradually reduced from its initial high-resistance state to a very low value. The cell resistance can be measured (or "read") at any time by applying a low-voltage signal to the electrodes and measuring the resulting current flow through the cell. The signal value for the read operation is low enough that the read operation does not disturb the programmed cell state.

[0019] The above process is in Fig. 1. This figure shows the evolution of the cell state in terms of the electrical conductivity (the inverse of the resistance) of the PCM cell as a function of the number of programming pulses. Fig. The cell shown in Figure 1 is a mushroom cell type, with a chalcogenide material such as GST (germanium antimony tellurium) sandwiched between a first "top" electrode and a second "bottom" electrode. The smaller bottom electrode acts as a heating element to heat a dome of amorphous chalcogenide within the otherwise crystalline material. The resistance is initially high (low conductivity) due to the presence of the high-resistance amorphous dome between the electrodes. Successive programming pulses cause partial crystallization of the amorphous volume, progressively reducing the cell resistance. After a certain number of pulses, the conductivity gradient rises steeply, causing the cell to switch to the low-resistance (high conductivity) state.The cell can be reset to its initial high-resistance state by applying a pulse of sufficient strength to melt the chalcogenide material near the bottom electrode. The high-resistance amorphous dome is then restored upon cooling.

[0020] Fig. Figure 2 is a schematic block diagram showing the structure of a first artificial neuron device 1 according to one or more embodiments of the invention. The neuron device 1 contains a PCM cell, represented by the variable resistor 2, which may be of the mushroom cell type, as indicated in the enlargement. The PCM cell 2 is connected within an input circuit 3. The input circuit 3 has a neuron input 4 for receiving neural input signals during operation. The neural input signals may be generated by one or more other circuits in a neuromorphic system in which the neuron 1 is connected. For example, output signals from other neurons may be supplied as input signals to the neuron 1, for example, via synaptic circuits. Signals representing external neural stimuli, e.g.Circuits that emulate sensory receptors can also be provided as neural input signals.

[0021] The input circuit 3 contains a current source 5 for supplying a constant read current I READto the PCM cell 2 during operation. The input circuit 3 is selectively configurable in response to a set of control signals defining alternating read and write (programming) phases of operation. These control signals are generated by a control signal generator indicated at 6, which may be provided external to the neuron 1 and may supply control signals to multiple neurons in a neuromorphic system. In general, the set of control signals may comprise one or more control signals, and the input circuit 3 may be selectively configurable in response to one or more of these signals. In this embodiment, the control signals include a read signal (READ) comprising a periodic train of rectangular pulses, as in Fig. 2. The read phase of neuron operation occurs when the read signal is HIGH. The write phase of neuron operation occurs during the period in which the read signal is LOW. In particular, in one or more embodiments, the control signals include a write signal (WRITE) having a periodic rectangular pulse train, and the write phase corresponds to the period in which this write signal is HIGH. This occurs during the period in which READ is LOW, with the READ and WRITE signals defining alternating read and write phases in operation. The control signal set for this embodiment also includes a READ signal, which is the negation of the READ signal.

[0022] The input circuit 3 further includes a set of access units to enable current flow through the PCM cell 2 during operation. One or more embodiments use three access units, here implemented by FETs (field effect transistors) 7, 8, and 9 connected between a first (here, the lower) terminal of the cell 2 and a reference terminal of the circuit, here a ground signal (i.e., mass). The gate of the first FET 7 receives the read signal READ and enables current flow through the cell 2 in response to the read phase. The gate of the second FET 8 is connected to the neuron input 4 and enables current flow through the cell 2 in response to neural input signals. The gate of the third FET 9 receives a neural output signal, or "spike," generated at an output of the neuron 1, as explained below, thereby enabling current flow through the cell 2 in response to this signal.The current source 5 is connected between a second (here the upper) terminal of the cell 2 and a first voltage supply line V. DD The input circuit also includes a switch 10 connected between the upper cell terminal and a second voltage supply line V DDA The switch 10 can be actuated in response to the control signal READ to apply a programming current to the cell during the write phase of operation when the access unit 8 or 9 is activated. In particular, the switch 10 closes when the control signal READ is HIGH, thereby connecting the cell 2 to the supply line V during this period and thus during the write phase. DDA connected when WRITE is HIGH. The voltage V DDA is usually higher than the voltage V DD to provide a high programming current that is sufficiently high for programming cell 2.

[0023] Neuron 1 additionally contains an output circuit designated 12. Output circuit 12 has a neuron output 13 and a digital latch 14. In this embodiment, latch 14 is connected to input circuit 3 via an inverter 15 to receive a measurement signal that depends on the cell resistance during operation. In particular, the measurement signal is supplied to a data input D of the latch. The read control signal READ is supplied to an enable input LE of the latch. The function of the latch is to latch a digital value that depends on the measurement signal when its enable input LE goes HIGH, i.e., in response to the read phase of the operation defined by READ = HIGH. The resulting latched value is provided at a latch output Q. When the latch enable input LE goes LOW, i.e.,READ = LOW, the latch output Q remains as it was when LE was last HIGH.

[0024] The output circuit 12 of this embodiment also includes a logic gate, here an AND gate 16, connected between the latch 14 and the neuron output 13. One input of the AND gate 16 is connected to the latch output Q, and the other input receives the write control signal WRITE. The AND gate 16 thus provides a neural output signal (spike) at the output 13 during the write phase (WRITE = HIGH), when the latch output Q is also HIGH. Neuronal spikes are thus easily synchronized with the write phase. If neural input signals originate from spikes of other, similar neurons in a network configuration, the input signals can be easily synchronized with the write phase in this way.

[0025] The various circuit components of neuron 1 can be implemented in a well-known manner, and the neuron device can be fabricated as an integrated nanoelectronic circuit using well-known materials processing techniques. For example, current source 5 can be implemented by a transistor, switch 10 can be realized by a transistor or a diode, and components 14 to 16 can be implemented using conventional transistor logic. The periodicity of control signals can be adjusted as desired based on cell characteristics and desired operating speeds. As an example, a typical signal period for the above circuit can be 200 to 500 ns.

[0026] In operation, during the read phase, when READ = HIGH, FET 7 is turned on and switch 10 is open. In this configuration, the read current I READsupplied from the current source 5 to the PCM cell 2. This read current is too small to change the PCM cell state as previously explained. The resulting voltage at the upper cell terminal, in Fig. 2 with V PCC depends on the resistance of the PCM cell. During the write phase, when WRITE = HIGH, switch 10 is closed, since READ is also HIGH. If a neural input signal is received at input 4 during this phase, FET 8 becomes conductive, and a programming current for programming the cell resistance is supplied to PCM cell 2. (A sufficiently large current for cell programming can be achieved by appropriately selecting the supply voltage V DDA and / or the properties of the access unit 8 and / or the properties of the neural input signal, as will be apparent to those skilled in the art.) In this way, the cell resistance can be progressively changed, as described with reference to Fig. 1, from a first (here high-impedance) state to a second (here low-impedance) state in response to successive neural input signals received during write phases of neuron operation. The voltage V PCC at the upper cell terminal during the read phase, which provides the measurement signal, changes from a HIGH value to a LOW value when the cell resistance changes. This signal is inverted by inverter 15, whose output thus changes from LOW to HIGH. In particular, when the cell resistance changes to the low-ohmic state, the voltage V PCC a given threshold V TH , and the inverted measurement signal at the inverter output changes from LOW to HIGH. Before this point (i.e., when the cell resistance has not reached the second, low-resistance state), in the reading phase V PCC > V TH, the D input of the latch 14 is LOW, and a first value, here logic 0, is held by the latch 14 during the read phase (READ = HIGH at the latch input LE). The latch output Q thus remains at logic 0. Subsequently, when the cell resistance has reached the second, low-resistance state, V PCC < V TH , the D input of latch 14 goes HIGH, and a second value, here a logic 1, is latched by latch 14 during this read phase. The latch output Q thus switches to logic 1. The latch output Q remains HIGH for the next write phase when WRITE goes HIGH. The AND gate 16 then generates a spike at neuron output 13 during this write phase.

[0027] From the above, it can be seen that the neuron output circuit 12 generates a peak at the output 13 during the write phase when a logic 1 is latched by the latch 14, i.e., when the cell resistance has reached the low-resistance state, as indicated by the measurement signal in the immediately preceding read phase. In this embodiment, the input circuit 3 is configurable in response to this peak to supply a reset current to the PCM cell 2 to reset the cell resistance to the high-resistance state. In particular, a peak generated at the neuron output 13 during a write phase is applied to the gate of the FET 9, thereby allowing a reset current to flow through the PCM cell 2 during this write phase. A sufficiently large reset current can be achieved here by appropriately selecting a value or a combination of properties of the access unit 9, the supply voltage V DDAand the neuron output signal properties (e.g., amplitude and / or duration), as will be apparent to those skilled in the art. PCM cell 2 is thus reset to its initial pre-accumulation state during the write phase in which neuron 1 fires.

[0028] As previously described, spikes generated when neuron 1 fires can be propagated to one or more other neurons in a network arrangement, providing input signals to those neurons. Spikes can be propagated via synaptic circuits that can modify spike properties (e.g., amplitude and / or duration) according to synaptic weighting. Synaptic circuits can be implemented in a variety of ways, and the synaptic implementation is formally independent of the operation of the neurons described herein. It is sufficient to recognize that neuronal input signals can vary in form, and their effect on programming cell resistance can vary accordingly.

[0029] The neuron operation described above is conveniently shown in the signal timing diagram of Fig. 3. The upper section (a) of this diagram shows an example WRITE signal as a pulse train with a period of 200 ns, which defines a write phase of 100 ns. Section (b) shows an example READ signal. Section (c) shows neural input signals applied to input 4 during the first and third write phases in the figure. Section (d) gives the voltage V PCC during the phases approaching and exceeding the firing threshold. In the first write phase (WRITE = HIGH), a neural input signal is received, and the cell resistance is reduced via the programming operation. In the next read phase (READ = HIGH), the cell resistance is still above the firing threshold (V PCC > V TH). During the second write phase, no input signal is received, and the cell resistance remains unchanged. In the third write phase, another input signal is received, and the cell resistance is further reduced. In the next read phase, the measured cell resistance has exceeded the trigger threshold (V PCC < V TH ), as highlighted by the circle in the figure. A spike is then generated at neuron output 13 during the fourth write phase, as indicated in section (e). This spike causes a cell reset, as described above, causing the measured cell resistance to return to its initial high-resistance state in the following read phase.

[0030] It can be seen that the above embodiment provides an efficient, fully functional neuron implementation for connectivity and operation in a neural network configuration. The device uses a hybrid of analog components (PCM cell, access units, current source, and switches) and digital components (latches, inverters, AND logic gates), all of which are typically very small. The circuit thus provides a very compact neuron implementation, enabling seamless, high-density integration into multi-neuron networks, for example, via high-density synaptic arrays. The control signals for controlling the circuit configuration are simple periodic signals. These can be applied globally in a multi-neuron system to synchronize neuron operations and can be easily generated from a system clock.

[0031] A second neuron device embodying the invention will be described with reference to the Fig. 4 and Fig. 5. The neuron structure is described in Fig. 4 and corresponds essentially to that of Fig. 2. Like elements are designated by like reference numerals, and only major differences will be described below. The neuron 20 of this embodiment has an input circuit 21 in which the read current source is implemented by a PMOS (P-type metal-oxide-semiconductor) transistor 22, the gate electrode of which is biased at V BIAS The switch between PCM cell 2 and the supply voltage V DDA is also implemented by a PMOS transistor 23. This transistor 23 receives the read control signal READ at its gate. Due to the PMOS operation, the transistor 23 is turned on when READ is LOW. The operation of the switch 23 is thus equivalent to that of the switch 10 in Fig. 2, but the inverted control signal READ is not required. In this embodiment, the control signal generator 24 generates two control signals READ and WRITE, where WRITE is the negation of the signal WRITE in Fig. 2. The reading phase is again defined by READ = HIGH, whereas the writing phase is defined by WRITE = LOW.

[0032] The output circuit 25 of the neuron 20 contains a latch 14 as before, but no inverter is required. The D input of the latch 14 is thus directly connected to the upper terminal of the PCM cell 2, and the latch output Q is Fig. 2 is inverted. The AND gate of Fig. 2 is replaced in the output circuit by a NOR gate 26. The second input of the NOR gate 26 receives the control signal WRITE, causing the gate 26 to generate a spike at the neuron output 13 (WRITE = LOW) in response to the write phase when logic 0 is latched by the latch 14. This occurs when the cell resistance is set to the low-ohmic state (V PCC < V TH ) has fallen.

[0033] The operation of neuron 20 is shown in the timing diagram of Fig. 5 for a series of neural input signals of varying duration. The input signal received here in the fourth write phase causes the cell to switch to the low-resistance state. In the following read phase, the measured cell resistance has reached the trigger threshold (V PCC < V TH) is exceeded. A spike is then generated at neuron output 13 during the next write phase. This spike causes the cell to reset, as described above, thereby returning the measured cell resistance to its initial high-impedance state in the following read phase.

[0034] Neuron 20 thus functions in general like Neuron 1, but the number of control signals is reduced due to the omission of the READ signal, and the circuit design is even more compact. For example, an implementation of Neuron 20 with only fifteen transistors can be achieved using a Fig. 6 shown minimalist buffer design and one in Fig. 7. An implementation of neuron 20 in the 14 nm technology node occupies an area of ​​less than 1 µm 2, and the power consumption of the logic circuit is less than 10% of that of PCM cell 2.

[0035] Fig.Figure 8 is a simple schematic diagram indicating how neurons 1, 20 may be connected in a neuromorphic system embodying the invention. The system 30 comprises a plurality of interconnected neurons, three of which are indicated as N1, N2, and N3. A control signal generator 31 generates a set of global control signals CS for controlling the configuration of the neural circuitry. This set of control signals is applied to at least a plurality of neurons N1, N2, N3, etc. in the system 30 and may be applied to all neurons in the system. The neurons are interconnected via an array of synapses S, arranged in rows and columns in the figure. The output 13 of each neuron provides an input to all synapses S in a respective column of the array. The input 4 of each neuron receives the outputs from all synapses in a corresponding row of the array.In this way, each synapse S is connected between a corresponding pair of neurons for relaying output signals from one neuron (the "pre-neuron") and the input of the other neuron (the "post-neuron"). As previously described, synapses can modify these signals according to synaptic weighting, and system 30 can include additional neuron / synapse connections (not shown) to allow adjustment of synaptic weights, e.g., based on relative temporal occurrence of pre- and post-neuron spikes. However, the details of synaptic operation are formally independent of the neuron functionality described herein.

[0036] Of course, numerous changes and modifications can be made to the embodiments described above. For example, control signals do not have to be rectangular pulse trains. Control pulses can, for example, be shaped with leading and / or trailing edges if this is desirable for the operation of the cell. Furthermore, separate read and write control signals are used to define the read and write phases in the above embodiments. This allows read and write phases to be separated in time by a time interval between them. Separating the phases in this way may be advantageous depending on the operating characteristics of the cell, particularly for fast operation. However, in other embodiments, alternating read and write phases could be defined by different values ​​of a single control signal.While in the above embodiments, the access unit 9 is used to provide a powerful cell reset mechanism, other reset mechanisms may be envisaged, e.g., via a global reset signal selectively applied to the cell in response to a spike event. The circuit configuration may be controlled in various other ways via different control signals, and other logic arrangements, e.g., using different logic gates and / or latch input / output arrangements, are also possible. Output circuits may also be envisaged in which the latch is directly connected to the neuron output. Input circuits, in some embodiments, may also use a single access unit that responds to more than one signal to enable current flow, e.g.,a FET that functions as more than one of the above-mentioned FETs 7 through 9. Input circuits can also be designed to operate with a single voltage supply line if necessary.

[0037] Neurons embodying the invention may, of course, use PCM cells other than the mushroom cell type, as well as other resistive memory cells. Examples include resistive RAM (RRAM) cells, such as conductive bridge RRAM cells, oxide or metal oxide RRAM cells, and carbon RRAM cells. Additionally, the above circuit examples have been described for operation in which the neuron fires, with the output signal being generated when the memory cell is in a low-resistance state, and the cell is then reset to a high-resistance state. During the accumulation phase, the cell resistance is thus gradually reduced by successive neuronal input signals.Other embodiments may rely on operation in which the neuron fires when the cell is in a high-resistance state, the cell is reset to a low-resistance state, and the cell resistance is progressively increased by successive neural input signals in the accumulation phase. Any resistive memory cell, possibly including bipolar devices in which the resistance can be progressively increased, may be used in such embodiments, one example being CBRAM (conductive bridge RAM) cells. Suitable circuit modifications to adapt to such cell operation will be readily apparent to those skilled in the art.

[0038] When a component is described herein as being connected to another component, such components may generally be connected directly or indirectly, e.g., via intervening components, unless otherwise stated.

[0039] The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limiting to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, practical application, or technical improvement over technologies commonly available in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

[1] Device (1) for artificial neurons, comprising: a resistive memory cell (2) connected within an input circuit (3); wherein the input circuit (3) includes a neuron input (4) configured to receive neural input signals and a current source (5) for supplying a read current to the cell (2); wherein the input circuit (3) is further configured to be selectively configurable in response to a set of control signals defining alternating read and write phases of operation, and is further configured to supply the read current to the cell (2) during the read phase and to supply a programming current to the cell (2) to program the cell resistance upon receiving a neural input signal during the write phase, wherein the cell resistance is progressively changed from a first state to a second state in response to successive neural input signals; and an output circuit (12) having a neuron output (13) and a digital buffer (14) connected to the input circuit (3) and configured to receive a measurement signal as a function of the cell resistance, wherein the buffer (14) is configured to be functionally capable of storing, in response to the reading phase, a digital value dependent on the measurement signal such that a first value is buffered when the cell resistance has not reached the second state and a second value is buffered when the cell resistance has reached the second state, wherein the output circuit (12) is configured to provide a neural output signal at the neuron output (13) during the write phase when the second value is latched. [2] The device (1) of claim 1, wherein the input circuit (3) is further configured to supply a reset current to the cell (2) in response to the neural output signal to reset the cell resistance to the first state. [3] The device (1) of claim 1 or 2, wherein the output circuit (12) includes a logic gate (16) connected between the latch (14) and the neuron output (13), the logic gate (16) being configured to be operative to provide the neural output signal in response to the write phase when the second value is latched. [4] Device (1) according to claim 3, wherein the input circuit (3) includes at least one access unit (7, 8, 9) connected between a first terminal of the cell (2) and a reference terminal of the circuit, the at least one access unit (7, 8, 9) being configured to enable a current flow through the cell (2) in response to the read phase and the neural input signal. [5] Device (1) according to claim 2, wherein the input circuit (3) includes respective access units (7, 8, 9) connected between a first terminal of the cell (2) and a reference terminal, the respective access units (7, 8, 9) being configured to enable current flow through the cell (2) in response to the read phase, the neural input signal and the neural output signal. [6] The device (1) of claim 4, wherein the current source (5) is connected to a second terminal of the cell (2) and the input circuit (3) comprises a switch (10) connected to the second terminal, the switch (10) being configured to be operatively capable of supplying the programming current to the cell (2) during the write phase. [7] The device (1) of claim 6, wherein the latch (14) is connected to the second terminal of the cell (2) and configured to receive the measurement signal, and wherein the output circuit (12) includes a NOR gate connected between the latch (14) and the neuron output (13) and configured to be operative to provide the neural output signal in response to the write phase when the second value is latched. [8] Device (1) according to claim 6, wherein the buffer (14) is connected to the second terminal of the cell (2) via an inverter (15) configured to provide the measurement signal, and wherein the output circuit (12) includes an AND gate (16) connected between the buffer (14) and the neuron output (13) and operative to provide the neural output signal in response to the write phase when the second value is buffered. [9] The device (1) of any one of claims 1 to 8, wherein the resistive memory cell (2) comprises a phase change memory cell, and wherein the cell resistance is progressively reduced between the first and second states in response to successive neural input signals. [10] Device (1) according to one of claims 1 to 9, wherein the set of control signals comprises a read signal and a write signal, each defining the alternating read and write phases. [11] Device (1) according to claim 5, wherein: the resistive memory cell (2) comprises a phase change memory cell and the cell resistance is progressively reduced between the first and second states in response to successive neural input signals; the current source (5) is connected to a second terminal of the cell (2), and the input circuit (3) includes a switch (10) connected to the second terminal, the switch (10) being configured to be operatively capable of supplying the programming current to the cell (2) during the write phase; the buffer (14) is connected to the second terminal of the cell (2) and configured to receive the measurement signal; and the output circuit (12) includes a NOR gate connected between the latch (14) and the neuron output (13) and configured to be operative to provide the neural output signal in response to the write phase when the second value is latched. [12] A neuromorphic system comprising a plurality of interconnected neurons, each comprising a device (1) according to any one of claims 1 to 11 and a control signal generator (6) configured to generate the set of control signals, the set of control signals being provided to at least a plurality of neurons in the system.

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