Double-side polishing process and double-side polishing device

Abstract

Double-sided polishing process, including: simultaneously polishing both surfaces of a semiconductor wafer (W) by holding the semiconductor wafer (W) in a carrier (8), inserting the held semiconductor wafer (W) between an upper turntable (2) and a lower turntable (3), to each of which a polishing pad (4, 5) is attached, and bringing both surfaces of the semiconductor wafer (W) into sliding contact with the polishing pads (4, 5), wherein the semiconductor wafer (W) is polished under a condition that a thickness A (mm) of the polishing pad (4) attached to the upper turntable (2) and a thickness B (mm) of the polishing pad (5) attached to the lower turntable (3) satisfy the relationships 1.0 ≤ A+B ≤ 2.0 and A / B > 1.0.

Description

TECHNICAL FIELD

[0001] The present invention relates to a double-side polishing method and a double-side polishing apparatus. [STATE OF THE ART]

[0002] Regarding the flatness required for semiconductor wafers, such as silicon wafers, the requirements for F-ZDD (Front Z-Height Double Differentiation), an evaluation indicator for a shape at the periphery of a semiconductor wafer, have recently increased. This is especially true for semiconductor wafers where F-ZDD < 0 is required, meaning that the semiconductor wafer shapes must have a sagging geometry at the periphery.

[0003] In a semiconductor wafer production process, the semiconductor wafer is usually subjected to double-side polishing. In double-side polishing, a semiconductor wafer is placed between polishing pads individually attached to upper and lower turntables, and the semiconductor wafer is subjected to sliding motion to simultaneously polish both the front and back surfaces (see, for example, Patent Literature 1). Double-side polishing is conventionally performed using upper and lower turntables to which similar polishing pads of the same thickness are attached. In this case, the F-ZDD can be made smaller than 0 by increasing the thickness of the polishing pads. LIST OF CITING PATENTS LITERATURE

[0004] Patent literature 1: JP 2014 - 223 704 A

[0005] JP 2016 - 22 542 A describes a double-side polishing device which comprises carriers for holding a wafer. SUMMARY OF THE INVENTION PROBLEM TO BE SOLVED BY THE INVENTION

[0006] On the other hand, there is still a demand for GBIR (Global BackSurface-Referenced Ideal Plane / Range = range of positive and negative deviation from a back-surface-referenced ideal plane for the entire surface), one of the evaluation indicators for the flatness of a semiconductor wafer, to be controlled at a lower value than before. This means that the GBIR must be equal to or less than a value also required by customers.

[0007] However, during double-sided polishing, if the thickness of the polishing pads is increased to control the F-ZDD to less than 0 as described above, the semiconductor wafer will have a convex shape, increasing the GBIR, and the GBIR will become larger than the required value. That is, there is a trade-off between the GBIR and the F-ZDD, and it has been difficult to meet both requirements.

[0008] The present invention was made in view of the problems described above. It is an object of the present invention to provide a double-side polishing method and a double-side polishing apparatus capable of obtaining a semiconductor wafer in which F-ZDD < 0 while controlling the GBIR value to be equal to or less than a required value. MEANS TO SOLVE THE PROBLEM

[0009] In order to achieve the above object, the present invention provides a double-side polishing method comprising: simultaneously polishing both surfaces of a semiconductor wafer by holding the semiconductor wafer in a carrier, inserting the held semiconductor wafer between an upper turntable and a lower turntable each having a polishing pad attached thereto, and bringing both surfaces of the semiconductor wafer into sliding contact with the polishing pads, wherein the semiconductor wafer is polished under a condition that a thickness A (mm) of the polishing pad attached to the upper turntable and a thickness B (mm) of the polishing pad attached to the lower turntable satisfy the relationships 1.0 ≤ A+B ≤ 2.0 and A / B > 1.0.

[0010] The present invention enables a semiconductor wafer after double-side polishing to have a sufficiently small GBIR by controlling the sum (A+B) of the thicknesses of the polishing pads attached to the upper and lower turntables, and enables a semiconductor wafer after double-side polishing to have an F-ZDD controlled to an optional negative value by optimizing the ratio (A / B) of the thicknesses of the polishing pads on the upper and lower turntables. That is, the present invention makes it possible to control the F-ZDD of a semiconductor wafer after double-side polishing to an optional and appropriate negative value less than 0 while keeping the GBIR sufficiently small.

[0011] In the inventive double-side polishing method, it is preferable that the semiconductor wafer is polished under a condition that the thickness A (mm) of the polishing pad attached to the upper turntable and the thickness B (mm) of the polishing pad attached to the lower turntable further satisfy a relationship of 1.5 ≤ A / B ≤ 2.5.

[0012] As described above, when 1.5 ≤ A / B is satisfied, it becomes safer to control the F-ZDD of a semiconductor wafer after double-side polishing to a negative value. When A / B ≤ 2.5, the polishing pad mounted on a lower turntable is fixed to have sufficient thickness and prevent cracking during double-side polishing.

[0013] It is preferable that the polishing pad attached to each of the upper turntable and the lower turntable has a Shore A hardness of 85 or more and 95 or less.

[0014] If the polishing pads mounted on the upper and lower turntables each have a Shore A hardness of 85 or higher, it is possible to more accurately control the GBIR and F-ZDD. If the polishing pads each have a Shore A hardness of 95 or lower, it is difficult to cause scratches on a semiconductor wafer.

[0015] It is preferable that the thickness B of the polishing pad attached to the lower turntable is 0.3 mm or more.

[0016] The polishing pad attached to the lower turntable with a thickness B of 0.3 mm or more is preferable because it avoids the polishing pad from causing a strength problem.

[0017] To achieve the above object, the present invention further provides a double-side polishing apparatus comprising: an upper turntable and a lower turntable each having a polishing pad attached thereto, and a carrier having a holding hole formed therein for holding a semiconductor wafer between the upper turntable and the lower turntable, where a thickness A (mm) of the polishing pad attached to the upper turntable and a thickness B (mm) of the polishing pad attached to the lower turntable satisfy relationships of 1.0 ≤ A+B ≤ 2.0 and A / B > 1.0.

[0018] The above-described double-side polishing apparatus enables a semiconductor wafer after double-side polishing to have a GBIR that is sufficiently small because the sum (A+B) of the thicknesses of the polishing pads attached to the upper and lower turntables is optimized, and further enables the semiconductor wafer after double-side polishing to have an F-ZDD that is controlled to an appropriate negative value because the ratio (A / B) of the thicknesses of the polishing pads attached to the upper and lower turntables is optimized.

[0019] The inventive double-side polishing apparatus is preferably an apparatus in which the thickness A (mm) of the polishing pad attached to the upper turntable and the thickness B (mm) of the polishing pad attached to the lower turntable further satisfy a relationship of 1.5 ≤ A / B ≤ 2.5.

[0020] The inventive double-side polishing apparatus, in which the upper and lower polishing pads satisfy 1.5 ≤ A / B, enables the F-ZDD of a semiconductor wafer after double-side polishing to be reliably controlled to a value less than 0. The polishing pad attached to a lower turntable is sufficiently thick due to A / B ≤ 2.5 and is reliably prevented from cracking during double-side polishing.

[0021] It is preferable that the polishing pad attached to each of the upper turntable and the lower turntable has a Shore A hardness of 85 or more and 95 or less.

[0022] The inventive double-side polishing apparatus enables more precise control of GBIR and F-ZDD when the polishing pads mounted on an upper turntable and a lower turntable each have a Shore A hardness of 85 or more. When the polishing pads each have a Shore A hardness of 95 or less, it is difficult to cause scratches on a semiconductor wafer.

[0023] It is preferable that the thickness B of the polishing pad attached to the lower turntable is 0.3 mm or more.

[0024] The polishing pad fixed on the lower turntable with a thickness B of 0.3 mm or more is preferable because it avoids the polishing pad from causing a strength problem. EFFECT OF THE INVENTION

[0025] The inventive double-side polishing method and apparatus enable double-side polishing to achieve a semiconductor wafer with F-ZDD < 0 while controlling the GBIR value to be equal to or smaller than a required value. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram showing an example of a double-side polishing apparatus of the present invention; Fig. Figure 2 is a graph to show the GBIR and F-ZDD measured in Examples 1-3 and Comparative Examples 1-3. DESCRIPTION OF EMBODIMENTS

[0026] With respect to the present invention, the embodiments will be described below, but the present invention is not limited thereto.

[0027] As described above, in current techniques, polishing pads must be thickened to control a semiconductor wafer to an F-ZDD of less than 0 after double-side polishing. However, thickening the polishing pads leads to an increase in the GBIR of a semiconductor wafer undergoing double-side polishing. Accordingly, it has been difficult to control the F-ZDD to less than 0 while controlling the GBIR to a value equal to or lower than a customer's required value.

[0028] The present inventors have worked extensively to solve such a problem. Consequently, the present inventors have found that the GBIR and the F-ZDD can be controlled by the sum (A+B) and the ratio (A / B) of the thickness A (mm) of a polishing pad attached to the upper turntable and the thickness B (mm) of a polishing pad attached to the lower turntable, respectively, thereby optimizing this sum and ratio to complete the present invention.

[0029] First, the inventive double-side polishing device will be described with reference to Fig. 1. As described in Fig.1, the inventive double-side polishing apparatus 1 includes an upper turntable 2 and a lower turntable 3 arranged vertically facing each other. An upper polishing pad 4 and a lower polishing pad 5 are fixed to the upper turntable 2 and the lower turntable 3, respectively. A carrier 8 having a holding hole formed therein for holding a semiconductor wafer W is arranged between the upper turntable 2 and the lower turntable 3. When the semiconductor wafer W is double-sided polished, the semiconductor wafer W is held in the holding hole of the carrier 8 and inserted between the upper turntable 2 and the lower turntable 3. A sun gear 6 is provided midway between the upper turntable 2 and the lower turntable 3, and an internal gear 7 is provided at a peripheral portion therebetween.

[0030] Some teeth of the sun gear 6 and the internal gear 7 mesh with the corresponding outer peripheral teeth of the carrier 8. The sun gear 6 and the internal gear 7 are driven to rotate with the upper turntable 2 and the lower turntable 3. As a result, the carrier 8 rotates the sun gear 6. The inventive double-side polishing apparatus 1 can thus be a four-way double-side polishing apparatus in which the upper turntable 2, the lower turntable 3, the sun gear 6, and the internal gear 7 are respectively driven. In this case, the semiconductor wafer W is held in the holding hole of the carrier 8, and its two surfaces are simultaneously polished with the upper polishing pad 4 and the lower polishing pad 5. During double-side polishing, a polishing agent is supplied.

[0031] In the inventive double-side polishing apparatus 1, the thickness A (mm) of the upper polishing pad 4 on the upper turntable 2 and the thickness B (mm) of the lower polishing pad 5 on the lower turntable 3 satisfy the relationships 1.0 ≤ A+B ≤ 2.0 and A / B > 1.0. The inventive double-side polishing apparatus 1 using polishing pads in which the thickness of the upper polishing pad and the thickness of the lower polishing pad are different from each other is capable of controlling the GBIR and the F-ZDD by the value of A+B and the value of A / B, respectively. When the value of A+B and the value of A / B are each within the above-described range, it is possible to control the F-ZDD to an optional and appropriate negative value while controlling the GBIR to be sufficiently small.

[0032] When A+B > 2.0, the GBIR increases excessively. On the other hand, when A+B < 1.0, the value of B becomes too small, which means that the lower polishing pad 5 becomes too thin, causing cracking of the lower polishing pad 5 during double-sided polishing. When A / B ≤ 1.0, it becomes impossible to achieve F-ZDD < 0.

[0033] In the inventive double-side polishing apparatus 1, the thickness A (mm) of the upper polishing pad 4 fixed to the upper turntable 2 and the thickness B (mm) of the lower polishing pad 5 fixed to the lower turntable 3 preferably satisfy the relationship 1.5≤A / B≤2.5. When 1.5≤A / B, it becomes more secure to realize F-ZDD<0. When A / B≤2.5, the lower polishing pad 5 is ensured to have a sufficient thickness, thereby being securely protected from cracking caused during double-side polishing. The thickness B of the lower polishing pad 5 fixed to the lower turntable is preferably 0.3 mm or more, that is, B≥0.3. The lower polishing pad 5 having a thickness B of 0.3 mm or more is preferable because it prevents the polishing pad from causing a strength problem.

[0034] The upper and lower polishing pads 4 and 5, which are attached to the upper and lower turntables 2 and 3, respectively, preferably each have a Shore A hardness of 85 or more and 95 or less. When the Shore A hardness of the polishing pads 4 and 5 is 85 or more, GBIR and F-ZDD can be more accurately controlled. When the Shore A hardness of the polishing pads 4 and 5 is 95 or less, it is difficult to cause scratches on the semiconductor wafer. For example, foamed polyurethane pads can be used as the polishing pads 4 and 5.

[0035] The carrier 8 for holding the semiconductor wafer W can be made of a material such as metal or metal with any coating. The holding hole of the carrier 8 can be provided with a resin insert on the inner circumference.

[0036] The polishing agent added during double-sided polishing can, for example, be an aqueous inorganic alkaline solution containing colloidal silica.

[0037] The inventive double-side polishing method using the double-side polishing apparatus 1 described above will be described below.

[0038] In the double-side polishing method of the present invention, both surfaces of a semiconductor wafer W are simultaneously polished by inserting the semiconductor wafer W held in the carrier 8 between the upper turntable 2 and the lower turntable 3 having polishing pads 4 and 5 attached thereto, and bringing both surfaces of the semiconductor wafer W into sliding contact with the polishing pads 4 and 5. In this case, polishing is performed under a condition that the thickness A (mm) of the upper polishing pad 4 and the thickness B (mm) of the lower polishing pad 5 satisfy the relationships 1.0 ≤ A+B ≤ 2.0 and A / B > 1.0.

[0039] The F-ZDD can be controlled to an optional and appropriate negative value while controlling the GBIR to be small by using polishing pads in which the thickness of the upper polishing pad and the thickness of the lower polishing pad are different from each other as described above, controlling the GBIR and the F-ZDDD by the value of A+B and the value of A / B, respectively, and polishing under a condition that the value of A+B and the value of A / B are within the ranges described above.

[0040] Polishing is preferably performed under a condition that A and B satisfy the relationship of 1.5≤A / B≤2.5. When 1.5≤A / B, it becomes more secure to realize F-ZDD<0. When A / B≤2.5, it is ensured that the lower polishing pad 5 has a sufficient thickness, thereby securely preventing cracking caused by double-side polishing. The thickness B of the lower polishing pad 5 fixed to the lower turntable is preferably 0.3 mm or more, that is, B≥0.3. The lower polishing pad 5 having a thickness B of 0.3 mm or more is preferable because it prevents the polishing pad from causing a strength problem.

[0041] As the upper and lower polishing pads 4 and 5 attached to the upper and lower turntables 2 and 3, respectively, it is preferable to use one having a Shore A hardness of 85 or more and 95 or less. When the Shore A hardness of the polishing pads 4 and 5 is 85 or more, GBIR and F-ZDD can be more accurately controlled. When the Shore A hardness of the polishing pads 4 and 5 is 95 or less, it is difficult to cause a scratch on the semiconductor wafer. EXAMPLE

[0042] Hereinafter, the present invention will be described in more detail by showing examples and comparative examples, but the present invention is not limited to these examples. (Example 1)

[0043] Using the double-side polishing device 1 as shown in Fig.As shown in Figure 1, five silicon wafers with a diameter of 300 mm were polished according to the double-side polishing method of the present invention. Each silicon wafer was subjected to SC-1 cleaning after double-side polishing and subsequent flatness evaluation. [Conditions for double-sided polishing]

[0044] In this case, DSP-20B (from Fujikoshi Machinery Corp.) was used as a double-side polishing device, with the thickness A of the upper polishing pad being 1.40 mm and the thickness B of the lower polishing pad being 0.60 mm, that is, A+B = 2.00 (mm) and A / B = 2.33. The material of the polishing pad was foamed polyurethane with a Shore A hardness of 90.

[0045] The support was made of a titanium substrate. The retaining hole was provided with an insert on the inner circumference. The insert material was FRP (fiber-reinforced plastic), in which glass fibers were impregnated with an epoxy resin. A KOH-based polishing compound containing silica abrasive grains was used. The average particle diameter of the silica abrasive grains was 35 nm, the abrasive grain concentration was 1.0 mass%, and the pH of the polishing compound was 10.5.

[0046] The polishing load was set to 150 gf / cm 2 The polishing time was set to a time after which the silicon wafer had the same thickness as the carrier. The speed of each drive part was set as follows: upper turntable: -13.4 rpm, lower turntable: 35 rpm, sun gear: 25 rpm, and internal gear: 7 rpm.

[0047] The dressing of the upper and lower polishing pads was carried out by bringing a dressing plate, on which diamond abrasive grains were electroplated, into sliding contact with the upper and lower polishing pads under flowing pure water. [Cleaning condition]

[0048] For SC-1 cleaning of a silicon wafer subjected to double-sided polishing, a cleaning agent in the mixing ratio NH4OH:H2O2:H2O = 1:1:15 was used. [Conditions for assessing flatness]

[0049] Flatness was determined by measuring GBIR and F-ZDD using Wafer Sight (manufactured by KLA-Tencor Co., Ltd.). When calculating F-ZDD, a zone of the M49 mode (aka: Polar Sites) was set to 30 mm long (2 mm EE) of 72 sectors, and the average value of each angle was adopted at 148 mm.

[0050] Regarding the five silicon wafers subjected to double-side polishing in Example 1, the mean value of GBIR and the mean value of F-ZDD in Fig. 2. In Fig. 2, the GBIR is represented by a relative value based on a value requested by the customer, i.e. a relative value when the required value is set to 1.

[0051] As from Fig. As can be seen from Figure 2 and Table 1, Example 1 achieved a relative GBIR value of 0.90, which was the required value and lower than the GBIR values in Comparative Examples 1 and 2 using prior techniques described later. In Example 1, silicon wafers with good flatness were obtained. Furthermore, it was found that the F-ZDD was -7.4 (nm / mm 2 ) and becomes less than 0. [Table 1] A [mm] B [mm] A+B AWAY F-ZDD [nm / mm 2 ] GBIR Comparison example 1 1.20 1.20 2.40 1.00 1.0 1.15 Comparison example 1 1.50 1.00 2.50 1.50 -6.4 1.40 Comparison example 1 0.50 0.50 1.00 1.00 3.5 0.50 Example 1 1.40 0.60 2.00 2.33 -7.4 0.90 Example 2 1.20 0.65 1.85 1.85 -4.0 0.73 Example 3 0.60 0.40 1.00 1.50 -1.1 0.40 (Example 2)

[0052] Double-sided polishing was performed under the same conditions as in Example 1, except that the thickness of the upper polishing pad was 1.20 mm and the thickness of the lower polishing pad was 0.65 mm. Flatness was evaluated by the same method as in Example 1. That is, the double-sided polishing in Example 2 was performed under the conditions of A+B = 1.85 and A / B = 1.85.

[0053] As from Fig. As shown in Figure 2 and Table 1, Example 2 achieved a relative GBIR value of 0.73, which met the required value, and was lower than the GBIR values in Comparative Examples 1 and 2 using the prior techniques described later. In Example 2, silicon wafers with good flatness were obtained. Furthermore, the F-ZDD was found to be -4.0 (nm / mm2), which is less than 0. (Example 3)

[0054] Double-sided polishing was performed under the same conditions as in Example 1, except that the thickness of the upper polishing pad was 0.60 mm and the thickness of the lower polishing pad was 0.40 mm. Flatness was evaluated by the same method as in Example 1. That is, the double-sided polishing in Example 2 was performed under the conditions of A+B = 1.00 and A / B = 1.50.

[0055] As from Fig. As can be seen from Figure 2 and Table 1, in Example 3, a relative GBIR value of 0.40 was achieved, which met the required value and was lower than the GBIR values in Comparative Examples 1-3 using the prior techniques described later. In Example 3, silicon wafers with good flatness were thus obtained. Furthermore, the F-ZDD was found to be -1.1 (nm / mm2), which is less than 0. (Comparison example 1)

[0056] Double-sided polishing was performed under the same conditions as in Example 1, except that the thickness of both the upper polishing pad and the lower polishing pad was 1.20 mm. Flatness was evaluated by the same method as in Example 1. That is, in Comparative Example 1, double-sided polishing was performed under the conditions of A+B = 2.4 > 2.0 and A / B = 1.0.

[0057] These results are in Fig. 2 and Table 1. As can be seen from Fig. 2 and Table 1, the F-ZDD was 1.0 (nm / mm 2 ) and became 0 or more. When A / B ≤ 1.0, the GBIR exceeded the required value. The GBIR became 1.15, thus exceeding the required value. It was confirmed that when A+B > 2.0, the GBIR increased and the flatness deteriorated. (Comparison example 2)

[0058] Double-sided polishing was performed under the same conditions as in Example 1, except that the thickness of the upper polishing pad was 1.50 mm and the thickness of the lower polishing pad was 1.00 mm. Flatness was evaluated by the same method as in Example 1. That is, in Comparative Example 2, double-sided polishing was performed under the conditions of A+B = 2.50 and A / B = 1.50.

[0059] As from Fig. As can be seen from Figure 2 and Table 1, the GBIR resulted in 1.40, exceeding the required value. The GBIR exceeded the required value when A+B > 2.0. (Comparison example 3)

[0060] Double-sided polishing was performed under the same conditions as in Example 1, except that both the thicknesses of the upper and lower polishing pads were 0.50 mm. Flatness was evaluated by the same method as in Example 1. That is, the double-sided polishing in Comparative Example 2 was performed under the conditions of A+B = 1.00 and A / B = 1.00.

[0061] As from Fig. 2 and Table 1, the F-ZDD was 3.5 (nm / mm 2 ) and became 0 or more. The GBIR exceeded the required value at A / B ≤ 1.0.

[0062] From the results of Examples 1-3 and Comparative Examples 1-3 described above, it was confirmed that silicon wafers meeting the required GBIR and F-ZDD < 0 were obtained using the double-side polishing method or the double-side polishing apparatus of the present invention. It should be noted that double-side polishing under the conditions of A+B < 1.0 resulted in breakage of the lower polishing pad during processing because the thickness of the lower polishing pad was too thin, and thus double-side polishing could not be completed.

Claims

[1] Double-sided polishing process, comprising: simultaneously polishing both surfaces of a semiconductor wafer (W) by holding the semiconductor wafer (W) in a carrier (8), inserting the held semiconductor wafer (W) between an upper turntable (2) and a lower turntable (3), to each of which a polishing pad (4, 5) is attached, and bringing both surfaces of the semiconductor wafer (W) into sliding contact with the polishing pads (4, 5), wherein the semiconductor wafer (W) is polished under a condition that a thickness A (mm) of the polishing pad (4) attached to the upper turntable (2) and a thickness B (mm) of the polishing pad (5) attached to the lower turntable (3) satisfy the relationships 1.0 ≤ A+B ≤ 2.0 and A / B > 1.

0. [2] The double-side polishing method according to claim 1, wherein the semiconductor wafer (W) is polished under a condition that the thickness A (mm) of the polishing pad (4) attached to the upper turntable (2) and the thickness B (mm) of the polishing pad (5) attached to the lower turntable (3) further satisfy a relationship of 1.5 ≤ A / B ≤ 2.

5. [3] The double-side polishing method according to claim 1 or 2, wherein the polishing pad (4, 5) attached to each of the upper turntable (2) and the lower turntable (3) has a Shore A hardness of 85 or more and 95 or less. [4] The double-side polishing method according to any one of claims 1 to 3, wherein the thickness B of the polishing pad (5) attached to the lower turntable (3) is 0.3 mm or more. [5] A double-side polishing apparatus (1) comprising: an upper turntable (2) and a lower turntable (3), each having a polishing pad (4, 5) attached thereto, and a carrier (8) having a holding hole formed therein for holding a semiconductor wafer (W) between the upper turntable (2) and the lower turntable (3), wherein a thickness A (mm) of the polishing pad (4) attached to the upper turntable (2) and a thickness B (mm) of the polishing pad (5) attached to the lower turntable (3) satisfy relationships of 1.0 ≤ A + B ≤ 2.0 and A / B > 1.

0. [6] The double-side polishing apparatus (1) according to claim 5, wherein the thickness A (mm) of the polishing pad (4) attached to the upper turntable (2) and the thickness B (mm) of the polishing pad (5) attached to the lower turntable (5) further satisfy a relationship of 1.5 ≤ A / B ≤ 2.

5. [7] Double-side polishing device (1) according to claim 5 or 6, wherein the polishing pad (4, 5) attached to each of the upper turntable (2) and the lower turntable (3) has a Shore A hardness of 85 or more and 95 or less. [8] Double-side polishing apparatus (1) according to any one of claims 5 to 7, wherein the thickness B of the polishing pad (5) attached to the lower turntable (3) is 0.3 mm or more.

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