Integrated circuit assemblies with an optical redistribution layer

Abstract

A component (100) formed into an assembly, comprising the following: a substrate (101) having a structured surface with an optical contact area (102); an optical redistribution layer feature (oRDL feature) (138); a lining (139) that encloses the oRDL feature; and a build-up material (110, 130) extending over the structured surface of the substrate (101) and around sections of the oRDL feature (138), wherein the oRDL feature (138) extends through an opening in an outer surface of the build-up material (110, 130) and forms a pin extending from the outer surface to an outside of the component (100) formed into the assembly.

Description

CLAIMING PRIORITY

[0001] This application claims priority over US patent application No. 15 / 089524 entitled “INTEGRATED CIRCUIT PACKAGES INCLUDING AN OPTICAL REDISTRIBUTION LAYER”, which was filed on April 2, 2016 and is incorporated herein in its entirety by reference. BACKGROUND

[0002] The assembly of an IC chip or IC semiconductor wafer often involves the partial fabrication of electrically isolated interconnect features by forming structured layers of metal and structured layers of electrically insulating or dielectric material (which may be referred to as the buildup or buildup material). The interconnect features can provide pathways for electrically conductive contact points on the chip that are to be electrically connected to an external interface of the assembly containing the fabricated IC chip. The interconnect features can also relocate points of electrical connection from positions above or above certain areas of the IC chip (e.g., contact points that may be located in central or densely packed regions of the IC chip) to positions scaled for the electrical interface of the assembly.The interconnection characteristics can therefore be referred to as electrical redistribution layer (eRDL) characteristics.

[0003] US patent 2015 / 0349019 A1 discloses a method for manufacturing an image sensor using multiple insulating films. The method involves creating openings in the insulating films. Filler elements are used for these openings.

[0004] US patent 2012 / 0 199 893 A1 describes a method for manufacturing an image acquisition device. The method uses a photoelectric conversion section arranged on a semiconductor substrate, two insulating layers, and a waveguide.

[0005] Bakir, MS [ua]: Dual-Mode Electrical-Optical Flip-Chip I / O Interconnects and a Compatible Probe Substrate for Wafer-Level Testing. In: Electronic Components and Technology Conference, 2006, 768 - 775 describes a cost-effective compatible electrical and optical flip-chip I / O interconnect to meet the performance requirements of future high-performance chips.

[0006] US Patent 2010 / 0314704A1 describes a solid-state imaging device comprising a light-receiving unit formed in a semiconductor base and configured to perform a photoelectric conversion; an insulating layer arranged on the semiconductor base; a film which, together with the insulating layer, forms a sheathing of a waveguide and is formed by coating in an outer part of the interior of a hole, the hole being formed in the insulating layer above the light-receiving unit; a core of the waveguide, the core being made of a material with a higher refractive index than a material for the insulating layer and a material for the film formed by coating, and the core being formed in an inner part of the interior of the hole;and an inner lens integrated with the waveguide, wherein the inner lens has a lens surface formed at the bottom of the hole at the interface between the film formed by coating and the core. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The material described herein is presented in the accompanying figures as an example and is not exhaustive. For the sake of simplicity and clarity, the elements shown in the figures are not necessarily to scale. For example, the dimensions of some elements may be exaggerated relative to others for clarity. Furthermore, where appropriate, reference symbols have been repeated in the figures to indicate corresponding or analogous elements; they show: Fig. 1 a cross-sectional view of a component formed into an assembly according to some embodiments, which includes an optical redistribution layer feature (RDL feature); Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E, Fig. 2F, Fig. 2G, Fig. 2H, Fig. 2I, Fig. 2 years Fig. 2K, Fig. 2L and Fig. 2M cross-sectional views of components formed into an assembly that include an optical RDL feature while a method for manufacturing the component formed into an assembly is carried out, and show flowcharts for a method for manufacturing a component formed into an assembly that includes an optical RDL feature, according to some embodiments; Fig. 3 a cross-sectional view of a component formed into an assembly which includes an optical RDL feature, according to some embodiments; Fig. 4 a cross-sectional view of a component formed into an assembly which includes an optical RDL feature which is connected both electrically and optically to a printed circuit board component (PCB component), according to some embodiments; Fig. 5 and Fig. 6 Cross-sectional views of assemblies integrating components formed into the assembly with optical RDL features, and show top views of the assemblies according to some embodiments; Fig. 7 a mobile computing platform and a data server machine that use an assembly with an optical RDL feature, according to some embodiments; and Fig. 8 A functional block diagram of an electronic computing device according to some embodiments. DETAILED DESCRIPTION

[0008] One or more embodiments are described with reference to the accompanying figures. Although certain configurations and arrangements are shown and discussed in detail, it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements are possible without departing from the concept and scope of the description. It will be obvious to those skilled in the art that the techniques and / or arrangements described herein can also be used in a variety of other systems and applications that differ from those described in detail herein.

[0009] The following detailed description refers to the accompanying drawings, which form part of this document and show exemplary embodiments. Furthermore, it should be understood that other embodiments may be used and that structural and / or logical modifications may be made without deviating from the scope of the claimed subject matter. It should also be noted that directions and references such as upward, downward, above, below, and so on may only be used to simplify the description of the features in the drawings and are not intended to restrict the application of the claimed subject matter. Terms such as "upper (r / s)" and "lower (r / s)," "above" and "below" may be understood as referring to the XZ coordinates shown, and terms such as "adjacent" may be understood as referring to XY coordinates or to non-Z coordinates.Therefore, the following detailed description should not be understood in a restrictive sense, and the scope of the claimed subject matter is defined only by the attached claims and their equivalents.

[0010] Numerous details are set forth in the following description. However, it will be obvious to those skilled in the art that various embodiments discussed herein can be implemented without these specific details. In some cases, well-known methods and devices are shown not in detail but in block diagram form to prevent confusion regarding the embodiments. References to "an embodiment" in this description mean that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the phrase "in an embodiment" appearing at different points throughout this description does not necessarily refer to the same embodiment.Furthermore, the specified features, structures, functions, or characteristics can be combined in any suitable way in one or more embodiments. For example, a first embodiment can be combined with a second embodiment wherever the specified features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0011] As used in the description and the attached claims, the singular forms "ein / e / r" and "der / die / das" are intended to include the plural forms as well, unless the context indicates otherwise. It should be noted that the term "and / or" as used herein also refers to and encompasses any and all possible combinations of one or more associated listed elements.

[0012] As used throughout the description, a list of items joined by the phrase "at least one" or "one or more" can mean any combination of the listed items. For example, the phrase "at least one of A, B, or C" can mean: A; B; C; A and B; A and C; B and C; or A, B, and C.

[0013] The terms “coupled” and “connected,” along with their derivatives, may be used herein to describe functional or structural relationships between components. It should be noted that these terms are not intended to be synonymous. Rather, in certain embodiments, “connected” may be used to indicate that two or more elements are directly, physically, optically, or electrically connected. “Coupled” may be used to indicate that two or more elements are either directly or indirectly (with other intervening elements between them) physically, optically, electrically, or electromagnetically connected, and / or that two or more elements cooperate or interact with each other (e.g., in a cause-and-effect relationship).

[0014] The terms “above,” “below,” “between,” and “on,” as used herein, refer to a relative position of a component or material with respect to other components or materials when such physical relationships are significant. For example, in the context of materials, a material positioned above or below another material may be in direct contact with the other material and / or with one or more materials in between. Similarly, a material positioned between two materials may be in direct contact with the two materials and / or with one or more materials in between. In contrast, a first material “on top” of a second material is in direct contact with that second material. Similar distinctions should be made in the context of component arrangements.

[0015] This document describes components assembled into a module that exhibit optical redistribution layer features. Some manufacturing instructions may be partially directed toward the fabrication of IC chips that have optical features within and / or on top of a substrate. Optical features may include optical devices such as optical converters, light-emitting diodes (LEDs), laser diodes, photovoltaic cells, optical amplifiers, optical detectors, optical modulators, and / or parts of such devices.

[0016] In some embodiments discussed below, a chip assembly method creates optically transparent interconnect features by forming layers of an optically transparent material and layers of a build-up material (which may include a dielectric material). The optically transparent interconnect features provide pathways for optical features created on the IC chip to couple optically with optically transparent inputs and / or outputs on an external optical interface of an assembly containing the IC chip. The assembly-level optical interconnect features also relocate chip-level optical I / O to locations on the assembly that are more suitable for the external optical interface of a circuit board or other host to which the assembly is mounted.Accordingly, such intermediate connection features can be referred to as optical redistribution layer (oRDL) features.

[0017] The assembly processing for generating oRDL features can advantageously offer reduced complexity, reduced costs, increased simplicity, and / or increased flexibility in the fabrication of optical components and can advantageously facilitate the inclusion of optical components in an assembly. Additionally, the assembly processing for generating oRDL features described herein can advantageously integrate the oRDL features with eRDL features of a chip assembly. Such integrated assembly redistribution layers can, in turn, offer reduced complexity, reduced costs, increased simplicity, and / or increased flexibility in integrating electronic components with optical components.

[0018] Fig. Figure 1 shows a cross-sectional view of a section of a component 100 configured as an assembly, with an oRDL feature 138 according to some embodiments. The component 100 configured as an assembly comprises an IC chip 101. The IC chip 101 comprises an optical component, such as, but not limited to, a photodiode operable to receive over an optical band or a laser diode operable to transmit over an optical band. At least one section of the IC chip 101 has a semiconductor lattice structure suitable for semiconductor devices such as, but not limited to, transistors. In various embodiments, the substrate 101 may comprise a Group IV semiconductor material such as silicon. In some embodiments, the substrate 101 may comprise a Group III / Group V composite semiconductor material such as gallium arsenide.

[0019] The substrate 101 has one or more optical contact areas 102 comprising an optically transparent or optically sensitive material. The optical contact areas 102 can be optically coupled to one or more optical devices that can receive optical input signals (e.g., incident light) through the optical contact areas 102 and that, in turn, can be operated to respond to the optical signals by converting and / or transmitting them. Such optical devices can include, for example, optical converters, optical diodes, optical amplifiers, optical detectors, optical modulators, photovoltaic cells, and / or parts of such devices. The optical contact areas 102 can also serve to emit optical signals by generating and / or propagating them. Such optical devices can include, for example, light-emitting diodes and laser diodes.

[0020] In various embodiments, one or more of the optical contact areas 102 can be optically coupled to parts of optical devices within the substrate 101. The optical contact areas 102 can accordingly be operated to receive incident optical signals (e.g., incident light) and to guide or otherwise deliver the optical signals to parts of optical devices, or to guide or otherwise deliver optical signals from parts of optical devices.

[0021] The substrate 101 additionally comprises one or more electrical contact areas 104, which include an electrically conductive material. The electrical contact areas 104 can be electrically coupled to one or more electronic devices that can receive electrical signals (e.g., electrical currents) through the electrical contact areas 104 and that, in turn, can be operated to respond to the electrical signals by processing and / or propagating them, or to supply electrical signals through the electrical contact areas 104. Such electronic devices can include transistors, diodes, and thyristors, and / or parts thereof. Some embodiments of the component 100 assembled into the assembly may not have electrical contact areas 104.

[0022] In various embodiments, one or more of the electrical contact areas 104 can be electrically coupled to parts of electrical devices within the substrate 101. The electrical contact areas 104 can accordingly be operated to receive electrical signals (e.g., electrical currents) and to conduct the electrical signals to parts of electrical devices, or to conduct or otherwise supply electrical signals from parts of electrical devices. Some electrical contact areas 104 can be electrically conductive contact points for electrically coupling electrical devices of the substrate 101 with structures outside the substrate 101.

[0023] Optical contact areas 102 and electrical contact areas 104 are positioned on a structured side or area of ​​the substrate 101, such as the front or back of the substrate 101. Accordingly, the optical contact areas 102 and the electrical contact areas 104 form parts of the front or back surface of the substrate 101, which is a structured surface of the substrate 101.

[0024] The component 100 formed into the assembly comprises one or more dielectric build-up layers positioned over and / or on sections of the structured surface of the substrate 101. The various build-up layers comprise a dielectric material. For example, part of the assembly, such as the lower build-up layer 110 and the upper build-up layer 130, may comprise an organic material, an epoxy thermoset, or a thermoplastic material. The solder mask 106 arranged over the assembly may also be formed from a similar polymer material, which is likewise deposited and cured or applied as a dry film.

[0025] The assembly has a layered structure with various layers arranged one above the other. For example, the one or more assembly layers include a lower assembly layer 110, which is arranged over and / or on sections of the substrate 101. The lower assembly layer 110 is accordingly in direct contact with various sections of the structured surface of the substrate, including sections of optical contact areas 102 and sections of electrical contact areas 104. The assembly also includes an upper assembly layer 130, which is positioned over and / or on sections of the lower assembly layer 110. The upper assembly layer 130 is accordingly in direct contact with various sections of the lower assembly layer 110. The solder mask 106 is positioned over and / or on sections of the upper assembly layer 130. Although in Fig. 1 where only some of the build layers are shown, a build material in the component 100 formed into the assembly can comprise any number of build layers.

[0026] The component 100 formed into the assembly also includes one or more oRDL features 138 extending from the optical contact areas 102 to an outer surface of the component 100 formed into the assembly. As in Fig. As shown in Figure 1, for example, each oRDL feature 138 has a first endpoint that is optically coupled to optical contact areas 102. In some embodiments, the first endpoint can be in direct contact with optical contact areas 102. As shown, each oRDL feature 138 also has a second endpoint that is positioned at or extends through openings or apertures in an outer surface of the various build-up layers (e.g., openings in an outer surface of the solder mask 106). Between the first endpoint and the second endpoint, each oRDL feature 138 extends through the various build-up layers, and the various build-up layers accordingly extend around sections of the oRDL features 138.

[0027] oRDL features 138 comprise an optically transparent material (e.g., a material that transmits electromagnetic radiation in a given optical band). In some embodiments, oRDL features 138 comprise a material that is substantially transparent over a desired wavelength range over which optical devices can be operated on the substrate 101. In some embodiments, the optically transparent material may be an epoxy material. In some embodiments, the optically transparent material is polymethyl methacrylate (PMMA).

[0028] The assembly 100 comprises one or more linings 139 that surround, coat, or encapsulate one or more surfaces of oRDL features 138. The linings 139 are intended to contain optical energy within the oRDL features 138. The linings 139 may be optically reflective. In various embodiments, the linings 139 may be in direct contact with the oRDL features 138. The linings 139 of some embodiments comprise an electrically conductive material (e.g., a metal) and / or a material with a refractive index lower than that of a material of the oRDL features 138 to provide sufficient refractive index contrast for internal reflection. In some embodiments, the linings 139 may comprise aluminum, copper, and / or titanium. In some embodiments, the linings 139 comprise a metal nitride, for example, without limitation, titanium nitride.The linings 139 can advantageously reduce the optical signal loss into the build layers surrounding the oRDL features 138.

[0029] In other embodiments of the component 100 formed into the assembly, however, one or more oRDL features 138 may not include linings 139. For such embodiments, material properties of the assembly structure (e.g., the lower assembly layer 110, the upper assembly layer 110, the upper layer 130, and / or the solder mask 106) can advantageously reduce the optical signal loss by providing a favorable optical reflectance, for example, as a result of the refractive index contrast with the material used in the oRDL features 138. In some embodiments, the assembly structure may include a material that is essentially opaque to the optical wavelength transmitted by the oRDL features 138.

[0030] The linings 139 substantially enclose or cover all surfaces of the oRDL features 138. In some embodiments, however, the lining 139 is present on side walls of the oRDL features 138, but not on one or more surfaces intended to couple light vertically (z-dimension). The absence of linings 139 in selected areas allows oRDL features 138 to directly contact optical contact areas 102. The linings 139 may also be absent from surfaces of the assembly intended to optically couple with a component outside the assembly component 100. In other embodiments, the linings 139 may only partially enclose or otherwise cover the oRDL features 138. For example, the linings 139 may enclose the portions of oRDL features 139 that are not surrounded by different build-up layers.Other sections of oRDL features that are not encased by the linings 139 may, for example, be in contact with reflective surfaces of the buildup layers (as discussed above).

[0031] In embodiments that include the generation of eRDL features, the assembly component 100 also includes one or more eRDL features 114 and one or more solder joints 107. Before the assembly component 100 is integrated into a host, the solder joints 107 may be substantially spherical. After the assembly component 100 is mounted on a host, the solder joints 107 may no longer be substantially spherical (possibly as a result of a remelting process) and may assume a more cylindrical or even hourglass shape. Embodiments of the assembly component 100 that do not have electrical contact areas 104 may also lack eRDL features 114 and solder joints 107.

[0032] One or more of the eRDL features 114 extend from the electrical contact areas 104 to the solder joints 107. As in Fig. As shown in Figure 1, each eRDL feature 114 has a first endpoint coupled to an electrical contact area 104, which is an electrically conductive contact point on the substrate 101. In various embodiments, the first endpoint can be in direct contact with the electrical contact areas 104. The eRDL features 114 also have a second endpoint positioned proximal to openings or apertures in one or more of the build-up layers, for example, a ball-and-gauge array (BGA) contact point surrounded by a solder mask 106. The solder joints 107 are located within and / or adjacent to the openings or apertures in the solder mask 106. The second endpoint of each eRDL feature 114 is coupled to a solder joint 107.Between the first terminal and the second terminal, the eRDL features 114 extend through the various structure layers, and the various structure layers accordingly extend around parts of eRDL features 114.

[0033] The eRDL features 114 can comprise any electrically conductive material, such as a metal. Accordingly, the soldered connections 107 are electrically connected to the electrical contact areas 104 via the eRDL features 114.

[0034] The solder joints 107 extend outward by a first distance from an outer surface of the assembly material. Similarly, oRDL features 138 extend vertically (e.g., z-dimension) beyond the outer surface of the assembly to form optically transparent pins extending outward by a second distance from the outer surface. In some embodiments, the second distance may be substantially equal to the first distance.

[0035] The optically transparent pins, extending outwards from the outer surface, have a longitudinal length (e.g., z-dimension) oriented substantially perpendicular to a structured surface of the substrate 101, and a transverse width (e.g., x-dimension) oriented substantially parallel to the substrate 101. In some embodiments, the ratio of the longitudinal length to the transverse width is greater than 2. In some embodiments, this ratio is greater than 3 and can even be greater than 5.

[0036] In some embodiments, the longitudinal length of the optically transparent pins 138 is essentially equal to a solder ball diameter and / or a z-height of a solder joint. A subsequent integration process can advantageously be facilitated by oRDL features 138 that extend to the same z-height as the eRDL features 114. For such embodiments, both oRDL features 138 and eRDL features 114 can interface with substantially coplanar features of a host outside the component 100 formed into the assembly.

[0037] In various embodiments, the component 100 formed into the assembly can comprise one or more regions in which the oRDL features 138 and the eRDL features 114 physically overlap. Sections of oRDL features can be positioned over, above, and / or on top of parts of eRDL features 114 and can accordingly overlap sections of eRDL features 114. Similarly, sections of eRDL features 114 can be positioned over, above, and / or on top of sections of oRDL features 138 and can accordingly overlap sections of oRDL features 138. In some such embodiments, a section of the assembly can be positioned between overlapping sections of oRDL features 138 and sections of eRDL features 114. In other embodiments, sections of the eRDL features 114 that overlap sections of the oRDL features 138 can be in direct contact with these sections of the oRDL features 138.In embodiments comprising a lining 139, sections of the eRDL features 114 that overlap sections of the oRDL features 138 can be in direct contact with the lining 139 that covers these sections of the oRDL features 138.

[0038] The material and / or structural properties of the oRDL features 138 and the eRDL features 114 can advantageously allow them to be located in close proximity to one another without either feature interfering with the functionality of the other. Sections of the two types of features can accordingly overlap or otherwise be located in close proximity to one another (e.g., adjacent within the same build-up layer) without inherently disrupting or hindering the operation of either RDL feature type. As a result, manufacturing processes for producing oRDL features can be integrated into manufacturing processes for producing eRDL features.Such integrated manufacturing processes can, in turn, advantageously offer reduced complexity, reduced costs, increased simplicity and / or increased flexibility in the manufacture of components that integrate electronic devices with optical devices.

[0039] As discussed above, the assembly component 100 comprises the substrate 101, the optical contact areas 102, various build-up layers such as the lower build-up layer 110 and the upper build-up layer 130, and the oRDL features 138. The assembly component 100 also includes the linings 139, the electrical contact areas 104, the solder mask 106, and the eRDL features 114, although these features may be absent in some embodiments of the assembly component 100. Since these features can be monolithically formed, as discussed in detail below, the assembly component 100 is accordingly a monolithically assembled component.

[0040] Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E, Fig. 2F, Fig. 2G, Fig. 2H, Fig. 2I, Fig. 2 years Fig. 2K, Fig. 2L and Fig. Figure 2M shows cross-sectional views of an assembly component that includes an oRDL feature when a method for manufacturing the assembly component is carried out, and illustrates flowcharts of a method for manufacturing an assembly component that includes an oRDL feature according to some embodiments.

[0041] A method 250 can be undertaken to manufacture a component 200 configured as an assembly. In some embodiments, the method 250 comprises, as in Fig. Figure 2A shows the receiving of a workpiece in operation 252 and the deposition and structuring of a build-up layer in operation 254. In the illustrative embodiment, an IC chip 201, which has a structured surface with one or more optical areas 202, is received. In the illustrated embodiment, which includes the generation of eRDL features, the structured surface of the IC chip 201 also has one or more electrical areas 204. The IC chip can comprise a semiconductor lattice suitable for use in a semiconductor device fabrication process and can include a material such as silicon or gallium arsenide.

[0042] In Operation 254, a first build-up layer 210 is deposited over the IC chip 201 and the optical contact areas 202. The first build-up layer 210 is then structured to at least partially expose the IC chip 201 and the optical contact areas 202. In the illustrated embodiment, which includes the generation of eRDL features, the first build-up layer 210 is also deposited over the electrical contact areas 204 and is likewise structured to at least partially expose the electrical contact areas 204. The first build-up layer 210 can comprise a dielectric material such as an organic material, an epoxy thermoset, or a thermoplastic material. Any thin-film, dry-film, or rotational-cure deposition process known in the art can be used in Operation 254.

[0043] At the in Fig. In the embodiment shown in Figure 2B, which includes the generation of linings around oRDL features, a lining layer 211 is deposited over the first build layer 210 in Operation 256. The lining layer 211 can also be deposited over any exposed sections of the IC chip 201 and over any exposed optical contact areas 202. In the embodiment shown, which includes the generation of eRDL features, the lining layer 211 is also deposited over any exposed electrical contact areas 204. Any deposition process known in the prior art can be used in Operation 256. For example, a metal can be deposited by physical vapor deposition (PVD).

[0044] At the in Fig. In the embodiment shown in Figure 2C, which includes the creation of linings around oRDL features, one or more openings 241 are formed through the lining layer 211 in operation 258. The openings 241 can be formed, for example, by laser drilling or a suitable etching process. The openings 241 are formed by sections of the lining layer 211 over the optical contact areas 202. The formation of openings 241 accordingly exposes sections of the optical contact areas 202.

[0045] The lining layer 211 can comprise a conductive material and / or a material with a refractive index below that of a material subsequently deposited as the oRDL. In some embodiments, the lining layer 211 is a metal. In some such embodiments, the lining layer 211 can comprise aluminum, copper, and / or titanium. In some embodiments, the lining layer 211 can comprise a metal nitride, such as titanium nitride, without limitation.

[0046] As further in Fig. Figure 2C shows that method 250 continues with operation 260, in which an oRDL 212 is deposited over the build layer 210, any exposed sections of the IC chip 201, and any exposed optical contact areas 202. The oRDL 212 is then cured. In the illustrated embodiment, which includes the creation of liners around oRDL features, the oRDL 212 is deposited over the liner layer 211 and over any exposed sections of the optical contact areas 202 through the openings 241.

[0047] The oRDL 212 comprises an optically transparent material. In some embodiments, the oRDL 212 comprises an epoxy material. In various embodiments, the oRDL 212 comprises PMMA.

[0048] In some embodiments, which are characterized by Fig. To represent the oRDL 212 in 2D, it is polished back (e.g., by chemical-mechanical planarization), thereby removing the top layer. Polishing exposes the first build-up layer 210 and a structure of different sections of the oRDL 212 between sections of the exposed first build-up layer 210 (e.g., x-dimensionally). Polishing can also planarize the oRDL 212 with an upper surface of the exposed build-up layer 210.

[0049] In the illustrated embodiment, which includes the creation of linings around oRDL features, the polishing also removes sections of the lining layer 211 above the build-up layer 210 to expose the build-up layer 210. In such embodiments, sections of the lining layer 211 are left between the IC chip 201 and sections of the oRDL 212 that may be positioned above the IC chip 201. Furthermore, sections of the lining layer 211 are left between the build-up layer 210 and the various sections of the oRDL 212 between the sections of the exposed build-up layer 210.

[0050] In some embodiments, as described in Fig. In the embodiment shown in Figure 2E, which includes the generation of eRDL features, one or more openings 242 can be formed completely through sections of the build-up layer 210 to expose sections of electrical contact areas 204. The openings 244 can be formed, for example, by laser drilling or a suitable etching process. In the embodiment shown, which includes the generation of linings around oRDL features, a further lining layer 221 is deposited on the build-up layer 210, on the oRDL 212, and on any exposed sections of the electrical contact areas 204. The lining layer 221 can, for example, be any of the materials provided above for the lining layer 211.

[0051] [In some embodiments, as described in Fig. As shown in Figure 2F, which includes the generation of linings around oRDL features, in Operation 268 another buildup layer 220 is deposited over the lining layer 221. The buildup layer 220 can be any of the materials provided above for the buildup layer 210. The upper layer 220 is then textured, leaving exposed sections of the lining layer 221. Exposed sections of the lining layer 221 are then removed in Operation 270, leaving sections of the lining layer 221 between the oRDL 212 and the buildup layer 220. With reference to Fig. 2G, when removing 272, can thin or completely remove the second build-up layer 220, leaving exposed sections of the build-up layer 210 and sections of the lining layer 221 above the oRDL 212. In the illustrated embodiment, which includes the generation of eRDL features, removing the build-up layer 220 additionally leaves exposed sections of parts of the electrical contact areas 204.

[0052] In some embodiments, which are characterized by Fig. In the embodiment where 2G are represented, a further build-up layer 230 is deposited over the build-up layer 210 and the oRDL 212. In the illustrated embodiment, which includes the production of linings around oRDL features, the build-up layer 230 is also arranged over sections of the lining layer 221 above the oRDL 212.

[0053] In the illustrated embodiment, which includes the generation of eRDL features, the build-up layer 230 is also deposited over exposed sections of the electrical contact areas 204. In such embodiments, several openings 243 are then formed in operation 276 through sections of the build-up layer 230 over the electrical contact areas 204. The openings 243 can be formed, for example, by laser drilling or a suitable etching process.

[0054] With reference to Fig. In operation 278, an eRDL 214 is deposited over the build-up layer 230 and over exposed sections of the electrical contact areas 204 through the openings 243. The eRDL 214 is then structured to form various features such as one or more electrically conductive contact points and one or more eRDL features extending between the electrical contact areas 204 and the electrically conductive contact points.

[0055] With reference to Fig. In operation 280, a solder mask 206 is deposited over the eRDL 214 and over the build-up layer 230. One or more openings 244 are formed such that they extend completely through the solder mask 206 and expose sections of the electrically conductive contact points of the eRDL 214. Any known solder mask structuring process can be used in operation 280. In operation 284, one or more solder joints 207 are positioned within the openings 244 and over the exposed sections of the electrically conductive contact points. Remelting the solder then electrically couples the solder joints 207 to the exposed electrically conductive contact points of the eRDL 214.

[0056] In some embodiments, as further described in Fig. As shown in section 2J, a masking layer 208 is deposited over the build-up layer 230. The masking layer 208 is then structured to expose sections of the build-up layer 230. The masking layer 208 can be a photosensitive polymer or a hard mask that can be removed by reactive ion etching. Subsequently, in operation 288, several openings 245 are formed through the build-up layer 230.

[0057] In the illustrated embodiment, which includes the generation of eRDL features, the masking layer 208 is also deposited over the eRDL 214, the solder mask 206, and the solder joints 207, and the masking layer 208 is structured to expose sections of the solder mask 206. In operation 288, openings 245 are additionally etched into the solder mask 206.

[0058] In the illustrated embodiment, which includes the formation of linings around oRDL features, in operation 288 a further lining layer 231 is deposited on exposed sections of the oRDL 212 and also on sidewalls of the openings 245, which include sections of the masking layer 208 and the third build-up layer 230. The opening sidewalls also include sections of the solder mask 206 in the illustrated embodiment, which includes the formation of eRDL features. In operation 290, several openings 246 are formed completely through sections of the lining layer 230, thereby exposing sections of the oRDL 212. The openings 246 can be formed using methods similar to those used to form the openings through the lining layer 211.

[0059] Fig. Figure 2K shows operation 292, in which an oRDL 222 is deposited over the covercoat layer 208 and the exposed sections of the oRDL 212. In the illustrated embodiment, which includes the creation of linings around oRDL features, the oRDL 222 is also deposited over the lining layer 231 and through the openings 246 over the exposed sections of the oRDL 212. The oRDL 222 is then cured. The oRDL 222 can comprise a material similar to or identical with that of the oRDL 212.

[0060] As in Fig. In operation 250, as shown in figure 2L, the oRDL 222 is polished back, thereby removing the top layer of the oRDL 222. The polishing exposes the covercoat layer 208. In the illustrated embodiment, which includes the creation of linings around oRDL features, the polishing additionally removes sections of the lining layer 231 above the covercoat layer 208 to expose the covercoat layer 208.

[0061] The polishing process accordingly forms one or more oRDL features 238, which comprise sections of oRDL 212 and sections of RDL 222. In the illustrated embodiment, which includes the production of linings around oRDL features, the polishing process also forms one or more linings 239 around oRDL features 238. The linings 239 comprise sections of lining layer 211, sections of lining layer 221, and sections of lining layer 231.

[0062] In Fig. In operation 296, the masking layer 208 is removed to expose the build-up layer 230. In the illustrated embodiment, which includes the creation of eRDL features, the removal of the masking layer 208 exposes the solder mask 206 and the solder joints 207, which (together with the eRDL features 214) are positioned above the build-up layer 230. In the illustrated embodiment, which includes the creation of linings around oRDL features, the removal of the masking layer 208 additionally exposes sections of the linings 239.

[0063] The removal of the cover coat layer 208 accordingly forms a component 200 formed into an assembly similar to the component 100 formed into an assembly of Fig. 1 out. As shown, the component 200 assembled into the module comprises an IC chip 201, one or more optical contact areas 202 coupled to one or more oRDL features 238, one or more liners 239 enclosing oRDL features 238, one or more electrical contact areas 204 coupled to one or more eRDL features 214 and (via eRDL features 214) to one or more solder joints 207, and various build-up layers such as the first build-up layer 210, the second build-up layer 230, and the solder mask 206. The eRDL features 238 and the solder joints 207 extend outwards from an upper surface of the solder mask 206 to approximately equivalent distances (although in some embodiments the eRDL features 238 and the solder joints 207 are located at approximately equivalent distances). from the upper surface of the solder mask 206 outwards to different z-heights.

[0064] Fig. Figure 3 shows a cross-sectional view of a component formed into an assembly, which includes an oRDL feature, according to some embodiments. The component formed into an assembly 300 is similar to the component formed into an assembly 200. The component formed into an assembly 300 comprises an IC chip 301, one or more optical contact areas 302 coupled to one or more oRDL features 338 enclosed by one or more liners 339, and one or more electrical contact areas 304 coupled to one or more solder joints 307 via one or more eRDL features 314.

[0065] The component 300 assembled into the module comprises a superstructure 310. Although the superstructure 310 is similar to the assembly layer 210, the assembly layer 230, and the solder mask 206 of the component 200 assembled into the module, the superstructure 310 does not extend between and separate sections of the oRDL features 338 and sections of the eRDL features 314. Accordingly, sections of the eRDL features 314 directly contact sections of the linings 339 that enclose the oRDL features 338, and / or, in some embodiments, sections of the oRDL features 338 themselves.

[0066] Fig. Figure 4 shows a cross-sectional view of a component 300 formed into an assembly, which includes an oRDL feature that is coupled both electrically and optically to a PCB component 450, according to some embodiments. Fig. 4. A PCB component 450 comprises one or more optical contact areas 452, such as light-guiding areas, which are optically coupled to one or more optical devices on the PCB component 450. Similarly, the PCB 450 comprises one or more electrical contact areas 454 which are electrically coupled to one or more electrically conductive features 464.

[0067] As in Fig. As shown in Figure 4, the component 300 formed into an assembly can be oriented such that oRDL features 238 are placed near optical contact areas 452 and solder joints 307 are placed near electrically conductive features 464. The oRDL features 238 can then be optically coupled to the optical contact areas 452, and the solder joints 307 can be electrically coupled to the electrical contact areas 454 (e.g., by a remelting process that remelts both the oRDL pin and the solder). Accordingly, the component 300 formed into an assembly and the PCB 450 can be integrated into an assembly 400.

[0068] Fig. 5 and Fig. Figure 6 shows cross-sectional views of assemblies that integrate components formed into the assembly with oRDL features, and top views of the assemblies according to some embodiments. Fig. The assembly 500 comprises a component 501 formed into the assembly with oRDL features and eRDL features, a lower semiconductor plate 502, one or more solder joints 547 and one or more optical fibers 548. The optical fibers 548 are coupled to various optical contact areas on an upper surface 550 of the assembly 500.

[0069] The component 501 assembled into the module is an IC chip with a structured surface and a back surface opposite the structured surface. Similarly, the lower semiconductor wafer 502 has a structured surface and a back surface opposite the structured surface. As shown, the back surface of the component 501 assembled into the module is adjacent to the back surface of the lower semiconductor wafer 502. Solder joints 547 are arranged adjacent to the structured surface of the lower semiconductor wafer.

[0070] The structured surface of component 501, formed into the assembly, has one or more optical contact areas and one or more electrical contact areas, and the structured surface of the lower semiconductor plate 502 has one or more electrical contact areas. The assembly 500 comprises one or more optically transparent features 538, which in some embodiments may include optically transparent DSL (oRDL) features and which optically couple the oRDL features of component 501 formed into the assembly to optical fibers 548. The assembly 500 also comprises one or more electrically conductive features 514, which in some embodiments may include electrically conductive DSL (eRDL) features and which electrically couple the eRDL features of component 501 formed into the assembly to the electrical contact areas of the lower semiconductor plate, to the solder joints 547, or to both.

[0071] The component 501 formed into the assembly can include an optical transducer that can receive optical signals through optical fibers 548 and then transmit electrical signals to the lower semiconductor plate 502 and / or to the solder joints 547.

[0072] In Fig. The assembly 600 comprises a component 601 formed into the assembly with oRDL and eRDL features, a lower semiconductor plate 602, one or more solder joints 647, and one or more optical fibers 648. In some embodiments, the optical fibers 648 are coupled to an upper surface 650 of the assembly 600 in various optical contact areas. Compared to the assembly 500, the assembly 600 also includes an upper semiconductor plate 603.

[0073] The component 601 assembled into the assembly is an IC chip with a structured surface and a back surface opposite the structured surface. Similarly, the lower semiconductor wafer 602 has a structured surface and a back surface opposite the structured surface. The back surface of the component 601 assembled into the assembly is adjacent to the back surface of the lower semiconductor wafer 602, and the solder joints 647 are adjacent to the structured surface of the lower semiconductor wafer. The upper semiconductor wafer 603 has one or more electrically conductive features (which include eRDL features) projecting from an inward-facing surface, e.g., a surface facing the main part of the package 600.

[0074] The structured surface of component 601, formed into the assembly, has one or more optical contact areas and one or more electrical contact areas, and the structured surface of the lower semiconductor plate 602 has one or more electrical contact areas. Meanwhile, the assembly 600 includes one or more optically transparent features 638, which in some embodiments may include oRDL features and which optically couple the oRDL features of component 601, formed into the assembly, with the optical fibers 648.The assembly 600 also includes one or more electrically conductive features 614, which in some embodiments may include eRDL features and which electrically couple the eRDL features of the component 601 formed to the assembly with one or more of the electrical contact areas of the lower semiconductor plate, the solder joints 647 and the electrically conductive features of the upper semiconductor plate 603.

[0075] The component 601 formed into the assembly can include an optical transducer that can receive optical signals through optical fibers 648 and then transmit electrical signals to the lower semiconductor plate 602, the solder joints 647 and / or the upper semiconductor plate 603.

[0076] Fig. 4, Fig. 5 to Fig. Figure 6 shows components formed into assemblies with oRDL features, which are incorporated into various assemblies in different ways. In various embodiments, a monolithic component formed into an assembly with one or more oRDL features (such as component 200 or component 300) can be incorporated into an assembly together with one or more optically transparent fibers coupled to the oRDL features.

[0077] Based on the methods discussed herein, oRDL features can be integrated into packages in various ways. oRDL features can be placed on a top (or front) or bottom (or back) surface of a package. In various embodiments, multiple layers of oRDL features and / or eRDL features can be integrated into an IC chip. oRDL features can be integrated into a variety of assembly configurations, including ball-lattice BGA configurations, wafer-level BGA configurations, wafer-level and chip-scale assembly configurations, flip-chip configurations, and panel-level fan-out assembly configurations. oRDL features can also be integrated into a molded interconnect substrate.

[0078] Fig. Figure 7 shows a mobile computing platform and a data server machine that use an assembly including an oRDL feature, according to some embodiments. The server machine 706 can comprise any commercial server, which, for example, includes any number of high-performance computing platforms arranged within a rack and networked together for electronic data processing, and which, in the exemplary embodiment, includes a monolithic SoC 750 assembled into an assembly. The mobile computing platform 705 can be any portable device designed to display electronic data, process electronic data, transmit electronic data wirelessly, or the like. For example, the mobile computing platform 705 can be a tablet, smartphone, laptop, etc., and can have a display screen (e.g., a smartphone).a capacitive, inductive, resistive or optical touchscreen), an integrated system at chip level or assembly level 710 and a battery 715.

[0079] Either arranged within the integrated system 710 shown in the extended view 720, or arranged as a standalone chip assembled within the server machine 706, the monolithic SoC 750 comprises a memory block (e.g., RAM) and a processor block (e.g., a microprocessor, a multi-core microprocessor, a graphics processor, or the like). The chip assembled includes, for example, an oRDL feature as described elsewhere herein. The monolithic SoC 750 may further be combined with an integrated power management circuit (PMIC circuit) 730, an integrated radio frequency integrated circuit (RFIC circuit) 725 comprising a wideband radio frequency transmitter and / or receiver (TX / RX) (e.g., a 3G / 2 ...including a digital baseband and an analog front-end module, further comprising a power amplifier on a transmit path and a low-noise amplifier on a receive path), and a control unit 735 coupled to a circuit board, substrate or intermediate element 760.

[0080] Functionally, the PMIC 730 can perform battery power regulation, DC-to-DC conversion, etc., and thus has an input coupled to a 715 battery and an output that provides power to other functional modules. As further shown, the RFIC 725 in the exemplary embodiment has an output coupled to an antenna (not shown) to implement any number of wireless standards or protocols, including, without limitation, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocol referred to as 3G, 4G, and beyond.In alternative implementations, each of these modules can be integrated into separate ICs at the board level or integrated into the monolithic SoC 750.

[0081] Fig.Figure 8 is a functional block diagram of an electronic computing device according to some embodiments. The computing device 800 may, for example, be found within the platform 705 or the server machine 706. The device 800 further comprises a mainboard 802, which hosts a number of components, such as, without limitation, a processor 804 (e.g., an application processor), which may, for example, be in an assembly, as described elsewhere herein, coupled to the mainboard 802 by BGA connections of different heights (different volumes). The processor 804 may be physically and / or electrically coupled to the mainboard 802.In some examples, the 804 processor comprises an integrated circuit semiconductor wafer that is assembled within the 804 processor into a module, and connections between the IC semiconductor wafer and the 805 processor are further provided by BGA solder joints of varying heights, as described, for example, elsewhere herein. In general, the term "processor" or "microprocessor" can refer to any device or any section of a device that processes electronic data from registers and / or memories in order to transform such electronic data into other electronic data that can be further stored in registers and / or a memory.

[0082] In various examples, one or more 806 communication chips can be physically and / or electrically coupled to the 802 mainboard. In other implementations, the 806 communication chips can be part of the 804 processor. Depending on its applications, the 800 computing device can include other components, which may or may not be physically and electrically coupled to the 802 mainboard. These other components include volatile memory (e.g., DRAM), non-volatile memory (e.g., memory chips), and other memory components.ROM), flash memory, a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a touchscreen display, a touchscreen control unit, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard disk drive, a solid-state drive (SSD), a CD, a DVD, and so forth) or the like. Each of these other components may also be coupled to the 802 mainboard by BGA solder connections of varying heights, as described, for example, elsewhere herein.

[0083] The 806 communication chips can enable wireless communication for data transfer to and from the 800 computing device. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the corresponding devices do not include wires, although in some embodiments they may not. The 806 communication chips can implement any number of wireless standards or protocols, including but not limited to those described elsewhere herein. As discussed, the 800 computing device can include multiple 806 communication chips.For example, a first communication chip can be dedicated to short-range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip can be dedicated to long-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and the like.

[0084] Although certain features set forth herein are described with reference to various implementations, this description is not intended to be interpreted in a restrictive sense. Therefore, various modifications of the implementations described herein, as well as other implementations that are obvious to those skilled in the art, for whom this disclosure is intended, are considered to be within the scope and purpose of this disclosure.

[0085] The following examples belong to specific example implementation forms.

[0086] An example provides an assembly comprising: a substrate having a structured surface with an optical contact area; an optical redistribution layer (oRDL) feature; a liner encasing the oRDL feature; and a build-up material extending over the structured surface of the substrate and around portions of the oRDL feature.

[0087] Some embodiments provide an assembly in which the optical contact area is in direct contact with the oRDL feature. Some embodiments provide an assembly in which the oRDL feature extends from the optical contact area to an opening in an outer surface of the assembly material. Some embodiments provide an assembly in which the lining comprises an electrically conductive material and / or a material with a refractive index below that of the oRDL feature. Some embodiments provide an assembly in which the lining comprises aluminum, copper, titanium, and / or titanium alloy. Some embodiments provide an assembly in which the oRDL feature comprises an optically transparent material. Some embodiments provide an assembly in which the optically transparent material comprises polymethyl methacrylate.Some embodiments provide an assembly in which the oRDL feature extends through openings in an outer surface of the build material and forms a pin extending outward from the outer surface. Some embodiments provide an assembly comprising an electrical redistribution layer feature (eRDL feature), wherein the structured surface of the substrate has an electrical contact area, the build material extends around portions of the eRDL feature, and the eRDL feature extends from the electrical contact area to an additional opening in the build area.

[0088] Some embodiments provide an assembly comprising a solder joint located adjacent to the additional opening in the build material, wherein the solder joint is electrically coupled to the eRDL feature. Some embodiments provide an assembly in which the oRDL feature extends through the opening in the build material and forms a pin extending outward by a first distance from an outer surface of the build material, and wherein the solder joint extends outward by a second distance from the outer surface of the build material, the second distance being substantially equal to the first distance. Some embodiments provide an assembly comprising a region between the structured surface of the substrate and an outer surface of the build material in which the oRDL feature and the eRDL feature overlap.Some embodiments provide an assembly comprising: a lower semiconductor wafer with a structured surface having an electrical contact area and a back surface opposite the structured surface; a solder joint; and an optical fiber, wherein the substrate has a back surface opposite the structured surface; wherein the back surface of the substrate is adjacent to the back surface of the lower semiconductor wafer; wherein the solder joint is adjacent to the structured surface of the lower semiconductor wafer and is electrically coupled to the electrical contact area of ​​the lower semiconductor wafer; and wherein the optical fiber is optically coupled with the oRDL feature.

[0089] An example provides a system comprising a memory, a processor coupled to the memory, and a wireless interface to enable the processor to communicate with another device, the system having an assembly as provided above.

[0090] One example provides a monolithic component designed as an assembly, which includes: A substrate having a structured surface with one or more electrical contact areas and one or more optical contact areas; one or more electrical redistribution layer features (eRDL features); one or more optically transparent optical redistribution layer features (oRDL features); and a buildup layer extending over the structured surface of the substrate, around portions of the eRDL features and around portions of the oRDL features, wherein the buildup layer has an outer surface with one or more first openings and one or more second openings; wherein the eRDL features extend from the electrical contact areas to the first openings; wherein the oRDL features extend from the optical contact areas to the second openings; and wherein the oRDL features comprise an optically transparent material.

[0091] Some embodiments provide a monolithic assembly component that includes one or more regions between the structured surface of the substrate and the outer surface of the build-up layer, where the eRDL features and the oRDL features overlap. Some embodiments provide a monolithic assembly component in which the oRDL features are covered along their length with reflective linings. Some embodiments provide a monolithic assembly component in which the linings comprise a metallic material. Some embodiments provide a monolithic assembly component in which the linings are in direct contact with the oRDL features. Some embodiments provide a monolithic assembly component in which the metallic material comprises aluminum, copper, titanium, and / or titanium nitride.

[0092] Some embodiments provide a monolithic assembly component in which the oRDL features extend through the second openings and form pins that extend outward from the outer surface of the build-up layer. Some embodiments provide a monolithic assembly component that includes one or more solder joints located adjacent to the first openings, the solder joints being electrically coupled to the eRDL features. Some embodiments provide a monolithic housing component in which the pins extend outward by a first distance from the outer surface of the build-up layer, and in which the solder joints extend outward by a second distance from the outer surface of the build-up layer, the second distance being substantially equal to the first distance.Some embodiments provide a monolithic assembly component in which the oRDL features form pins extending outward from the outer surface of the build-up layer, and in which the oRDL features are encased along their length with a reflective lining. Some embodiments provide a monolithic assembly component in which one material of the oRDL features comprises polymethyl methacrylate.

[0093] An example provides an assembly comprising: the monolithic component formed into an assembly, as provided above; and one or more optically transparent fibers, wherein the optical fibers are optically coupled with the oRDL feature.

[0094] Some embodiments provide an assembly comprising: a lower semiconductor wafer having a structured surface with one or more electrical contact areas and a back surface opposite the structured surface; and one or more solder joints, wherein the monolithic component forming the assembly has a back surface opposite the structured surface of the substrate; wherein the back surface of the monolithic component forming the assembly is adjacent to the back surface of the lower semiconductor wafer; wherein the solder joints are adjacent to the structured surface of the lower semiconductor wafer; and wherein the solder joints are electrically connected to: the electrical contact areas of the lower chip and / or the eRDL features of the monolithic component forming the assembly.

[0095] Some embodiments provide an assembly comprising: an upper semiconductor wafer having a structured surface with one or more electrical contact areas; a lower semiconductor wafer having a structured surface with one or more electrical contact areas and a back surface opposite the structured surface; and one or more solder joints, wherein the component formed monolithically to form the assembly has a back surface opposite the structured surface of the substrate; wherein the back surface of the component formed monolithically to form the assembly is adjacent to the back surface of the lower semiconductor wafer; and wherein the solder joints are adjacent to the structured surface of the lower semiconductor wafer.and wherein the solder joints are electrically connected to: the electrical contact areas of the lower semiconductor plate, the eRDL features of the component monolithically formed into the assembly and / or the electrical contact areas of the upper semiconductor plate.;

[0096] Some embodiments provide an assembly comprising: the monolithically formed component as provided above; and a printed circuit board (PCB) having one or more electrical contact areas and one or more optical contact areas, wherein the solder joints of the monolithically formed component are electrically coupled to the electrical contact areas of the PCB; and the oRDL features of the monolithically formed component are optically coupled to the optical contact areas of the PCB.

[0097] An example provides a system that includes a memory, a processor coupled to the memory, and a wireless interface to allow the processor to communicate with another device, with the system comprising the setup as provided above.

[0098] An example provides a method for manufacturing a component formed into an assembly, wherein the method comprises: receiving a substrate having a structured surface with one or more optical contact areas; depositing a build-up layer over the substrate; structuring the build-up layer to at least partially expose the optical contact areas; depositing an optical redistribution layer (oRDL) over the build-up layer and the exposed optical contact areas; and polishing the oRDL to expose the build-up layer, wherein the polished oRDL is planar with the exposed build-up layer.

[0099] Some embodiments provide a method in which the oRDL layer comprises polymethyl methacrylate.

[0100] Some embodiments provide a method in which the build-up layer is a first build-up layer and which comprises: depositing a lining layer over the first build-up layer and the exposed optical contact areas; and depositing the oRDL over the lining layer and over the first build-up layer and the exposed optical contact areas.

[0101] Some embodiments provide a method in which the structured surface of the substrate has one or more electrical contact areas and which includes: forming openings that extend completely through the exposed first build-up layer to at least partially expose the electrical contact areas.

[0102] Some embodiments provide a method in which the lining layer is a first lining layer and which comprises: depositing a second lining layer over the polished oRDL, the exposed build-up layer and the exposed electrical contact areas; depositing a second build-up layer over the second lining layer; structuring the second build-up layer to expose portions of the second lining layer that do not cover the oRDL; and removing the exposed portions of the second lining layer to expose the first build-up layer and the exposed electrical contact areas.

[0103] Some embodiments provide a method in which a first lining layer material and a second lining layer material comprise titanium and / or titanium nitride.

[0104] Some embodiments provide a method that includes: depositing a third build-up layer over the first build-up layer, the second lining layer, and the exposed electrical contact areas; forming openings that extend completely through the third build-up layer to at least partially expose the electrical contact areas; depositing an electrical redistribution layer (eRDL) over the third build-up layer and the exposed electrical contact areas; structuring the eRDL to form one or more electrically conductive contact points and one or more eRDL features extending between the electrical contact areas and the electrically conductive contact points; and depositing a solder mask over the electrically conductive contact points, the eRDL features, and the third build-up layer.Forming openings that extend completely through the solder mask to at least partially expose the electrically conductive contact points; positioning one or more solder joints over the exposed electrically conductive contact points; and soldering the solder joints to electrically couple them to the exposed electrically conductive contact points.

[0105] Some embodiments provide a method in which the oRDL is a first oRDL and which comprises: depositing a masking layer over the solder mask and the solder joints; structuring the masking layer to expose sections of the solder mask over the first oRDL; forming openings extending completely through the masking layer, the solder mask, and the third build-up layer to expose sections of the second lining layer; depositing a third lining layer over the masking layer, over sidewalls of the openings extending through the masking layer, the solder mask, and the third build-up layer, and over the exposed second lining layer; forming openings extending completely through the third lining layer and the second lining layer to expose sections of the first oRDL; depositing a second oRDL over the solder mask and the exposed first oRDL;and polishing the second oRDL and sections of the third lining layer, wherein the polishing forms one or more oRDL features comprising sections of the first oRDL and sections of the second oRDL; and wherein the polishing forms one or more linings around the oRDL features comprising sections of the first lining layer, sections of the second lining layer, and sections of the third lining layer.

[0106] Some embodiments provide a method that includes removing the masking lacquer layer to expose the solder mask, solder joints, and sections of the lining around the oRDL features.

[0107] One example provides machine-readable storage media containing machine-executable instructions which, when executed, cause one or more processors to perform a procedure as provided above.

[0108] An example provides machine-readable storage media containing machine-executable instructions which, when executed, cause one or more processors to perform an operation comprising: receiving a substrate having a structured surface with one or more optical contact areas; depositing a build-up layer over the substrate; structuring the build-up layer to at least partially expose the optical contact areas; depositing an optical redistribution layer (oRDL) over the build-up layer and the exposed optical contact areas; and polishing the oRDL to expose the build-up layer, the polished oRDL being planar with the exposed build-up layer.

[0109] Some embodiments provide a machine-readable storage medium, wherein the oRDL layer comprises polymethyl methacrylate.

[0110] Some embodiments provide a machine-readable storage medium, wherein the build layer is a first build layer and the operation comprises: depositing a lining layer over the first build layer and the exposed optical contact areas; and depositing the oRDL over the lining layer and over the first build layer and the exposed optical contact areas.

[0111] Some embodiments provide a machine-readable storage medium wherein the structured surface of the substrate has one or more electrical contact areas and the operation comprises: forming openings that extend completely through the exposed first build-up layer to at least partially expose the electrical contact areas.

[0112] Some embodiments provide a machine-readable storage medium, wherein the lining layer is a first lining layer and the operation comprises: depositing a second lining layer over the polished oRDL, the exposed buildup layer and the exposed electrical contact areas; depositing a second buildup layer over the second lining layer; structuring the second buildup layer to expose portions of the second lining layer that do not cover the oRDL; and removing the exposed portions of the second lining layer to expose the first buildup layer and the exposed electrical contact areas.

[0113] Some embodiments provide a machine-readable storage medium, wherein a first lining layer material and a second lining layer material comprise titanium and / or titanium nitride.

[0114] Some embodiments provide a machine-readable storage medium, the operation comprising: depositing a third build-up layer over the first build-up layer, the second liner layer, and the exposed electrical contact areas; forming openings extending completely through the third build-up layer to at least partially expose the electrical contact areas; depositing an electrical redistribution layer (eRDL) over the third build-up layer and the exposed electrical contact areas; structuring the eRDL to form one or more electrically conductive contact points and one or more eRDL features extending between the electrical contact areas and the electrically conductive contact points; and depositing a solder mask over the electrically conductive contact points, the eRDL features, and the third build-up layer.Forming openings that extend completely through the solder mask to at least partially expose the electrically conductive contact points; positioning one or more solder joints over the exposed electrically conductive contact points; and soldering the solder joints to electrically couple them to the exposed electrically conductive contact points.

[0115] Some embodiments provide a machine-readable storage medium, wherein the oRDL is a first oRDL and the operation comprises: depositing a masking layer over the solder mask and solder joints; structuring the masking layer to expose sections of the solder mask over the first oRDL; forming openings extending completely through the masking layer, the solder mask, and the third build-up layer to expose sections of the second lining layer; depositing a third lining layer over the masking layer, over sidewalls of the openings extending through the masking layer, the solder mask, and the third build-up layer, and over the exposed second lining layer; forming openings extending completely through the third lining layer and the second lining layer to expose sections of the first oRDL;Deposition of a second oRDL over the solder mask and the exposed first oRDL; and polishing of the second oRDL and of sections of the third lining layer, wherein the polishing forms one or more oRDL features comprising sections of the first oRDL and sections of the second oRDL; and wherein the polishing forms one or more linings around the oRDL features comprising sections of the first lining layer, sections of the second lining layer, and sections of the third lining layer.

[0116] Some embodiments provide a machine-readable storage medium, the operation comprising: removing the masking lacquer layer to expose the solder mask, solder joints and sections of the lining around the oRDL features.

[0117] An example provides a device comprising: means for receiving a substrate having a structured surface with one or more optical contact areas; means for depositing a build-up layer over the substrate; means for structuring the build-up layer to at least partially expose the optical contact areas; means for depositing an optical redistribution layer (oRDL) over the build-up layer and the exposed optical contact areas; and means for polishing the oRDL to expose the build-up layer, wherein the polished oRDL is planar with the exposed build-up layer.

[0118] Some embodiments provide a device wherein the oRDL layer comprises polymethyl methacrylate.

[0119] Some embodiments provide a device in which the build-up layer is a first build-up layer and which comprises: means for depositing a lining layer over the first build-up layer and the exposed optical contact areas; and means for depositing the oRDL over the lining layer and over the first build-up layer and the exposed optical contact areas.

[0120] Some embodiments provide a device in which the structured surface of the substrate has one or more electrical contact areas and which comprises: means for forming openings that extend completely through the exposed first build-up layer in order to at least partially expose the electrical contact areas.

[0121] Some embodiments provide a device in which the lining layer is a first lining layer and which comprises: means for depositing a second lining layer over the polished oRDL, the exposed build-up layer and the exposed electrical contact areas; means for depositing a second build-up layer over the second lining layer; means for structuring the second build-up layer to expose portions of the second lining layer that do not cover the oRDL; and means for removing the exposed portions of the second lining layer to expose the first build-up layer and the exposed electrical contact areas.

[0122] Some embodiments provide a device in which a first lining layer material and a second lining layer material comprise titanium and / or titanium nitride.

[0123] Some embodiments provide a device comprising: means for depositing a third build-up layer over the first build-up layer, the second lining layer, and the exposed electrical contact areas; means for forming openings extending completely through the third build-up layer to at least partially expose the electrical contact areas; means for depositing an electrical redistribution layer (eRDL) over the third build-up layer and the exposed electrical contact areas; means for structuring the eRDL to form one or more electrically conductive contact points and one or more eRDL features extending between the electrical contact areas and the electrically conductive contact points; means for depositing a solder mask over the electrically conductive contact points, the eRDL features, and the third build-up layer;Means for forming openings extending completely through the solder mask to at least partially expose the electrically conductive contact points; means for positioning one or more solder joints over the exposed electrically conductive contact points; and means for soldering the solder joints to electrically couple them to the exposed electrically conductive contact points.

[0124] Some embodiments provide a device in which the oRDL is a first oRDL comprising: means for depositing a masking layer over the solder mask and the solder joints; means for structuring the masking layer to expose sections of the solder mask over the first oRDL; means for forming openings extending completely through the masking layer, the solder mask, and the third build-up layer to expose sections of the second lining layer; means for depositing a third lining layer over the masking layer, over sidewalls of the openings extending through the masking layer, the solder mask, and the third build-up layer, and over the exposed second lining layer; means for forming openings extending completely through the third lining layer and the second lining layer to expose sections of the first oRDL;Means for depositing a second oRDL over the solder mask and the exposed first oRDL; and means for polishing the second oRDL and sections of the third lining layer, wherein the polishing forms one or more oRDL features comprising sections of the first oRDL or sections of the second oRDL; and wherein the polishing forms one or more linings around the oRDL features comprising sections of the first lining layer, sections of the second lining layer, and sections of the third lining layer.

[0125] Some embodiments provide a device which includes: means for removing the masking lacquer layer to expose the solder mask, solder joints and sections of the lining around the oRDL features.

[0126] It is evident that the principles of the disclosure are not limited to the embodiments described above, but can be implemented with modifications and adaptations without deviating from the scope of the appended claims. For example, the embodiments described above may include a specific combination of features.

Claims

[1] A component (100) formed into an assembly comprising the following: a substrate (101) having a structured surface with an optical contact area (102); an optical redistribution layer feature (oRDL feature) (138); a lining (139) that encloses the oRDL feature; and a build-up material (110, 130) extending over the structured surface of the substrate (101) and around sections of the oRDL feature (138), wherein the oRDL feature (138) extends through an opening in an outer surface of the build-up material (110, 130) and forms a pin extending from the outer surface to an outside of the component (100) formed into the assembly. [2] The component (100) formed into the assembly according to claim 1, wherein the optical contact area (102) is in direct contact with the oRDL feature (138); or wherein the oRDL feature (138) extends from the optical contact area (102) to an opening in an outer surface of the build material (110, 130); or wherein the lining (139) comprises: an electrically conductive material and / or a material with a refractive index below a refractive index of the oRDL feature (138); or the lining (139) comprises: aluminium, copper, titanium and / or titanium material. [3] The component (100) formed into the assembly according to claim 1, wherein the oRDL feature (138) comprises an optically transparent material. [4] The component (100) formed into an assembly according to claim 1, comprising an electrical redistribution layer feature (eRDL feature) (114), wherein the structured surface of the substrate (101) has an electrical contact area (104), wherein the build material (110, 130) extends around sections of the eRDL feature (114) and wherein the eRDL feature (114) extends from the electrical contact area (104) to an additional opening in the build material (110, 130). [5] The component (100) formed into the assembly according to claim 4, comprising a solder joint (107) arranged adjacent to the additional opening in the assembly material (110, 130), wherein the solder joint (107) is electrically coupled to the eRDL feature (114). [6] The component (100) formed into the assembly according to claim 5, wherein the oRDL feature (138) extends through the opening in the build material (110, 130) and forms a pin extending outwards by a first distance from an outer surface of the build material (110, 130), and wherein the solder joint extends outwards by a second distance from the outer surface of the build material (110, 130), the second distance being substantially equal to the first distance. [7] The component (100) formed into the assembly according to claim 4, comprising a region between the structured surface of the substrate (101) and an outer surface of the build material (110, 130) in which the oRDL feature (138) and the eRDL feature (114) overlap. [8] System (710) comprising a memory, a processor coupled to the memory and a wireless interface to enable the processor to communicate with another device, wherein the system (710) comprises the component (100) formed into an assembly according to any one of claims 1 to 7. [9] Method (250) for manufacturing a component formed into an assembly, the method comprising: Receiving (252) a substrate having a structured surface with one or more optical contact areas; Deposition (254) of a build-up layer over the substrate; Structuring (254) the build-up layer to at least partially expose the optical contact areas; Deposition (260) of an optical redistribution layer (oRDL) over the build-up layer and the exposed optical contact areas; and polishing (262) the oRDL to expose the build-up layer, wherein the polished oRDL is planar with the exposed build-up layer, the build-up layer being a first build-up layer, and the process comprises: Deposition (256) of a lining layer over the first build-up layer and the exposed optical contact areas; and Deposition (260) of the oRDL over the lining layer and over the first build-up layer and the exposed optical contact areas, wherein the structured surface of the substrate has one or more electrical contact areas and the method comprises: Forming (264) openings extending completely through the exposed first build-up layer to at least partially expose the electrical contact areas, wherein the lining layer is a first lining layer and the method comprises: Deposition (266) of a second lining layer over the polished oRDL, the exposed build-up layer and the exposed electrical contact areas; Deposition (268) of a second build-up layer over the second lining layer; Structuring (268) the second build-up layer to expose sections of the second lining layer that do not cover the oRDL; and Removing (270) the exposed sections of the second lining layer to expose the first build-up layer and the exposed electrical contact areas. [10] Method (250) according to claim 9, wherein the oRDL layer comprises polymethyl methacrylate. [11] Method (250) according to claim 9 or 10, wherein a material of the first lining layer and a material of the second lining layer comprise titanium and / or titanium nitride. [12] Method (250) according to any one of claims 9-11, comprising: Deposition (274) of a third build-up layer over the first build-up layer, the second lining layer and the exposed electrical contact areas; Forming (276) openings that extend completely through the third build-up layer to at least partially expose the electrical contact areas; Deposition (278) of an electrical redistribution layer (eRDL) over the third build layer and the exposed electrical contact areas; Structuring (278) the eRDL to form one or more electrically conductive contact points and one or more eRDL features extending between the electrical contact areas and the electrically conductive contact points; Deposition (280) of a solder mask over the electrically conductive contact points, the eRDL features and the third build-up layer; Forming (282) openings that extend completely through the solder mask to at least partially expose the electrically conductive contact points; Positioning (284) one or more solder joints over the exposed electrically conductive contact points; and Soldering (284) the solder joints in order to electrically couple them to the exposed electrically conductive contact points. [13] Method (250) according to claim 12, wherein the oRDL is a first oRDL and the method comprises: Deposition (286) of a cover lacquer layer over the solder mask and the solder joints; Structuring (286) the masking lacquer layer to expose sections of the solder mask above the first oRDL; Forming (288) openings extending completely through the masking lacquer layer, the solder mask and the third build-up layer to expose sections of the second lining layer; Deposition (288) of a third lining layer over the covercoat layer, over side walls of the openings extending through the covercoat layer, the solder mask and the third buildup layer, and over the exposed second lining layer; Forming (290) openings extending completely through the third lining layer and the second lining layer to expose sections of the first oRDL; Deposition (292) of a second oRDL over the solder mask and the exposed first oRDL; and Polishing (294) of the second oRDL and of sections of the third lining layer, wherein the polishing forms one or more oRDL features, comprising sections of the first oRDL and sections of the second oRDL; and wherein the polishing forms one or more linings around the oRDL features, comprising sections of the first lining layer, sections of the second lining layer and sections of the third lining layer. [14] Machine-readable storage media containing machine-executable instructions which, when executed, cause one or more processors to perform a method (250) according to any one of claims 9 to 13.

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