Ion beam etching with spacer support of a magnetic spin-torque direct access memory

Abstract

Method for etching a magnetic tunnel junction structure, MTJ structure, comprising the following: Providing a ground electrode (16) on a substrate (10); Deposition of a stack of MTJ layers on the bottom electrode (16) comprising, in this order, a pinned layer (18), a tunnel barrier layer (20) and a free layer (22); Providing a top electrode (24) on the stack of MTJ layers; Structuring the top electrode (24), MTJ stack and bottom electrode (16) to form an MTJ device, with sidewall damage being formed on sidewalls of the MTJ device; shape-matched deposition of a dielectric spacer layer (28) over the substrate (10) and the MTJ device; vertical etching of the dielectric spacer layer (28) on horizontal surfaces of the substrate (10) and the MTJ device, wherein the dielectric spacer layer (28) is partially etched away on the side walls of the MTJ device to form a tapered spacer (29) that is wider on the bottom electrode (16) and narrower or absent on the free layer (22), wherein the tapered spacer (29) covers the tunnel barrier layer (20), the pinned layer (18) and the bottom electrode (16); and Subsequently, the sidewall damage is removed from the free layer (22) and a tapered tunnel barrier layer (20) is formed by applying horizontal physical etching to the MTJ device, the pinned layer (18) and the bottom electrode (16) being protected from physical etching by the tapered spacer (29).

Description

TECHNICAL FIELD

[0001] This application relates to the general field of magnetic tunnel junctions (MTJs) and, in particular, to etching processes for forming MTJ structures. BACKGROUND

[0002] The fabrication of magnetoresistive devices typically involves a sequence of processing steps during which multiple layers of metals and dielectrics are deposited and then patterned to form a magnetoresistive stack and electrodes for electrical connections. The magnetoresistive stack typically comprises the free and pinned layers of the device sandwiched around one or more dielectric layers that function as the tunnel junction for the magnetic tunnel junction (MTJ) device. To define these millions of MTJ cells in each magnetic random access memory (MRAM) device and prevent them from interacting with each other, precise patterning steps involving reactive ion etching (RIE) are typically involved.During RIE, high-energy ions remove materials vertically in areas not masked by photoresist by separating one MTJ cell from another.

[0003] However, the high-energy ions can also react laterally with the materials not removed. For MTJ cells, this lateral reaction can create a damaged area on the sidewall caused by oxygen, moisture, and other chemicals, reducing the magnetoresistance ratio and coercivity. This damage is cell-size dependent, meaning it will become more severe as the cell size decreases for future sub-nanonode products. To solve this problem, purely physical etching techniques, such as ion beam etching (IBE), have been applied to trim the surface of the MTJ stack to remove the damaged portion. However, when trimming directly by IBE, the volumes of the free layer and the pinned layer decrease together, making the size of the latter too small to stabilize the internal magnetization state, resulting in a smaller energy barrier and larger switching current.In addition, IBE-trimmed ferromagnetic materials can be redeposited into the free layer and top electrode due to their non-volatile nature in the pinned layer and bottom electrode, resulting in short-circuited devices.

[0004] Several references teach methods for removing sidewall damage. These include patent US 8,574,928 B2 and US patent applications US 2016 / 0 225 979 A1, US 2017 / 0 025 603 A1, US 2016 / 0 020 386 A1, and US 2006 / 0 132 983 A1. Other references teach methods for blocking material diffusion into a pinned layer. These include US patent applications US 2016 / 0 211 441 A1 and US 2012 / 0 012 952 A1. An angle-dependent RIE is known from US 2014 / 0 170 776 A1. Further prior art relating to the subject matter of the invention can be found, for example, in US 8 574 928 B2, US 2016 / 0 225 979 A1, US 2014 / 0 170 776 A1, US 2017 / 0 047 510 A1, and US 2006 / 0 261425 A1. All of these references are different from the present disclosure. SUMMARY

[0005] It is an object of the present invention to provide an improved method for forming MTJ structures.

[0006] Yet another object of the present disclosure is to provide a method for removing sidewall damage from the free layer while protecting the pinned layer in the fabrication of MTJ devices.

[0007] In accordance with the objectives of the present disclosure, a method for etching a magnetic tunneling junction (MTJ) structure is achieved. A bottom electrode is provided on a substrate. A stack of MTJ layers is deposited on the bottom electrode, including, in order, a pinned layer, a tunnel barrier layer, and a free layer. A top electrode is provided on the stack of MTJ layers. The top electrode, the MTJ stack, and the bottom electrode are patterned to form an MTJ device, wherein sidewall damage is formed on sidewalls of the MTJ device. A dielectric spacer is conformally deposited over the substrate and the MTJ device.The dielectric spacer layer is partially etched away on horizontal surfaces of the substrate and the MTJ device to form a tapered spacer that is wider on the bottom electrode and narrower or absent on the free layer. The tapered spacer covers the tunnel barrier layer, the pinned layer, and the bottom electrode. Sidewall damage is then removed from the free layer by applying a horizontal physical etch to the MTJ device, with the pinned layer and the bottom electrode protected from the physical etching by the dielectric spacer layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the accompanying drawings, which form an integral part of this disclosure, the following is shown: The Fig. 1 to 4 illustrate, in cross-sectional view, steps in a preferred embodiment of the present disclosure. DETAILED DESCRIPTION

[0009] In the present disclosure, ion beam etching (IBE) is applied to trim the surface of the MTJ stack to remove the damaged portion. In this process, only the free layer is trimmed, but the volume of the pinned layer remains unchanged. This way, the pinned layer is not too small to stabilize the internal magnetization state. Furthermore, sidewall redeposition can be completely eliminated, allowing the IBE or RIE+IBE process to be used for the MRAM chip fabrication process.

[0010] In this invention, a dielectric layer is introduced that has no or less coverage on the top free layer than the pinned bottom layer and electrode. This ensures that during the subsequent IBE trimming process, only the damage within the free layer is removed, while the pinned layer and bottom electrode remain intact. Since the size of MTJ cells is determined by the size of the free layer, one is able to remove the entire damaged section responsible for reduced performance at small sizes, while ensuring that the size of the pinned layer is large enough to stabilize the magnetization state. Furthermore, there are no longer any short-circuited devices induced by redeposition. The concept of employing this non-uniformly distributed dielectric on the MTJ is the novel feature of this disclosure.

[0011] With reference to the Fig. 1 to 4, the novel process is described in detail. The process begins with a conventional MTJ etching process. With more specific reference to Fig. 1 shows a bottom electrode 16 formed on the substrate 10, which has a metal via 12 and an insulating layer 14 formed therein. Layers are then deposited on the bottom electrode to form a magnetic tunnel junction. For example, the pinned layer 18, the tunnel barrier layer 20, and the free layer 22 are deposited, followed by the top electrode 24. There may be one or more pinned, barrier, and / or free layers. Finally, a hard mask layer 26 is deposited over the top electrode.

[0012] Using a photoresist process, the MTJ stack is etched, such as by RIE, IBE or by a mixed RIE / IBE process, by forming a uniform size of the top electrode, free layer, tunnel barrier, pinned layer and bottom electrode, as in Fig. 1 shown.

[0013] After the MTJ etching process, the wafer is unloaded from the etching tool and exposed to the atmosphere. The MTJ sidewall can be damaged either during the etching process or by exposure to the atmosphere, causing sidewall oxidation. This sidewall damage leads to lower MR ratios and poorer magnetic properties (lower coercivity (Hc), lower energy barrier (Eb), higher critical write current (Ic), higher critical write voltage (Vc)), and also induces non-uniformity in electrical and magnetic performance. This type of sidewall damage worsens particularly with decreasing MTJ size.

[0014] A novel process for removing sidewall damage without reducing the size of the pinned layer is now described. A spacer 28 is deposited on the patterned MTJ stack, as shown in Fig. 2. The spacer may be a dielectric hard mask material, such as SiON, SiN, and SiO2, and may have a thickness of approximately between 10 and 500 nm.

[0015] Next, as in Fig. 3, the dielectric on the top and bottom portions of the MTJ stack is etched away vertically by RIE or IBE. Since the dielectric thickness D1 along the sidewalls is greater than the thickness D2 above the hard mask 28 and the substrate layer 14, the vertical RIE or IBE etches away the entire dielectric layer 28 on top of the hard mask and the substrate, and also etches or thins only the portion of the sidewall spacer 28 that covers the upper layers of the MTJ stack, including the top electrode and the free layer. The resulting spacers 29 are therefore tapered such that they are wider at the bottom of the stack and narrower at the top of the stack. This uneven sidewall coverage 29, which in Fig. 3 is the key feature of the present disclosure. RIE etching is typically performed at a vertical angle equal to 0. IBE etching can cover a range of angles from 0 to 40 degrees, depending on the feature size and device density. The process can be stopped by timing or endpoint detection.

[0016] In an existing process, IBE is applied directly to MTJ structures to trim away the damaged gap. The size of the entire MTJ stack, including the free layer and pinned layer, decreases during the process. At some point, the pinned layer becomes too small to maintain its internal magnetization state. In addition, since the IBE process is a purely physical etching process with no selectivity, redeposition of the pinned layer and bottom electrode material cannot be prevented.

[0017] In the process of the present disclosure, due to the patterned spacer 29, the IBE process described in Fig. 4, only the damaged section within the free layer is removed, leaving the pinned layer and bottom electrode intact and preventing the problems described above. The free layer is trimmed to size D6 to remove the surface-damaged section within it. The pinned layer and bottom electrode remain intact due to the protection provided by their stronger spacer, retaining their original sizes and avoiding redeposition. Since the tunnel barrier and pinned layer are larger than the free layer, any remaining damaged section along the sidewalls of the tunnel barrier and pinned layers does not affect the central sections of the tunnel barrier and pinned layer, which effectively interact with the free layer and are responsible for device performance.

[0018] The trimming step can be an IBE, RIE, or a combination process. The trimming step should be configured such that the damaged portion of the free layer is removed nearly horizontally. This angle can be adjusted with respect to feature size and device density. For an IBE trimming process, a large angle of approximately 30 to 80 degrees from the vertical is preferred. For an RIE trimming process, an angle substantially equal to 0 from the vertical is preferred. A combination IBE and RIE process uses their respective preferred angles. Because it is made of a similar material to the spacer layer, the horizontal mask layer 26 can be easily removed during the trimming step.

[0019] It should be noted here that the thickness of the initial spacer deposit can be adjusted according to the required trimming amount of the free layer. This is due to the fact that the former (D2 in Fig. 2) the thickness of the horizontal sidewall cover after spacer deposition (D3) is determined, which determines the remaining thickness of the horizontal sidewall cover after spacer etching (D4 in Fig. 3) and after trimming (D5 in Fig. 4). The RIE and IBE conditions, such as power, pressure, and gas type, can be adjusted to also control sidewall coverage.

[0020] The trimming process removes the damaged sidewall of the free layer without reducing the size of the pinned layer. It also eliminates the problem of redeposition from the pinned layer and the bottom electrode, as these layers are covered by the spacer layer, thus minimizing the problem of current shunting that results in low yields of MRAM chips. Furthermore, this spacer-assisted IBE and / or RIE trimming is a self-aligning process that does not require photolithography. It thus prevents overlay challenges when the size drops below subnanometer devices. This process is particularly useful for MRAM chips with a size smaller than 60 nm, as problems associated with damaged sidewalls and redeposition from the bottom electrode become very severe for MRAM chips with smaller sizes.

[0021] Multiple deposition and etch cycles can be used, if necessary, to ensure that all sidewall damage as well as the sidewall dielectric deposition is removed from the free layer, while leaving some dielectric on the bottom of the MTJ stack to cover the pinned layer.

[0022] In summary, a dielectric spacer layer is deposited after the MTJ stack has been patterned either by RIE, IBE, or a mixed RIE / IBE process. The dielectric layer on the top and bottom of the MTJ structures is removed during the subsequent etchback process by RIE or IBE, while the dielectric layer on the sidewall is only partially etched away. The top portion of the sidewall cap is removed or thinner than the bottom portion, resulting in a tapered spacer that is wider at the bottom near the pinned layer and narrower at the top near the free layer.Angle-dependent IBE and / or RIE etches the top free layer faster than the pinned bottom layer and the bottom electrode, which are protected by the tapered spacer, ensuring that all sidewall damage to the free layer is removed while keeping the pinned layer intact to maintain its high pinning strength for the internal magnetization state and prevent a shorted device due to redeposition. The initial thickness of the spacer deposition can be tuned according to the required amount of free layer trimming.

[0023] Although the preferred embodiment of the present disclosure has been illustrated and this form has been described in detail, it will be readily understood by those skilled in the art that various changes may be made therein without departing from the spirit of the disclosure.

Claims

[1] A method for etching a magnetic tunnel junction structure, MTJ structure, comprising: Providing a bottom electrode (16) on a substrate (10); Depositing a stack of MTJ layers on the bottom electrode (16) comprising, in this order, a pinned layer (18), a tunnel barrier layer (20) and a free layer (22); Providing a top electrode (24) on the stack of MTJ layers; Structuring the top electrode (24), the MTJ stack, and the bottom electrode (16) to form an MTJ device, wherein sidewall damage is formed on sidewalls of the MTJ device; conformally depositing a dielectric spacer layer (28) over the substrate (10) and the MTJ device; vertically etching away the dielectric spacer layer (28) on horizontal surfaces of the substrate (10) and the MTJ device, wherein the dielectric spacer layer (28) on the sidewalls of the MTJ device is partially etched away to form a tapered spacer (29) that is wider on the bottom electrode (16) and narrower or absent on the free layer (22), the tapered spacer (29) covering the tunnel barrier layer (20), the pinned layer (18), and the bottom electrode (16); and then removing the sidewall damage from the free layer (22) and forming a tapered tunnel barrier layer (20) by applying a horizontal physical etch to the MTJ device, wherein the pinned layer (18) and the bottom electrode (16) are protected from the physical etching by the tapered spacer (29). [2] The method of claim 1, wherein the MTJ stack is patterned by a chemical, physical, or combination etching process comprising one of the following: reactive ion etching, RIE, ion beam etching, IBE, or a combination of RIE and IBE. [3] The method of claim 2, wherein the MTJ stack is patterned by reactive ion etching in which high energy ions remove materials vertically in the areas not masked by a photoresist, and wherein the sidewall damage is formed by the high energy ions reacting laterally with the unremoved materials. [4] The method of claim 2, wherein the sidewall damage is formed after the chemical or physical etching process when the MTJ device is exposed to the atmosphere, causing sidewall oxidation. [5] A method according to any one of the preceding claims, wherein the dielectric spacer layer (28) comprises hard mask materials. [6] A method according to any one of the preceding claims, wherein the horizontal physical etching is an angle-dependent RIE, IBE or a combination with an IBE angle from the vertical between about 30 and 80 degrees and an RIE angle from the vertical of 0 degrees. [7] The method of any preceding claim, wherein the steps of depositing the dielectric spacer layer (28), etching the dielectric spacer layer (28), and removing the sidewall damage are repeated as needed to ensure that all of the sidewall damage and all of the dielectric spacer layer (28) are removed from the free layer (22) while some of the dielectric spacer layer (28) covers the pinned layer (18). [8] A method for etching a magnetic tunnel junction structure, MTJ structure, comprising: providing a stack of MTJ layers on a substrate (10) comprising a bottom electrode (16) on the substrate (10), a pinned layer (18), a tunnel barrier layer (20), a free layer (22), a top electrode (24) and a hard mask layer (26) in this order on the bottom electrode (16); Patterning the MTJ stack to form an MTJ device, wherein sidewall damage is formed on sidewalls of the MTJ device; conformally depositing a dielectric spacer layer (28) over the substrate (10) and the MTJ device; vertically etching away the dielectric spacer layer (28) on horizontal surfaces of the substrate (10) and the MTJ device, wherein the dielectric spacer layer (28) on the sidewalls of the MTJ device is partially etched away, wherein the remaining dielectric spacer layer (28) on sidewalls of the MTJ device covers the tunnel barrier layer (20), the pinned layer (18), and the bottom electrode (16), and wherein the remaining dielectric spacer layer (28) is removed from the free layer (22) or is thinner on the free layer (22) than on the pinned layer (18) and the bottom electrode (16); and then removing the sidewall damage from the free layer (22) and forming a tapered tunnel barrier layer (20) by applying an angle-dependent ion beam etch, IBE, to the MTJ device, wherein the pinned layer (18) and the bottom electrode (16) are protected from the ion beam etching by the dielectric spacer layer (28). [9] The method of claim 8, wherein the MTJ stack is patterned by a chemical, physical, or combination etching process comprising one of the following: reactive ion etching, RIE, ion beam etching, IBE, or a combination of RIE and IBE. [10] The method of claim 9, wherein the MTJ stack is patterned by reactive ion etching in which high energy ions remove materials vertically in the areas not masked by a photoresist, and wherein the sidewall damage is formed by the high energy ions reacting laterally with the unremoved materials. [11] The method of claim 9, wherein the sidewall damage is formed after the chemical or physical etching process when the MTJ device is exposed to the atmosphere, causing sidewall oxidation. [12] The method of any one of claims 8 to 11, wherein the dielectric spacer layer (28) comprises a hard mask material including SiON, SiN and SiO2. [13] A method according to any one of claims 8 to 12, wherein the angle-dependent IBE has an angle from the vertical of about 30 and 80 degrees. [14] The method of any one of claims 8 to 13, wherein the steps of depositing the dielectric spacer layer (28), etching the dielectric spacer layer (28) and removing the sidewall damage are repeated as needed to ensure that all of the sidewall damage and all of the dielectric spacer layer (28) are removed from the free layer (22) while some of the dielectric spacer layer (28) covers the pinned layer (18). [15] A method for etching a magnetic tunnel junction structure, MTJ structure, comprising: Providing a stack of MTJ layers on a substrate (10) comprising a bottom electrode (16) on the substrate (10), a pinned layer (18), a tunnel barrier layer (20), a free layer (22), a top electrode (24), and a hard mask layer (26) in this order on the bottom electrode (16); Patterning the MTJ stack to form an MTJ device, wherein sidewall damage is formed on sidewalls of the MTJ device; conformally depositing a dielectric spacer layer (28) over the substrate (10) and the MTJ device; vertically etching away the dielectric spacer layer (28) on horizontal surfaces of the substrate (10) and the MTJ device, wherein the dielectric spacer layer (28) on the sidewalls of the MTJ device is partially etched away, wherein the remaining dielectric spacer layer (28) on sidewalls of the MTJ device covers the tunnel barrier layer (20), the pinned layer (18), and the bottom electrode (16), and wherein the remaining dielectric spacer layer (28) is removed from the free layer (22) or is thinner on the free layer (22) than on the pinned layer (18) and the bottom electrode (16); and then removing the sidewall damage from the free layer (22) and forming a tapered tunnel barrier layer (20) by applying a horizontal physical etch to the MTJ device, wherein the pinned layer (18) and the bottom electrode (16) are protected from the physical etching by the dielectric spacer layer (28). [16] The method of claim 15, wherein the MTJ stack is patterned by a chemical, physical, or combination etching process comprising one of the following: reactive ion etching, RIE, ion beam etching, IBE, or a combination of RIE and IBE. [17] The method of claim 16, wherein the sidewall damage is formed by exposing the MTJ device to the atmosphere after the chemical or physical etching process, causing sidewall oxidation; or wherein the MTJ stack is patterned by reactive ion etching in which high-energy ions remove materials vertically in the areas not masked by a photoresist, and wherein the sidewall damage is formed by the high-energy ions reacting laterally with the unremoved materials. [18] The method of any one of claims 15 to 17, wherein the dielectric spacer layer (28) comprises a hard mask material including SiON, SiN and SiO2. [19] The method of any one of claims 15 to 18, wherein the horizontal physical etching is an angle-dependent RIE, IBE, or a combination having an IBE angle from the vertical between about 30 and 80 degrees and an RIE angle from the vertical of 0 degrees. [20] The method of any one of claims 15 to 19, wherein the steps of depositing the dielectric spacer layer (28), etching the dielectric spacer layer (28), and removing the sidewall damage are repeated as needed to ensure that all of the sidewall damage and all of the dielectric spacer layer (28) are removed from the free layer (22) while some of the dielectric spacer layer (28) covers the pinned layer (18).

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