Ferroelectric 2T1C random access memory cell

Abstract

A memory device (100, 200, 600) comprising: an array (202) of ferroelectric random access memory cells (102, 204, 602), wherein at least one ferroelectric random access memory cell (102, 204, 602) comprises: a first transistor (106, 606) coupled between a bit line (BL) and a storage node (SN); a second transistor (108, 608) coupled between a reference line (BLB) and the storage node (SN); and a ferro-capacitor (104, 604) coupled between the storage node (SN) and a plate line, wherein the ferroelectric random access memory cell (102, 204, 602) is configured to generate a bit-level reference, wherein a reference voltage on the reference line (BLB) is derived from a non-switched (U-term) of the ferro-capacitor (104, 604) of the same ferroelectric random access memory cell (102, 204, 602) in comparison with a data voltage on the bit line (BL) during a read cycle.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is an international application of U.S. Patent Application No. 15 / 714,912, filed September 25, 2017, which claims the benefit of priority under 35 USC 119(e) of U.S. Provisional Patent Application Ser. No. 62 / 519,042, filed June 13, 2017. FIELD OF THE INVENTION

[0002] This disclosure relates generally to semiconductor memories, and more particularly to a ferroelectric random access memory (F-RAM) comprising two-transistor, one-capacitor F-RAM cells having improved signal margins, and methods of operating the same. STATE OF THE ART

[0003] Ferroelectric random access memories (FRAM) or storage devices typically comprise a grid or array of storage elements or cells, each comprising at least one ferroelectric capacitor or ferrocapacitor and one or more associated transistors for selecting the cell and controlling reading or writing. The ferrocapacitor comprises a ferroelectric material, such as lead zirconate titanate (PZT), which has a crystal structure with a dipole exhibiting two equal and stable polarization states. When an external electric field is applied to the ferrocapacitor, dipoles in the ferroelectric material become aligned, or polarized, in the field direction. After the electric field is removed, the dipoles retain their polarization state.This polarization state is read by applying a voltage to the ferrocapacitor via a plate line and an enabled bit line, which is initially precharged to 0 V. The amount of charge generated depends on whether the electric field produced by the applied voltage causes the polarization state of the ferroelectric material to switch. For example, the response of the ferrocapacitor when the polarization is not switched, known as the unswitched or U term, is linear, or proportional, to the applied voltage and, when a data line is connected to the non-inverting side of a sense amplifier and compared to a reference voltage, results in a data '0'.When the polarization is switched, known as the polarization switching or P-term, the response of the ferro-capacitor is non-linear, typically at least twice the U-term, and when the data line is connected to the non-inverting side of a sensor amplifier and compared to the reference voltage, results in the data '1'.

[0004] DE 198 33 570 A1 discloses a multi-port memory capable of operating at higher speeds while minimizing the adverse effect of a neighboring bit line due to parasitic capacitance. The multi-port memory includes complementary write data lines and a read data line, with the read data line sandwiched between the complementary write data lines.In a memory in which one terminal is a first terminal used exclusively for writing and the other terminal is a second terminal used exclusively for reading, and a group of bit lines includes complementary write data lines associated with the first terminal and a read data line associated with the second terminal, the complementary write data lines function as shield lines to minimize the adverse effect of noise or disturbances on the read data line. When the same column is accessed through the first terminal and the second terminal, one of the potentials on the complementary write data lines is driven high and the other is driven low. Adverse effects on the read data line are therefore canceled and thus minimized.In a memory with two groups of bit lines, each containing complementary write data lines and one read data line, the complementary write data lines belonging to each group are arranged to enclose the read data line belonging to the same group. In this case, the write data lines and the read data line belonging to the same group are not used simultaneously. During reading, the potentials on the write data lines on both sides of the read data line are fixed to specific values, and the write data lines on both sides of the read data line act as shield lines.

[0005] US 2010 / 0 246 238 A1 describes an array of ferroelectric memory cells that enables imprint attenuation. The array includes ferroelectric memory cells, each coupled to word lines, plate lines, and bit lines; a word line driver for driving the word lines; a plate line driver for driving the plate lines; a bit line driver for driving the bit lines; and an isolation device driver for driving isolation devices coupled between the bit lines and a plurality of bit lines.The imprinting mitigation method includes coupling the bit lines to a respective plurality of sense amplifiers, turning on a word line and pulsing a plate line associated with a row of ferroelectric memory cells, disconnecting the bit lines from the respective sense amplifiers, driving the plate line low and the bit lines high, driving the plate line high and the bit lines low, driving the plate line low and floating the bit lines, driving the bit lines with the sense amplifier, and turning off the word line and precharging the bit lines. The method can be performed after each memory access or at any time using a counter and a regeneration command.

[0006] A problem with conventional F-RAM devices is that the exact values ​​of the P-term and U-term can vary for each cell in the array due to process variations during device manufacturing. Thus, the existing F-RAM design, which uses a global reference voltage, is programmed to lie between the weakest U-term (which has the highest charge) and the weakest P-term (which has the lowest charge) of any F-RAM cell in the device. Furthermore, these values ​​of the weakest U-term and P-term can vary over the device's lifetime due to changes in temperature, voltage, and the number of read and / or write cycles the device has been subjected to.Thus, an effective F-RAM signal margin in conventional F-RAM devices is generally low and decreases with increasing use, resulting in reliability problems and shorter operating lifetime.

[0007] Accordingly, there is a need for an improved memory device utilizing F-RAM cells and methods of operating the same to maximize signal margin and extend the operating lifetime of the device. OVERVIEW

[0008] The present invention relates to a memory device according to claim 1. Advantageous embodiments may comprise features of dependent claims. A non-volatile semiconductor memory device and methods of operating the same are provided. According to embodiments, the memory device comprises an array of F-RAM cells. Generally, each F-RAM cell comprises a first or access transistor coupled between a bit line and a storage node (SN), a second or reference transistor coupled between a reference line and the SN, and a ferroelectric capacitor or ferro-capacitor coupled between the SN and a plate line.The device further includes a sense amplifier (SA) coupled to the bit line and the reference line for comparing a data voltage on the bit line with a reference voltage on the reference line, and a processing element configured to output control signals to the access transistor, the reference transistor, and the SA, and to apply voltage pulses to the plate line. Generally, the F-RAM cell is configured according to a bit-level reference scheme, wherein two pulses are applied to the plate line during a read cycle, and wherein a first of the two pulses is used as a data pulse, and a second of the two pulses is used as a reference pulse and an erase pulse.

[0009] According to one embodiment, the processing element is configured to apply a first pulse having a first peak voltage (V1) to the plate line during the read cycle to couple data from the SN to the bit line, and to apply a second pulse having a second peak voltage (V2) to the plate line to couple the reference voltage to the reference line and to serve as an erase pulse to solidify a U term in the ferro-capacitor.

[0010] Further features and advantages of embodiments of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. SHORT DESCRIPTION OF THE CHARACTERS

[0011] Embodiments of the invention will now be described, by way of example only, with reference to the accompanying schematic drawings, in which corresponding reference symbols indicate corresponding parts. Furthermore, the accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the invention and to enable any person skilled in the art to make and use the invention. Fig. 1 is a schematic block diagram of a portion of a memory device including a sense amplifier, precharge circuits, and an embodiment of a two-transistor, one-ferroelectric capacitor F-RAM cell (2T1C F-RAM cell); Fig. 2 is a block diagram of one embodiment of a memory device including a processing element and an array of 2T1C F-RAM cells; Fig. 3 is a timing diagram for describing one embodiment of a read cycle associated with the 2T1C F-RAM cell of Fig. 1 is associated; Fig. 4 is a timing diagram for describing another embodiment of a read cycle used with the 2T1C F-RAM cell of Fig. 1, wherein the memory device is configured to provide a span shift capability; Fig. 5 is a timing diagram for describing yet another embodiment of a read cycle associated with the 2T1C F-RAM cell of Fig. 1, wherein the memory device is configured to provide span shift capability and simultaneous reference pulse and sensor amplifier activation signals; Fig. 6 is a schematic block diagram of a portion of a memory device including 2T1C F-RAM cells and wherein a capacitance of the bit line is greater than the capacitance of the reference line; Fig. Figure 7 is a timing diagram for describing one embodiment of a read cycle associated with the 2T1C F-RAM cell of Fig. 6 is associated; Fig. Figure 8 is a timing diagram for describing another embodiment of a read cycle used with the 2T1C F-RAM cell of Fig. 6, wherein the memory device is configured to provide span shifting capability; Fig. 9 is a timing diagram for describing yet another embodiment of a read cycle associated with the 2T1C F-RAM cell of Fig. 1, wherein the memory device is configured to provide span shift capability and simultaneous reference pulse and sensor amplifier activation signals; and Fig. Figure 10 is a graph illustrating an improvement in F-RAM signal margin with a cell-generated reference voltage that tracks the bit-level U term over a fixed, global reference voltage.

[0012] The features and advantages of embodiments of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings. In the drawings, like reference numerals generally indicate identical, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION

[0013] This specification discloses one or more embodiments incorporating the features of this invention. The disclosed embodiment(s) are merely illustrative of the present invention. The scope of the present invention is not limited to the disclosed embodiment(s). The present invention is defined by the appended claims.

[0014] The described embodiment(s) and reference in the specification to "an embodiment," "an embodiment," etc., indicate that the described embodiment(s) may include particular features, structures, or properties, but not every embodiment necessarily includes the particular features, structures, or properties. Furthermore, such phrases do not necessarily refer to the same embodiment. Further, it is understood that where particular features, structures, or properties are described in connection with one embodiment, one skilled in the art will be able to implement such features, structures, or properties in connection with other embodiments, whether explicitly described or not.

[0015] Before describing the various embodiments in more detail, further explanations should be given with regard to certain terms that may be used throughout the patent specification.

[0016] The terms "ferroelectric random access memory cell" or "F-RAM cell" are used herein to describe an electronic circuit having a single memory cell comprising one or more transistors and a ferroelectric capacitor or ferrocapacitor coupled between a storage node (SN) and a plate line, and which stores a bit of binary information by switching polarization states of a ferroelectric material in the ferrocapacitor.

[0017] The term “1T1C” as used herein refers to an F-RAM cell architecture that includes a single transistor and a single ferro-capacitor.

[0018] The term “2T1C” as used herein refers to an architecture of an F-RAM cell comprising two transistors, i.e., a first or access transistor and a second or reference transistor, and a single ferro-capacitor.

[0019] The terms "F-RAM device" or "memory device" are used herein to generally describe a memory device comprising: an array of F-RAM cells, and a number of sense amplifiers (SA) coupled to the array via data lines or bit lines and reference lines for comparing a data voltage on the bit line with a reference voltage on the reference line; and one or more processing elements or controllers configured to output control signals to the access transistor, the reference transistor, and the SA, to apply voltages to the bit lines and reference lines, and to apply voltage pulses to a plate line of the ferro-capacitor. The processing elements may include registers, multiplexers, command and address circuits, timing controllers, and error check circuits.The processing elements, SA, and array may be integrally formed on a single integrated circuit (IC) or may comprise a number of externally coupled discrete devices or ICs.

[0020] "U-term" as used herein refers to a linear, charge-induced response of the ferro-capacitor when the polarization state is not switched during a read cycle, and which results in data '0' when the bit line is connected to a non-inverting side of the SA.

[0021] "P-term," as used herein, refers to a nonlinear, charge-induced response of the ferro-capacitor due to polarization switching during a read cycle, resulting in data '1' when the bit line is connected to a non-inverting side of the SA. Generally, the magnitude of the P-term is at least twice (2) that of the U-term.

[0022] Finally, the reference voltage is a voltage applied to the SA for comparison with the data voltage generated by the ferro capacitor. The data voltage is generated as a result of applying the first voltage (V1) to a switching or non-switching ferro capacitor. The reference voltage is generated as a result of applying the second voltage (V2) to a non-switching ferro capacitor. The V2 voltage is adjusted accordingly, typically higher than the V1 voltage, to create a reference voltage that is higher than the U-term voltage and lower than the P-term voltage.

[0023] Before describing in more detail the operation of a memory device including an F-RAM cell according to embodiments of the present invention, it is helpful to present an F-RAM memory cell and environment in which the present embodiments may be implemented.

[0024] Fig. 1 illustrates a schematic block diagram of a portion of a memory device 100 including a 2T1C F-RAM cell 102 according to an embodiment of the present disclosure. With reference to Fig. 1, the F-RAM cell 102 includes: a single ferro-capacitor 104 coupled between a storage node (SN) and a plate line (PL); a first or access transistor 106 coupled between the SN and a data line or bit line BL and controlled by a first word line (WL1); and a second or reference transistor 108 coupled between the SN and a reference line BL and controlled by a second word line (WL2). The 2T1C F-RAM cell 102 uses two voltage pulses applied to the plate line PL during a read operation to generate a bit-level reference, wherein a data voltage of the F-RAM cell is compared to a reference voltage based on the U-term of the same cell, i.e., a first voltage pulse (1st pulse) is used to generate a data voltage, and a second voltage pulse (2nd pulse) is used to generate a data voltage.Pulse) is used to generate the cell reference voltage and at the same time can take on the role of a quenching signal for the ferro-capacitor in order to solidify a U-term in the ferro-capacitor.

[0025] As in Fig. 1, the memory device 100 further includes a sense amplifier (SA) 110 for comparing a data voltage on the bit line BL with a reference voltage on the reference line BLB, a first or bit line precharge circuit 112, and a second or reference line precharge circuit 114. The bit line precharge circuit 112 is controlled by a processing element (not shown in this figure) and is configured to precharge and enable the bit line BL before the 1st pulse is applied to the plate line. Preferably, the bit line precharge circuit 112 and the processing element are further configured to discharge any residual voltage on the SN before the 1st pulse. The reference line precharge circuit 114 is also controlled by the processing element and is configured to discharge any residual voltage on the SN and enable the reference line before the 2nd pulse is applied to the plate line.

[0026] It will be appreciated that the use of two transistors, i.e., access transistor 106 and reference transistor 108, to sequentially couple the SN first to bit line BL and then to reference line BLB enables a read operation in which precharging of the bit line between the first and second voltage pulses is not required, thereby optimizing the operating frequency of the memory device.In addition, the generated reference voltage for each bit stored in the F-RAM cell 102 tracks the changes in the U-term of the same cell (ferro-capacitor 104), whether those changes are due to process variations in the cell's manufacturing, changes in temperature, or wear-and-tear stresses such as continuous cycling and data retention at high temperatures over an operational lifetime of the memory device 100, thereby providing a higher F-RAM signal margin and improving or maximizing the lifetime of the memory device compared to conventional 1T1C F-RAM cells that use a global reference voltage.

[0027] Fig. 2 illustrates a simplified block diagram of a memory device 200 comprising an array 202 of 2T1C F-RAM cells 204 according to an embodiment of the present disclosure arranged in a number of rows 206, each row sharing a first word line (WL1) and a second word line (WL2), and arranged in a number of columns 208, with cells in each column having a common data line or bit line (BL) and a reference line BLB. It should be understood, although not shown, that cells 204 in adjacent columns may share a bit line (BL) or reference line (BLB) to reduce the number of lines required and the resulting size of the array 202. With reference to Fig. 2, the memory device 200 further includes a controller or processing element 210, such as a microcontroller, a microprocessor, or a state machine, for issuing commands or control signals to each of the F-RAM cells 204 and to other peripheral circuitry to read or write to the memory array. Generally, the peripheral circuitry includes, as in the embodiment in Fig. 2, further comprising a row decoder 212, a column decoder 214 and a sensor amplifier / driver 216.

[0028] When a data word is to be stored or written to memory device 200, row decoder 212 selects a row of array 202 and applies an appropriately terminated control signal to the first word lines (WL1) of F-RAM cells 204 in the selected row. Column decoder 214 converts a column address and couples a data voltage from sense amplifier / driver 216 to bit line BL of each F-RAM cell 204, while processing element 210 couples bit line BL to the SN in the F-RAM cell. When BL is a logic '1' and 0 V is applied to plate line (PL), a logic '1' is written to the F-RAM cell. When the BL is logic '0' and 0 V is applied to the plate line (PL), the F-RAM cell is not repolarized and therefore remains U-term or logic '0', generated by the erase pulse during the read operation.

[0029] In general, when a data word is to be retrieved or read from the memory device 200, the row decoder 212 converts a row address by applying appropriately terminated control signals to the first and second word lines (WL1 and WL2) of F-RAM cells 204 in a selected row of the array 202. The column decoder 214 converts a column address by coupling a data voltage from the bit line BL of each F-RAM cell 214 in the selected row, generated by a first pulse applied to the plate line (PL) of the ferro-capacitor (not shown in this figure) in the cell, to the sense amplifier / driver 216 and then coupling a reference voltage from the reference line BLB of the same cell row, generated by a second pulse applied to the plate line (PL).The sense amplifier / driver 216 compares the data voltage of each F-RAM cell 204 in the selected row with the reference voltage of the same cell to determine whether a logic '0' or '1' was read from the cell.

[0030] A read cycle for reading a data bit from the F-RAM cell 102 from Fig. 1 according to an embodiment of the present disclosure will now be described with reference to Fig. 1 to 3 are described in more detail. With reference to Fig. 1, in this embodiment, the memory device 100 and the F-RAM cell 102 are configured such that a capacity (C BL ) of the bit line BL is substantially equal to or the same as a capacitance (C BLB ) of the reference line BLB. With reference to Fig. 3, the magnitude of a first peak voltage (V1) of the 1st pulse applied to the plate line to couple data from the SN to the bit line BL is lower than a second peak voltage (V2) of the 2nd pulse applied to the plate line to couple a reference voltage to the reference line.

[0031] With reference to Fig. 3, at a time t0, a PreQ_BL signal is applied to the bit line precharge circuit 112 by the processing element 210 to turn ON the bit line precharge circuit 112 and precharge the bit line BL to a predetermined voltage, for example, 0 V.

[0032] From time t0 to time t1, a control signal WL1 is applied to the word line WL1 to turn ON the access transistor 106 from a standard static timing, while the bit line precharge circuit 112 remains ON to discharge any internal residual voltage from the storage node SN.

[0033] From time t1 to time t2, the bit line precharge circuit 112 is turned OFF to enable the bit line BL, followed by the application of a first or data pulse having a peak voltage of V1 to the plate line of the F-RAM cell 102, thereby applying an electric field to the ferro capacitor 104 and developing a subsequent bit line voltage (V BL ) results in: VBL=(V1*CF) / (CF+CBL), where V BL is the bit line voltage, V1 is the peak voltage of the 1st pulse, C BL is a capacitance of the bit line and C F is a capacitance of the ferro-capacitor 104, the value of which depends on whether the polarization state of the ferroelectric material in the ferro-capacitor is switched (P-term, logical '1') or not switched (U-term, logical '0') by the application of the electric field.

[0034] From time t2 to time t3, the bit line voltage V BL from a pulse-on data voltage to a post-pulse data voltage (up-down data voltage) (U UD or P UD ), depending on whether the polarization state of the ferroelectric material in the ferro-capacitor 104 is switched (P UD ) or not switched (U UD ). The word line WL1 is turned OFF, thereby decoupling the bit line BL from the SN, followed by a control signal WL2 being applied to the word line WL2 to turn the reference transistor 108 ON from a standard static timing, while the reference line precharge circuit 114 remains ON to discharge any residual internal voltage from the storage node SN.

[0035] From time t3 to time t4, the reference line precharge circuit 114 is turned OFF to enable the reference line BLB, followed by the application of a second pulse having a peak voltage of V2 to the plate line of the F-RAM cell 102. Note that the direction of the electric field applied to the ferro-capacitor 104 as a result of the second pulse is the same as that of the first pulse. Thus, the polarization of the ferro-capacitor 104 is not switched, and the second pulse acts as a reference pulse to apply a subsequent reference voltage (V BLB ) to generate: BBLB=(V2*CFU) / (CFU+CBLB), where V BLB is the reference line voltage, V2 is the peak voltage of the 2nd pulse, C BLB is a capacitance of the reference line BLB and C FUis a capacitance of the ferro-capacitor 104 in a non-switched (U-term) polarization state. It should also be noted that since the ferro-capacitor 104 remains non-switched, the second pulse also functions as a quenching pulse.

[0036] Finally, from time t4 to time t5, the word line WL2 turns the reference transistor 108 OFF, thereby decoupling the reference line BLB from the SN, and an SA activation signal is applied to the SA 110 by the processing element 210 to allow the data voltage (U UD or P UD ) on the bit line BL and the reference voltage of the same cell 102, which is based on the U term of the ferro capacitor 104 in which SA are latched.

[0037] A read cycle to read a data bit from the F-RAM cell from Fig. 1 according to another embodiment of the present disclosure will now be described with reference to Fig. 1, Fig. 2 and Fig. 4 described in more detail. With reference to Fig. 1, the memory device 100 and the F-RAM cell 102 are again configured such that a capacity (C BL ) of the bit line BL is substantially equal to or the same as a capacitance (C BLB ) of the reference line BLB. With reference to Fig. 4, in this embodiment, the memory device 100 and the F-RAM cell 102 are configured to provide a range shift capability, wherein the magnitude of the voltage V2 of the 2nd pulse is variable or shifted in the range from 0 V to greater than V1, the peak voltage of the 1st pulse, V2: 0 V to > V1. Thus, the level of the data voltage (V BL ), which is either U UD or P UD can be determined depending on whether the polarization is switched or not.

[0038] With reference to Fig. 4, at a time t0, a PreQ_BL signal is applied to the bit line precharge circuit 112 to precharge the bit line BL to a predetermined voltage, for example, 0 V.

[0039] From time t0 to time t1, a control signal WL1 is applied to turn ON the access transistor 106, while the bit line precharge circuit 112 also remains ON, thereby discharging any internal residual voltage from the storage node SN.

[0040] From time t1 to time t2, the bit line precharge circuit 112 is turned OFF to enable the bit line BL, followed by applying a 1st pulse having a peak voltage of V1 to the plate line of the F-RAM cell 102, which generates a bit line voltage (V BL ) of (V1 * C F ) / (C F + C BL ) results.

[0041] From time t2 to time t3, the bit line voltage V BLfrom a pulse-on data voltage to a post-pulse data voltage (up-down data voltage) (U UD or P UD ) depending on whether the polarization state of the ferroelectric material in the ferro-capacitor 104 has been switched, and the word line WL1 is turned OFF, thereby decoupling the bit line BL from the SN, followed by the application of a control signal to the word line WL2 to turn the reference transistor 108 ON. The reference line precharge circuit 114 remains ON to discharge any residual internal voltage from the storage node SN.

[0042] From time t3 to time t4, the reference line precharge circuit 114 is turned OFF to enable the reference line BLB, followed by the application of a second pulse to the plate line of the F-RAM cell 102, which has a peak voltage of V2 shifted from 0 V to > V1. As in the above-described Fig. 3, the polarization of the ferro-capacitor 104 remains unswitched and the 2nd pulse acts as a reference pulse to generate a subsequent reference voltage (V BLB ) to generate: VBLB=(V2*CFU) / (CFU+CBLB), where V BLB is the reference line voltage, V2 is the peak voltage of the 2nd pulse, C BLB is a capacitance of the reference line BLB and C FU is a capacitance of the ferro-capacitor 104 in a non-switched (U-term) polarization state. The variable voltage V2 of the 2nd pulse, where the voltage can be shifted from 0 V to > V1, adds the ability to control the level of the data voltage (U UD or P UD ). It should also be noted that since the ferro-capacitor 104 remains switched, the 2nd pulse also functions as a quenching pulse.

[0043] Finally, from time t4 to time t5, the word line WL2 turns the reference transistor 108 OFF, thereby decoupling the reference line BLB from the SN, and an SA activation signal is applied to the SA 110 by the processing element 210 to allow the data voltage (U UD or P UD ) on the bit line BL and the reference voltage (U UD + ) are cached in the SA.

[0044] A read cycle to read a data bit from the F-RAM cell from Fig. 1 according to yet another embodiment of the present disclosure will now be described with reference to Fig. 1, Fig. 2 and Fig. 5. As with the above-mentioned Fig. 3 and Fig. 4, the memory device 100 and the F-RAM cell 102 are configured such that a capacitance (C BL) of the bit line BL is substantially equal to or the same as a capacitance (C BLB ) of the reference line BLB.

[0045] However, with regard to Fig. 5, in this embodiment, the memory device 100 and the F-RAM cell 102 are configured to provide a range shift capability, wherein the magnitude of the voltage V2 of the 2nd pulse is variable or shifted upward in the range from 0 V to > V1, and the SA activation signal is applied to the SA 110 during or simultaneously with the 2nd pulse, thereby eliminating the period from time t4 to time t5 and increasing an operating frequency of the memory device 100 / 200.

[0046] With reference to Fig. 5, at a time t0, a PreQ_BL signal is applied to the bit line precharge circuit 112 to precharge the bit line BL to a predetermined voltage, for example, 0 V.

[0047] From time t0 to time t1, a control signal WL1 is applied to turn ON the access transistor 106, while the bit line precharge circuit 112 also remains ON, thereby discharging any internal residual voltage from the storage node SN.

[0048] From time t1 to time t2, the bit line precharge circuit 112 is turned OFF to enable the bit line BL, followed by applying a 1st pulse having a peak voltage of V1 to the plate line of the F-RAM cell 102, which generates a bit line voltage (V BL ) of (V1 * C F ) / (C F + C BL ) results.

[0049] From time t2 to time t3, the bit line voltage V BL from a pulse-on data voltage to a post-pulse data voltage (up-down data voltage) (U UD or P UD) depending on whether the polarization state of the ferroelectric material in the ferro-capacitor 104 has been switched, and the word line WL1 is turned OFF, thereby decoupling the bit line BL from the SN, followed by the application of a control signal to the word line WL2 to turn the reference transistor 108 ON. The reference line precharge circuit 114 remains ON to discharge any residual internal voltage from the storage node SN.

[0050] From time t3 to time t4, the reference line precharge circuit 114 is turned OFF to enable the reference line BLB, followed by the application of a second pulse to the plate line of the F-RAM cell 102, which has a peak voltage of V2 shifted from 0 V to > V1. In addition, as described above, during or simultaneously with the second pulse, the SA enable signal is applied to the SA 110 to enable the data voltage (U UD or P UD) on the bit line BL and the reference voltage (U UO ) are temporarily stored in the SA 110, thereby eliminating the period from time t4 to time t5 and increasing an operating frequency of the memory device 100 / 200. Finally, the word line WL2 turns the reference transistor 108 OFF, thereby decoupling the reference line BLB from the SN.

[0051] Fig. 6 illustrates a portion of a memory device 600 including a 2T1C F-RAM cell 602 according to another embodiment of the present disclosure, wherein a capacitance of the bit line is greater than the capacitance of the reference line. Referring to Fig. 6, the F-RAM cell 602 includes: a single ferro capacitor 604 coupled between a storage node (SN) and a plate line (PL); a first or access transistor 606 coupled between the SN and a data line or bit line BL and controlled by a first word line (WL1); and a second or reference transistor 608 coupled between the SN and a reference line BLB and controlled by a second word line (WL2). The memory device 600 further includes a sense amplifier 610, a first or bit line precharge circuit 612, a second or reference line precharge circuit 614, and an additional bit line capacitance (C ADD ). The additional bit line capacitance can be used as in Fig. 6, may comprise one or more discrete capacitors coupled to the bit line BL or may comprise an intrinsic capacitance formed between the bit line BL and an electrical ground of a substrate (not shown) or an IC on which the memory device 600 is fabricated. Since the additional bit line capacitance (C ADD ) increases the total capacitance of the bit line BL, this is greater than or equal to the capacitance of the reference line BLB, (C BL + C ADD ) ≥ C BLB The aim of this cell configuration is to reduce the complexity of the PL source voltage, since the reference voltage can be generated such that V2 is equal to the voltage V1, which, however, results in the P-term margin being less than or equal to (V1 * C F ) / (C F + C BL + C ADD ) is.

[0052] A read cycle to read a data bit from the F-RAM cell from Fig. 6 according to an embodiment of the present disclosure will now be described with reference to the Fig. 2, Fig. 6 and Fig. 7 described in more detail. With reference to Fig. 6, the memory device 600 and the F-RAM cell 602 are again configured such that the additional bit line capacitance (C ADD ) increases the total capacitance of the bit line BL so that it is larger than the capacitance of the reference line BLB, (C BL + C ADD ) ≥ C BLB However, with regard to Fig. 7 in this embodiment, the magnitude of a first peak voltage (V1) of the 1st pulse is equal to or substantially the same as the magnitude of a second peak voltage (V2) of the 2nd pulse.

[0053] With reference to Fig. 6, at a time t0, a PreQ_BL signal is applied to the bit line precharge circuit 612 by the processing element 210 to turn ON the bit line precharge circuit and precharge the bit line BL to a predetermined voltage, for example, 0 V.

[0054] From time t0 to time t1, a control signal WL1 is applied to the word line WL1 to turn ON the access transistor 606 from a standard static timing, while the bit line precharge circuit 612 remains ON to discharge any internal residual voltage from the storage node SN.

[0055] From time t1 to time t2, the bit line precharge circuit 612 is turned OFF to enable the bit line BL, followed by applying a first or data pulse having a peak voltage of V1 to the plate line of the F-RAM cell 602, thereby applying an electric field to the ferro capacitor 604 and developing a subsequent bit line voltage (V BL ) results in: VBL=(V1*CF) / (CF+CBL+CADD), where V BL is the bit line voltage, V1 is the peak voltage of the 1st pulse, C BL is a capacitance of the bit line BL, C ADD is the additional bit line capacitance and C F is a capacitance of the ferro-capacitor 604, the value of which depends on whether the polarization state of the ferroelectric material in the ferro-capacitor is switched (P-term) or not switched (U-term).

[0056] From time t2 to time t3, the bit line voltage V BLfrom a pulse-on data voltage to a post-pulse data voltage (up-down data voltage) (U UD- or P UD- ), depending on whether the polarization state of the ferroelectric material in the ferro-capacitor 604 is switched (P UD- ) or not switched (U UD- ). The word line WL1 is turned OFF, thereby decoupling the bit line BL from the SN, followed by a control signal WL2 being applied to the word line WL2 to turn the reference transistor 608 ON from a standard static timing, while the reference line precharge circuit 614 remains ON to discharge any residual internal voltage from the storage node SN.

[0057] From time t3 to time t4, the reference line precharge circuit 614 is turned OFF to enable the reference line BLB, followed by the application of a second pulse having a peak voltage of V2 to the plate line of the F-RAM cell 602. Note that the direction of the electric field applied to the ferro-capacitor 604 as a result of the second pulse is the same as that of the first pulse. Thus, the polarization of the ferro-capacitor 604 is not switched, and the second pulse acts as a reference pulse to apply a subsequent reference voltage (V BLB ) to generate: VBLB=(V2*CFU) / (CFU+CBLB), where V BLB is the reference line voltage, V2 is the peak voltage of the 2nd pulse and is equal to V1, C BLB is a capacitance of the reference line BLB and C FUis a capacitance of the ferro-capacitor 604 in a non-switched (U-term) polarization state. It should also be noted that since the ferro-capacitor 604 remains non-switched, the second pulse also functions as a quenching pulse.

[0058] Finally, from time t4 to time t5, the word line WL2 turns the reference transistor 608 OFF, thereby decoupling the reference line BLB from the SN, and an SA activation signal is applied to the SA 610 by the processing element 210 to allow the data voltage (U UD- or P UD- ) on the bit line BL and the reference voltage of the same cell 602, which is based on the U term of the ferro capacitor 604 in which SA are temporarily stored.

[0059] A read cycle to read a data bit from the F-RAM cell from Fig. 6 according to another embodiment of the present disclosure will now be described with reference to Fig. 2, Fig. 6 and Fig. 8 described in more detail. With reference to Fig. 6, the memory device 600 and the F-RAM cell 602 are again configured such that the additional bit line capacitance (C ADD ) increases the total capacitance of the bit line BL, so that (C BL + C ADD ) ≥ C BLB .

[0060] However, with regard to Fig. 8, in this embodiment, the memory device 600 and the F-RAM cell 602 are also configured to provide a range shift capability, wherein the magnitude of the voltage V2 of the 2nd pulse is variable or shifted in the range from 0 V to > V1. The data voltage (V BL ) can be either U UD- or P UD-depending on whether the polarization is switched or not, and the voltage V2 of the 2nd pulse can be shifted up or down from 0 V to > V1 to measure the span and to adjust the reference voltage (V BLB ) on U UD so that P UD- > U UD > U UD- , where P UD- the data voltage on the bit line BL of the F-RAM cell 602 when the polarization is switched, and U UD- the data voltage on the bit line BL of the F-RAM cell 602 is when the polarization is not switched, and U UD is the final reference voltage.

[0061] With reference to Fig. 8, at a time t0, a PreQ_BL signal is applied to the bit line precharge circuit 612 to precharge the bit line BL to a predetermined voltage, for example, 0 V.

[0062] From time t0 to time t1, a control signal WL1 is applied to turn ON the access transistor 606, while the bit line precharge circuit 612 also remains ON, thereby discharging any internal residual voltage from the storage node SN.

[0063] From time t1 to time t2, the bit line precharge circuit 612 is turned OFF to enable the bit line BL, followed by applying a 1st pulse having a peak voltage of V1 to the plate line of the F-RAM cell 602, which generates a bit line voltage (V BL ) of (V1 * C F ) / (C F + C BL + C ADD ) results.

[0064] From time t2 to time t3, the bit line voltage V BL from a pulse-on data voltage to a post-pulse data voltage (up-down data voltage) (U UD - or P UD -) depending on whether the polarization state of the ferroelectric material in the ferro-capacitor 604 has been switched, and the word line WL1 is turned OFF, thereby decoupling the bit line BL from the SN, followed by the application of a control signal to the word line WL2 to turn the reference transistor 608 ON. The reference line precharge circuit 614 remains ON to discharge any residual internal voltage from the storage node SN.

[0065] From time t3 to time t4, the reference line precharge circuit 614 is turned OFF to enable the reference line BLB, followed by applying a second pulse to the plate line of the F-RAM cell 102, which has a peak voltage shifted up or down from 0 V to V2. As in the above-described embodiment with reference to Fig. 7, the polarization of the ferro-capacitor 604 remains unswitched and the 2nd pulse acts as a reference pulse to generate a subsequent reference voltage (V BLB ) to generate: VBLB=(V2*CFU) / (CFU + CBLB), where V BLB is the reference line voltage, V2 is the peak voltage of the 2nd pulse, C BLB is a capacitance of the reference line BLB and C FU is a capacitance of the ferro-capacitor 104 in a non-switched (U-term) polarization state. The variable voltage of the 2nd pulse, which is shifted up and down from 0 V to > V1, adds the ability to control the level of the data voltage P UD - or U UD - to measure. It should also be noted that since the ferro capacitor 604 remains switched, this second pulse also functions as a clear pulse.

[0066] Finally, from time t4 to time t5, the word line WL2 turns the reference transistor 608 OFF, thereby decoupling the reference line BLB from the SN, and an SA activation signal is applied to the SA 610 by the processing element 210 to allow the data voltage (U UD - or P UD - ) on the bit line BL and the reference voltage (U UD ) on the reference line BLB in the SA.

[0067] A read cycle to read a data bit from the F-RAM cell from Fig. 6 according to yet another embodiment of the present disclosure will now be described with reference to Fig. 2, Fig. 6 and Fig. 9. As with the above-mentioned Fig. 7 and Fig. 8, the memory device 600 and the F-RAM cell 602 are configured such that the additional bit line capacitance (C ADD ) increases the total capacitance of the bit line BL, so that (C BL + C ADD ) ≥ C BLB .

[0068] However, with regard to Fig. 9, in this embodiment, the memory device 600 and the F-RAM cell 602 are configured to provide a range shift capability, wherein the magnitude of the voltage of the 2nd pulse is variable or shifted in the range from 0 V to > V1, and the SA activation signal is applied to the SA 610 during or simultaneously with the 2nd pulse, thereby eliminating the period from time t4 to time t5 and increasing an operating frequency of the memory device 600 / 200.

[0069] With reference to Fig. 9, at a time t0, a PreQ_BL signal is applied to the bit line precharge circuit 612 to precharge the bit line BL to a predetermined voltage, for example, 0 V.

[0070] From time t0 to time t1, a control signal WL1 is applied to turn ON the access transistor 606, while the bit line precharge circuit 612 also remains ON, thereby discharging any internal residual voltage from the storage node SN.

[0071] From time t1 to time t2, the bit line precharge circuit 612 is turned OFF to enable the bit line BL, followed by applying a 1st pulse having a peak voltage of V1 to the plate line of the F-RAM cell 602, which generates a bit line voltage (V BL ) of (V1 * C F ) / (C F + C BL + C ADD ) results.

[0072] From time t2 to time t3, the bit line voltage V BLfrom a pulse-on data voltage to a post-pulse data voltage (up-down data voltage) (U UD - or P UD - ) depending on whether the polarization state of the ferroelectric material in the ferro-capacitor 604 has been switched, and the word line WL1 is turned OFF, thereby decoupling the bit line BL from the SN, followed by the application of a control signal to the word line WL2 to turn the reference transistor 608 ON. The reference line precharge circuit 614 remains ON to discharge any residual internal voltage from the storage node SN.

[0073] From time t3 to time t4, the reference line precharge circuit 614 is turned OFF to enable the reference line BLB, followed by the application of a second pulse to the plate line of the F-RAM cell 602, which has a peak voltage shifted from 0 V to > V1. In addition, as described above, during or simultaneously with the second pulse, the SA enable signal is applied to the SA 610 to allow the data voltage (U UD - or P UD - ) on the bit line BL and the reference voltage (U UO - ) are temporarily stored in the SA 610, thereby eliminating the period from time t4 to time t5 and increasing an operating frequency of the memory device 600 / 200. Finally, the word line WL2 turns the reference transistor 608 OFF, thereby decoupling the reference line BLB from the SN.

[0074] Fig. Figure 10 is a graph illustrating an improvement in F-RAM signal margin with a cell-generated reference voltage based on a bit-level U-term versus a fixed, global reference voltage. With reference to Fig. 10, in which a bit line voltage (V BL) versus bit error count, a global reference voltage, represented by line 1002, is programmed to lie between the weakest U term (which has the highest charge) and the weakest P term (which has the lowest charge) of any F-RAM cell in the array of a memory device.For example, for a memory device having a Beginning Of Life (BOL) signal margin and using the global reference voltage, the effective U-term margin (illustrated by line 1006) to the generated global reference voltage (illustrated by line 1002) is across from the first F-RAM cell 1004, which has the weakest U-term (with the highest charge), and is approximately 40 mV, while the effective P-term margin (illustrated by line 1026) to the generated global reference voltage (illustrated by line 1002) is across from the second F-RAM cell 1024, which has the weakest P-term (with the lowest charge), and is approximately 50 mV.

[0075] For a memory device having a BOL signal span and using a cell-generated reference voltage based on a bit-level U-term (represented by line 1014), the effective U-term span (line 1006) of the first F-RAM cell 1004 to the generated reference voltage 1008 is also approximately 40 mV, but the effective P-term span (line 1010) of this first F-RAM cell 1004, which is equal to the F-RAM cell 1012, to the generated reference voltage 1008 is approximately 110 mV. The effective U-term span (line 1018) of the second F-RAM cell 1016 to the generated reference voltage 1020 is also approximately 40 mV, but the effective P-term span (line 1022) of this second F-RAM cell 1016, which is equal to the F-RAM cell 1024, to the generated reference voltage 1020 is approximately 80 mV. The total U-term span of the device is thus approximately 40 mV, and the total P-term span of the device is approximately 80 mV.

[0076] Thus, it can be understood that although the magnitude of the voltage V2 of the 2nd pulse is set to a fixed voltage throughout the lifetime of the memory device, the generated reference voltage based on the U-term of the same cell tracks its changes, whether due to temperature, continuous cycling, or data retention at high temperatures, so that the bit-level P-term signal margin can be maximized over the lifetime of the device, thereby extending the lifetime of the memory device. Furthermore, the magnitude of the voltage V2 of the 2nd pulse can be selected or adjusted to provide further advantages over a conventional F-RAM cell that uses a global reference voltage.

[0077] For example, in one embodiment, the voltage V2 of the 2nd pulse may be selected or adjusted to generate a minimum BOL U-term signal margin while maximizing the P-term signal margin, thereby increasing the device lifetime, which would otherwise be shortened by continuous cycling and P-term degradation due to data retention. In another embodiment, the voltage V2 of the 2nd pulse may be selected or adjusted to generate a maximum BOL U-term signal margin with a minimum EOL P-term signal margin, thereby increasing the insensitivity of the memory device to reflow problems due to thermal depolarization. Alternatively, the voltage V2 of the 2nd pulse may be selected or adjusted to intermediate values ​​of the above embodiments to optimize both the lifetime and the insensitivity of the memory device.

[0078] It should be recognized that the detailed description section should be used to interpret the claims, rather than the summary and summary sections. The summary and summary sections may set forth one or more, but not all, embodiments of the present invention as conceived by the inventor(s) and are thus not intended to limit the present invention and the appended claims in any way.

[0079] Thus, memory devices comprising 2T1C F-RAM cells and methods of operating the same have been disclosed to improve F-RAM signal margins and a timing application that optimizes operating frequency and extends the lifetime of the memory device. Embodiments of the present invention have been described above using functional building blocks that illustrate the implementation of specified functions and their relationships. The boundaries of these functional building blocks have been arbitrarily defined herein for ease of description. Other boundaries may be defined as long as the specified functions and their relationships are adequately performed.

Claims

[1] A memory device (100, 200, 600) comprising: an array (202) of ferroelectric random access memory cells (102, 204, 602), wherein at least one ferroelectric random access memory cell (102, 204, 602) comprises: a first transistor (106, 606) coupled between a bit line (BL) and a storage node (SN); a second transistor (108, 608) coupled between a reference line (BLB) and the storage node (SN); and a ferro-capacitor (104, 604) coupled between the storage node (SN) and a plate line, wherein the ferroelectric random access memory cell (102, 204, 602) is configured to generate a bit-level reference, wherein a reference voltage on the reference line (BLB) is derived from a non-switched (U-term) of the ferro-capacitor (104, 604) of the same ferroelectric random access memory cell (102, 204, 602) in comparison with a data voltage on the bit line (BL) during a read cycle. [2] The storage device (100, 200, 600) of claim 1, further comprising: a sensor amplifier (110, 610) coupled to the bit line (BL) and the reference line (BLB) for comparing the reference voltage on the reference line (BLB) with the data voltage on the bit line (BL); and a processing element (210) configured to output control signals to the first transistor (106, 606), the second transistor (108, 608) and the sensor amplifier (110, 610) and to apply voltage pulses to the plate line, wherein the processing element (210) is configured to apply a first voltage pulse having a first peak voltage (V1) to the plate line during the read cycle to couple data from the storage node (SN) to the bit line (BL), and to apply a second voltage pulse having a second peak voltage (V2) to the plate line to couple a reference voltage to the reference line (BLB) and to serve as an erase pulse to solidify a U term in the ferro-capacitor (104, 604). [3] The memory device (100, 200, 600) of claim 2, wherein the plate line, the reference line (BLB), and the second transistor (108, 608) are configured such that the reference voltage tracks changes in the U term of the ferro-capacitor (104, 604) of the same ferroelectric random access memory cell (102, 204, 602). [4] The memory device (100, 200, 600) of claim 2, wherein the bit line capacitance is substantially equal to a reference line capacitance. [5] The memory device (100, 200, 600) of claim 4, wherein the processing element (210) is configured such that the second peak voltage (V2) is greater than the first peak voltage (V1). [6] The memory device (100, 200, 600) of claim 4, wherein the processing element (210) is configured to shift the second peak voltage (V2) of the second voltage pulse from zero volts to greater than the first peak voltage (V1). [7] The memory device (100, 200, 600) of claim 2, wherein the bit line capacitance is greater than a reference line capacitance. [8] The storage device (100, 200, 600) of claim 2, further comprising: a bit line precharge circuit (112, 612) controlled by the processing element (210) and configured to discharge and enable the bit line (BL) prior to the first voltage pulse; and a reference line precharge circuit (114, 614) controlled by the processing element (210) and configured to discharge any residual voltage at the storage node (SN) and release the reference line (BLB) prior to the second voltage pulse. [9] The memory device (100, 200, 600) of claim 8, wherein the bit line precharge circuit (112, 612) and the processing element (210) are further configured to discharge any residual voltage at the storage node (SN) prior to the first voltage pulse. [10] The memory device (100, 200, 600) of claim 9, wherein the ferroelectric random access memory cell (102, 204, 602) is configured such that the bit line precharge circuit (112, 612) remains electrically decoupled from the bit line (BL) during the read cycle between the first voltage pulse and the second voltage pulse. [11] The memory device (100, 200, 600) of claim 2, wherein the processing element (210) is configured such that the second peak voltage (V2) is greater than the first peak voltage (V1). [12] The memory device (100, 200, 600) of claim 11, wherein the processing element (210) is configured to shift the voltage, the second peak voltage (V2) of the second voltage pulse, from zero volts to greater than the first peak voltage (V1). [13] The memory device (100, 200, 600) of claim 1, wherein the plate line, the reference line (BLB), and the second transistor (108, 608) are configured such that the reference voltage tracks changes in a non-switched (U-term) of the ferro-capacitor (104, 604) of the same ferroelectric random access memory cell (102, 204, 602). [14] The memory device (100, 200) of claim 1, further comprising a bit line precharge circuit (112, 612) controlled by the processing element (210) and configured to discharge and enable the bit line (BL) prior to the first voltage pulse, and wherein the ferroelectric random access memory cell (102, 204, 602) is configured such that the bit line precharge circuit (112, 612) remains electrically decoupled from the bit line (BL) during the read cycle between the first voltage pulse and the second voltage pulse.

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