Cache structure that uses a logical directory

Abstract

Method for operating an access to a cache memory via an effective address, comprising a tag field and a cache row index field, wherein the cache memory comprises a primary cache directory that is logically addressed and logically tagged, wherein the method comprises: Determine (501) a first group of bits and a second group of bits of the marker field; Providing a record index that is logically indexed using row index bits of the cache row index field and logically marked using the first group of bits; Providing a validation directory that is logically indexed using the row index bits and set bits, and logically marked using the second group of bits; a first search (503) for the row index bits and the first group of bits of the effective address in the record directory and generating a record identifier that indicates the record containing the respective cache row of the effective address; second search (505) for the record identifier, the row index bits and the second group of bits of the effective address in the validation directory; as a response to the detection of the presence of the cache line in the sentence based on the second search, generating (507) a hit signal.

Description

BACKGROUND

[0001] The present invention relates to the field of digital computer systems and, more particularly, to a method for controlling access to a cache memory.

[0002] Recent microprocessor architecture allows software to use so-called "virtual" (or sometimes "logical") addresses to reference memory locations. Memory access itself is performed using a "physical" (or sometimes "absolute") address. To translate between the two, a data structure called a translation lookaside buffer (TLB) is typically included. The translation process is sometimes called dynamic address translation (DAT), particularly in IBM z / Architecture.

[0003] In a typical microprocessor system, multiple levels of cache are used to accelerate memory access by maintaining a copy of the memory contents "close" to the processor core. For cache implementations that support DAT, a common implementation indexes the cache directory using a portion of the logical address, and the so-called "tag" information against which the lookup request is compared uses absolute addresses. This requires translating the logical address used by the program into an absolute address, usually involving a lookup in the TLB.

[0004] However, with ever-growing microprocessor core caches, TLBs must also grow, and the power consumption of TLB lookups in addition to directory lookups contributes significantly to microprocessor core performance. Furthermore, the TLB size is limited by timing constraints, as the TLB lookup itself becomes part of the critical path.

[0005] There are already published documents in this context. Document US 6 122 709 A describes a cache memory system having a cache memory with a plurality of cache lines. An index part of a tag array comprises an n-bit pointer entry for each cache line; and a common tag part of a tag array contains a number of entries, each entry containing common tag information that is shared between multiple cache lines. Document US 2003 / 0 188 178 A1 describes a system and method for providing locally granular, hardware-controlled memory encryption. The method comprises receiving an address within a selected memory region and using the address to access an encryption indicator. The encryption indicator indicates whether data stored in the selected memory page is encrypted.Finally, document WO 2016 / 082 793 A1 describes a cache memory system comprising a plurality of previous level caches and a current level cache; each previous level cache comprises a plurality of cache lines; and the current level cache comprises an exclusive tag RAM and an inclusive tag RAM.

[0006] Despite some improvements, it has not yet been possible to adjust TLB sizes - as described above - so that the TLBs optimally support the microprocessor core performance. SUMMARY

[0007] This object is achieved by the subject matter of the independent claims. Further advantageous embodiments are described in the respective dependent claims. Embodiments of the present invention can be freely combined with one another, provided they are not mutually exclusive.

[0008] In one particular aspect, the invention relates to a method for operating access to a cache memory via an effective address, comprising a tag field and a cache line index field, the cache memory having a primary cache directory that is logically addressed and logically tagged. The method comprises: determining a first group of bits and a second group of bits of the tag field; providing a record directory that is logically indexed using line index bits of the cache line index field and logically tagged using the first group of bits; providing a validation dictionary that is logically indexed using the row index bits and set bits and logically tagged using the second group of bits; first, searching for the row index bits and the first group of bits of the effective address in the set directory and generating a set identifier that indicates the set containing the respective cache line of the effective address; second, a search for the record identifier, the row index bits and the second group of bits of the effective address in the validation dictionary; in response to determining the presence of the cache line in the set based on the second search, generating a hit signal.

[0009] In a further aspect, the invention relates to a computer program product comprising a computer-readable data storage medium with computer-readable program code formed thereon, wherein the computer-readable program code is configured to implement all steps of the method according to the preceding embodiments.

[0010] In another aspect, the invention relates to an apparatus for controlling access to a cache line via an effective address, comprising a tag field and a cache line index field, wherein the tag field comprises a first group of bits and a second group of bits. The apparatus comprises: - a primary cache directory that is logically addressed and logically tagged; - a record directory logically indexed using line index bits of the cache line index field and logically tagged using the first group of bits; - a validation dictionary logically indexed using the row index bits and set bits and logically tagged using the second group of bits; wherein the set directory is configured to receive the row index bits and the first group of bits of the effective address and to generate a set identifier indicating the set containing the respective cache line of the effective address; wherein the validation directory is configured to receive the set identifier, the row index bits, and the second group of effective address bits and to return a set identifier indicating the set in which the cache line is located. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In the following, embodiments of the invention will be explained in more detail by way of example only, with reference to the drawings in which: Fig. 1 illustrates a computer system according to an example of the present disclosure; Fig. 2 is a block diagram illustrating a diagram for accessing a cache structure of a two-level cache memory; Fig. 3 a flowchart of a method for operating the cache memory of Fig. 2 is; Fig. 4 a flowchart of a method for resolving synonyms in the cache memory of Fig. 2 is. Fig. 5 is a flowchart of a method for controlling access to a cache memory; DETAILED DESCRIPTION

[0012] The cache memory is a set-associative cache.

[0013] The present method uses a logically indexed, logically tagged directory that stores all translation-relevant information in the L1 cache. To save as much performance as possible, the present method uses a sentence directory to select the potential hit setting for the other L1 cache structures. The sentence directory is used as a cache array late selector and thus may contribute nothing to the performance and area budget compared to a conventional design. When using the sentence directory to save additional performance, a "vertically stacked" directory (i.e., the validation directory) is used instead of a conventional set-associative directory structure.As a result, only a single record can be read at a time, whereas in the prior art all records belonging to a given index could be read in parallel. For example, since the cache directory can be used to resolve synonym problems, the validation directory records may not need to be accessed in parallel.

[0014] The present method may have the advantage of providing an improved set-associative cache with fast access time yet low power consumption compared to prior art methods where an L1 cache hit requires validation from a higher-level cache.

[0015] Due to its relatively large size, the TLB typically cannot be placed in close proximity to the memory array. As a result, the total memory access time of a set-associative cache increases with the size of its TLB and memory arrays. The present method uses a logically tagged and logically indexed validation directory and can thus avoid the need to power a TLB for L1 cache hit signal generation.

[0016] According to a particular embodiment, if the second search does not confirm the presence of the cache line in the set, generating a miss signal. The miss signal is a cache miss signal indicating a cache miss for the requested effective address (also referred to as a logical or virtual address). The cache miss signal may also be generated if the first search to locate the requested logical address in the set directory fails. In response to the generated miss signal, the requested cache line may be searched for in a higher cache level or in main memory (e.g., RAM).

[0017] According to a particular embodiment, the cache further comprises a translation lookaside buffer (TLB), wherein a given entry in the primary cache directory stores a valid bit, a portion of the effective address, and a set index, wherein, in the event that the second lookup does not confirm the presence of the cache line in the set, the method further comprises: looking up the line index bits in the primary cache, resulting in a logical pointer for each set in the primary cache directory, the logical pointer comprising the set index and the portion of the effective address; selecting a logical pointer of the logical pointers whose set index matches the set identifier; looking up the effective address in the TLB to identify an absolute address associated with the effective address;searching the effective address in a higher-level secondary cache directory of the cache memory to obtain an entry corresponding to the effective address in each set in the secondary cache directory, the entry having a different absolute address; comparing each obtained absolute address of the secondary cache directory with the absolute address of the TLB, resulting in another set identifier of a set of the secondary cache directory; comparing the logical address of the entry of the set of the secondary cache directory having the different set identifier with the selected logical pointer, and based on the comparison results, asserting the error signal or updating the set and validation directories;

[0018] For example, the TLB and the parent cache are used in the event of a cache miss in the child cache. This can provide reliable validation or confirmation of the cache miss at the lower cache level.

[0019] According to a particular embodiment, the primary cache search is performed in parallel with the initial search. This embodiment can further accelerate data access.

[0020] According to a specific embodiment, the method further comprises: generating the hit signal when the valid bit of the logical pointer is set to a valid state. The valid bit is an information bit indicating whether the data in a cache line is valid. This can further save processing time that would otherwise be required for accessing invalidated data and processing induced corrections.

[0021] According to a particular embodiment, the TLB lookup and the secondary cache directory lookup are performed in parallel. This embodiment can further accelerate data access.

[0022] According to a particular embodiment, the first group of bits are the least significant bits from the tag field, and the second group of bits are the most significant bits from the tag field. The second group of bits may be complementary to the first group of bits for confirming the search result of the sentence dictionary. For example, if the effective address has a stored tag of 0:49 bits, the first group of bits may be 37:49 and the second group of bits may be 0:36. However, any subset of the stored tag 0:49 may be used as the first or second group of bits. The width of the first groups of bits (i.e., number of bits) may be based on a balance between constraints on incorrect predictions (not too small) and timing constraints (not too wide comparisons).Using the bits next to the row index (50:55) of the effective address for the first group can be advantageous because it works even for programs with small memory footprints. For example, if bits 0:12 are used for the first group, most programs may not be able to use n-fold (e.g., n = 8) associativity because only large programs can have effective addresses that differ by 0:12, so normal-sized programs could use only one set. In other words, the bits of the first group (e.g., 37:49) are chosen so that they differ for most memory accesses and do not yet overlap with the row index.

[0023] According to a particular embodiment, the validation directory is constructed from a physical array structure that stores one directory entry per cache line from all records in the cache. This embodiment may allow only a single record to be read at a time, whereas in the prior art, all records belonging to a given index could be read in parallel. This embodiment may thus further accelerate data access. For example, the result of the record directory (e.g., a record identifier) ​​may be used as an extension to the row index (e.g., bits 50:55) for searching the validation directory.

[0024] According to a particular embodiment, a given entry in the primary cache directory stores a valid bit, a portion of the effective address, and a set index, the method further comprising: in parallel with the first search, searching the row index bits in the primary cache directory, resulting in a valid bit value for each set in the primary cache directory; selecting a valid bit value from the valid bit values ​​whose associated set index matches the set identifier; wherein generating the hit signal is performed when the valid bit value indicates a valid state. This can further save processing time that would otherwise be required for accessing invalidated data and processing induced fixes.

[0025] According to a particular embodiment, the primary cache directory is an L1-level cache directory. According to a particular embodiment, the secondary cache directory is an L2-level cache directory. These embodiments can be seamlessly integrated into existing systems.

[0026] According to a particular embodiment, the cache memory is a multi-level cache directory further comprising a secondary cache directory. The cache memory is a set-selective memory.

[0027] According to a particular embodiment, a given entry in the primary cache directory stores a valid bit, a portion of the effective address, and a set index. The method further comprises: receiving a second effective address synonym of the effective address; repeating the first and second searches using the second effective address; if the second search does not confirm the presence of the cache line indicated by the second effective address, invalidating the set directory entry corresponding to the second effective address; performing the first search using the second effective address to detect a miss; searching the second effective address in the primary cache directory, resulting in a logical pointer for each set in the primary cache directory, the logical pointer comprising the set index and the portion of the second effective address;searching the second effective address in a higher-level secondary directory cache of the cache memory to obtain an entry corresponding to the second effective address in each set in the secondary cache directory; comparing the logical address of the entry of the secondary cache directory set with each of the logical pointers, and based on the comparison results, confirming the presence of the cache line in the primary cache directory; updating the set and validation directories by overwriting entries related to the effective address with the second effective address;Repeating the first search, the second search, and the generation of the conditional hit signal. This embodiment may have the advantage of effectively solving cache synonym problems. It solves synonym problems by relying on the next-level cache(s). It uses the L1 cache directory to connect the L1 cache and the L2 cache.

[0028] Fig. 1 illustrates a computer system 100 according to an example of the present disclosure. The computer system 100 may be based on the z / Architecture offered by International Business Machines (IBM). The computer system 100 may use a set-associative cache memory structure. The computer system 100 includes at least one processing unit 101. The processing unit 101 may be connected to various peripheral units, including input / output (I / O) units 104 (such as a display monitor, a keyboard, and a permanent data storage unit), a memory unit 106 (such as random-access memory (RAM)) used by the processing units to execute program instructions, and firmware 108, the primary purpose of which is to retrieve and load an operating system from one of the peripheral units whenever the computer is first powered on.The processing unit 101 exchanges data with the peripheral units (e.g., firmware 118, I / O units 114, and memory 116) through various means, including a generalized interconnect or bus 120.

[0029] Processing unit 101 includes a processor core 122 with a plurality of registers and execution units that execute program instructions to operate the computer. An exemplary processing unit includes the PowerPC™ processor marketed by International Business Machines Corporation. Processing unit 101 may also have one or more caches. For example, the processing unit is shown as having two caches 126 and 130. Caches are used to temporarily store values ​​that are repeatedly accessed by a processor to speed up processing by avoiding the lengthy step of loading the values ​​from memory 116.

[0030] Caches 126 and 130 are set-associative caches that allow the processor to achieve a relatively short access time to a subset of data or instructions previously transferred from a memory 116.

[0031] Cache 126 may be packaged integrally with processor core 122. Cache 126 may include instruction arrays (not shown) and data arrays 141 implemented using high-speed memory devices. Instructions and data may be directed to the respective cache by examining a signal indicating whether the processor core requests an operation whose operand is an instruction versus data. Cache 126 may further include a cache directory 142 associated with data array 141. For example, each cache line in data array 141 has a corresponding entry in cache directory 142. Cache directory 142 may indicate whether the data identified by an effective address is stored in data array 141. For example, a processor instruction referencing an effective address may be provided to cache 126.If the effective address is in cache directory 142, the processor knows it can get the referenced data from data array 141 if access criteria are met, where access criteria may require that the valid bit be set, etc. For example, the effective address includes a tag field, a row index field, and a byte field. The tag field of the effective address is used to provide cache "hit" information, as described herein. The row index field of the effective address is used to get N cache lines, for example, within data cache array 141, indexed by the row index field, where N is the number of sets in an N-associative cache. One of the N cache lines can be selected using a set identifier (as part of a late select), and the byte field of the effective address is used to index a specific byte within the selected cache line.

[0032] Data array 141 and cache directory 142 may be constructed from conventional memory arrays, such as those readily available in configurations of, for example, 4M or 8M chip arrays. Cache 126 is associated with a cache control unit (not shown), which manages, for example, the transfer of data between processor core 122 and the caches.

[0033] The data cache array 141 has many cache lines that individually store various data values. The cache lines are divided into groups of cache lines called "sets." An exemplary cache line includes a state bit field, an exclusivity bit field, and a value field for storing the current instruction or current data. The state bit field and inclusivity bit fields are used to maintain cache coherence in a multiprocessor computer system. The address tag is a subset of the full address of the corresponding memory block. A comparison match of an incoming effective address with one of the tags within the address tag field indicates a cache "hit." The collection of all address tags in a cache (and sometimes the state bit and inclusivity bit fields) is called a directory, and the collection of all value fields is the cache entry array.

[0034] Cache 126 may be referred to as a Level 1 (L1) cache, and cache 130 may be referred to as a Level 2 (L2) cache because it supports the (L1) cache 126. For example, cache 130 may act as an intermediary between memory 116 and the L1 cache and may store a larger amount of information (instructions and data) than the L1 cache can, but at the expense of longer access times. For example, cache 130 may have a data storage capacity of 256 or 512 kilobytes, while the L1 cache may have 64 kilobytes of total data storage. Cache 130 is connected to bus 120, and all loads of information from memory 116 to processor core 122 may pass through cache 130. Although Fig. While Figure 1 illustrates only a two-level cache hierarchy, multi-level cache hierarchies can be provided, with multiple levels of serially connected caches. For example, the components of processing unit 101 can be packaged on a single integrated chip.

[0035] Also in Fig. 1 shows a translation lookaside buffer (TLB) 143 for translating an effective address into a corresponding absolute address. Specifically, the TLB 143 can translate the page number portion of an effective address into a corresponding real page number. For example, the tag field of an effective address can be sent to the TLB 143 to be translated into a corresponding real page number.

[0036] In another example, computer system 100 may include at least two translation lookaside buffers, a first of which (TLB1) is a first-level buffer and a second of which (TLB2) is a second-level translation lookaside buffer arranged to feed the first with address information in case of a missing address of the first. For example, the address translation tables in memory may have a multi-layered structure. For example, for a two-layer table, the first-level table, called the segment level, contains entries that each allocate one MB of memory by referencing a second-level table, called the page table, which contains 256 entries that allocate 4 KB of memory. TLB2 may have two types of entries: 1 MB segments and individual 4 KB pages.If no translation is available in the first-level TLB (TLB1), TLB2 is searched for a 4 KB page entry that provides the required translation. If not, TLB2 is searched for a segment entry for the segment containing the address to be translated. If such an entry is found, the translation using the in-memory tables is short-circuited because the corresponding page table can be accessed directly without needing to access the in-memory segment table. And TLB1 can have a two-dimensional array of entries, e.g., 32 entries long and 4 entries wide. Each entry contains a virtual address that has been translated and the real address it has been translated to. In this example, TLB 143 can be TLB1.

[0037] In one particular example, computer system 100 may be used as a hardware resource in a virtualized environment, such as IBM's z / VM. For example, processing unit 101 may receive requests from virtual machines or a guest running under a hypervisor in a logical partition.

[0038] Fig. 2 is a block diagram illustrating a scheme for accessing a cache structure 200 of a two-level cache memory via an effective address (or logical address or virtual address) 201 according to an example of the present disclosure. The cache memory is a set-associative cache having, for example, m sets in L1 cache and n sets in L2 cache. m may be equal to n, but need not be. The cache structure 200 includes an L1 cache 226 and an L2 cache 230. The L1 cache 226 includes, as described with reference to Fig. 1, the data cache array 141 and the cache directory 142. In Fig. 2, the L1 cache 226 further includes a set directory 203 and a validation directory 205. The L2 cache 230 includes a cache directory 242 and a cache array (not shown).

[0039] The record directory 203 is indexed using row index bits of the row index field 210 of the effective address 201 and logically tagged using a first group of bits 212a of the tag field 212 of the effective address 201. The validation directory 205 is logically indexed using row index bits of the row index field 210 of the effective address 201 and record bits. The validation directory 205 is logically tagged using a second group of bits 212b of the tag field 212 of the effective address 201. The first and second groups of bits 212a and 212b are shown non-overlapping for explanation purposes. The first and second groups of bits may overlap. For example, the second group of bits may include bits 0:49, which may allow to have sentence dictionary update rules that are relaxed, which e.g.allows the sentence directory and the validation directory not to be strictly synchronized at all times.

[0040] Each entry of the set directory 203 has at least the first group of bits 212a and one valid bit. For example, if the processor core supports threads (e.g., threads th1 and th2), the entry may have one valid bit associated with each thread (e.g., the entry may be: LA.37:49, th0 vld, th1 vld). Each entry of the validation directory 205 has at least the second group of bits. In one particular example, the entry of the validation directory 205 further has a valid bit, an exclusivity bit, and a key. The valid bit indicates that the entry is valid. The exclusivity bit indicates that the cache line is exclusively owned. It is called an exclusivity bit because if a particular core has exclusive ownership of a line, no other core can have a copy of the associated line. Cache lines are exclusively requested when data is modified.And many cores can have a row in a read-only state. The key is a data storage key for protection and can contain any other set of miscellaneous information. In a specific example, the validation dictionary entry 205 further includes an ASCE element and a REAL element, where ASCE refers to an address space control element (pointer to dynamic address translation tables) and the REAL element indicates that the entry is a real entry.

[0041] The L1 and L2 cache arrays 141 store the data copy from memory 116, and each entry in the L1 and L2 directories 142 and 242 stores the second group of bits 212b, the address space identifier, and so on. For example, the L1 directory 142 contains the following fields: valid bit, logical address, e.g., 45:49, and L2 set ID. The valid bit indicates whether the L1 directory entry is valid or invalid. The logical address 45:49 is an extension of the logical L1 address 50:55 to allow access to the L2 directory. The L2 set ID indicates which L2 directory set contains the L1 cache entry. For example, an entry of the L1 directory 142 may be as follows: set0 - L2CC(45:49), th0 logdir vld, th1 logdir vld, ptrdir vld, where L2CC(45:49) is bits 45:49 of the effective address (also called the logical address).Bit 45 is stored only for data caching because L2 is for 4M data, while L2 is for 2M instruction size. "logdir vld" indicates that the translation stored in the L1 cache is valid. "ptrdir vld" is a valid bit, indicating that the data in the L1 cache is valid. The "45:49" bits can be derived from the cache sizes (e.g., the number of lines). For example, if the L1 cache has 64 lines per set, the line index is 50:55, and if L2 has 1024 lines per set, the indexing can be wider, resulting in an index of 45:55. However, since the L1 directory has already been indexed at 50:55, referencing an L2 coordinate can be done by maintaining only LA.46:49 and the L2 record ID in the L1 directory entry.

[0042] To describe Fig. To simplify Figure 2, a simplified example of an L1 cache can be considered. In this example, the L1 cache has 64 lines and 8 sets (i.e., m = 8), and a cache line is addressed using a 64-bit logical address (0:63) (abbreviated LA(0:63)). Therefore, in this example, the line size is 256 bytes. In this example, the set directory 203 may use LA(37:49) as a tag (the first group of bits). The tag of the validation directory 205 may be LA(0:49) or LA(0:36), plus any additional information required to distinguish between different address spaces.

[0043] The validation directory 205 can be referred to as a "stacked" logical directory because the validation directory is constructed from a physical array structure that stores one directory entry per row. Following the example above, the validation directory has 8 x 64 rows = 512 rows, rather than eight array structures each having 64 rows. The advantage of such a structure may be that an array row can only have a limited number of bits (for physical reasons). Adding more rows involves comparatively little overhead relative to extending the width of a row or adding more array structures. The "stacked" approach may be advantageous because it consumes less area and power. However, the L1 cache directory 142 has an eight-array structure, each having 64 rows.

[0044] Fig. 2 further illustrates details of the structure of the L1 cache directory 142 and the L2 cache directory 242. The L1 cache directory 142 has a set-associative directory structure with multiple L1 sets, e.g., a number m of L1 sets and respective comparators L1CP1 through L1CPm. The L2 cache directory 242 has a set-associative directory structure with multiple L2 sets, e.g., a number n of L2 sets and respective comparators L2CP1 through L1CPn. The L2 cache directory 242 uses portions of the effective address 201 as an index and the absolute address as a tag.

[0045] For example, an L2 directory entry may include the following: "set0 - AA.17:51," where set0 is the set index of the set containing the entry, AA is the absolute address associated with the effective address used to index the L2 directory. In another example, the L2 directory entry may further include two additional elements: "key(0:3), FP," where "key" is a 4-bit tag that must match according to the rules described in the architectural principles (e.g., z / Architecture) of operation of computer system 100, and FP (fetch protection) enables key comparison.

[0046] The cache structure 200 further includes the TLB 143.

[0047] During a cache lookup, the set directory 203 receives as input the index LA(50:55) and a first group of bits LA(37:49), and the set directory 203 generates or predicts the set with a set ID designated Set(0:7) that stores the requested cache line. For example, the set directory 203 can be searched to find the set ID. Using the set ID Set(0:7) in addition to the index LA(50:55), the validation directory 205 is looked up to confirm the cache hit using a tag comparison 220, which can result in identifying a corresponding directory entry in the validation directory 205. For example, the set ID determined by the set directory 203 is used to select one of the eight 64-line sections, and LA(50:55) is used to select the line within the section.

[0048] In parallel with searching the record directory 203, the L1 cache directory 142 is looked up to retrieve the valid bit for this directory entry. The valid parts are part of the L1 cache directory 142 because multiple entries may need to be invalidated simultaneously. If the tag compare 220 detects a hit 244 and the valid bit is set, the valid compare 240 indicates that a cache hit has been found. Otherwise, a cache miss 245 may be found. The data array 141 may receive a record identifier from the record directory 203 and may provide data of the requested cache lines using the line index 210 and the byte offset 213 of the effective address 201 and the record identifier. In the event of a cache miss, a warning may be provided to indicate that the provided data corresponds to a cache miss.

[0049] Only in case of a cache error 245 or in case the search in the record directory 203 fails (leads to a cache error) are the data structures in the lower part of Fig. 2. Specifically, the TLB 143 is looked up using the effective address 201 and the hit match 251 (including portions of the logical address 201 and translation-relevant information, such as an address space identifier) ​​to determine the absolute address for the request. The hit match 251 can be performed by the TLB's own comparison logic. In parallel with the search of the TLB 143, the L2 cache directory 242 is looked up, e.g., using bits 46:55 of the effective address 201. And the hit match 261 searches for a hit in the L2 cache directory 242 by comparing the absolute address output by the TLB with the absolute addresses of the L2 cache directory identified using the logical address 201.The result of the hit comparison 261 is an indication of which L2 set detected the hit (the diagram assumes 8 sets (i.e., n = 8) in the L2 cache). This hit information is then used in the L1 directory comparison 270 to see if the line hitting the L2 cache is already stored in the L1 cache. For this purpose, the L1 directory comparison 270 also uses received logical input pointers (referred to as out1 through outm) to the L2 cache. Each logical pointer (e.g., Out1) is associated with a respective L1 set and contains the L2 index and L2 set ID, and the valid bit of the L1 directory entry corresponding to the index LA(50:55).

[0050] Fig. 3 is a flowchart of a method for operating the cache memory of Fig. 2. Upon receiving an access request, e.g., via an effective or logical address, to access a given cache line, in step 310 the set directory 203 (referred to as setp) and the L1 cache directory 142 (referred to as ptrdir) are accessed. The access may, for example, be performed in parallel. The access to the set directory 203 and the L1 cache directory 142 is performed using the row index bits of the effective address (e.g., LA(50:55)). The access to the set directory 203 may or may not result in a set identifier indicating the set in which the cache lines are present. The access to the L1 cache directory 142 may or may not result in multiple entries of respective L1 sets, since the L1 cache directory uses only the row index bits of the effective address as input.

[0051] In the case (query 220) of a cache miss resulting from searching the set directory 203, steps 380 through 387 may be performed. In the case (query 220) of a cache hit, steps 330 through 370 may be performed, and the set directory 203 may provide a set identifier indicating the set in which the requested cache line is present.

[0052] In step 330, the validation directory 205 (referred to as logdir) may be searched using the record identifier received from the record directory 203 and the row index bits of the effective address (e.g., LA(50:55)).

[0053] In step 340, the valid bit associated with the addressed cache line may be determined. This may be determined by selecting the entry of the plurality of entries using the set identifier and reading the value of the valid bit of the selected entry.

[0054] In case (350) the validation directory 205 provides a cache miss as a result of the search 330 or the valid bit has a value indicating an invalid state, the record directory entry hit by the search of step 310 may be invalidated 370. Otherwise, a cache hit may be resolved in step 360, e.g., by providing a hit signal.

[0055] In step 380, a TLB lookup is performed using the logical address of the request. The result of this lookup is the matching absolute address. Next, in step 381, the L2 cache directory 242 is looked up and compared with the absolute address as supplied by the TLB. In the case of an L2 miss, step 382 branches to 383 to resolve the L1 miss and the L2 miss. After resolving the L1 miss and the L2 miss, all data structures are updated so that the cache line can be found in the set directory 203 on the next request.

[0056] If step 382 detects an L2 hit, step 384 compares the L1 cache directory contents, as identified by searching the sentence directory 203 against the L2 directory contents in step 310, to see if the cache line is actually in L1. If the comparison result shows an L1 hit, step 385 decides to branch to step 386. This occurs when the request does not hit the sentence directory 203, but the cache line is actually in the L1 cache. This may be the case, for example, because the sentence directory is incorrect, or it could be because the current request is for a different synonym than the synonym stored in L1 so far (which, for the current request, is the same as saying "the sentence directory was incorrect"). In either case, step 386 updates the sentence directory 203 and the validation directory 205 to match the current request.No actual data transfer needs to occur. If step 385 did not detect an L1 hit, this indicates that the cache line is not in the L1 cache—regardless of its synonym—but is in the L2 cache. Therefore, in step 387, the L1 miss is resolved, which involves transferring data from L2 to L1 and updating the record dictionary and validation dictionary so that an L1 hit is found on the repeated request.

[0057] Each of steps 370, 383, 386, and 387 is followed by step 399 to repeat the request, resulting in a clear L1 hit.

[0058] Fig. 4 is a flowchart of a method for resolving synonyms in the cache of Fig. 2 according to the present disclosure.

[0059] In step 401, a second effective address (referred to as synonym B) is received. The second effective address is a synonym of a previously processed effective address, referred to as synonym A. In other words, synonym B is used for a cache line while another synonym A is already in the L1 cache.

[0060] For example purposes, Fig. 4 shows the addresses synonyms A and B in hexadecimal. For simplicity, 20-bit addresses (5 hexadecimal digits) are shown. In this example, the byte index or offset into the cache line is not shown. Bits are numbered from left to right (bit 0 is the most significant bit), so each address has bits 0:19. Synonym A = 12345 and Synonym B = 67895. In this example, record directory 203 can be indexed using bits 16:19 (i.e., the last hexadecimal digit of the address) and can be tagged using bits 8:15. As in Fig. 4, three example use cases A) to C) 430 are shown.

[0061] In use case A), synonyms A and B have the same index (setp index = 5) and have different tags in set directory 203. Synonyms A and B are assigned to the same absolute address.

[0062] In use case B), synonyms A and B have the same index (setp index = 5) and have the same tags in set directory 203. Synonyms A and B are assigned to the same absolute address.

[0063] In use case C), lines A and B have the same index (setp index = 5) and have the same tags in set directory 203. However, they are assigned to different absolute addresses.

[0064] In step 403, the sentence dictionary is searched to identify a cache hit for the requested synonym B. This is considered a case of "sentence dictionary wrong" because the sentence dictionary 203 provided a sentence that ultimately did not actually detect a hit.

[0065] However, the search in step 405 for synonym B in the validation directory 205 would result in a cache miss. If the lookup were performed for synonym A, the search in the validation directory 205 would detect a hit (and step 360 can be executed). However, since the access was for synonym B, the address as read from the validation directory 205 will not match the requested address.

[0066] In step 407, the entry corresponding to synonym B in sentence dictionary 203 is invalidated. And repeated access using synonym B is triggered in step 409.

[0067] Steps 403 to 420 are executed for use cases B) and C).

[0068] In step 411, the sentence dictionary 203 is searched to identify a cache miss for the requested synonym B.

[0069] Upon identifying the cache miss from step 411, step 413 is executed. In step 413 (which performs step 384), the L1 cache directory contents associated with synonym B are compared with the L2 cache directory contents associated with synonym B to determine that the cache line is indeed in L1.

[0070] Upon identifying or finding the cache hit in step 314, the sentence dictionary 203 and the validation dictionary 205 may be updated in step 415. The update may be performed, for example, by overwriting synonym A information with synonym B.

[0071] Upon performing the update of step 415, retry of the access using synonym B may be triggered in step 417. The retry results in a sentence dictionary hit in step 428, followed by a validation dictionary hit in step 419, resulting in the cache access being resolved in step 420.

[0072] Steps 411 to 420 may be executed for use case A). For example, if synonym B is received from use case A), an error may be found as in step 411. In other words, for a received synonym B from use case A, only steps 411 to 420 may be executed.

[0073] Fig. 5 is a flowchart of a method for controlling access to a cache memory, e.g., 200, via an effective address, e.g., 201, having a tag field 212 and a cache line index field 210.

[0074] In step 501, a first group of bits 212a and a second group of bits 212b of the tag field 212 may be determined.

[0075] In step 503, the row index bits and the first group of bits 212a of the effective address may be searched in the record directory 203, thereby generating a record identifier to indicate the record containing a cache line of the effective address 201.

[0076] In step 505, the set identifier and line index bits 210 and the second group of bits 212b of the effective address 201 may be searched in the validation directory 205 to verify the presence of the cache line in the set with the set identifier provided in step 503. This step 505 may indicate or confirm the presence or absence of the cache line in the set by indicating whether it is present in the validation directory 205.

[0077] In response to determining the presence of the cache line in the set based on the second search of step 505, a hit signal may be generated in step 507. The hit signal may be used to provide the cache line data from data array 141.

[0078] In a particular example, step 503 and / or step 505 may result in a cache miss in that the sought addresses are not found in the set directory 203 or the validation directory, respectively. In this case, the cache miss may be confirmed by accessing the TLB 143 and the secondary cache directory 242, as described in steps 380 through 399. TLB INVALIDATIONS

[0079] According to a particular embodiment, the method further comprises, in response to receiving a request to invalidate a validation directory entry of the validation directory, accordingly setting a valid bit of the corresponding primary cache directory entry in the primary cache directory.

[0080] According to a particular embodiment, the method further comprises providing a first auxiliary data structure in association with the primary cache directory, wherein each entry of the first auxiliary data structure comprises bits of the effective address reflecting information specified in TLB flush requests of the multiprocessor system that identify an entry in the first auxiliary data structure corresponding to the received request, the identified entry specifying the primary cache directory entry.

[0081] For example, if an address space for a guest operating system is evicted by a corresponding hypervisor, the cache lines are still in the L1 cache. However, there is no longer a valid translation for them. This means that the data in the L1 cache should no longer be accessible by a request using the removed translation. To make these entries inaccessible, they should be invalidated in the L1 cache because the L1 cache directory is logically tagged. Before invalidation, the affected entries should be searched for. For example, a bit can be used as part of the entry information in the validation directory to indicate that a particular entry belongs to a guest operating system. If TLB invalidation removes all translation information related to that guest operating system, all directory entries in the validation directory 205 with the guest bit set should be invalidated.

[0082] In the validation directory 205, only a single entry can be looked up at a time to determine whether it should be invalidated (or deleted). To mitigate this problem, the L1 directory 142 is extended with a substructure "ptrdirext" (i.e., the first auxiliary data structure) that stores translation-relevant information for each entry in the validation directory 205. As with the L1 directory, all sentences in the first auxiliary data structure can be accessed in parallel. For example, an entry of the first auxiliary data structure may have "set0 - th ASCE(44:49), PGSZ(0:1), SX(37:43)", where PGSZ refers to a page size (e.g., dynamic address translation results may be for page sizes of 4k, 1M, or 2G), SX(37:43) refers to bits 37:43 of the effective address, and ASCE(44:49) are bits 44:49 of the effective address used as an address space identifier by a respective thread th .

[0083] For example, a sequence of virtual addresses associated with virtual data memory referenced by an address space control element (ASCE) can be called an address space. Address spaces can be used to provide levels of isolation between users. The structure of the first auxiliary data structure can allow entries associated with a given address space to be deleted more efficiently using the ASCE bits.

[0084] With this substructure, TLB invalidations that should only affect specific translations can be performed significantly faster than by individually cleaning up all entries in the validation dictionary.

[0085] The ptrdirext substructure is written to the validation directory 205 along with any updates. A trade-off can be made between the size of the ptrdirext and the accuracy of TLB invalidations. To resolve the case of guest versus hypervisor ownership, a single bit is needed to make the distinction. If a TLB flush is performed based on an address space identifier, such as the ASCE in z / Architecture—that is, a 51-bit value plus some control information—it may be sufficient to store only a few bits, or a hash of some bits, to filter out which entries should be flushed and which should not.An example implementation of ptrdirext can store a portion of the ASCE bits, guest-level identifier bits, a page size specification (for TLB architectures that support multiple page sizes), a segment index, or a portion of the segment index (for TLB architectures that support multi-level page tables, where a higher level is called the "segment table" and invalidations based on the segment table are possible).

[0086] For example, if the valid bit is part of the L1 directory entries, the actual invalidation of entries can also be performed in parallel for all entries of a set in a given L1 directory.

[0087] According to a particular embodiment, the method further comprises providing a second auxiliary data structure in association with the primary cache directory. The second auxiliary data structure includes absolute addresses associated with entries of the primary cache directory. In response to receiving a request to store an entry in the cache, using the second auxiliary data structure to identify an absolute address of a data storage location and storing the entry at the data storage location using the absolute address. For example, the second auxiliary data structure may be logically indexed. For example, for the purpose of cache functions that require the absolute address, the absolute address is added in a substructure (i.e., the second auxiliary data structure) as part of a separately accessible "payload."This substructure is a logical part of the cache directory but is not used as part of the tag. This simplifies memory processing, as stores sent to memory must know their absolute address. It also enables other cache functions that potentially need to know, or would benefit from, the absolute address of cache lines found in the L1 cache.

[0088] A possible combination of features described above can be the following: A method for operating access to a cache memory via an effective address, comprising a tag field and a cache line index field, the cache memory having a primary cache directory that is logically addressed and logically tagged, the method comprising: determining a first group of bits and a second group of bits of the tag field; providing a record directory that is logically indexed using line index bits of the cache line index field and logically tagged using the first group of bits; providing a validation dictionary that is logically indexed using the row index bits and set bits and logically tagged using the second group of bits; first, searching for the row index bits and the first group of bits of the effective address in the set directory and generating a set identifier that indicates the set containing the respective cache line of the effective address; second, a search for the record identifier, the row index bits and the second group of bits of the effective address in the validation dictionary; in response to determining the presence of the cache line in the set based on the second search, generating a hit signal.

[0089] The method according to feature combination 1, if the second search does not confirm the presence of the cache line in the set, generating an error signal.

[0090] The method of feature combination 1 or 2, wherein the cache memory further comprises a translation lookaside buffer TLB, wherein a given entry in the primary cache directory stores a valid bit, a portion of the effective address, and a set index, wherein in the event that the second lookup does not confirm the presence of the cache line in the set, the method further comprises: searching for the row index bits in the primary cache directory, resulting in a logical pointer for each entry found, the logical pointer comprising the set index of the set in which the entry exists and the portion of the effective address; selecting a logical pointer of the logical pointers whose record index matches the record identifier; searching the effective address in the TLB to identify an absolute address associated with the effective address; searching for the effective address in a higher-level secondary cache directory of the cache memory to obtain an entry corresponding to the effective address in each set of the secondary cache directory, the entry having a further absolute address; comparing each obtained absolute address of the secondary cache directory with the absolute address of the TLB, resulting in a further set identifier of a set of the secondary cache directory; comparing the logical address of the entry of the set of the secondary cache directory having the further set identifier with the selected logical pointer, and based on the comparison results, asserting the error signal and / or updating the set and validation directories accordingly.

[0091] The method of any preceding combination of features, wherein the primary cache search is performed in parallel with the first search.

[0092] The method according to one of the preceding feature combinations, further comprising: generating the hit signal is performed when the valid bit of the logical pointer is set to a valid state.

[0093] The method according to feature combinations 3, where the search in the TLB and the search in the secondary cache directory are performed in parallel.

[0094] The method according to any one of the preceding combinations of features, wherein the first group of bits are the least significant bits from the tag field and the second group of bits are the most significant bits from the tag field.

[0095] The method of any preceding combination of features, wherein the validation directory is constructed from a particular physical array structure that stores a particular directory entry per cache line of all sets of the cache memory.

[0096] The method of any preceding combination of features, wherein a given entry in the primary cache directory stores a valid bit, a portion of the effective address, and a set index, the method further comprising: in parallel with the first search, searching the row index bits in the primary cache directory resulting in a valid bit value for each found entry in the primary cache directory, selecting a valid bit value of the valid bit values ​​whose associated set index matches the set identifier, wherein generating the hit signal is performed when the valid bit value indicates a valid state.

[0097] The method of any preceding combination of features, wherein the primary cache directory is an L1 level cache directory.

[0098] The method of feature combination 3, wherein the secondary cache directory is an L2 level cache directory.

[0099] The method of any preceding combination of features, wherein the cache memory is a multi-level cache directory further comprising a secondary cache directory.

[0100] The method of any preceding combination of features, wherein a given entry in the primary cache directory stores a valid bit, a portion of the effective address, and a set index, the method further comprising: receiving a second effective address that is a synonym of the effective address; repeating the first and second searches using the second effective address; if the second search does not confirm the presence of the cache line to which the second effective address refers, invalidating the record directory entry corresponding to the second effective address; performing the first search using the second effective address to detect an error; searching for the second effective address in the primary cache directory, resulting in a logical pointer for each record in the primary cache directory, the logical pointer comprising the record index and the portion of the second effective address; searching for the second effective address in a higher-level secondary cache directory of the cache memory to obtain an entry corresponding to the second effective address in each set in the secondary cache directory; comparing the logical address of the entry of the secondary cache directory set with each of the logical pointers, and based on the comparison results, confirming the presence of the cache line in the primary cache directory; updating the record and validation directories by overwriting entries relating to the effective address with the second effective address; repeating the last three steps of feature combination 1.

[0101] The method of any preceding combination of features, further comprising: in response to receiving a request to invalidate an entry of the validation directory, accordingly setting a valid bit of the corresponding entry in the primary cache directory.

[0102] The method of feature combination 14, further comprising providing a first auxiliary data structure in association with the primary cache directory, wherein each entry of the first auxiliary data structure comprises bits of the effective address reflecting information specified in TLB flush requests of the multiprocessor system that identify an entry in the first auxiliary data structure corresponding to the received request, the identified entry specifying the primary cache directory entry.

[0103] The method of any preceding feature combination, further comprising: providing a second auxiliary data structure in association with the primary cache directory, the second auxiliary data structure being logically indexed and physically tagged; in response to receiving a request to store an entry in the L1 cache, using the second auxiliary data structure to identify the absolute address of a data storage location and storing the entry at the storage location using the absolute address.

[0104] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, may be implemented by computer-readable program instructions.

[0105] The present invention may be a system, a method, and / or a computer program product. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions stored thereon for causing a processor to perform aspects of the present invention.

[0106] The computer-readable storage medium may be any physical device that can retain and store instructions for use by an instruction-executing system. The computer-readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of the computer-readable storage medium includes the following: a portable computer diskette, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM).Flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD), memory stick, floppy disk, mechanically encoded device such as punched cards or raised structures in a groove on which instructions are stored, and any suitable combination thereof. A computer-readable storage medium, as used herein, shall not be construed as containing transient signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., pulses of light carried through a fiber optic cable), or electrical signals carried through a wire.

[0107] Computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to respective computing / processing units or to an external computer or storage unit via a network such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, fiber optic transmission lines, wireless transmission, routers, firewalls, switching units, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing unit receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the respective computing / processing unit.

[0108] Computer-readable program instructions for performing operations of the present invention may be assembly language instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, or the like, as well as conventional procedural programming languages ​​such as the C programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server.In the latter case, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, over the Internet using an Internet service provider). In some embodiments, electronic circuits, including, for example, programmable logic circuits, field programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may execute the computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuits to perform aspects of the present invention.

[0109] Aspects of the present invention are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowcharts and / or block diagrams, as well as combinations of blocks in the flowcharts and / or block diagrams, may be implemented by computer-readable program instructions.

[0110] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine such that the instructions, executed by the processor of the computer or other programmable data processing device, produce a means for implementing the functions / steps defined in the flowchart block(s) and / or block diagrams.These computer-readable program instructions may also be stored on a computer-readable storage medium that can direct a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer-readable storage medium having instructions stored thereon comprises an article of manufacture, including instructions that implement aspects of the function / step specified in the flowchart block(s) and / or block diagrams.

[0111] The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of process steps to be performed on the computer, other programmable apparatus, or other device to produce a computer-executable process such that the instructions executing on the computer, other programmable apparatus, or other device implement the functions / steps defined in the block(s) of flowcharts and / or block diagrams.

[0112] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions comprising one or more executable instructions for performing the particular logical function(s). In some alternative implementations, the functions indicated in the block may occur in a different order than shown in the figures. For example, two blocks shown in succession may actually execute substantially concurrently, or the blocks may sometimes execute in reverse order depending on the corresponding functionality.It is further understood that each block of the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by special purpose hardware-based systems that perform the specified functions or steps, or by combinations of special purpose hardware and computer instructions.

Claims

[1] A method for operating an access to a cache memory via an effective address, comprising a tag field and a cache line index field, the cache memory having a primary cache directory that is logically addressed and logically tagged, the method comprising: Determining (501) a first group of bits and a second group of bits of the marking field; Providing a record directory that is logically indexed using line index bits of the cache line index field and logically marked using the first group of bits; Providing a validation dictionary that is logically indexed using the row index bits and set bits and logically marked using the second group of bits; a first search (503) for the row index bits and the first group of bits of the effective address in the set directory and generating a set identifier indicating the set containing the respective cache line of the effective address; second searching (505) for the record identifier, the row index bits and the second group of bits of the effective address in the validation directory; in response to determining a presence of the cache line in the set based on the second search, generating (507) a hit signal. [2] The method of claim 1, if the second search does not confirm the presence of the cache line in the set, generating a miss signal. [3] The method of claim 1, wherein the cache further comprises a translation lookaside buffer (TLB), wherein a given entry in the primary cache directory stores a valid bit, a portion of the effective address, and a set index, wherein if the second lookup does not confirm the presence of the cache line in the set, the method further comprises: Searching for the row index bits in the primary cache directory, resulting in a logical pointer for each entry found, where the logical pointer has the set index of the set in which the entry exists and the section of the effective address; Selecting a logical pointer of the logical pointers whose record index matches the record identifier; Searching for the effective address in the TLB to identify an absolute address associated with the effective address; searching for the effective address in a higher-level secondary cache directory of the cache memory to obtain an entry corresponding to the effective address in each set of the secondary cache directory, the entry having a further absolute address; Comparing each obtained absolute address of the secondary cache directory with the absolute address of the TLB, resulting in a further set identifier of a set of the secondary cache directory; Comparing the logical address of the entry of the secondary cache directory set having the further set identifier with the selected logical pointer, and based on the comparison results, asserting the miss signal and / or updating the set and validation directories accordingly. [4] The method of claim 3, wherein the searching of the primary cache directory is performed in parallel with the first search. [5] The method of claim 4, further comprising: generating the hit signal is performed when the valid bit of the logical pointer is set to a valid state. [6] The method of claim 3, wherein the TLB search and the secondary cache directory search are performed in parallel. [7] The method of claim 1, wherein the first group of bits are the least significant bits from the tag field and the second group of bits are the most significant bits from the tag field. [8] The method of claim 1, wherein the validation directory is constructed from a particular physical array structure that stores one directory entry per cache line of all sets of the cache memory. [9] The method of claim 1, wherein a given entry in the primary cache directory stores a valid bit, a portion of the effective address, and a set index, the method further comprising: in parallel with the first search, searching the row index bits in the primary cache directory resulting in a valid bit value for each found entry in the primary cache directory, selecting a valid bit value of the valid bit values whose associated set index matches the set identifier, wherein generating the hit signal is performed when the valid bit value indicates a valid state. [10] The method of claim 1, wherein the primary cache directory is an L1 level cache directory. [11] The method of claim 3, wherein the secondary cache directory is an L2 level cache directory. [12] The method of claim 1, wherein the cache memory is a multi-level cache directory further comprising a secondary cache directory. [13] The method of claim 1, wherein a given entry in the primary cache directory stores a valid bit, a portion of the effective address, and a set index, the method further comprising: Receiving a second effective address that is a synonym of the effective address; Repeating the first and second searches using the second effective address; if the second search does not confirm the presence of the cache line to which the second effective address refers, invalidating the record directory entry corresponding to the second effective address; performing the first search using the second effective address to detect an error; first searching for the second effective address in the primary cache directory, resulting in a logical pointer for each record in the primary cache directory, the logical pointer comprising the record index and the portion of the second effective address; second searching for the second effective address in a higher-level secondary cache directory of the cache memory to obtain an entry corresponding to the second effective address in each set in the secondary cache directory; Comparing the logical address of the entry of the set of the secondary cache directory with each of the logical pointers, and based on the comparison results, confirming the presence of the cache line in the primary cache directory; Updating the record and validation directories by overwriting entries related to the effective address with the second effective address; Repeat the steps of the first search, the second search and the generation of the hit signal. [14] The method of claim 1, further comprising: in response to receiving a request to invalidate an entry of the validation directory, accordingly setting a valid bit of the corresponding entry in the primary cache directory. [15] The method of claim 14, further comprising providing a first auxiliary data structure in association with the primary cache directory, wherein each entry of the first auxiliary data structure comprises bits of the effective address reflecting information specified in TLB flush requests of the multiprocessor system that identify an entry in the first auxiliary data structure corresponding to the received request, the identified entry specifying the primary cache directory entry. [16] The method of claim 1, further comprising: providing a second auxiliary data structure in association with the primary cache directory, the second auxiliary data structure being logically indexed and physically tagged; in response to receiving a request to store an entry in the L1 cache, using the second auxiliary data structure to identify the absolute address of a data storage location and storing the entry at the data storage location using the absolute address. [17] An apparatus for controlling access to a cache line via an effective address, comprising a tag field and a cache line index field, the tag field comprising a first group of bits and a second group of bits; the apparatus comprising: - a primary cache directory that is logically addressed and logically marked; - a record directory logically indexed using line index bits of the cache line index field and logically marked using the first group of bits; - a validation directory logically indexed using the row index bits and set bits and logically marked using the second group of bits; wherein the set directory is configured to receive the row index bits and the first group of bits of the effective address and to generate a set identifier indicating the set containing the respective cache line of the effective address; wherein the validation directory is configured to receive the set identifier, the row index bits, and the second group of effective address bits and to return a set identifier indicating the set in which the cache line is located. [18] A computer program product comprising a computer-readable data storage medium having computer-readable program code formed thereon, wherein the computer-readable program code is configured to implement the following steps: Determining a first group of bits and a second group of bits of the marking field; Providing a record directory that is logically indexed using line index bits of the cache line index field and logically marked using the first group of bits; Providing a validation dictionary that is logically indexed using the row index bits and set bits and logically marked using the second group of bits; first searching for the row index bits and the first group of bits of the effective address in the set directory and generating a set identifier that indicates the set containing the respective cache line of the effective address; second search for the record identifier, the row index bits and the second group of bits of the effective address in the validation dictionary; in response to determining a presence of the cache line in the set based on the second search, generating a hit signal. [19] The computer program product of claim 18, further comprising the steps of: in response to receiving a request to invalidate an entry of the validation directory, accordingly setting a valid bit of the corresponding entry in the primary cache directory. [20] The computer program product of claim 19, further comprising the steps of: providing a first auxiliary data structure in association with the primary cache directory, wherein each entry of the first auxiliary data structure comprises bits of the effective address reflecting information specified in TLB flush requests of the multiprocessor system that identify an entry in the first auxiliary data structure corresponding to the received request, the identified entry specifying the primary cache directory entry.

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