Self-adapting analog-to-digital converter

Abstract

A method for performing an analog-to-digital conversion using an analog-to-digital converter (ADC) with a successive approximation register (SAR), the method comprising: performing bit tests using a digital-to-analog converter (DAC) circuit of the SAR-ADC to convert a first sample of an analog input signal into an N-bit output; before performing bit trials on a second sample of the analog input signal, precharging M bits of the N-bit output from the first sample onto the DAC circuit, where M is less than N; prior to conversion, comparing the second sample to a range having an upper limit and a lower limit, the upper limit and the lower limit being based on a representation of the precharged M bits; if the comparison indicates that the second sample is within the range, performing bit trials on the second sample to determine the remaining (NM) bits; if the comparison indicates that the second sample is not within the range, performing bit trials on the second sample to determine all N bits; and Controlling a value of M using at least one result of a previous bit attempt.

Description

AREA OF REVELATION

[0001] This document refers generally, but not restrictively, to integrated circuits and, in particular, to analog-to-digital converter (ADC) circuits. BACKGROUND

[0002] An analog-to-digital converter (ADC) circuit can be used to convert an analog signal into a digital signal, which can then be further processed or used in the digital domain. A successive approximation (SAR) ADC circuit can perform bit trials to compare portions of the analog signal to a reference voltage to determine the digital bit values ​​of a digital word representing a particular sample of the analog signal. A SAR ADC can use a capacitor array of a digital-to-analog converter (DAC) to perform the bit trials to determine the respective digital bit values ​​of the digital word.

[0003] US 7 038 609 B1 relates to an enhanced-performance SAR converter in which the most significant bits of the SAR are effectively precharged with a value that makes the output of the associated DAC nearly equal to the signal to be converted. A normal SAR conversion is then completed with the unprecharged SAR bits. The value for precharging the most significant SAR bits is preferably obtained from a low-resolution, high-speed converter, such as a flash ADC. The range of DAC bits used in the normal SAR part of the conversion can be extended so that errors up to a certain size can be corrected in the high-speed converter. Reducing the power consumption of a SAR system can be achieved by lowering the comparator supply voltage.Under these conditions, significant comparator input voltage fluctuations are to be expected in a SAR converter architecture with a capacitor array DAC (CAPDAC). If the input voltage fluctuation becomes too large, damage to the comparator input components or inaccuracies may occur. In one example of the teaching, the most significant bits are provided by sampling the input signal via a flash ADC, which is not subject to the input voltage limitation described above.

[0004] US 9,712,181 B1 concerns the topic of precharging several of the most significant bits with predetermined bit decisions during operation of a SAR ADC before performing the bit tests. A system and method are provided for progressively precharging the predetermined bit decisions so that the voltages applied to the comparator inputs are maintained within a limited range of permissible input voltages. SUMMARY OF REVELATION

[0005] This disclosure presents techniques that can increase the speed of a SAR ADC and / or reduce its power consumption. The present inventors propose a self-adapting SAR ADC approach in which one or more bits from a conversion of a previous sample of the analog input signal can be precharged to a DAC circuit of the ADC. If the precharged bits are determined to be acceptable, bit trials can be performed on the current sample to determine the remaining bits. If these are not acceptable, the ADC can discard the precharged bits and perform bit trials for all bits. The self-adapting SAR ADC can include a control loop to tune, e.g., increase or decrease, the number of bits precharged in a subsequent bit trial using historical data.

[0006] In one aspect, this disclosure is directed to a method for performing analog-to-digital conversion using a successive approximation register (SAR) analog-to-digital converter (ADC). The method comprises: performing bit trials using a digital-to-analog converter (DAC) circuit of the SAR ADC to convert a first sample of an analog input signal to an N-bit output; prior to performing bit trials on a second sample of the analog input signal, precharging M bits of the N-bit output from the first sample to the DAC circuit, where M is less than N; prior to conversion, comparing the second sample to a range having an upper bound and a lower bound, the upper bound and the lower bound being based on a representation of the precharged M bits;if the comparison indicates that the second sample is within the range, performing bit trials on the second sample to determine the remaining (NM) bits; if the comparison indicates that the second sample is not within the range, performing bit trials on the second sample to determine all N bits; and controlling a value of M using at least one result of a previous bit trial.

[0007] In one aspect, this disclosure is directed to a method for performing analog-to-digital conversion using first and second successive approximation register (SAR) analog-to-digital converters (ADCs). The method comprises: converting a first sample of an analog input signal to an N-bit output; before performing bit trials on a second sample of the analog input signal, precharging at least some of the most significant bits (MSBs) of the N-bit output from the first sample to a DAC circuit of the first ADC; using the first ADC, comparing the second sample to a first range having a first upper bound and a first lower bound, the first upper bound and the first lower bound based on a representation of the precharged MSBs;if the comparison indicates that the second sample is within the first range, precharging M bits of the N-bit output from the first sample to a DAC circuit of the second ADC; prior to conversion, comparing the second sample to a second range having a second upper bound and a second lower bound, the second upper bound and the second lower bound being based on a representation of the precharged M bits; if the comparison indicates that the second sample is within the second range, performing bit trials on the second sample to determine the remaining (NM-precharged MSB) bits; and if the comparison indicates that the second sample is not within the second range, performing bit trials on the second sample to determine the (N-precharged MSB) bits.

[0008] In one aspect, this disclosure is directed to a self-adapting successive approximation register (SAR) analog-to-digital converter (ADC), comprising: a switched-capacitor digital-to-analog converter (DAC) circuit having a plurality of capacitor elements, each element having a first plate and a second plate and corresponding to a digital bit position, the DAC circuit configured to sample an analog input signal and convert a first sample of an analog input signal into an N-bit output; and control circuitry. The control circuitry is configured to: perform bit trials using the DAC circuit to convert the first sample of the analog input signal into the N-bit output;before performing bit tests on a second sample of the analog input signal, preloading M bits of the N-bit output from the first sample onto the DAC circuit, where M is less than N; before conversion, comparing the second sample to a range having an upper bound and a lower bound, the upper bound and the lower bound being based on a representation of the preloaded M bits; if the comparison indicates that the second sample is within the range, performing bit tests on the second sample to determine the remaining (NM) bits; if the comparison indicates that the second sample is not within the range, performing bit tests on the second sample to determine all N bits; and controlling a value of M using at least one result of a previous bit test.

[0009] This summary is intended to provide an overview of the subject matter of the present patent application. It is not intended to provide an exclusive or exhaustive explanation of the invention. The detailed description is included to provide further information about the present patent application. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the drawings, which are not necessarily drawn to scale, like numbers may describe similar components in different views. Like numbers with different letter suffixes may represent different instances of similar components. The drawings generally illustrate various embodiments discussed in this document by way of example and not by way of limitation. Fig. 1 is a functional block diagram of an example SAR ADC that can implement various techniques of this disclosure. Fig. 2 is a flowchart showing an example of a method for operating a successive approximation register (SAR) analog-to-digital converter (ADC) integrated circuit device. Fig. Figure 3 is a functional block diagram of an example ADC with a main ADC and an auxiliary ADC. Fig. 4 is a flowchart showing an example of a method for operating a successive approximation register (SAR) analog-to-digital converter (ADC) integrated circuit device, the ADC having a main ADC and an auxiliary ADC. DETAILED DESCRIPTION

[0011] A SAR-ADC (Successive Approximation Routine) converts an analog signal into a digital word in a successive approximation manner using a binary search. A traditional SAR-ADC first determines the most significant bit (MSB), followed by the MSB-1 bit, the MSB-2 bit, and finally the least significant bit (LSB). For an N-bit word, the traditional SAR-ADC approach uses N-bit trial cycles of a digital-to-analog converter (DAC) circuit to determine the N bits. The present inventors have recognized that there can be several challenges with this traditional approach, including limitations on the speed of the SAR-ADC and high power consumption.

[0012] This disclosure describes, among other things, techniques that can increase the speed of the SAR ADC and / or reduce its power consumption. As described in detail below, the present inventors propose a self-adapting SAR ADC approach in which one or more bits from a conversion of a previous sample of the analog input signal can be precharged to the DAC circuit. Before performing bit trials on a current sample, the current sample can be compared to a range having an upper bound and a lower bound based on a representation of the precharged M bits. If the current sample is determined to be within the range, bit trials can be performed on the current sample to determine the remaining bits.

[0013] In this way, a conversion time can be reduced by one or more bit trial cycles, improving the ADC's speed and reducing its power consumption for small signals and large, but slowly changing signals. If the comparison indicates that the current sample is not within range, the ADC can discard the preloaded bits and instead perform bit trials on all bits. The self-adapting SAR ADC can include a control loop to tune, e.g., increase or decrease, the number of bits preloaded in a subsequent bit trial using historical data.

[0014] Fig. 1 is a functional block diagram of an example SAR-ADC 100 that can implement various techniques of this disclosure. In the example, a differential analog input voltage is sampled and held using a sampling circuit 105, and a differential output voltage of a DAC circuit 110 is compared to the sampled and held voltage using a comparator circuit 115. The bit values ​​of the DAC circuit 110 are adjusted based on the output of the comparator circuit. Conversion can begin with the DAC set to mid-scale. The comparator 115 determines whether the DAC output is greater or less than the sampled input voltage, and the result is stored as a one or zero for that bit of the DAC. The conversion then proceeds to the next bit value until all bits of the digital value are determined.One iteration of changing the DAC output and comparing the voltage to the sampled input can be referred to as a bit trial. SAR logic circuitry 120 controls ADC operation during the bit trials. When the bit trials are complete, the digital value of the sampled and held voltage is available at the Dout output.

[0015] In some example implementations, DAC circuit 110 may include two switched-capacitor DAC (CDAC) arrays, a first CDAC, referred to as a "P-DAC," connected to a non-inverting input of comparator 115, and a second CDAC, referred to as an "N-DAC," connected to an inverting input of comparator 115. Each CDAC includes a plurality of capacitors, each capacitor having a first and a second plate.

[0016] Each of the capacitors of the CDAC array has an associated switch operable to selectively connect a first plate, e.g., the lowest or "bottom" plate, to either the first reference voltage Vrefp or the second reference voltage "Vrefn," depending on the bit test result. Generally, Vrefn corresponds to ground, and Vrefp is positive relative to Vrefn. In some implementations, the basic SAR algorithm may incorporate a "guess->decide->set" approach to switching bit test capacitors. Each bit can be "set" (e.g., connected to Vrefp) at the beginning of that particular bit test, and based on the bit test output, that bit setting can be maintained or "reset" (e.g., connected to Vrefn).

[0017] As mentioned above, this disclosure describes, among other things, a self-adapting SAR ADC approach in which one or more bits from a conversion of a previous sample of the analog input signal may be precharged to a DAC circuit of the ADC. If the precharged bits are determined to be acceptable, bit trials may be performed on the current sample to determine the remaining bits. If these are not acceptable, the ADC may discharge the precharged bit trial capacitors and perform bit trials on all bits. The self-adapting SAR ADC may include a control loop to tune, e.g., increase or decrease, the number of bits precharged in a subsequent bit trial using historical data.

[0018] In addition to the SAR logic circuitry 120, and according to various techniques of this disclosure, the control circuitry 130 may further include: a first memory circuit 132 coupled to the output of the SAR logic circuitry 120 and configured to store at least one previous digital output result Dout, a second memory circuit 134, e.g., registers, coupled to the output of the comparator 115 and configured to store a success indication for past conversions, and a precharge width control circuit 136 configured to receive information stored in the second memory circuit 134 and to determine and control a bit width to be precharged.

[0019] The SAR-ADC 100 from Fig. 1 can receive an analog input signal. Using DAC circuit 110, SAR-ADC 100 can perform bit trials to convert a first sample of an analog input signal into an N-bit output (Dout), as described above.

[0020] According to this disclosure, control circuitry 130 may store the N-bit output in first storage circuit 132. Before performing bit trials on a second sample of the analog input signal, precharge width control circuit 136 may precharge M bits of the N-bit output from the first sample to DAC circuit 110, e.g., to capacitor elements of a capacitive DAC, where M is less than N. For example, SAR logic control circuit 120 may receive a value of M from precharge width control circuit 136 and precharge M bits of the N-bit output from the first sample to DAC circuit 110.

[0021] In one non-limiting specific example, the control circuit may store a 10-bit output in the first storage circuit 132. Before performing bit trials on a second sample of the analog input signal, the SAR logic control circuit 120 may receive a value of M = 4 from the precharge width control circuit (or precharge depth control circuit) 136 and precharge 4 bits (e.g., MSB, MSB-1, MSB-2, and MSB-3) of the 10-bit output from the first sample onto the DAC circuit 110, e.g., onto capacitor elements of a capacitive DAC.

[0022] The present inventors have determined that prior to conversion, it may be desirable to compare the second sample to upper and lower bounds to determine if convergence is possible. That is, the precharge width control circuit 136 may compare the second sample to a range having an upper bound and a lower bound based on a representation of the precharged M bits, e.g., the precharged bits plus offsets. For example, the precharge width control circuit 136 may 1) compare the second sample to an upper bound determined by the precharged M bits plus a first offset, e.g., a positive offset, and 2) compare the second sample to a lower bound determined by the precharged M bits plus a second offset, e.g., zero offset. The offsets may be provided using either digital or analog techniques.In some example analog implementations, the first and second offsets may be provided by switching the remaining (NM) bits, e.g., capacitors in the DAC circuit 110 or capacitors coupled to the DAC circuit 110, between high and low.

[0023] For example, SAR logic circuitry 120 may set the remaining (NM) bits high after a precharge, and precharge width control circuitry 136 may compare the second sample to an upper limit determined by the representation of the precharged M bits plus the offset provided by the remaining (NM) bits being set high. Then, SAR logic circuitry 120 may set the remaining (NM) bits low, and precharge width control circuitry 136 may compare the second sample to a lower limit determined by the representation of the precharged M bits plus the offset provided by the remaining (NM) bits being set low.In some example implementations, some of the remaining (NM) bits may be set high and some may be set low to provide an upper or lower bound that is less than a maximum upper bound and greater than a lower minimum bound.

[0024] If the comparison indicates that the second sample is greater than the lower limit and less than the upper limit, then the second sample is within range, and the binary search will converge to a digital output for conversion. If the precharge width control circuit 136 determines from the comparison that the second sample is within range, the SAR logic circuitry 120 may perform bit trials on the second sample to determine the remaining (NM) bits. In this way, the SAR ADC may store M bit trial cycles as a result of the precharged M bits. Continuing with the above non-limiting specific example, the SAR logic circuitry 120 may perform bit trials on the second sample to determine the remaining 6 bits of the 10-bit output, thereby saving 4 bit trial cycles.

[0025] If the comparison indicates that the second sample is greater than the upper limit or less than the lower limit, then the second sample is not within range, and the binary search will not converge to a digital output for conversion. If the precharge width control circuit 136 determines from the comparison that the second sample is not within range, the SAR logic circuitry 120 may not use the precharged bits. Instead, the SAR logic circuitry 120 may perform bit trials on the second sample to determine all N bits.

[0026] In addition, as mentioned above, the SAR-ADC 100 can Fig. 1 be self-adaptive. In particular, the SAR ADC may include a control loop to control, e.g., increase or decrease, the number of M bits precharged in a subsequent bit attempt using historical data. For example, the precharge width control circuit 136 may store data in the second storage circuit 134 for at least some previous samples, e.g., registers representing a result of comparing the precharged M bits to a respective sample. Using the stored data, the precharge width control circuit 136 may control a value of M.

[0027] As an example, precharge width control circuit 136 may store data in second memory circuit 134, e.g., registers representing the results of comparing the precharged M bits to K previous samples. Precharge width control circuit 136 may determine a success indication using the stored data and may select the value of M from a set of values ​​of M based on the success indication.

[0028] In some examples, the precharge width control circuit 136 may compare the number of successful results stored in the second memory 134 with the total number of stored K previous samples to determine a success indication. In other examples, the precharge width control circuit 136 may compare the number of unsuccessful results stored in the second memory 134 with the total number of stored K previous samples to determine a success indication. In some examples, the precharge width control circuit 136 may compare the number of successful results stored in the second memory 134 with the number of unsuccessful results to determine a success indication.

[0029] Based on the success indication, precharge width control circuit 136 may select a lower value of M if the success indication is below a first threshold and may select a higher value of M if the success indication is above a second threshold. In some examples, the first and second thresholds may have the same value. In other examples, the first and second thresholds may be different values ​​to provide hysteresis.

[0030] In one non-limiting specific example, precharge width control circuit 136 may store the results of 20 previous comparisons of precharged M bits with previous samples in second storage circuit 134. For example, a success could be stored in a register as a "1" and a failure as a "0." For example, if 15 successes and 5 failures occurred, precharge width control circuit 136 may compare the number of successful results (15) to the total number of stored previous samples (20) to determine a success indication of 75%. Assuming a first threshold of 45% and a second threshold of 55%, precharge width control circuit 136 may select a higher value of M because the success indication is above the second threshold.For example, assuming M was initially set to 4, precharge width control circuit 136 may select a value of 8, allowing more bits to be precharged. This allows ADC 100 to adjust its precharge bit width using historical data without user control and is therefore self-adapting.

[0031] In some example implementations, instead of storing data in the second memory circuit 134, e.g., registers representing only the results of comparing the precharged M bits with a number of K previous samples, the precharge width control circuit 136 may additionally or alternatively calculate and store data representing the maximum value of M that would have caused the sample to fall within the range of the precharged M bits, referred to in this disclosure as "M_best." The value of M_best may be calculated for one or more previous samples based on the digitized values ​​of those samples.

[0032] In an example implementation, after converting and using the previous sample and the current sample, the precharge width control circuit 136 may determine M_best by determining how many bits from the previous sample could have been precharged while keeping the current sample within the range of precharged bits. The precharge width control circuit 136 may store values ​​of M_best for multiple samples in the second storage circuit 134. As described below, the ADC 100 may adjust its precharge bit width M using the stored values ​​of M_best.

[0033] In some examples, precharge width control circuit 136 may set a next value of M to the minimum M_best over the previous K samples. In other examples, precharge width control circuit 136 may set a next value of M to the M value that would have minimized the total bit attempts over the previous K samples. The total number of bit attempts required for the previous K samples when precharging M bits may be calculated based on the stored values ​​of M_best.

[0034] In some examples, precharge width control circuit 136 may increment M to this next higher value if the next higher value of M would have had a success indication rate above a threshold for the previous K samples. In other examples, precharge width control circuit 136 may decrement M to this lower value if the next lower value of M would have resulted in a lower total number of bit attempts than the current value of M over the previous K samples.

[0035] Fig. 2 is a flowchart illustrating an example of a method 200 for operating an integrated circuit device with a successive approximation register (SAR). At block 202, an ADC, such as the ADC 100 of Fig. 1, perform bit tests, e.g., using the DAC circuit 110 of Fig. 1 to convert a first sample of an analog input signal into an N-bit output, e.g., 10-bit. At block 204, prior to performing bit tests on a second sample of the analog input signal, a SAR logic control circuit, e.g., the SAR logic 120 of Fig. 1, a value of M from a precharge width control circuit, e.g., circuit 136 of Fig. 1, and can preload M bits, e.g. 4 bits, of the N-bit output, e.g. 10 bits, from the first sample to the DAC circuit.

[0036] At block 206, prior to conversion, a precharge width control circuit, e.g., circuit 136 of Fig. 1, compare the second sample to a range having an upper limit and a lower limit, where the upper limit and the lower limit are based on a representation of the precharged M bits. For example, the precharge width control circuit 136 may 1) compare the second sample to an upper limit determined by the representation of the precharged M bits plus a first offset, e.g., a positive offset, and 2) compare the second sample to a lower limit determined by the representation of the precharged M bits plus a second offset, e.g., zero offset.

[0037] If at block 208, the comparison indicates that the second sample is within range ("YES" branch of block 208), the SAR logic circuitry may perform bit trials on the second sample to determine the remaining (NM) bits (block 210). If the comparison indicates that the second sample is not within range ("NO" branch of block 208), the SAR logic circuitry may perform bit trials on the second sample to determine all N bits (block 212).

[0038] If the comparison indicates that the second sample is greater than the lower limit and less than the upper limit, then the second sample is within range, and the binary search will converge to a digital output for conversion. If the precharge width control circuit 136 determines from the comparison that the second sample is within range, the SAR logic circuitry 120 may perform bit trials on the second sample to determine the remaining (NM) bits. In this way, the SAR ADC may store M bit trial cycles as a result of the precharged M bits. Continuing with the above non-limiting specific example, the SAR logic circuitry 120 may perform bit trials on the second sample to determine the remaining 6 bits of the 10-bit output, thereby saving 4 bit trial cycles.

[0039] If the comparison indicates that the second sample is greater than the upper limit or less than the lower limit, then the second sample is not within range, and the binary search will not converge to a digital output for conversion. If the precharge width control circuit 136 determines from the comparison that the second sample is not within range, the SAR logic circuitry 120 may not use the precharged bits. Instead, the SAR logic circuitry 120 may perform bit trials on the second sample to determine all N bits. At block 214, the precharge width control circuit 136 may control (or self-tune) a value of M using at least one result of a previous bit trial using one or more of the various techniques described above.

[0040] Using various techniques of this disclosure, a conversion time can be reduced by one or more bit trial cycles by predicting M from a previous sample. In some implementations, it may be desirable to use the time reduction to increase the speed and reduce the power consumption of the ADC. In other implementations, where speed and power consumption are less of an issue, the bit trial cycles saved by predicting M can be used to increase the signal-to-noise ratio of the sample. For example, the comparator, e.g., comparator 115 of Fig. 1, perform multiple comparisons with the same DAC voltage, and the comparator outputs can be averaged together to reduce the thermal noise of the comparator.

[0041] In some implementations, it may be desirable to use time reduction to perform background calibration of ADC bit weights to improve linearity. Higher-accuracy ADCs may require repeated calibration to ensure the ADC is compensated for, for example, capacitor voltage coefficient temperature drift and offset drift.

[0042] Background calibration operates in the background and can be transparent to normal ADC operation, during which analog-to-digital signal conversions are performed. Because background calibration operates in the background of normal operation, the effects of power supply and temperature on ADC bit weights can also be monitored.

[0043] One background calibration approach involves using one or more redundant ADC channels. However, such an approach can result in additional hardware, power consumption, and complexity.

[0044] In another approach, the same sample can be converted twice, and the capacitor(s) to be calibrated can be modulated after the first conversion. For example, dither can be added after the first conversion to determine a second result. In another example, instead of adding dither, the DAC elements, e.g., capacitors, etc., within a DAC element array can be "shuffled" and regrouped, and then selected to receive a reference voltage. Using either of these approaches, the difference between the results of the first and second conversions can contain the error information that can be used for calibration, and the signal component can be removed by this process.

[0045] According to this disclosure, any bit trial cycles stored by predicting M from a previous sample may, for example, be used to perform a background calibration after the ADC converges to N-bit accuracy. For example, if 6 bit trial cycles were stored in the conversion time (compared to a conventional conversion process), at least some of these bit trial cycles may be used to reconvert the sample after adding dither or shuffling and regrouping the DAC elements. The control circuitry may determine a difference between the results of the first and second conversions, which may contain the error information that may be used for calibration, and the signal component may be removed by this process.

[0046] The present inventors also recognized the desirability of using both a main ADC and an auxiliary ADC (or "mini-ADC"). The mini-ADC can provide low resolution using a smaller sampling capacitor and a relatively low-noise, low-power comparator, and a main ADC can provide high resolution.

[0047] A mini-ADC can help convert higher input voltage ranges using a low-voltage supply and can allow the main ADC to turn off its comparator during the acquisition phase. The mini-ADC can convert the input voltage to 2-bit accuracy using a binary search algorithm, for example. The mini-ADC can perform this conversion before the main ADC performs any action. The mini-ADC can then transmit the low-resolution conversion results to the main ADC, which can then resolve the remaining bits.

[0048] For a conventional binary search ADC, an initial estimate is Vref / 2, so the maximum error in the initial estimate is Vref / 2. However, using the predictive ADC of this disclosure, the initial estimate could potentially be Vref while the actual input voltage could be 0, resulting in twice the maximum error. As such, the present inventors recognized that it may be desirable to use a mini-ADC to prevent the main ADC from having an initial estimate that is too far from the actual input voltage. In this case, the voltage at certain nodes in the main ADC's DAC could be out of bounds, leading to accuracy problems and possibly overvoltage of the transistors.

[0049] Fig. 3 is a functional block diagram of an example of an ADC system 300 having a main ADC 100 and an auxiliary ADC 302. The main ADC circuit 100 has features similar to those described above with respect to Fig. 1, and for clarity, these features will not be described in detail again. The mini-ADC circuit 302 may be coupled between an input IN of the main ADC 100 and the precharge width control circuit 136.

[0050] Similar to the above and in accordance with this disclosure, the system 300 may convert a first sample of an analog input signal into an N-bit output, and the control circuitry 130 may store the N-bit output in the first memory circuit 132.

[0051] Before performing bit tests on a second sample of the analog input signal, precharge width control circuit 136 may precharge at least some of the MSBs from the first sample to a DAC circuit in mini-ADC 302, e.g., to capacitor elements of a capacitive DAC. It may be desirable to compare the second sample to upper and lower bounds to determine if convergence is possible. That is, precharge width control circuit 136 may compare the second sample to a range having an upper bound and a lower bound based on a representation of the precharged MSBs, e.g., the precharged MSBs plus offsets.

[0052] For example, precharge width control circuit 136 may 1) compare the second sample to an upper limit determined by the precharged MSBs plus a first offset, e.g., a positive offset, and 2) compare the second sample to a lower limit determined by the precharged MSBs plus a second offset, e.g., zero offset. In some examples, the first and second offsets may be provided by switching the remaining (NM) bits, e.g., capacitors in the DAC circuit of mini-ADC 302, between high and low.

[0053] If the comparison indicates that the second sample is less than the lower limit or greater than the upper limit, then the second sample is not within the range defined by the MSBs plus an offset, and the binary search will not converge to a digital output for conversion. Consequently, system 300 may perform a full SAR conversion to determine a result.

[0054] If the comparison indicates that the second sample is greater than the lower limit and less than the upper limit, then the second sample is within the range defined by the MSBs plus an offset, and the binary search will converge to a digital output for conversion. If the comparison indicates that the second sample is within the range, the precharge width control circuit 136 may precharge M bits of the N-bit output from the first sample to the DAC circuit 110 of the main ADC 100. For example, the precharge width control circuit 136 may transfer charge from a capacitive DAC of the mini-ADC to the capacitive DAC of the main ADC, thereby precharging the MSBs precharged on the mini-ADC 302. Then the precharge width control circuit 136 can precharge additional bits after the mini-ADC MSB bits, so that M bits of the N-bit output are now precharged to the DAC of the main ADC.

[0055] Similar to the above, prior to a conversion, the precharge width control circuit 136 may compare the second sample to another range having an upper bound and a lower bound, where the upper bound and lower bound are based on a representation of the precharged M bits, e.g., the precharged M bits plus offsets. If the comparison indicates that the second sample is greater than the lower bound and less than the upper bound, then the second sample is within the range, and the binary search will converge to a digital output for the conversion. If the precharge width control circuit 136 determines from the comparison that the second sample is within the range, the SAR logic circuitry 120 may perform bit trials on the second sample to determine the remaining bits. In this way, the SAR ADC may store M bit trial cycles as a result of the precharged M bits.

[0056] If the comparison indicates that the second sample is not within range, the SAR logic circuitry 120 may discard the bits after the precharged MSB bits and perform bit attempts on the second sample, starting with the bit after the last bit precharged by the mini-ADC 302.

[0057] In addition, as mentioned above, the SAR-ADC 100 can Fig. 1 be self-adaptive. In particular, the SAR ADC may include a control loop to control, e.g., increase or decrease the number of M bits preloaded in a subsequent bit trial using historical data, as described above, which is not described again in detail for the sake of clarity.

[0058] Fig. 4 is a flowchart illustrating an example of a method 400 for operating a successive approximation register (SAR) analog-to-digital converter (ADC) integrated circuit device, wherein the ADC includes a main ADC and an auxiliary ADC. At block 402, an ADC system, e.g., the system 300 of Fig. 3, perform bit tests, e.g., using the DAC circuit 110 of Fig. 3, to convert a first sample of an analog input signal into an N-bit output, e.g., 10-bit. At block 404, prior to performing bit tests on a second sample of the analog input signal, a SAR logic control circuit, e.g., the SAR logic 120 of Fig. 3, at least some of the MSBs of the N-bit output from the first sample to the DAC circuit of a mini-ADC, e.g., the mini-ADC of Fig. 3, preload.

[0059] At block 406, the precharge width control circuit 136 may compare the second sample to a first range having an upper limit and a lower limit based on a representation of the precharged MSBs, e.g., the precharged MSBs plus offsets. If the comparison is not within the first range (“NO” branch of decision block 406), then the binary search does not converge to a digital output for conversion, and the system, e.g., the system 300 of Fig. 3, may perform bit trials on the second sample to determine all N bits (block 408). If the comparison indicates that the second sample is within range ("YES" branch of decision block 406), the precharge width control circuit 136 may precharge M bits of the N-bit output from the first sample to the DAC circuit 110 of the main ADC 100 (block 410).

[0060] For example, the control circuit 130 of Fig. 3 the charge from a capacitive DAC of the Mini-ADC 302 of Fig. 3 to the capacitive DAC of the main ADC 100 of Fig. 3, thereby precharging the MSBs precharged onto the mini-ADC 302. Then, the precharge width control circuit 136 can precharge additional bits after the MSBs, so that M bits of the N-bit output are now precharged onto the DAC of the main ADC.

[0061] At block 412, prior to conversion, the precharge width control circuit 136 may compare the second sample to a second range having an upper bound and a lower bound, wherein the second upper bound and the second lower bound are based on a representation of the precharged M bits, e.g., the precharged M bits plus offsets.

[0062] If the precharge width control circuit 136 determines from the comparison that the second sample is not within range ("NO" branch of decision block 414), the SAR logic circuitry 120 may discard the bits after the precharged MSB bits and then perform bit trials on the second sample, starting with the bit after the last bit precharged by the mini-ADC (block 416). In other words, the SAR logic circuitry 120 may determine the remaining (N-(precharged MSB)) bits.

[0063] If the comparison indicates that the second sample is greater than the lower limit and less than the upper limit, the precharge width control circuit 136 determines from the comparison that the second sample is within range ("YES" branch of decision block 414), and the SAR logic circuitry 120 may perform bit trials on the second sample to determine the remaining (NM (precharged MSB)) bits (block 418). In this way, the SAR ADC may store bit trial cycles as a result of the precharged M bits.

[0064] At block 420, the precharge width control circuit 136 may control (or self-tune) a value of M using at least one result of a previous bit attempt using one or more of the various techniques described above.

[0065] In addition, any bit trial cycles generated using the techniques of Fig.4 can be used to increase the SNR or to perform background calibration techniques as described above. Various comments

[0066] Each of the non-limiting aspects or examples described herein may stand alone or may be combined in various permutations or combinations with one or more of the other examples.

[0067] The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "aspects" or "examples." Such examples may include elements in addition to those shown or described. However, the inventors of the present invention also contemplate examples in which only those elements shown or described are provided.Furthermore, the inventors of the present invention also intend examples that use any combination or permutation of those elements shown or described (or one or more aspects thereof), either with reference to a particular example (or one or more aspects thereof) or with reference to other examples (or one or more aspects thereof) shown or described herein.

[0068] In the event of any inconsistency between this document and any other documents incorporated by reference, the usage in this document shall prevail.

[0069] Throughout this document, the terms "a," "an," or "one" are used as is customary in patent documents to include one or more than one, regardless of any other instances or uses of "at least one" or "one or more." Throughout this document, the term "or" is used to refer to a non-exclusive "or," which includes "A or B," "A but not B," "B but not A," and "A and B," unless otherwise noted. Throughout this document, the terms "including" and "wherein" are used as the plain English equivalents of the respective terms "having" and "wherein."Furthermore, the terms "including" and "comprising" in the following claims are open-ended terms, meaning that a system, apparatus, article, composition, formulation, or process that includes elements in addition to those listed after such a term in a claim is still considered within the scope of that claim. Furthermore, in the following claims, the terms "first," "second," and "third," etc., are used merely as labels and are not intended to impose numerical requirements regarding their objects.

[0070] Method examples described herein may be at least partially machine- or computer-implemented. Some examples may include a computer-readable medium or a machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. Implementation of such methods may include code such as microcode, assembly language code, high-level language code, or the like. Such code may include computer-readable instructions for performing various methods. The code may form portions of computer program products. Further, in one example, the code may be tangibly stored on one or more transient, non-transitory, or non-transitory tangible computer-readable media, such as during execution or at other times.Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact discs and digital video discs), magnetic cartridges, memory cards or flash drives, random access memories (RAMs), read-only memories (ROMs), and the like.

[0071] The above description is intended to be illustrative and not restrictive. For example, the examples described above (or one or more aspects thereof) may be used in combination with one another. Other embodiments may be used, as would be apparent to one of ordinary skill in the art upon review of the above description. The abstract is provided to enable the reader to quickly ascertain the essence of the technical disclosure. It is presented with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above detailed description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that any unclaimed disclosed feature is essential to any claim.Rather, the subject matter of the invention may lie in fewer than all features of a particular disclosed embodiment. Accordingly, the following claims are incorporated into the detailed description as examples or embodiments, each claim standing on its own as a separate embodiment, and it is intended that such embodiments may be combined with one another in various combinations and permutations. The scope of the invention should be determined by reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

[1] A method for performing an analog-to-digital conversion using an analog-to-digital converter (ADC) with a successive approximation register (SAR), the method comprising: performing bit tests using a digital-to-analog converter (DAC) circuit of the SAR-ADC to convert a first sample of an analog input signal into an N-bit output; before performing bit trials on a second sample of the analog input signal, precharging M bits of the N-bit output from the first sample onto the DAC circuit, where M is less than N; prior to conversion, comparing the second sample to a range having an upper limit and a lower limit, the upper limit and the lower limit being based on a representation of the precharged M bits; if the comparison indicates that the second sample is within the range, performing bit trials on the second sample to determine the remaining (NM) bits; if the comparison indicates that the second sample is not within the range, performing bit trials on the second sample to determine all N bits; and Controlling a value of M using at least one result of a previous bit attempt. [2] The method of claim 1, further comprising: if the comparison indicates that the second sample is within the range, performing additional bit attempts on the second sample using one or more remaining clock cycles of a preset number of clock cycles to convert the second sample such that a signal-to-noise ratio is increased. [3] The method of claim 1, further comprising: If the comparison indicates that the second sample is within range after the ADC has converged to N-bit accuracy, performing additional bit trials using one or more remaining clock cycles to perform an ADC background calibration. [4] The method of claim 1, wherein comparing the second sample to a range having an upper limit and a lower limit, the upper limit and the lower limit being based on a representation of the precharged M bits, comprises: Comparing the second sample with an upper limit determined by the representation of the precharged M bits plus a first offset; and Comparing the second sample with a lower bound determined by the representation of the preloaded M bits plus a second offset. [5] The method of claim 1, further comprising: for at least some previous samples, storing data representing a result of comparing the precharged M bits with the respective sample; and Control the value of M using the stored data. [6] The method of claim 5, further comprising: Determining an indication of success using the stored data, wherein controlling the value of M using the stored data comprises: Selecting the value of M from a set of values ​​of M based on the success indication. [7] The method of claim 6, wherein selecting the value of M from a set of values ​​of M based on the success indication comprises: Selecting a lower value of M if the success indication is below a first threshold; and Select a higher value of M if the success indication is above a second threshold. [8] The method of claim 1, further comprising: for at least some previous samples, storing data representing a maximum value of M (M_best) resulting in a respective sample being within the range, wherein M_best is calculated based on a sequence of values ​​of the previous samples; and Control the value of M for the next conversion using the stored data representing M_best. [9] A method for performing an analog-to-digital conversion using a first and a second analog-to-digital converter (ADC) with a successive approximation register (SAR), the method comprising: Converting a first sample of an analog input signal into an N-bit output; before performing bit trials on a second sample of the analog input signal, precharging at least some of the most significant bits (MSBs) of the N-bit output from the first sample to a DAC circuit of the first ADC; using the first ADC, comparing the second sample to a first range having a first upper limit and a first lower limit, the first upper limit and the first lower limit based on a representation of the precharged MSBs; if the comparison indicates that the second sample is within the first range, precharging M bits of the N-bit output from the first sample to a DAC circuit of the second ADC; prior to conversion, comparing the second sample to a second range having a second upper limit and a second lower limit, the second upper limit and the second lower limit being based on a representation of the precharged M bits; if the comparison indicates that the second sample is within the second range, performing bit trials on the second sample to determine the remaining NM-preloaded MSBs; and if the comparison indicates that the second sample is not within the second range, performing bit trials on the second sample to determine the N-precharged MSBs. [10] The method of claim 9, further comprising: if the comparison indicates that the second sample is within the second range, performing additional bit attempts on the second sample using one or more remaining clock cycles of a preset number of clock cycles to convert the second sample such that a signal-to-noise ratio is increased. [11] The method of claim 10, further comprising: for at least some previous samples, storing data representing a result of comparing the precharged M bits with the respective sample; and Controlling a value of M using the stored data. [12] The method of claim 11, further comprising: Determining an indication of success using the stored data, wherein controlling a value of M using the stored data comprises: Selecting the value of M from a set of values ​​of M based on the success indication. [13] The method of claim 12, wherein selecting the value of M from a set of values ​​of M based on the success indication comprises: Selecting a higher value of M if the success indication is below a threshold; and Select a lower value of M if the success indication is above the threshold. [14] The method of claim 12, wherein preloading M bits of the N-bit output from the first sample to a DAC circuit of the second ADC comprises: Precharging at least some of the M bits of the N-bit output using at least some of the MSBs from the DAC circuit of the first ADC. [15] The method of claim 12, wherein the first ADC has a lower resolution than the second ADC. [16] Self-adapting analog-to-digital converter (ADC) with successive approximation register (SAR) having: a switched-capacitor digital-to-analog converter (DAC) circuit comprising a plurality of capacitor elements, each element having a first plate and a second plate and corresponding to a digital bit position, the DAC circuit being configured to sample an analog input signal and convert a first sample of an analog input signal into an N-bit output; and a control circuit arrangement which is designed to: Performing bit trials using the DAC circuit to convert the first sample of the analog input signal into the N-bit output; before performing bit trials on a second sample of the analog input signal, precharging M bits of the N-bit output from the first sample onto the DAC circuit, where M is less than N; prior to conversion, comparing the second sample to a range having an upper limit and a lower limit, the upper limit and the lower limit being based on a representation of the precharged M bits; if the comparison indicates that the second sample is within the range, performing bit trials on the second sample to determine the remaining (NM) bits; if the comparison indicates that the second sample is not within the range, performing bit trials on the second sample to determine all N bits; and Controlling a value of M using at least one result of a previous bit attempt. [17] A self-adapting successive approximation register (SAR) analog-to-digital converter (ADC) according to claim 16, wherein, if the comparison indicates that the second sample is within the range, the control circuitry is further configured to: Performing additional bit attempts on the second sample using one or more remaining clock cycles of a preset number of clock cycles to convert the second sample such that a signal-to-noise ratio is increased. [18] A self-adapting successive approximation register (SAR) analog-to-digital converter (ADC) according to claim 16, wherein, if the comparison indicates that the second sample is within the range after the ADC converges to N-bit accuracy, the control circuitry is further configured to: Perform additional bit trials using one or more remaining clock cycles to perform ADC background calibration. [19] A self-adapting successive approximation register (SAR) analog-to-digital converter (ADC) according to claim 16, wherein the control circuitry configured to compare the second sample to a range having an upper limit and a lower limit, the upper limit and the lower limit being based on a representation of the precharged M-bits, is configured to: Comparing the second sample with an upper limit determined by the representation of the precharged M bits plus a first offset; and Comparing the second sample with a lower bound determined by the representation of the preloaded M bits plus a second offset. [20] Self-adapting analog-to-digital converter (ADC) with successive approximation register (SAR) according to claim 16, wherein the control circuitry is further configured to: for at least some previous samples, storing data representing a result of comparing the precharged M bits with the respective sample; and Control the value of M using the stored data.

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