Resistor and gate control in decoder circuits for read and write optimization

Abstract

Circuit diagram, including: a memory field or array (104, 400) comprising a plurality of memory cells; a path (414, 417) configured to supply a voltage for biasing one memory cell (MC) of the plurality of memory cells, wherein the path comprises: a variable resistance circuit (416) configured to: before switching on the memory cell (MC), an associated resistor is set to a high resistance level; and in response to an end time of an initial power-on period, to adjust the associated resistance from a high resistance level to a low resistance level, wherein the initial power-on period extends from a power-on time (t2) to the end time (t3) which precedes a read result acquisition event of the read operation.

Description

BACKGROUND

[0001] In some storage devices, such as those using phase-change memory, when reading data from a memory cell in a particular state during a read operation, the cell conducts a current spike or other current waveform similar to the current waveform of the memory cell used to program the cell in the other state. Consequently, the current spike conducted during the read operation can unintentionally alter the logical value of the data stored in the memory cell. Such an event can be referred to as a read error or a write error. To avoid or minimize the likelihood of such undesired events occurring, methods to reduce the similarity between the memory cell current conducted during a read operation and the memory cell current conducted during a write operation may be desirable.

[0002] US 2011 / 0188289 A1 relates to a memory with resistive memory elements arranged in a matrix between word lines and bit lines, wherein the amplitude of a signal used to access a memory element is modified as a function of the memory element's position in the matrix. US 2015 / 0262661 A1 relates to reducing write noise in a memory, wherein it is determined whether a so-called snapback occurs during a capture interval. US 2013 / 0003440 A1 relates to a driver circuit for controlling a three-dimensional array of memory cells. US 2012 / 0300532 A1 relates to changing the resistance state of a resistive memory element by applying voltage pulses. US 2013 / 0051137 A1 relates to detecting a snapback by a coupling capacitor in a phase-shift memory array. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The accompanying figures, which are included in and form part of this specification, illustrate various aspects of the invention and, together with the description, serve to explain its principles. Where appropriate, the same reference numbers or reference numerals are used in the figures to refer to identical or similar elements. Fig. 1A is a block diagram of an example storage system. Fig. Figure 1B is a block diagram of a memory module containing a variety of memory systems. Fig. 1C is a block diagram of a hierarchical storage system. Fig. 2A is a block diagram of example components of a controller of the storage system from Fig. 1A. Fig. 2B is a block diagram with example components of a memory chip of the memory system from Fig. 1A. Fig. Figure 3 is a perspective view of an example memory cell coupled to a word line and a bit line. Fig. Figure 4 is a block diagram of an example circuit coupled to a memory array configured to perform read and write operations on a selected memory cell. Fig. Figure 5 is a schematic circuit diagram representation of an example configuration of a word line circuit with variable resistance from the example circuit. Fig. 4. Fig. Figure 6 is a schematic circuit diagram representation of an example configuration of a bitline circuit with variable resistance from the example circuit. Fig. 4. Fig. Figure 7 is a time diagram of signals, voltages, and currents generated by the circuit. Fig. 4 are generated during an example of read and write operations. Fig. Figure 8 is a schematic circuit diagram representation of another example configuration of the word line circuit with variable resistance from the example circuit. Fig. 4. Fig. Figure 9 is a schematic circuit diagram representation of another example configuration of the bitline circuit with variable resistance from the example circuit. Fig. 4. Fig. 10 is a timing diagram of gate voltages applied to the transistor circuits of the Fig. 8 and Fig. 9 for carrying out the reading and writing operations from Fig. 7 will be created. DETAILED DESCRIPTION

[0004] According to the invention, circuits, a system and a method are provided having the features of the independent claims; dependent claims relate to preferred embodiments.

[0005] It should be noted at the outset that the following embodiments relate to apparatus, devices, systems, circuits, and methods for controlling resistance levels in selection paths or selected paths and / or gate voltages applied to transistor circuits in the selection paths on a memory chip or cube during read and write operations. In one embodiment, a circuit comprises a memory field or array containing a plurality of memory cells and a path configured to supply a voltage for biasing one of the plurality of memory cells. The path includes a variable-resistance circuit configured to: set an associated resistor to a high resistance level or...to set the voltage level before the memory cell is switched on; and to adjust the associated resistance from the high resistance level to a low resistance level in response to an end time of an initial switch-on period.

[0006] In some embodiments, the variable resistance circuit includes a transistor configured to: receive an input voltage and, in response to receiving the input voltage, adjust the associated resistor to the high resistance level.

[0007] In some embodiments, the transistor is configured to adjust its associated resistor in response to a change in the input voltage level from a high resistance level to a low resistance level. In some embodiments, the transistor is configured to adjust its associated resistor in response to receiving an input voltage at a medium voltage level to a high resistance level. In some embodiments, the transistor is configured to adjust its associated resistor in response to receiving an input voltage at a minimum voltage level to a high resistance level. In some embodiments, a word line decoder incorporates the transistor.

[0008] In some embodiments, a bit line decoder contains the transistor.

[0009] In some embodiments, a second path configured to supply a second voltage for biasing the memory cell comprises: a second variable-resistance circuit configured to set a second associated resistor to a second high resistance level prior to turning on the memory cell; and to adjust the second associated resistor from the second high resistance level to a second low resistance level in response to the end time of the initial turn-on period.

[0010] In some embodiments, the variable resistance circuit is configured to set the associated resistor to the high resistance level prior to a word line selection period of a read operation to read data from the memory cell.

[0011] In some embodiments, the variable resistance circuit comprises a pair of transistors connected in parallel, wherein one of the transistors of the pair is configured to turn off in order to adjust the associated resistance to the high resistance level, and wherein both transistors of the pair are configured to turn on in order to adjust the associated resistance from the high resistance level to the low resistance level.

[0012] In another embodiment, a circuit comprises: a memory array with a plurality of memory cells, a voltage generator configured to generate a voltage during a read operation to read data from one of the plurality of memory cells, a transistor circuit, and a bias circuit. The transistor circuit is configured to receive the voltage and pass it to a bias line coupled to the memory cell. The bias circuit is configured to: bias the transistor circuit according to a first bias setting during a bias line setting period prior to a turn-on time when the memory cell conducts a peak portion of a memory cell current, and switch to biasing the transistor circuit according to a second bias setting after the peak portion and prior to a read result acquisition time of the read operation.

[0013] In some embodiments, the transistor circuit includes a p-channel metal oxide semiconductor field-effect transistor (PMOS transistor), and wherein the biasing circuit is configured to switch to biasing the PMOS transistor according to the second bias setting by lowering a gate voltage applied to the PMOS transistor from a first voltage level to a second voltage level.

[0014] In some embodiments, the first voltage level includes a medium voltage level or an intermediate voltage level.

[0015] In some embodiments, the PMOS transistor contains one of several transistors of a word line decoder.

[0016] In some embodiments, the transistor circuit includes an n-channel metal oxide semiconductor field-effect transistor (NMOS transistor), and the biasing circuit is configured to switch to biasing the NMOS transistor according to the second bias setting by increasing a gate voltage applied to the NMOS transistor from a first voltage level to a second voltage level.

[0017] In some embodiments, the NMOS transistor contains one of several transistors of a word line decoder.

[0018] In another embodiment, a system comprises: a memory array with a plurality of memory cells, a word line coupled to a memory cell of the plurality of memory cells, a bit line coupled to the memory cell, a word line decoder, a bit line decoder, and a decoder / decoder controller. The memory cell is configured to conduct a peak portion or spike portion of a memory cell current when the memory cell powers on during the read operation. The word line decoder is configured to set a word line voltage or potential on the word line. The bit line decoder is configured to set a bit line voltage or potential on the bit line.The decoder controller is configured to reduce the first effective gate-to-source voltage of a first transistor circuit in the word line decoder and the second effective gate-to-source voltage of a second transistor circuit in the bit line decoder to reduced voltage levels before the spike occurs. These reduced voltage levels are configured to decrease the width of the spike. After the spike peak or maximum occurs, the decoder controller is configured to increase the first and second effective gate-to-source voltages from their respective reduced levels to their respective increased levels, configured for a subsequent event associated with the memory cell.

[0019] In some embodiments, the decoder controller is configured to increase a gate voltage to raise the second effective gate-to-source voltage of the second transistor circuit.

[0020] In some embodiments, the decoder controller is configured to decrease a gate voltage in order to increase the first effective gate-to-source voltage of the first transistor circuit.

[0021] In some embodiments, the respective reduced voltage levels correspond to an associated intermediate voltage level or medium voltage level.

[0022] In a further embodiment, a method comprises: supplying a voltage to a bias line coupled to a memory cell via a path; biasing a transistor of the path with a gate voltage or potential at a first gate voltage level before the memory cell is switched on, using a decoder controller; and biasing the transistor with the decoder controller with the gate voltage to a second gate voltage level, which increases a gate-to-source voltage of the transistor in response to the detection of the end of an initial switch-on period.

[0023] In another embodiment, a circuit includes: means for supplying a voltage to bias a memory cell during a read operation for reading data from the memory cell; means for setting a resistance to a high resistance level before an on-time of the read operation; and means for changing the resistance to a low resistance level in response to the end of an initial on-time period of the read operation.

[0024] Other embodiments are possible, and each embodiment can be used alone or in combination with the others. Accordingly, various embodiments will now be described with reference to the accompanying figures.

[0025] The following embodiments describe devices, apparatuses, systems, circuits, and methods for controlling resistors in selection paths and / or gate voltages applied to transistor circuits in the selection paths on a memory chip or cube during read and write operations. The actions performed to control the resistors and / or gate voltages can minimize the width of the current peaks or spikes passed through during read operations, thereby minimizing the probability of write errors occurring during read operations. Before discussing these and other embodiments, the following paragraphs describe exemplary memory systems and storage devices that can be used with these embodiments.It should be understood that these are only examples, and other suitable types of storage systems and / or storage devices may also be used.

[0026] Fig. Figure 1A is a block diagram illustrating a memory system 100. The memory system 100 can include a controller 102 and a memory, which may consist of one or more memory dies 104. In the terminology used here, the term "die" or "die" refers to the set of memory cells and associated circuitry for managing the physical operation of these memory cells, which are formed on a single semiconductor substrate. The controller 102 can provide an interface to a host system and transmit command sequences for read, program, and erase operations to the non-volatile memory die(s) 104. In some embodiments, the controller 102 can be located on the memory die(s) 104. In other embodiments, the controller 102 can be separate and, as a component separate from the memory die(s), connect one or more memory die(s) or die(s) to a controller.

[0027] The Controller 102 can take the form of a processing circuit, a microprocessor or processor, and a computer-readable medium that stores computer-readable program code (e.g., software or firmware) executable by, for example, the (micro)processor, logic gates, switches, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded or mounted microcontroller. The Controller 102 can be configured with hardware and / or firmware to perform the various functions described below and illustrated in the flowcharts. Furthermore, some of the components shown as internal components of the controller can also be stored or located outside the controller, and other components can be used externally.Additionally, the term "operationally in communication with" could mean: directly in communication with or indirectly (wired or wireless) in communication with, through one or more components that may or may not be shown or described here.

[0028] In the terminology used here, the Controller 102 is a device that manages the data stored in the memory chips and communicates with a host, such as a computer or other electronic device. In addition to the specific functions described here, the Controller 102 can perform various other functions. For example, the Controller 102 can format the memory chips 104 to ensure they function correctly, remove faulty memory cells, and allocate spare cells to replace future failed cells. Some of the spare cells can be used to maintain the firmware for the operation of the Controller 102 and to implement other functions. When a host needs to read data from or write data to the memory chip(s) 104 during operation, the host communicates with the Controller 102.If the host provides a logical address on which data is to be read / written, the controller 102 can translate the logical address received from the host into a physical address in the memory die(s) 104. (Alternatively, the host can provide the physical address.) The controller 102 can also perform various memory management functions, such as, but not limited to, wear balancing (distributing write operations to prevent certain memory areas (e.g., memory blocks) from being worn out by repeated overwriting) and garbage collection (once a memory area (e.g., a block) is full, only the valid parts (e.g., pages) of the data are moved to a new memory area (e.g., a new block), allowing the original memory area to be erased and reused).

[0029] The interface between the controller 102 and the non-volatile memory chip(s) 104 can be any suitable interface, such as a flash interface, including those configured for toggle mode 200, 400, 800, 1000 or higher, or double data rate (DDR), including, but not limited to, low power DDR or DDR1, DDR2, DDR3, DDR4 or later variants, including, but not limited to, those adopted or implemented by JEDEC. In some embodiments, the memory system 100 can be a card-based system, such as a Secure Digital (SD) or Micro Secure Digital (Micro-SD) card. In alternative embodiments, the memory system 100 can be part of an embedded memory system.

[0030] In the Fig. In the example shown in Figure 1A, the memory system 100 is depicted as comprising a single channel between the controller 102 and the memory die(s) 104. However, the subject matter described here is not limited to memory systems with a single memory channel. In some memory systems, for example, depending on the capabilities of the controller, there may be 2, 4, 8, or more channels between the controller 102 and the memory die(s) 104. In each of the embodiments described here, more than a single channel may exist between the controller and the memory die(s) 104, even if a single channel is shown in the figures.

[0031] Fig. Figure 1B shows a memory module 200, which comprises a variety of memory systems 100. As such, the memory module 200 can include a memory controller 202, which has an interface to a host and to a memory system 204, which comprises a variety of memory systems 100. The interface between the memory controller 202 and the memory systems 100 can be a bus interface, such as a Serial Advanced Technology Attachment (SATA), a PCIe (Peripheral Component Interface Express), an embedded MultiMediaCard (eMMC), an SD interface, or a USB (Universal Serial Bus) interface. The memory module 200 can also be a solid-state drive (SSD), as found, for example, in portable computing devices such as laptops and tablet PCs, as well as in mobile phones.

[0032] Fig. Figure 1C is a block diagram illustrating a hierarchical storage system 210. The hierarchical storage system 210 can contain a variety of storage controllers 202, each controlling a corresponding storage system 204. Host systems 212 can access storage within the hierarchical storage system 210 via a bus interface. Examples of bus interfaces include an Express Non-Volatile Memory (NVMe) interface, a Fibre Channel over Ethernet (FCoE) interface, an SD interface, a USB interface, a SATA interface, a PCIe interface, DDR4, LPDDR4, or an eMMC interface. In one embodiment, the Fig. Storage system 210 shown in Figure 1C is a rack-mountable mass storage system that can be accessed by multiple host computers, such as in a data center or other location where mass storage is needed.

[0033] Fig. Figure 2A is a block diagram illustrating exemplary components of the controller 102. The controller 102 can include a front-end module 108 connected to a host, a back-end module 110 connected to the memory chip(s) 104, and various other modules that perform different functions of the non-volatile memory system 100. In general, a module can consist of hardware or a combination of hardware and software. For example, each module can contain an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a circuit, a digital logic circuit, an analog circuit, a combination of discrete circuits, gates, or any other type of hardware, or a combination thereof.Additionally or alternatively, each module may contain memory hardware that holds instructions executable by a processor or processor circuitry to implement one or more features of the module. If one of the modules contains the portion of memory that holds instructions executable by the processor, the module may or may not contain the processor. In some examples, each module may simply be the portion of memory that holds instructions executable by the processor to implement the features of the corresponding module, without the module containing any other hardware. Because each module includes at least some hardware, even if the included hardware contains software, each module can be interchangeably referred to as a hardware module.

[0034] The controller 102 can include a buffer management / bus controller module 114, which manages buffers in random access memory (RAM) 116 and controls the internal bus arbitration for communication on an internal communication bus 117 of the controller 102. A read-only memory (ROM) 118 can store and / or access system startup / boot code. Although in Fig. While 2A is depicted as separate from the controller 102, in other configurations one or both of the RAM 116 and ROM 118 may reside within the controller 102. In other configurations, parts of the RAM 116 and ROM 118 may be located both inside and outside the controller 102. Furthermore, in some implementations, the controller 102, the RAM 116, and the ROM 118 may reside on separate semiconductor chips.

[0035] Additionally, the front-end module 108 can include a host interface 120 and a physical layer interface (PHY) 122, which provide the electrical interface with the host or the next-level memory controller. The choice of host interface 120 type can depend on the type of memory used. Example host interface 120 types include DDR4, LPDDR4, SATA, SATA Express, SAS, Fibre Channel, USB, PCIe, and NVMe. The host interface 120 typically facilitates the transmission of data, control, and timing signals.

[0036] The backend module 110 can contain an error correction code (ECC) engine or module 124, which encodes the data bytes received from the host and decodes and corrects the data bytes read from the non-volatile memory chip(s) 104. The backend module 110 can also contain an instruction sequencer 126, which generates instruction sequences, such as program, read, and erase command sequences, that are transferred to the non-volatile memory chip(s) 104. Additionally, the backend module 110 can contain a RAID module 128 (Redundant Array of Independent Drives), which manages the generation of RAID parity and the recovery of failed data. RAID parity can be used as an additional layer of integrity protection for the data written to the storage system 100. In some cases, the RAID module 128 can be part of the ECC engine 124.A memory interface 130 provides the instruction sequences for the memory chip(s) 104 and receives status information from the memory chip(s) 104. Along with the instruction sequences and status information, data to be programmed into and read from the memory chip(s) 104 can be transmitted via the memory interface 130. In one implementation, the memory interface 130 can be a DDR (Double Data Rate) interface and / or a toggle-mode interface 200, 400, 800, 1000 or higher. A control layer 132 can control the overall operation of the backend module 110.

[0037] Additional modules of the in Fig. The non-volatile memory system 100 shown in Figure 2A may include a media management layer 138, which performs wear compensation of the memory cells of the memory chips 104, address management, and / or facilitates convolution operations. The memory system 100 may also include other discrete components 140, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that can interface with the controller 102. In some embodiments, one or more of the RAID module 128, the media management layer 138, and the buffer management / bus controller 114 are optional components that may not be included in the controller 102.

[0038] Fig. Figure 2B is a block diagram illustrating exemplary components of a memory cube 104. The memory cube 104 can contain a memory cell structure 142, which comprises a multitude of memory cells. For some example configurations, the memory cells can be arranged in a two- or three-dimensional array. For such example configurations, the memory cell structure 142 can be referred to as a memory array.

[0039] Exemplary types of memory cells of memory cell structure 142 include those that have a memory element or section and a selection element or section. The memory element of the memory cell can be configured to store data with, or at, one of a plurality of n-bit logic values, where n is an integer of one or more. Each n-bit logic value can be a binary value, where n represents the number of digits of the binary value. For example, if n is one, the plurality of 1-bit logic values ​​contains a logic 1 value and a logic 0 value. To store the data with a logic n-bit value, the memory element can be configured to be programmed into one of a plurality of states, each state corresponding to one of a plurality of logic n-bit values.For some example configurations, the states can be resistance states, where different states correspond to different resistances or resistance values ​​of the memory element. For example, a first state can be high resistance, and a second state can be low resistance. A memory element programmed in the high resistance state will have a higher resistance than when programmed in the low resistance state. Additionally or alternatively, the states can be threshold voltage states, where different states correspond to different threshold voltages to turn on and / or conduct a predetermined threshold current.

[0040] The selection element (alternatively referred to as selector or selector part or section) can enable the programming of the memory element for storing data or the reading of data from the memory element, but it cannot itself store data or possess any storage capabilities. Additionally or alternatively, the selection element can have an associated threshold voltage and switch on to conduct current when biased with a voltage at or above the threshold voltage. Biasing the selection element with a voltage or potential at or above the threshold voltage can enable the programming or reading of the memory element.

[0041] Exemplary memory types for the memory element or memory cell in general may include resistive random-access memory (“ReRAM”) or phase-change / phase-transition memory (“PCM”), although other memory types, including volatile or other non-volatile memory, are also possible. Non-restrictive example elements include an ovonic threshold switch (“OTS”), a doped chalcogenide alloy material, a thin-film silicon material, a metal-metal oxide switch, or a field-assisted superlinear threshold switch (“FAST”). Additionally or alternatively, the memory cells of the memory cell structure 142 may be configured as crosspoint memory (e.g., 3D XPoint).

[0042] The memory cell structure 142, which is located within and / or above or on a substrate, can be arranged in two or three dimensions, such as a two-dimensional memory structure or a three-dimensional memory structure with one or more memory layers above the base memory layer.

[0043] In a two-dimensional memory structure, the memory cells are arranged in a single plane or on a single memory device plane. In a two-dimensional memory structure, the memory elements are typically arranged in a plane (e.g., in a plane in the xy direction) that extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate can be a wafer over, on, or in which the layer of memory elements is formed, or it can be a support substrate that is attached to the memory elements after they have been formed. As a non-restrictive example, the substrate can contain a semiconductor such as silicon.

[0044] Memory cells can be arranged at the level of a single storage device or apparatus in an ordered array, for example, in multiple rows and / or columns. However, the memory elements can also be arranged in irregular, disordered, or non-orthogonal configurations. Furthermore, as described in more detail below, the memory elements can each be connected to two or more bias lines, alternatively referred to as electrodes or contact lines. Types of bias lines include word lines and bit lines. As described in more detail below, to read data from or program data into a particular memory cell, the memory cell in question can be biased with a voltage difference or differential.This includes a high and a low voltage, where the high voltage has a higher voltage level than the low voltage. Two bias lines are coupled to the given memory cell and configured to bias the given memory cell with an associated voltage difference. One of the two bias lines is configured to bias the given memory cell with a high voltage of the voltage difference, and the other of the two bias lines is configured to bias the given memory cell with a low voltage of the voltage difference. In the terminology used here, the word lines are those bias lines configured to bias the respective memory cells with the high voltage, and the bit lines are those bias lines configured to bias the respective memory cells with the low voltage.However, the terms word line and bit line can be used interchangeably or interchangeably, so that the bias lines configured to bias the memory cells with the high voltage are referred to as bit lines and the bias lines configured to bias the memory cells with the low voltage are referred to as word lines.

[0045] In a three-dimensional storage structure, the memory cells of an array are arranged such that the memory cells occupy multiple levels or multiple storage device levels, thereby forming a three-dimensional structure (i.e. in the x, y and z directions, one of which is essentially perpendicular and the other directions are essentially parallel to the main surface of the substrate).

[0046] Additional possibilities for organizing the memory cells of the memory cell structure 142 are possible. As a non-restrictive example, the memory cells can be organized into blocks and the blocks into layers. Additionally, the memory cells of the memory cell structure can be connected by bias or bias lines, including word and bit lines, as described previously. The circuitry on the memory chip can be configured to bias the word and bit lines with different voltages to perform the memory operations associated with the memory cells, including read, program, and erase operations.

[0047] Fig. Figure 3 shows a perspective view of a memory cell 302, which is coupled to a word line 304 and a bit line 306. Memory cell 302 can be considered representative of an example memory cell of the in Fig. The memory cell structure 142 shown in Figure 2B can be represented. Furthermore, word line 304 and bit line 306 can be representative of corresponding parts or sections of a word line and a bit line that are coupled to a memory cell of the memory cell structure 142. Physically, memory cell 302 can be located between word line 304 and bit line 306. Additionally, in some example configurations, as shown in Figure 2B, the memory cell 302 can be located between word line 304 and bit line 306. Fig. As shown in Figure 3, the word line 304 and the bit line 306 are aligned in parallel planes and extend in mutually perpendicular directions within their respective planes. Additionally, the word line 304, although not in Fig. Figure 3 shows that it can be one of several word lines that extend parallel to each other in an associated plane, and likewise, bit line 306 can be one of several bit lines that extend parallel to each other in an associated plane.

[0048] Additionally, in the Fig. In the example configuration shown in Figure 3, the memory cell 302 contains a memory element 308 and a selection element 310. Although not shown, some embodiments may include electrodes or carbon between the memory element 308 and the selection element 308 or 310, and / or between these elements 308, 310 and the word line 304 and / or the bit line 306. The memory element 308 and the selection element 310 may be coupled together.

[0049] Additionally, in the Fig. In the example configuration shown in Figure 3, memory element 308 is adjacent to and / or coupled with word line 304, and selection element 310 is adjacent to and / or coupled with bit line 306. In other example configurations, memory element 308 can be adjacent to and / or coupled with bit line 306, and selection element 310 can be adjacent to and / or coupled with word line 304. A word line is also called a row line, an interchangeable term as used here. A bit line can also be called a column line, an interchangeable term as used here. And what is referred to here as a word line can just as well be called a bit line or a word line, provided the two terms are consistently used interchangeably.

[0050] Memory element 308 and selector element 310 can each have an associated threshold voltage. The level of the threshold voltage of memory element 308 can depend on and / or correspond to a state in which memory element 308 is programmed and / or to a data or logic value of the data that memory element 308 stores. In some example configurations, memory element 308 can be configured to store a single data bit with either a logic 1 or a logic 0 value. Memory element 308 can be programmed either in a high-impedance state to store the logic 1 value, or in a low-impedance state to store the logic 0 value, or alternatively in the high-impedance state to store the logic 0 value and in the low-impedance state to store the logic 1 value.The storage element 308 can have a higher threshold voltage when programmed in the high-impedance state than when programmed in the low-impedance state.

[0051] Additionally, for some example configurations, memory cell 302 may have an associated or total threshold voltage based on a combination of the threshold voltage of memory element 308 and the threshold voltage of selection element 310. In certain example configurations, memory element 308 and selection element 310 may be connected in series or coupled together such that the total threshold voltage of memory cell 302 is the sum of the threshold voltage of memory element 308 and the threshold voltage of selection element 310, or close to it, if a threshold current to trigger on memory element 308 is approximately equal to the threshold current to trigger on selection element 310.

[0052] As described in more detail below, a read voltage differential can be applied across memory cell 302 to read data from memory cell 302, for example, by sending or determining the logical level of the data stored by memory cell 302. The voltage differential can be the difference between a first voltage generated on or at word line 304 and a second voltage generated on or at bit line 306. Memory cell 302 can be configured to turn on in response to a read voltage differential that is at or above the total combined threshold voltage of memory cell 302; that is, for example, the sum of the threshold voltage of memory element 308 and the threshold voltage of select element 310. When not turned on, memory cell 302 can be considered to be off and may exhibit a relatively high impedance across memory cell 302.Furthermore, when memory cell 302 is powered on, it can be configured to conduct a cell current. Alternatively, when powered off, memory cell 302 can instead conduct a relatively smaller cell current, e.g., a "leakage current," which sums up for the other powered-off cells on a word or bit line, but must not exceed the read current of a selected memory cell in the low-impedance state.

[0053] To query or determine the logical level of the data stored by memory cell 302, a read voltage applied between a selected word line and a selected bit line is generated at a voltage level greater than the threshold voltage of the selection element 310, and furthermore greater than the level of the total threshold voltage of memory cell 302 when memory element 308 is programmed in the low-impedance state, and less than the level of the total threshold voltage of the memory cell when memory element 308 is programmed in the high-impedance state. In this way, whether or not memory cell 302 conducts cell current in response to the read voltage difference indicates the logical level (e.g., either a logic 1 or a logic 0) of the data stored by memory cell 302 (or, in particular, memory element 308).Whether memory cell 302 conducts current in response to a bias voltage with the read voltage difference can be described as the read response of the memory cell. A read operation for reading data from a memory cell is described in more detail below.

[0054] Additionally, as described in more detail below, a programming voltage differential can be applied across memory cell 302 to program data into memory cell 302. With some memory cell technologies, such as phase-change memory (PCM), the programming voltage differential can be applied to cause memory cell 302 to conduct the memory cell current differently in order to store different logical levels of data. For example, a programming voltage differential applied to a PCM cell to program the memory element of the PCM cell into a high-impedance state can cause the PCM cell to conduct a relatively steady or constant amount of current (e.g., about 100 microamperes (µA)) for a certain period of time and then cause the PCM cell to quickly, e.g.,to switch to a currentless state or a current level relatively close to zero or significantly below the constant current level in less than 2 nanoseconds (ns). The current transition can be described as the fast trailing edge of the memory cell current for programming the PCM cell into a high-impedance state. Alternatively, a programming voltage differential applied to a PCM cell element can cause the PCM cell to conduct a gradually decreasing current level over a given time period, e.g., 100 ns, by slowly reducing the voltage across memory cell 302.

[0055] On Fig. Referring back to 2B, the memory cube 104 may further contain read / write circuits 144, which contain a plurality or p-number of read blocks (also called read modules or read circuits) 146. As described in detail below, the read blocks 146 are configured to participate in reading or programming the memory cells.

[0056] The memory matrix 104 can also contain a word line decoder (otherwise called a row decoder or x-decoder) 148 and a bit line address or decoder (otherwise called a column decoder or y-decoder) 150. The word line decoder 148 can decode a word line address (also called a row or x-address) and, when reading or writing data to / from the memory cells, select a specific word line corresponding to the decoded word line address. The bit line decoder 150 can decode a bit line address (also called a column address or y-address) to select a bit line or a specific group of bit lines corresponding to the bit line address when reading or writing data to / from the memory cells.

[0057] Furthermore, the non-volatile memory chip 104 can include a peripheral circuit 152. The peripheral circuit 152 can contain control logic circuits (also called controllers or on-chip controllers) 154, which can be implemented as a state machine and provide on-chip control of memory operations as well as status information for the controller 102. The peripheral circuit 152 can also include an on-chip address decoder 156, which provides an address interface between the addressing used by the controller 102 and / or a host and the hardware addressing used by the row and column decoders 148, 150. In addition, the peripheral circuit 152 can also include volatile memory 158 and non-volatile memory 159 that are independent of or separate from the memory cell structure 142.The volatile and non-volatile memory 158, 159 can be used to store data or other information on the memory chip 104, e.g., for previous or current access data states or alternatives to the control logic 154 or another component of the peripheral circuit 152 for performing memory operations on the memory chip 104, e.g., to adjust the timing or sequence for read or write operations or to perform read-modify-write operations. Such memory can also serve as firmware for controlling on-chip microsequences. An example configuration of the volatile memory 158 can include latches or state-controlled flip-flops, although other configurations are also possible.

[0058] Furthermore, the peripheral circuit 152 can include a power / energy / current control circuit 160 configured to generate voltages and supply them at specific levels to the memory cell structure 142 and / or the word lines and bit lines coupled to the memory cells of the memory cell structure 142 and / or bias memory cells of the memory cell structure and / or the word lines and bit lines coupled to the memory cells. The voltages supplied by the power control circuit 160 include read voltages, programming voltages (including programming voltage pulses), erase voltages (including erase voltage pulses), and other voltages that can be supplied to the word lines and bit lines of the memory cell structure 142, the read / write circuits 144, including the read blocks 146, and / or other circuit components on the memory chip 104.Additionally, the power control circuit 160 can communicate with and / or be controlled by the control logic circuit 154, the read / write circuits 144, and / or the read blocks 146 to supply the voltages or potentials at suitable levels and at suitable times for carrying out the storage operations. For clarity, and unless otherwise specified, the combination of the power control circuit 160, the read / write circuit 144, and the read blocks 146, which are used to bias word lines and bit lines at suitable levels during a specific storage operation (e.g., a programming operation, a verification operation, a programming-verification operation, a read operation, a read operation within or as part of a verification or read operation, or an erase operation), is referred to collectively here as the power supply circuit.A power supply circuit can refer to the power control circuit 160, the sampling / read block circuit 146, other circuit components of the read / write circuit 144, or any combination thereof. The power supply circuit can include one of several circuit topologies or configurations to provide the voltages at suitable levels for performing the read, write, and erase operations, such as driver circuits, charge pumps, reference voltage generators, and pulse generation circuits, or a combination thereof. Other types of circuits for generating the voltages are also possible.

[0059] Fig. Figure 4 is a block diagram with an example circuit configured to perform a read operation and a program operation on a selected memory cell MC(s). The selected memory cell MC(s) can be one of several memory cells MC configured in a memory field or array 400. The memory array 400 can consist of at least a portion of the memory cell structure 142. Fig. 2B.

[0060] As described in more detail below, the example circuit can be used in Fig. 4. It can be configured to reduce and / or minimize the width of a current spike in the memory cell current that the selected memory cell MC(s) conducts upon power-up. Reducing the width of the current spike can, in turn, reduce the amount of energy in the current spike, which in turn reduces the amount of heat generated by the selected memory cell MC(s) when conducting the current spike. This, in turn, reduces and / or minimizes the probability that the selected memory cell MC(s) will perform an incorrect or erroneous write operation by being programmed into a different state, e.g., a different resistance state, while conducting the current spike.

[0061] For example, in PCM technology, to program the selected memory cell MC(s) into a high-impedance state, the circuit biases the selected memory cell MC(s) to cause it to conduct a specific amount of memory cell current (e.g., about 100 microamperes (µA)) for a certain period of time and then rapidly decrease the amount of memory cell current to less than 20 µA or very close to 0 µA. This rapid decrease in memory cell current is called a fast trailing edge.A write error or read error can occur during a read operation where the selected memory cell MC(s), programmed in the low-impedance state, is turned on and conducts a cell current that rapidly falls in a manner similar to a fast trailing edge, thereby reprogramming the selected memory cell from the low-impedance state to the high-impedance state or closer to the high-impedance state, thereby undesirably reducing or eliminating the read margin, which increases the bit error rate (BER) as experienced by the controller 102 or a host.

[0062] In PCM technology, the selected memory cell MC(s) can be programmed in more detail to a high-impedance or low-impedance state. The selected memory cell is described as programmed to high impedance when its memory element (e.g., memory element 308 from Fig. 3) is programmed to high resistance, and the selected memory cell is referred to as programmed to low resistance if its memory element is programmed to low resistance.

[0063] A read operation is performed on the selected memory cell MC(s) to determine the logical level of the data stored by the selected memory cell by determining whether the memory element of memory cell MC(s) is programmed in a high-impedance or low-impedance state. During the read operation, the selected memory cell MC(s) is biased by a bias circuit with a voltage differential up to a predetermined voltage differential level sufficient to enable the selected memory cell MC(s) to turn on when it is in the low-impedance state, i.e., transitioning from an off state to an on state. Whether the selected memory cell remains in the off state or transitions to the on state indicates whether the selected memory cell is programmed in a high-impedance or low-impedance state.In particular, the predetermined voltage difference level is a level that is above the threshold voltage level of a selected element of the selected memory cell (e.g., selection element 310 from ). Fig. 3) and is additionally either above the total threshold voltage level of the selected memory cell MC(s) if the selected memory cell is programmed in the low-impedance state (LRS), or below the total threshold voltage level of the selected memory cell MC(s) if the selected memory cell is programmed in the high-impedance state (HRS). Accordingly, the selected memory cell remains switched off (remains in the off state) when the predetermined voltage difference level is reached if the selected memory cell is programmed in the high-impedance state, and if the selected memory cell is programmed in the low-impedance state, then the selected memory cell, including the selection element (e.g., the OTS), switches on (changes from the off state to the on state).

[0064] In PCM technology, the selected memory cell MC(s) can generally be in the off state whether its memory element is programmed in a high-resistance or low-resistance state. A resistance of its selection element can determine or indicate whether the selected memory cell MC(s) is in the on state (powered on) or in the off state (powered off). When the selected memory cell is in the off state, the selection element can have a resistance at an associated high resistance level, such as on the order of 1 gigaohm (GΩ) in some example configurations, and when the selected memory cell is in the on state, the selection element can have a resistance at an associated low resistance level, such as on the order of 1 kOhm (kΩ) in some example configurations.

[0065] At the start of a read operation to read a logical level of data stored in the selected memory cell MC(s), the selected memory cell is in an off state (switched off), regardless of whether it is programmed in a high-impedance or low-impedance state. Before the start, the memory state may be the end of a recent or previous cycle, such as an immediately preceding read or write cycle, or a standby state. In PCM, this can result in selected or select lines 304 and 306 being in Fig. 3. The same voltage is enforced. In the off state, the selected memory cell MC(s) may not conduct any current (or may conduct 0 microamperes (µA) of the cell current). As described in detail below, the read voltage begins to rise to the specified voltage difference level, and when the specified voltage difference level is reached, the behavior of the selected memory cell MC(s)—i.e., whether the selected memory cell turns on and conducts a significant current above, for example, 10 nanoamperes (nA)—depends on whether the selected memory cell MC(s) is programmed in the high-resistance or low-resistance state.When the predetermined voltage difference level is reached and the selected memory cell is programmed in the high-resistance state, the selected memory cell remains off because its selector switch (OTS) remains off. Therefore, the resistance of the selector switch remains at its associated high resistance level, and the selected memory cell continues to conduct a small current, e.g., less than 1 nA. Conversely, when the predetermined read voltage difference is reached if the selected memory cell MC(s) is programmed in the low-resistance state, the selected memory cell MC(s) turns on (transitions from the off state to the on state). The resistance of the selector switch decreases, e.g., exponentially from the associated high resistance level of 1 GΩ to the associated low resistance level of 1 kΩ, and the selected memory cell MC(s) conducts a significant current for a remaining portion or period of the read operation.B. more than 10 µA. The amplitude waveform of the cell current conducted by the selected memory cell MC(s) when initially switched on during the read operation comprises a current peak section (or simply current peak), a current fall section in which the amplitude falls from a peak amplitude to a current level generally well below the peak amplitude, and a steady-state section during which the cell current remains at a relatively constant level or within a relatively small range of current intensities. The current amplitude components of the current occur in this order when the selected memory cell MC(s) is first switched on during the read operation: the cell current conducted by the selected memory cell MC(s) rises instantaneously from 0 µA to a peak amplitude, and then falls from the peak.from its maximum to a much lower level, it then remains at a steady level, generally within a range far below the peak current level.

[0066] In some embodiments, the peak amplitude can be on the order of milliamperes (mA), e.g., 3 mA, and the current level to which the cell current drops and within which it remains during the steady-state phase can be on the order of ten microamperes (µA), e.g., in a range of 20–35 µA. The relatively constant level of the cell current can depend on and / or be controlled by current sources, which the bias circuit uses to generate the initial voltage difference that is applied to the selected element when the storage element is in the low-resistance state.

[0067] When the voltage difference across the selected memory cell MC(s) reaches the predetermined voltage difference level, the selected memory cell, which remains in the off state and conducts no current, indicates that the selected memory cell is programmed in the high-impedance state and thus stores data at a logic level corresponding to the high-impedance state. Conversely, when the voltage difference across the selected memory cell MC(s) reaches the predetermined voltage level that exceeds the combined threshold voltage of the selection element and the memory element (if in LRS), the selected memory MC(s) transitions from the on state to the off state and conducts a current spike followed by a current drop, indicating that the selected memory cell MC(s) is programmed in the low-impedance state and thus stores data at a logic level corresponding to the low-impedance state.

[0068] The problem of a read error or incorrect write operation occurring during read operations may be due to the current spike and subsequent current drop that the selected memory cell conducts when programmed in the low-resistance state and powered on. Specifically, the current drop period may resemble a fast falling or trailing edge, which is used to program the selected memory cell MC(s) in the high-resistance state. An excessively wide current spike can deliver too much energy, which in turn overheats the selected memory cell MC(s), causing it to undesirably change its resistance state from a low-resistance to a high-resistance state, especially since the decay rate of the spike current is in the same range as that used to write a PCM bit to the high-resistance state.This event during reading, the increase in the resistance and threshold voltage (Vt) of the selected memory cell MC(s) in the low-impedance state, is referred to as a read error or write error or incorrect write operation.

[0069] The peak amplitude, or amplitude maximum, of the current spike can depend on inherent properties or characteristics of the memory cell technology. For example, in PCM technology, the peak current might be the difference between the threshold voltage of the selected element of the selected memory cell MC(s) and a holding voltage of the selected element, divided by the dynamic resistance dv / di of the selected memory cell. Since the peak current is an inherent property of the memory cell technology, reducing the peak by manipulating the bias voltage of the selected memory cell MC(s) may not be feasible.If the voltage across the selected element collapses rapidly (less than 1 ns) during power-up, the voltage previously across the element is partially transferred to the selected memory element MC(s) when the voltage across the selected memory cell drops to the reduced power-up voltage across the selected memory cell, by discharging the charge stored in the capacitance in the drivers and select lines (the decoders, selected word lines and / or bit lines and / or the traces formed in the decoders that connect the selected word lines and bit lines to the global nodes driven by voltage generators (current sources)), causing the temporary current spike.

[0070] The circuit in Fig. 4 is configured to reduce the probability of a read error or miswrite when reading data from the selected memory cell MC(s), which is configured to conduct a current spike when biased during a read operation, by reducing the spike width and increasing the decay rate. The width is a time measurement indicating how long the memory cell current remains above a predetermined current value, e.g., 40 µA. After the current spike reaches its maximum value, the width is greater, and the energy the current spike carries to heat the selected memory cell, the greater the slower or longer it takes for the memory cell current to decay to the predetermined current level. Conversely, the faster the memory cell current decays to the predetermined current level, the smaller the width and the less energy the current spike carries to heat the selected memory cell MC(s).

[0071] The circuits from Fig. Four can be configured to reduce and / or minimize peaks or maxima by adjusting the resistances of variable-resistance circuits driving the selected lines. In more detail, the memory cells MC of the 400 array are coupled to bias lines, including bit and word lines. If the selected memory cell MC(s) is to be biased for a read or write operation, the paths can be configured to different supply voltages to bias the selected memory cell MC(s) during the read and write selection.For example, a selected word line path is configured to deliver a globally selected word line voltage to a selected word line coupled to the selected memory cell MC(s), and a selected bit line path is configured to deliver a globally selected bit line voltage to a selected bit line coupled to the selected memory cell MC(s).

[0072] Variable resistance circuits configured in and driving adjacent paths can be manipulated to reduce the width of current spikes. During a read operation, a variable resistance circuit configured in a path (either a word line path or a bit line path) can be configured to set an associated resistor to a high resistance level in preparation for, or before, the memory cell is turned on. The variable resistance circuit can be configured to set its associated resistor to the high resistance level when the selected memory cell is turned on and conducting the current spike. The variable resistance circuit can then be configured to set the associated resistor from the high resistance level to a low resistance level in response to the end time of an initial turn-on period.When the selected memory cell MC(s) conducts the current spike in response to power-on, current flows through the path to pass through the selected memory cell MC(s). If the variable resistor circuit in the path is initially set to exhibit the high resistance level when the selected memory cell MC(s) is powered on, the width of the current spike may be smaller or shorter than if the variable resistor circuit were set to the low resistance level when the selected memory cell MC(s) is powered on.

[0073] The initial turn-on period is the time elapsed from a turn-on time to the end time. The turn-on time is a period during the read operation in which the selected memory cell (MC(s)) is turned on to conduct the current spike, provided the selected memory cell is in a low-resistance state. Additionally or alternatively, the turn-on time is a time (e.g., a predetermined time) that the controller is configured to recognize as the point at which the selected memory cell turns on, provided it is configured in a state, e.g., a low-resistance state, to turn on during the read operation. The turn-on time can act as a "time-out," as the turn-on time configured by the controller to identify can be the latest possible time that the selected memory cell can turn on to conduct the current spike.If the selected memory cell does not turn on to conduct the current spike by the turn-on time, the controller may assume that the selected memory cell is configured in a different state, e.g., a high-impedance state, so that the selected memory cell will not turn on and conduct the current spike during the remainder of the read operation.

[0074] The end time, or end point, is a later point in time that occurs after the switch-on time and ends the initial switch-on period. The end time can correspond to a predefined or threshold current to which the storage cell current drops after reaching its peak value.

[0075] The variable resistor circuit can be configured to adjust its associated resistance to a low resistance level in response to the end time of an initial power-on period, controlled by a controller such as a decoder controller, as described in more detail below. The controller can be configured to identify the end time and, in response, change or adjust the level, such as a voltage level, of a control signal it outputs to the variable resistor circuit. In response to this level change, the variable resistor circuit can adjust its associated resistance from a high resistance level to a low resistance level.

[0076] The controller can be configured to identify the end time of the initial power-on period in various ways. In some example configurations, the controller can be configured to detect that the end time occurs a predetermined time after a reference time during a read operation. In some example configurations, the reference time might be, for example, the start time of a read operation. The controller can include or use a timer that tracks or monitors a time interval after the start of the read operation. When the timer indicates that the elapsed time has reached the predetermined interval, the controller can determine that the end time has occurred and, in response, change the level of the control signal to change the resistance level of the variable resistor circuit to the low resistance level.

[0077] In other example configurations, the controller can be configured to detect that the end time is within a predetermined period—i.e., the initial power-on period—after the power-on time. In these configurations, the power-on time can be the reference time. The controller can be configured to detect when the power-on time occurs and to track or monitor a period of time after the power-on time, for example, by using a timer. When the timer indicates that the time elapsed after the power-on time has reached the predetermined period, the controller can determine that the end time has occurred and, in response, change the level of the control signal to change the resistance level of the variable resistor circuit to the low resistance level.

[0078] In other example configurations, the end time can be the period during which the memory cell current decays from the maximum current peak to a predetermined or threshold current level. The controller can be configured to measure the amount of cell current conducted by the selected memory cell MC(s) and detect when the cell current reaches the threshold current level. Upon detecting that the cell current has reached the threshold current level, the controller can determine that the end time has occurred and, in response, change the level of the control signal to reduce the resistance level of the variable resistor circuit to the low resistance level.

[0079] Furthermore, the controller can be configured to identify the power-on time, similar to the end time, in various ways. For example, the controller can be configured to identify the power-on time as the time that occurs a predetermined interval after a reference time. When the controller detects that the interval elapsed after the reference time has reached the predetermined interval, it can determine that the power-on time has occurred. In such configurations, the controller determines that the power-on time has occurred regardless of whether the selected memory cell MC(s) has actually been powered on.

[0080] In other example configurations, the controller can be configured to determine the turn-on time by measuring the magnitude of the memory cell current and detecting when the magnitude of the memory cell current exceeds a threshold indicating that the selected memory cell MC(s) is conducting the current spike. In response to the detection that the memory cell current has exceeded the threshold, the controller can determine that the selected memory cell MC(s) was initially turned on and the turn-on time has elapsed.

[0081] Other ways to configure the controller to determine the turn-on time and / or the end time of the initial turn-on time, and / or other ways to change the variable resistance circuit from the high resistance level to the low resistance level in response to the end of the initial turn-on time, are possible.

[0082] In some example configurations, the variable-resistance circuit is a component of a word line decoder and / or is configured or placed in a selected word line path to supply a globally selected word line voltage to a selected word line to bias the selected memory cell MC(s). In other example configurations, the variable-resistance circuit is a component of a bit line decoder and / or is configured or placed in a selected bit line path to supply a globally selected bit line voltage to a selected bit line to bias the selected memory cell MC(s).

[0083] In other example configurations, the circuit includes two variable-resistance circuits: a first variable-resistance circuit configured in the word line decoder and / or the selected word line path, and a second variable-resistance circuit configured in the bit line decoder and / or the selected word line path. Both the first and second variable-resistance circuits can set their respective resistances to a high level before the selected memory cell MC(s) is turned on and / or before the turn-on time, and set their respective resistances to a low level in response to the turn-on of the selected memory cell MC(s).

[0084] Generally, the high resistance level is higher than the low resistance level. In some embodiments, the high resistance level lies within a range of multiple high resistance levels or steps. In some embodiments, the range of multiple high resistance levels extends from 2 kiloohms (kΩ) to 1 GΩ. In other embodiments, the range of multiple high resistance levels extends from 40 kΩ to 80 kΩ. In other embodiments, the range of multiple high resistance steps extends from approximately 50 kΩ to approximately 60 kΩ. In other embodiments, the range of multiple high resistance steps extends from 1 kΩ to 30 kΩ. In other embodiments, the range of multiple high resistance steps extends from 6 kΩ to 20 kΩ. In other embodiments, the range of multiple high resistance steps extends from approximately 12 kΩ to approximately 14 kΩ.In some embodiments, the low resistance level also lies within a range of multiple low resistance levels. In some embodiments, the range of multiple low resistance levels extends from 1 kΩ to 50 kΩ. In other embodiments, the range of multiple low resistance levels extends from 15 kΩ to 40 kΩ. In other embodiments, the range of multiple low resistance values ​​extends from approximately 25 kΩ to approximately 30 kΩ. In other embodiments, the range of multiple low resistance levels extends from 100 Ω to 20 kΩ. In other embodiments, the range of multiple low resistance levels extends from 4 kΩ to 12 kΩ. In other embodiments, the range of multiple low resistance levels extends from approximately 7 kΩ to approximately 9 kΩ.

[0085] Additionally or alternatively, the high and low resistance levels can be set to such relative values ​​that the difference between them can lie within a range of resistance differences. In some examples, the resistance difference ranges from 10 kΩ to 50 kΩ. In others, it ranges from 20 kΩ to 40 kΩ. In other examples, it ranges from approximately 26 kΩ to approximately 32 kΩ. In other examples, it ranges from 100 Ω to 10 kΩ. In other examples, it ranges from 2 kΩ to 8 kΩ. In still other examples, it ranges from approximately 4 kΩ to 6 kΩ.

[0086] Additionally or alternatively, the high and low resistance levels can be positioned such that the high resistance level is at least 20% higher than the low resistance level. In some example implementations, the high resistance level is at least 50% higher than the low resistance level. In other example implementations, the high resistance level is at least 500% (five times) higher than the low resistance level.

[0087] In some example configurations, the variable-resistance circuit includes a transistor circuit comprising one or more transistors. The one or more transistors may be part of a decoder's array of transistors, such as a word line decoder or a bit line decoder. By configuring it in a selected word line path or a selected bit line path, the transistor circuit can be configured to receive a globally selected voltage (e.g., a globally selected word line voltage or a globally selected bit line voltage) and pass the globally selected voltage to a selected bias line (e.g., the selected word line or the selected bit line) coupled to the selected memory cell(s).

[0088] When the variable-resistance circuit is configured as a transistor circuit, a controller can operate as a bias circuit and be configured to bias the transistor circuit according to bias settings. A bias setting is a set of one or more voltage levels used to bias one or more transistors in the transistor circuit. When the controller biases one or more transistors in the transistor circuit according to a bias setting, the controller biases the transistor(s) to the voltage level(s) specified in the bias setting. The one or more transistors in the transistor circuit can receive and / or be biased by one or more voltages at one or more input terminals.During a read operation prior to the turn-on time, the controller, acting as a bias circuit, can bias the transistor circuit according to an initial bias setting during a bias line setting period prior to the turn-on time. See below regarding... Fig. As described in more detail in section 7, the bias line setting period can be a bit line setting period or a word line setting period. The first bias setting can adjust one or more voltage levels from one or more voltages to configure the transistor circuit to exhibit a corresponding resistance at the high resistance level. After a sufficient time for the current peak to decay into the current's read range, e.g., at the end of the first turn-on period, the controller can switch to biasing the transistor circuit according to a second bias setting. The biasing circuit can switch from the first bias setting to the second bias setting by adjusting or changing at least one of the voltage levels from at least one of the voltages.The second bias setting can adjust one or more voltage levels to configure the transistor circuit to have the associated resistance at the low resistance level. Such a transition can be gradual to avoid a temporary increase in memory cell current beyond a safe read range (and to prevent read glitches); for example, maintaining a read current of less than 35 µA.

[0089] In some example configurations, one or more transistors in the transistor circuit can be configured as metal-oxide-semiconductor field-effect transistors (MOSFETs). In certain example configurations, when configured as part of a word line decoder, the one or more MOSFETs can each be configured as p-channel metal-oxide-semiconductor field-effect transistors (PMOS transistors). In other example configurations, when configured as part of a bit line decoder, the one or more transistors can each be n-channel metal-oxide-semiconductor field-effect transistors (NMOS transistors).

[0090] When the controller is configured as MOSFETs, it can be configured to generate one or more gate voltages to set an effective gate-source voltage for the transistor circuit. If the transistor circuit contains a single MOSFET, the effective gate-source voltage can be the gate-source voltage of that single MOSFET. If the transistor circuit contains multiple MOSFETs, such as two MOSFETs connected in parallel, the effective gate-source voltage can be a combination of the gate-source voltages generated at the respective gate and source terminals of the MOSFETs.

[0091] Before the selected memory cell MC(s) turn on and conduct the current spike, the controller is configured to set an effective gate-to-source voltage of the transistor circuit to a reduced voltage level, configured to reduce the width of the current spike by increasing the resistance in the driver circuit, such as in the decoder, which may be an increase in resistance relative to the amount of capacitance in the driver circuit.

[0092] The reduced effective gate-to-source voltage reduces the bandwidth relative to the bandwidth that would result if the transistor circuit generated an effective gate-to-source voltage at a higher or full voltage level than the reduced voltage level when the selected memory cell MC(s) turns on to conduct the current spike. Additionally or alternatively, the effective gate-to-source voltage at the reduced voltage level can configure the transistor circuit with an associated resistor at the higher resistance level. The increased resistance can isolate a decoder capacitance that stores charge which the decoder might otherwise deliver to the selected memory cell MC(s) when the selected memory cell turns on.Isolating the capacitor reduces the rate of charge transfer from the charge stored in the capacitor to the selected memory cell in the on-state. This, in turn, reduces the amount of energy that could be incorrectly written to the selected memory cell during the read operation, as it is supplied to the selected memory cell above the read level. After a current spike occurs, for example, when the memory cell current drops to a threshold current value and / or when the controller identifies the end of an initial turn-on period, the controller can be configured to increase the effective gate-to-source voltage from the reduced voltage level to the increased voltage level. This allows the transistor circuit and its associated resistance to be configured at the low resistance level.

[0093] In example configurations where the variable resistor circuit includes a transistor circuit, the resistance is a resistance between two terminals of the transistor circuit, or contains a resistance between two terminals of the transistor circuit. For transistor circuit configurations comprising a single transistor, the resistance value or level of the variable resistor circuit is the resistance value of a resistor between two terminals of the single transistor. For configurations containing a plurality of transistors, the resistance level or value of the variable resistor circuit is a combination (e.g., a series or parallel combination) of resistance levels of resistors, with each resistor being located between two terminals of one of the plurality of transistors.The high and / or low resistance levels can depend on the type of one or more transistors. Generally, NMOS transistors have higher electron mobility characteristics than PMOS transistors. Therefore, configurations using NMOS transistors can provide high and low resistance values ​​that are overall lower than the high and low resistance values ​​provided by configurations using PMOS transistors. In an example implementation, described in more detail below, the variable resistance circuit in the word line decoder contains a PMOS transistor exhibiting both high and low resistance levels above 20 kΩ and a voltage difference of approximately 25–30 kΩ, while the variable resistance circuit in the bit line decoder contains an NMOS transistor exhibiting both high and low resistance levels below 15 kΩ and a voltage difference of approximately 5 kΩ.

[0094] The low resistance level, the second bias setting, and / or the increased effective gate-to-source voltage level can be configured for a subsequent event associated with the selected memory cell MC(s), with the subsequent event following the power-on time. An example of a subsequent event is a read result acquisition event, where a read / acquire circuit outputs a read result signal indicating a logical value of the data stored in the selected memory cell MC(s). Viewing the output of the read circuit before the read result acquisition event occurs can lead to an incorrect determination of the logical value of the data.However, adjusting the resistance from the high resistance level to the low resistance level, switching from the first bias setting to the second bias setting, and / or increasing the effective gate-to-source voltage from the reduced voltage level to the increased voltage level can cause the sensing result detection event to occur faster than if the adjustment, switching, and / or increase had not taken place after the current spike occurred.

[0095] Another subsequent event can be a write operation. Adjusting the resistance from a high resistance level to a low resistance level, switching from the first bias setting to the second bias setting, and / or increasing the effective gate-to-source voltage from a reduced voltage level to an increased voltage level can configure the variable resistance circuit, such as the transistor circuit, to provide a current high enough to perform the write operation and / or low enough to avoid large voltage drops that would cause insufficient current through the selected memory cell(s) during the write operation, without increasing the write voltage and the load on the selected transistors.

[0096] In variable-resistance circuit configurations comprising a single transistor, the transistor can have a sufficiently large gate width or channel size to conduct a current optimized for programming operations when biased with a maximum gate-to-source voltage. However, such a gate width or channel size may be too large for safe read operations, as it can deliver an excessively wide current peak and energy through the selected memory cell MC(s) during the read operation.Accordingly, by first adjusting gate voltages to increase a resistance and / or decrease a gate-to-source voltage, the individual transistor can have an effective gate width or channel size that is optimal for read operations, particularly for read operations where the selected memory cell MC(s) conducts a current spike when programmed in a low-resistance state. Similarly, by manipulating the gate voltage before and after the current spike, the same individual transistor can have an effective size that is optimal for both read and write operations on the selected memory cell MC(s).

[0097] A more detailed description can be found in Fig. The example circuit shown in Figure 4 performs a read operation to read data stored in the selected memory cell MC(s) and a write operation to program data into the selected memory cell. During a read operation, the magnitude of the cell current Icell flowing through the selected memory cell MC(s) can indicate or suggest a logical value of the data stored in the selected memory cell MC(s). As part of the read operation, the circuit can be configured to detect the cell current Icell to determine the logical value of the data. For a programming operation, the circuit can be configured to bias the selected memory cell MC(s) so that it draws or writes the cell current Icell in a specific, predetermined manner.The circuit can be configured to accept a corresponding number of predetermined states, such as a high-impedance or low-impedance state, each indicating a different logical value of data that the selected memory cell MC(s) can store. For example, as previously described, the circuit can be configured to bias the selected memory cell so that it conducts the cell current Icell with a fast trailing edge to be programmed into the high-impedance state, and to bias the selected memory cell so that it conducts the cell current Icell with a gradual decay to be programmed into the low-impedance state.

[0098] The circuit configured to perform and / or participate in the read and write operations may include a word line decoder 402, a bit line decoder 404, a word line voltage generator 406, a bit line voltage generator 408, a read circuit 410, and a decoder controller 412. In some example configurations, the circuit may include additional components, in Fig. 4 components not shown, such as a circuit for controlling the read circuit 410 for carrying out read operations and / or a circuit for controlling the word line voltage generator 406 and / or the bit line voltage generator 408.

[0099] The word line decoder 402 can be used for at least one part or section of the word line decoder 148. Fig. 2B corresponds to the bit line decoder 404, at least a part or section of the bit line decoder 150. Fig. 2B and the word line read voltage generator or word line voltage generator 406 and the bit line read voltage generator or bit line voltage generator 408 can be components of the power supply circuit. As described in detail below, the decoder controller 412 can be a component of the control logic 154. Fig. 2B and be configured to control components of the word line decoder 402 and the bit line decoder 404, such as variable resistance circuits and / or transistors, to control the biasing of the word lines and bit lines of the memory array 400 during memory operations.

[0100] As in Fig. As shown in Figure 4, each of the memory cells MC can be coupled to one of a plurality of bit lines and one of a plurality of word lines. In particular, each of the memory cells MC can comprise a first end or terminal coupled to a corresponding plurality of bit lines and a second end or terminal coupled to a corresponding plurality of word lines. For a given read operation to read data from a selected memory cell MC(s) or a given programming operation to program data into the selected memory cell MC(s), the other memory cells MC of the array 400, which are biased with voltages but are otherwise not subject to the read or programming operation, are referred to as unselected memory cells.Unselected memory cells are not subject to the read or program operation because, although they are simultaneously biased at the time the selected word line and bit line are biased, the circuit does not determine the logical values ​​of data that may be stored in the other, unselected memory cells MC during the read operation, nor does it program data into the unselected memory cells MC during the program operation. As in . Fig. As indicated in section 4, for a specific read or programming operation, the word line coupled to the selected memory cell MC(s) is referred to as the selected word line. The other word lines coupled to unselected memory cells MC are referred to as unselected word lines. Similarly, the bit line coupled to the selected memory cell MC(s) is referred to as the selected bit line. The other bit lines coupled to unselected memory cells MC are referred to as unselected bit lines.

[0101] To perform a read operation on the selected memory cell MC(s), the circuit can apply a read voltage differential at a predetermined level across the selected memory cell MC(s). How the selected memory cell MC(s) responds to the read voltage differential at the predetermined level—for example, whether or how much cell current Icell the selected memory cell MC(s) draws in response to the read voltage differential at the predetermined level—can indicate the logical value of the data stored by the selected memory cell MC(s). To generate the read voltage differential, the circuit is configured to apply a selected word line voltage V. WL_SEL to generate on the selected word line (or the selected word line with the selected word line voltage V) WL_SEL to pre-tension) and a selected bit line voltage V BL_SELto generate on the selected bit line (or the selected bit line with the selected bit line voltage V) BL_SEL to pre-tension).

[0102] The predetermined reading voltage difference level can be the difference between the selected word line voltage V WL_SEL at a predetermined selected word line reading voltage level V WL_RD and the selected bit line voltage V BL_SEL at a predetermined selected bit line read voltage level V BL_RD be configured to read data stored in the selected memory cell MC(s). Depending on the configuration of the memory system 100 and / or the memory technology used for the memory cells MC, the read circuit can be configured to use a selected word line voltage level V. WL_RD and selected bit line voltage level V BL_RDhigher than the other, in order to generate the read voltage difference at the read voltage difference level with a predetermined polarity relative to the first and second connections or terminals of the selected memory cell MC(s). In the example configurations described here, the selected word line read voltage level V WL_RD higher than the selected bit line read voltage level V BL_RD In other words, the circuit for performing a read operation is configured to generate a higher voltage on the selected word line than the voltage it generates on the selected bit line in order to read data from the selected memory cell MC(s). Other configurations are possible, including those where the selected bit line read voltage level V BL_RD is higher than the selected word line reading voltage level V WL_RD .

[0103] To perform a write operation on the selected memory cell MC(s), the circuit can apply a write or program voltage differential over a period of time to write or program data into the selected memory cell MC(s) using one of a variety of logic levels or values. In single-bit configurations, where the selected memory cell MC(s) stores a single data bit, the logic levels can include a logic 0 and a logic 1. How the selected memory cell MC(s) responds to the programming voltage differential, for example, how the selected memory cell conducts the cell current Icell, can indicate or determine the logical value of the data that the selected memory cell stores.If the circuit wants to program the selected memory cell MC(s) in a phase-change memory to the high-impedance state, the circuit can bias the selected memory cell MC(s) with a programming voltage differential that causes the selected memory cell MC(s) to conduct the cell current Icell with a current that has a fast trailing edge, and if the circuit wants to program the selected memory cell MC(s) to be in the low-impedance state, the circuit can bias the selected memory cell MC(s) with a programming voltage differential that causes the selected memory cell MC(s) to conduct the cell current Icell with an amplitude that decays gradually, e.g. from 70 µA to 30 µA in 100 ns.Depending on the implementation, the high-impedance state can correspond to a logic 0 value and the low-impedance state to a logic 1 value, or alternatively, the high-impedance state can correspond to a logic 1 value and the low-impedance state to a logic 0 value. As with a read operation, the circuit for generating the programming voltage difference to perform a write operation is configured to use a selected word line voltage V. WL_SEL to generate on the selected word line (or the selected word line with the selected word line voltage V) WL_SEL to pre-tension) and a selected bit line voltage V BL_SEL to generate on the selected bit line (or the selected bit line with the selected bit line voltage V) BL_SEL to pre-tension).

[0104] To perform either a read operation to read data from the selected memory cell MC(s) or a programme operation to program data into the selected memory cell MC(s), the word line voltage generator 406 is configured to generate a global selected word line voltage V GWL_SEL generated at a globally selected word line node GWL_SEL . The global selected word line voltage V generated at the globally selected word line node GWL_SEL GWL_SEL or B GWL_SEL can be delivered or created along a selected word line (WL) path 414, which extends from the globally selected word line node GWL_SEL to the selected word line. The selected word line can be configured to have the globally selected word line voltage V. GWL_SELto receive from the selected word line path 414 and / or to be biased with this voltage and to supply the selected memory cell MC(s) with the selected word line voltage V WL_SEL in response to the global selected word line voltage V GWL_SEL to generate and pre-tension.

[0105] As in Fig. As shown in Figure 4, the selected word line path 414 can originate from the global selected word line node GWL_SEL and pass through the word line decoder 402 to connect and / or couple with the selected word line. The word line decoder 402 can be configured to selectively connect the global selected word line node GWL_SEL to any of the word lines for or during a given memory operation. The word line that the word line decoder 402 connects to the global selected word line node GWL_SEL for the given memory operation is the selected word line. The other word lines that the word line decoder 402 can connect to the global selected word line node GWL_SEL, but does not connect for the given memory operation, are the unselected word lines.

[0106] The Word Line Decoder 402 can contain a variety of switches (e.g., transistors) that turn on and off to selectively connect the selected global word line node GWL_SEL to the selected word line and selectively disconnect the selected global word line node GWL_SEL from the other word lines. The switches of the Word Line Decoder 402 can have any of several different configurations. Some decoder configurations use a single switch level where each word line is connected to a single switch and where the global selected word line voltage V GWL_SELThe signal is routed through a single switch on the word line decoder 402 to reach the selected word line. Other decoder configurations use a tree or multiple switch levels, with different combinations of switches in the levels being turned on and off to connect the global selected word line node GWL_SEL to a specific selected word line, and the global selected word line voltage V GWL_SEL is routed through at least two switches of the word line decoder 402 in order to reach the selected word line.

[0107] For a specific read or program operation, a particular overall state of the switches configured in the on and off states forms the selected word line path 414. In some example configurations, the decoder controller 412 is configured to output a word line address control signal WL_ADDR (which may contain a single signal or multiple signals) to the word line decoder 402 according to the word line address of the selected word line. In response to receiving the word line address control signal WL_ADDR, the switches of the word line decoder 402 are configured in on and off states according to the word line address control signal WL_ADDR to form the selected word line path 414 from the global selected word line node GWL_SEL to the selected word line.Those word lines that are not electrically connected to the global word line node GWL_SEL and the selected word line path 414 are the unselected word lines during the given read or program operation.

[0108] Additionally, the selected word path 414 can contain a variable-resistance word path circuit 416, which has an associated resistance that contributes to the total resistance of the selected word path 414. The variable-resistance word path circuit 416 is configured to adjust its associated resistance to a resistance level from a plurality of resistance levels, and further configured to adjust its associated resistance from one resistance level to another within that plurality of resistance levels. The plurality of resistance levels can be discrete resistance levels or steps, or alternatively, a range of continuous resistance levels extending from a minimum resistance level to a maximum resistance level within that range.

[0109] The variable-resistance word line circuit 416 can be configured to set and / or adjust its associated resistance in response to receiving a word line control signal CTRL_WL output by the decoder controller 412. In some example configurations, a resistance level to which the variable-resistance word line circuit 416 sets its associated resistance corresponds to a level, such as a voltage level, of the word line control signal CTRL_WL. Additionally, the variable-resistance word line circuit 416 can adjust its associated resistance from a first resistance level to a second resistance level in response to a corresponding change in the level of the word line control signal CTRL_WL.In some example configurations, the word line control signal CTRL_WL can be part of, or one of the signals of, the word line address control signal WL_ADDR, while in other configurations the word line control signal CTRL_WL can be separate from the word line address control signal WL_ADDR.

[0110] Furthermore, for some example configurations, the variable-resistance word line circuit 416 may include a transistor circuit containing one or more transistors. As part of the selected word line path 414, the transistor circuit is configured to supply the global selected word line voltage V. GWL_SEL to receive and the selected word line voltage V GWL_SELto forward to the selected word line. The transistor circuit may have an associated resistor and is configured to adjust the resistance level of its associated resistor in response to receiving the word line control signal CTRL_WL. In certain configurations, the word line control signal CTRL_WL includes one or more voltages, and the transistor circuit is configured to receive the one or more input voltages and adjust its resistance to a level corresponding to one or more voltage levels of the one or more input voltages and / or accordingly. Additionally, the transistor circuit may be configured to adjust the resistance level of its resistor circuit in response to a change in the voltage level of one or more input voltages.

[0111] In certain example configurations, the transistor circuit includes one or more metal-oxide-semiconductor field-effect transistors (MOSFETs), each of which includes a corresponding gate terminal configured to receive a voltage from the word line control signal CTRL_WL. In this context, the word line control signal voltage CTRL_WL is a gate voltage applied to the gate terminal. The associated resistance of the transistor circuit may include a drain-to-source resistor or a combination of drain-to-source resistors across one or more drain-source terminal pairs of the MOSFET(s). A given MOSFET receiving the gate voltage may be configured, for example, to adjust a drain-to-source resistor to a resistance value dependent on the voltage level of the received gate voltage.In particular, the drain-to-source resistance of a given MOSFET can depend on the magnitude of the associated gate-to-source voltage difference between the gate and source terminals of that MOSFET. The relationship between the magnitude of the gate-to-source voltage difference between its gate and source terminals and its drain-to-source resistance can generally be inversely proportional to the relationship between the MOSFET's drain-to-source resistance and its overall drain-to-source resistance. Accordingly, adjusting the gate voltage level to match the source voltage level can decrease the gate-to-source voltage, which in turn can increase the drain-to-source resistance of the MOSFET. Conversely, adjusting the gate voltage level to a level further away from the source voltage level can increase the gate-to-source voltage, which can again decrease the drain-to-source resistance of the MOSFET.

[0112] Additionally, in example configurations where the transistor circuit includes one or more MOSFETs, the transistor circuit can contain an effective gate-to-source voltage with an associated effective voltage level. In configurations where the transistor circuit includes a single MOSFET, the effective gate-to-source voltage is the gate-to-source voltage of the single MOSFET, and the associated effective voltage level is the voltage level of the gate-to-source voltage of the single MOSFET. In configurations where the transistor circuit contains multiple MOSFETs, the effective gate-to-source voltage is or is a combination of the gate-to-source voltages of the multiple MOSFETs, and the associated effective voltage level is a combination, such as a sum, of the voltage levels of the gate-to-source voltages.

[0113] The decoder controller 412 can be configured to set and / or control the associated resistance of the word line circuit with variable resistor 416.

[0114] In particular, the decoder controller 412 can be configured to output the word line control signal CTRL_WL at a level, such as a voltage level, that sets, or allows the associated resistor of the variable-resistance word line circuit 416 to a resistance level corresponding to the level of the word line control signal CTRL_WL. Additionally, the decoder controller 412 can be configured to set the resistance of the associated resistor by adjusting the level, such as the voltage level, of the word line control signal CTRL_WL that it outputs to the word line control circuit 416, and / or to control the setting of the associated resistor.

[0115] In configurations where the variable-resistance word line circuit 416 contains or is configured as a transistor circuit, the decoder controller 412 can operate as a bias circuit or function as one configured to bias the transistor circuit. The decoder controller 412 can bias the transistor by outputting and / or applying one or more voltages of the word line control signal CTRL_WL to one or more input terminals of the one or more transistors in the transistor circuit. In certain configurations containing one or more MOSFETs, the input terminal is a gate terminal, and the decoder controller 412 can output the word line control signal CTRL_WL as one or more gate voltages that bias one or more gate terminals of the one or more MOSFETs.If the transistor circuit contains, for example, a single MOSFET, the decoder controller 412, acting as a bias circuit, can adjust and / or control the resistance of the transistor circuit by applying a gate voltage at a specific voltage level to a gate terminal of the single MOSFET. Additionally, the decoder controller 412 can adjust the resistance of the variable-resistance word line circuit 416 by setting a voltage level of the gate voltage applied to the gate terminal of the single MOSFET. In another example, if the transistor circuit contains a large number of MOSFETs, the decoder controller 412, acting as a bias circuit, can adjust and / or control the resistance of the variable-resistance word line circuit 416 by applying multiple gate voltages at corresponding voltage levels to several gate terminals of the multiple MOSFETs.Additionally, the decoder controller 412 can adjust the associated resistance of the word line circuit with variable resistance 416 by setting at least one voltage level of the multitude of gate voltages that it applies to the gate terminals of the multitude of MOSFETs.

[0116] Additionally, in configurations where the variable-resistance word line circuit 416 contains or is configured as a transistor circuit, the decoder controller 412 can operate as a bias circuit by biasing the transistor circuit of the word line decoder 402 according to a word line bias setting. The word line bias setting can include, indicate, and / or specify one or more voltages applied to one or more transistors of the transistor circuit, and the voltage level(s) of those voltages.The Decoder Controller 412 can bias the transistor circuit according to the word line bias setting by biasing one or more transistors of the transistor circuit with one or more voltages at one or more voltage levels, as specified by the word line bias setting. Additionally, the Decoder Controller 412 can be configured as a biasing circuit to bias the transistor circuit with different word line bias settings, such as a first word line bias setting and a second word line bias setting. The first and second word line bias settings can differ from each other by containing at least one voltage with different voltage levels.If the decoder controller 412 biases the transistor circuit according to the first word line bias setting, the decoder controller 412 can be configured to switch to biasing the transistor circuit with a second word line bias setting by changing or setting the voltage level of at least one voltage applied to the transistor circuit.

[0117] As described in more detail below, the variable-resistance word line circuit 416 can be configured during a read operation to at least partially control the width of a current spike or peak fraction of the memory cell current Icell that the selected memory cell MC(s) conducts when switched on, when configured in a specific state, e.g., a low-resistance state. For this purpose, during the read operation, the variable-resistance word line circuit 416 can be configured to set its associated resistance to a high resistance level before or in preparation for the switch-on of the selected memory cell MC(s) and / or in preparation for or before a switch-on time of the selected memory cell MC(s).The variable-resistance word line circuit 416 can be configured to maintain its associated resistance at a high resistance level during an initial power-on period, while the selected memory cell MC(s) initially powers on and conducts a current spike of the memory cell current Icell. After the current spike reaches its maximum, the variable-resistance word line circuit 416 can be configured to adjust its associated resistance from a high resistance level to a low resistance level, where the low resistance level is lower than the high resistance level. In some example configurations, the decoder controller 412 is configured to effect the transition from the high resistance level to the low resistance level by changing the level of the word line control signal CTRL_WL.

[0118] If the selected memory cell MC(s) is configured in the respective state to conduct the current spike upon initial power-up, setting the associated resistance of the variable-resistance word line circuit 416 to the high resistance level during the current spike can result in the current spike having a minimized and / or reduced width compared to the width the current spike would have if the associated resistance of the variable-resistance word line circuit 416 were set to the low resistance level. However, after the current spike has occurred, setting the variable-resistance word line circuit 416 to the low-resistance circuit can be advantageously accelerated if the read circuit 410 can determine the logical value of the data stored in the selected memory cell MC(s), for example, by the global selected word line voltage V. GWL_SELThe voltage can drop below a trigger voltage level Vtrp more quickly than if the variable-resistance word line circuit 416 is held at the high resistance level. Additionally or alternatively, by setting the variable-resistance word line circuit 416 to the low resistance level after the current peak has occurred, it can provide an optimized resistance level at a lower resistance to the selected word line path 414 for a subsequent programming operation on the selected memory cell MC, compared to the high resistance level.

[0119] Fig. Figure 5 shows a circuit diagram of an example configuration of the word line circuit with variable resistance 416. Fig. 4. In the example configuration of the Fig. 5 is the word line circuit with variable resistance 416 configured as a p-channel MOSFET, designated as PMOS transistor M1. As in Fig. As shown in Figure 5, the drain and source terminals of the PMOS transistor M1 are coupled to the selected word line path 414. The PMOS transistor M1 can be one of the switches that the decoder controller 412 is to turn on in order to electrically connect the global selected word line node GWL_SEL to the selected word line. Although in Fig. Not shown in Figure 5, for some example configurations of the word line decoder 402, one or more other switches (e.g., transistors) may be arranged in the selected word line path 414 between the source terminal of the PMOS transistor M1 and the global selected word line node GWL_SEL, and / or in the selected word line path 414 between the drain terminal of the PMOS transistor M1 and the selected word line. In other example configurations, the source terminal may be directly connected to the global selected word line node GWL_SEL, and / or the drain terminal may be directly connected to the selected bit line.

[0120] The PMOS transistor M1 can be configured to turn on and off. When turned on, the PMOS transistor M1 can form a conducting path between its drain and source terminals to allow a certain amount of current to flow between these terminals and, in return, at least a portion of the selected global word line voltage V. GWL_SEL from its source terminal to its drain terminal in the direction of the selected word line. Furthermore, in the off state, the PMOS transistor M1 may not form a conductive path between its drain and source terminals and may itself generally be an open circuit, carrying the global selected word line voltage V. GWL_SEL from its source terminal to its drain terminal in the direction of the selected word line.

[0121] The PMOS transistor M1 can include a gate terminal configured to receive a PMOS gate voltage VgPT, which is a voltage of the reference to Fig. The PMOS transistor M1 can be configured to switch on and off in response to the PMOS gate voltage VgPT. Whether the PMOS transistor M1 is switched on or off depends on the voltage level of the PMOS gate voltage VgPT. In particular, the PMOS transistor M1 can have an associated threshold voltage VtP. An example of an associated threshold voltage is 0.5 V, although other voltage levels are possible. If the voltage level of the PMOS gate voltage VgPT provides a gate-to-source voltage across the gate and source terminals of the PMOS transistor M1 that is less than the associated threshold voltage VtP, the PMOS transistor M1 is switched off.When the voltage level of the PMOS gate voltage VgPT provides an amount of gate-to-source voltage at the gate and source terminals of the PMOS transistor M1 that is greater than or equal to the associated threshold voltage VtP, the PMOS transistor M1 is turned on.

[0122] The Decoder Controller 412 is configured to control the switching on and off of the PMOS transistor M1 by controlling and / or adjusting the voltage level of the PMOS gate voltage VgPT. Generally, the Decoder Controller 412 decreases the magnitude of the gate-to-source voltage at the gate and source terminals of the PMOS transistor M1 by increasing the voltage level of the PMOS gate voltage VgPT, and increases the magnitude of the gate / source voltage at the gate and source terminals of the PMOS transistor M1 by decreasing the voltage level of the PMOS gate voltage VgPT. Additionally, the Decoder Controller 412 can generate the PMOS gate voltage VgPT at a specific voltage level that provides a gate-to-source voltage of the PMOS transistor M1 with the associated threshold voltage level VtP.The lower the PMOS gate voltage VgPT generated by the decoder controller 412 is from a specific voltage level, the higher the gate-to-source voltage of the PMOS transistor M1. Conversely, the higher the PMOS gate voltage VgPT generated by the decoder controller 412 is above a specific voltage level, the lower the gate-to-source voltage of the PMOS transistor M1. Accordingly, the decoder controller 412 can be configured to decrease the voltage level of the PMOS gate voltage VgPT to increase the amplitude of the gate-to-source voltage, and conversely, to increase the voltage level of the PMOS gate voltage VgPT to decrease the amplitude of the gate-to-source voltage.

[0123] Furthermore, the PMOS transistor M1 can have an associated drain-to-source resistance RdsP across its drain and source terminals. In configurations where the variable-resistance word line circuit 416 is configured as PMOS transistor M1, the associated resistance of the variable-resistance word line circuit 416 is the drain-to-source resistance RdsP of the PMOS transistor M1. The PMOS transistor M1 can exhibit an inverse relationship between its drain-to-source resistance RdsP and its gate-to-source voltage. That is, the larger the gate-to-source voltage, the smaller the value of its drain-to-source resistance RdsP, and conversely, the smaller the gate-to-source voltage, the larger the value of its drain-to-source resistance RdsP.

[0124] As previously described, in configurations where the variable-resistance word line circuit 416 is implemented as a transistor circuit with one or more MOSFETs, the transistor circuit can have an effective gate-to-source voltage. For the single-transistor configuration from Fig. 5 is the effective gate-to-source voltage of the transistor circuit, the gate-to-source voltage of the PMOS transistor M1, and the voltage level of the effective gate-to-source voltage is the voltage level of the gate-to-source voltage of the PMOS transistor M1.

[0125] During a read operation to read data from the selected memory cell MC(s) ( Fig. 4) Before a power-on time, the decoder controller 412 can generate the PMOS gate voltage VgPT at an initial voltage level, which reduces the gate-to-source voltage and, in turn, increases the drain-to-source resistance RdsP. The decoder controller 412 can maintain the PMOS gate voltage VgPT at this initial level during an initial power-on period when the selected memory cell MC(s) conducts a current spike of the memory cell current Icell, if it is programmed to be in a specific state, such as a low-resistance state.By maintaining the PMOS gate voltage VgPT at the first level during the initial turn-on period, the PMOS transistor M1 has a gate-to-source voltage at the reduced voltage level, and its drain-to-source resistance RdsP is set to the high or increased resistance level during the initial turn-on period when the selected memory cell MC(s) conducts the current spike. At the end of the initial turn-on period, the decoder controller 412 can begin to reduce the PMOS gate voltage VgPT from the first voltage level to a second voltage level, which in turn increases the gate-to-source voltage to a higher voltage level and reduces the drain-to-source resistance RdsP to a low or decreased resistance level.

[0126] The first voltage level, at which the decoder controller 412 generates the PMOS gate voltage VgPT, can supply a gate-to-source voltage of the PMOS transistor M1 at a reduced voltage level, configured to reduce the width of the current peak of the memory cell current Icell. The width is reduced relative to the width of a current peak that the selected memory cell MC(s) would conduct if the decoder controller 412 generated the PMOS gate voltage VgPT at the second level, so that the gate-to-source voltage is at the increased voltage level and the drain-to-source resistance RdsP is at the low or reduced resistance level during the initial turn-on time.

[0127] The initial power-on period may end before a subsequent event associated with the selected memory cell MC(s) occurs. This subsequent event may be a read result acquisition event, in which the read circuit 410 generates and / or outputs a read result signal SR indicating the logic level of the data stored in the selected memory cell MC(s). As the initial power-on periods end, the drop in the PMOS gate voltage VgPT, and thus the increase in the gate-to-source voltage to the elevated voltage level and the drop in the drain-to-source resistance RdsP to the lower or reduced resistance level, allows for a faster drop in the global selected word line voltage V. GWL_SELThis also means that the read result acquisition event occurs earlier compared to when the decoder controller 412 maintains the PMOS gate voltage VgPT at the initial voltage level, thus keeping the gate-to-source voltage at the reduced level and the drain-to-source resistance RdsP at the high or elevated resistance level. The start of a subsequent event can begin after a timeout of appropriate duration to ensure that the selected memory cell MC(s) has been turned on when it is in the low-resistance state and the resulting current spike has dissipated. The decoder controller 412 can then reduce the elevated resistance by decreasing the PMOS gate voltage VgPT to increase the gate-to-source voltage level.

[0128] Additionally or alternatively, a subsequent event associated with the selected memory cell MC(s) can be a write operation. An example memory operation, where the circuit can perform a read operation to read data from the selected memory cell MC(s) and immediately afterwards a write operation to program data into the selected memory cell, can be a read-modify-write operation. During the write operation, the selected word line can supply the selected memory cell MC(s) with the selected word line voltage V. WL_SELThe selected memory cell MC(s) is biased to a sufficiently high voltage level for at least part of a write period to cause it to conduct a specific desired amount of current over that portion of the write period. This allows the selected memory cell MC(s) to be configured in a specific state (e.g., a low-impedance or high-impedance state) to store data at a desired logic level. While the PMOS transistor M1, with its gate-to-source voltage at the reduced voltage level and an increased drain-to-source resistance RdsP, is suitable for minimizing the current peak width during the initial turn-on period, it may present an excessively large voltage drop and / or excessively high drain-to-source resistance RdsP to ensure that the selected word line voltage V is maintained. WL_SELat a sufficiently high voltage level and / or that the selected memory cell MC(s) conducts the specified desired amount of cell current during the write period. Accordingly, after the end of the initial turn-on times, the PMOS gate voltage VgPT is reduced, the gate-to-source voltage is increased to the elevated voltage level, and the drain-to-source resistance RdsP is reduced to the lower or decreased resistance level. This can allow a smaller voltage drop across the PMOS transistor M1 and / or a larger current flow through the PMOS transistor M1 to better ensure that the selected word line supplies the selected memory cell MC(s) with a sufficiently high selected word line voltage V. WL_SEL pre-loaded and / or the selected memory cell MC(s) is able to conduct a sufficiently large cell current during the write period.

[0129] The Decoder Controller 412 can be configured to generate the PMOS gate voltage VgPT at a corresponding maximum and minimum voltage level. The Decoder Controller 412 can be configured to generate the PMOS gate voltage VgPT at the maximum voltage level to turn off the PMOS transistor M1. When the PMOS gate voltage VgPT is generated at the maximum voltage level, the PMOS transistor M1 can exhibit a gate-to-source voltage at a minimum voltage level and a drain-to-source resistance RdsP at a maximum resistance level. When the gate terminal is biased at the maximum voltage level with the PMOS gate voltage, the conduction path between the source and drain terminals of the PMOS transistor M1 will accordingly have minimum conductance and / or maximum resistance.When generating the PMOS gate voltage VgPT at the minimum voltage level, the PMOS transistor M1 can exhibit a gate-to-source voltage at a maximum voltage level and a drain-to-source resistance RdsP at a minimum level. When biased with the PMOS gate voltage VgPT at the minimum voltage level, the PMOS transistor M1 is considered fully turned on, in that its trace between its source and drain terminals exhibits maximum conductivity and / or minimum resistance.

[0130] In some example configurations, the maximum and minimum voltage levels can correspond to and / or be equal to the maximum and minimum supply voltage levels that result in the maximum or rail-to-rail voltage switch for the memory operation. Depending on the memory configuration, the memory chip can use 104 different maximum and minimum voltage levels for read and write operations. Additionally or alternatively, the maximum and minimum voltage levels can depend on the memory technology of the PMOS transistor M1. Two types of transistors that can be used for the PMOS transistor M1 are a triple-well transistor and a non-triple-well transistor. For a specific type of triple-well transistor, the minimum PMOS gate voltage level for the transistor to select the word line high is 4.5 V, and the maximum PMOS gate voltage level is 9 V.For a specific type of non-triple-well transistor, the minimum PMOS gate voltage level is 0 V and the maximum PMOS gate voltage level is 8 V. These voltage level values ​​are merely examples, and other minimum and maximum gate voltage levels applied to the PMOS transistor M1 are possible.

[0131] In at least some example configurations, the first PMOS gate voltage level, VgPT, which sets the gate-to-source voltage of the PMOS transistor M1 to a reduced level and the drain-to-source resistance RdsP to a high or increased level, is an intermediate voltage level between the maximum and minimum voltage levels. In certain example configurations, the first voltage level is greater than the associated threshold voltage, VtP, which is below the maximum voltage level and greater than the minimum voltage level. In an example configuration using a non-triple-well PMOS transistor where the maximum voltage level is 8 V, the minimum voltage level is 0 V, and the threshold voltage, VtP, is 0.5 V, the first PMOS gate voltage level is 4.5 V.In another example configuration using a triple-well PMOS transistor with a maximum voltage of 9 V, a minimum voltage of 4.5 V, and a threshold voltage of 0.5 V, the first voltage level of the PMOS gate voltage is 6 V. This first voltage level is an intermediate voltage between the maximum and minimum voltage levels. These voltage levels are merely examples, and other voltage levels, including a threshold voltage (VtP) below the maximum and above the minimum voltage levels, are possible.

[0132] If the PMOS transistor M1 is biased with the PMOS gate voltage VgPT at an intermediate voltage level between the maximum and minimum voltage levels, the PMOS transistor M1 can be considered partially switched on, since its conduction path between its source and drain terminals may lie between a maximum and a minimum conductance and / or resistance value, and a non-zero current may flow through the PMOS transistor M1.

[0133] Additionally, in some example configurations, the second voltage level of the PMOS gate voltage VgPT, which increases the gate-to-source voltage and decreases the drain-to-source resistance RdsP to a lower or reduced level, can be the minimum voltage level. This results in the gate-to-source voltage of the PMOS transistor M1 being at its maximum magnitude and the drain-to-source resistance RdsP between the drain and source terminals being at its minimum level. In other example configurations, the second level is higher than the minimum voltage level but still lower than the first voltage level, providing an increased gate-to-source voltage level and / or a reduced drain-to-source resistance.

[0134] As previously described, after the initial power-on time, one or more subsequent events related to the selected memory cell MC(s) can occur, including a read result capture event and a write operation. The second voltage level can be the PMOS gate voltage level at the time the subsequent event occurs or begins. In some example configurations, there can be multiple second voltage levels because the second voltage level at which the PMOS gate voltage VgPT is at the time of the capture event may be different (e.g., higher) than the second voltage level at which the PMOS gate voltage VgPT is at the beginning of the write operation. As an illustrative example, at the end of the initial power-on time, the decoder controller 412 can begin to decrease the PMOS gate voltage VgPT from the first voltage level.When the read result acquisition event occurs, the decoder controller 412 can generate the PMOS gate voltage VgPT at a given voltage level lower than the first voltage level. The decoder controller 412 can further decrease the level of the PMOS gate voltage VgPT so that at a later time, when the write period begins, the PMOS gate voltage VgPT is at a voltage level lower than both the first voltage level and the given voltage level at which the PMOS gate voltage VgPT was at the time of the read result acquisition event. In other configurations, the second voltage level can be a single voltage level reached at the time of the acquisition event, and the decoder controller 412 can be configured to maintain the PMOS gate voltage VgPT at the second voltage level from the time of the acquisition event for at least part of the write period.In both cases, the decoder controller 412 can be configured to reduce the PMOS gate voltage VgPT at a time after the maximum of the peak fraction of the cell current Icell and before the occurrence of at least one subsequent event associated with the selected memory cell(s) MC, so that at the time of the occurrence of the subsequent event, the PMOS transistor M1 has a gate-to-source voltage at a higher voltage level and a drain-to-source resistance at a lower resistance level than during the initial turn-on period when it conducted the current peak.

[0135] Additionally or alternatively, the 412 decoder controller can, at least for some example configurations, reduce the PMOS gate voltage VgPT from the first voltage level to the second voltage level, so that until the subsequent event associated with the selected memory cell MC(s) occurs, the drain-to-source resistance RdsP experiences at least a minimal change (e.g., a minimal decrease) in resistance level. In some example configurations, the change in resistance level can be on the order of kiloohms (kΩ), e.g., at least 1 kΩ. In certain example configurations, the change in resistance level can be a decrease on the order of several tens of kiloohms, e.g., greater than 10 kΩ, 20 kΩ, or 30 kΩ, as non-limiting examples.

[0136] With reference to Fig. 4 The bit line voltage generator 408 is configured to additionally perform either a read operation to read data from the selected memory cell MC(s) or a program operation to program data into the selected memory cell in order to generate a global selected bit line voltage V GBL_SEL to generate GWB_SEL at a globally selected bit line node . The global selected bit line voltage V GBL_SEL The voltage generated at the globally selected bitline node GBL_SEL can be delivered along a selected bitline path (BL) 417 extending from the globally selected bitline node GBL_SEL to the selected bitline. The selected bitline can be configured to supply the globally selected bitline voltage V GBL_SELto receive from the selected bit line path 417 and / or to be biased with this voltage and to supply the selected memory cell MC(s) with the selected bit line voltage V BL_SEL in response to the globally selected bit line voltage V GBL_SEL to generate and pre-tension.

[0137] As in Fig. As shown in Figure 4, the selected bitline path 417 can pass from the global selected bitline node GBL_SEL through the bitline decoder 404 to connect to and / or couple with the selected bitline. The bitline decoder 404 can be configured to selectively connect the global selected bitline node GBL_SEL to any bitline for or during a given memory operation. The bitline that the bitline decoder 406 connects to the global selected bitline node GBL_SEL for the given memory operation is the selected bitline. The other bitlines that the bitline decoder 404 can connect to the globally selected bitline node GBL_SEL, but does not connect for the given memory operation, are the unselected bitlines.

[0138] Similar to the Word Line Decoder 402, the Bit Line Decoder 404 can contain a variety of switches (e.g., transistors) that turn on and off to selectively connect the selected global bit line node GBL_SEL to the selected bit line and selectively disconnect the selected global bit line node GBL_SEL from the other, unselected bit lines. The switches of the Bit Line Decoder 404 can have various configurations, such as a single-stage configuration or a multi-stage configuration, as previously described for the Word Line Decoder 402. Depending on the configuration of the Bit Line Decoder 404, the global selected bit line voltage V can be GBL_SEL pass through one or more switches of the bit line decoder 404 to reach the selected bit line.

[0139] For a specific read or program operation, a particular overall state of the switches configured in the on and off states forms the selected bitline path 417. In some example configurations, the decoder controller 412 is configured to output a bitline address control signal BL_ADDR (which may contain a single signal or multiple signals) to the bitline decoder 404 according to the bitline address of the selected bitline. In response to receiving the bitline address control signal BL_ADDR, the switches of the bitline decoder 404 are configured in on and off states according to the bitline address control signal BL_ADDR to form the selected bitline path 417 from the global selected bitline node GBL_SEL to the selected bitline.Those bit lines that are not electrically connected to the global bit line node GBL_SEL and the selected bit line path 417 are the unselected bit lines during the given read or program operation.

[0140] Additionally, the selected bitline path 417 may contain a bitline circuit or variable-resistance bitline circuit 418, which has an associated resistance that contributes to the total resistance of the selected bitline path 417. The variable-resistance bitline circuit 418 is configured to adjust its associated resistance to a resistance level from a plurality of resistance levels, and further configured to adjust its associated resistance from one resistance level to another resistance level within that plurality of resistance levels. The multiple resistance levels may be discrete resistance levels or, alternatively, a range of continuous resistance levels extending from a minimum resistance level to a maximum resistance level within that range.

[0141] The variable-resistance bitline circuit 418 can be configured to set and / or adjust its associated resistance in response to receiving a CTRL_BL bitline control signal output by the decoder controller 412. In some example configurations, a resistance level to which the variable-resistance bitline circuit 418 sets its associated resistance corresponds to a level, such as a voltage level, of the CTRL_BL bitline control signal. Additionally, the variable-resistance bitline circuit 418 can adjust its associated resistance from a first resistance level to a second resistance level in response to a corresponding change in the level of the CTRL_BL bitline control signal.In some example configurations, the bitline control signal CTRL_BL can be part of, or one of the signals of, the bitline address control signal BL_ADDR, while in other configurations the bitline control signal CTRL_BL can be separate from the bitline address control signal BL_ADDR.

[0142] Additionally, the variable-resistance bitline circuit 418 may, for some example configurations, include a transistor circuit containing one or more transistors. As part of the selected bitline path 417, the transistor circuit is configured to supply the globally selected bitline voltage V. GBL_SEL to receive and the selected bit line voltage V GWL_SELto forward to the selected bit line. The transistor circuit may have an associated resistor and is configured to adjust the resistance level of its associated resistor in response to receiving the bit line control signal CTRL_BL. In certain configurations, the bit line control signal CTRL_BL includes one or more voltages, and the transistor circuit is configured to adjust its resistance to a level that corresponds to and / or matches one or more of the voltage levels of those voltages. Additionally, the transistor circuit may be configured to adjust the resistance level of its resistor circuit in response to a change in the voltage level of those one or more voltages.

[0143] In certain example configurations, the transistor circuit includes one or more MOSFETs, each of which has a corresponding gate terminal configured to receive a voltage from the bit-line control signal CTRL_BL. In this context, the voltage of the bit-line control signal CTRL_BL is a gate voltage applied to the gate terminal. The associated resistance of the transistor circuit may consist of a drain-to-source resistor or a combination of drain-to-source resistors across one or more drain-source terminal pairs of the MOSFET(s). A given MOSFET receiving the gate voltage may be configured, for example, to adjust a drain-to-source resistor to a resistance value dependent on the voltage level of the received gate voltage.In particular, the drain-to-source resistance of a given MOSFET can depend on the magnitude of the associated gate-to-source voltage difference between the gate and source terminals of that MOSFET. The relationship between the magnitude of the gate-to-source voltage difference between its gate and source terminals and its drain-to-source resistance can generally be inversely proportional to the relationship between the MOSFET's drain-to-source resistance and its overall drain-to-source resistance. Accordingly, adjusting the gate voltage level to match the source voltage level can decrease the gate-to-source voltage, which in turn can increase the drain-to-source resistance of the MOSFET. Conversely, adjusting the gate voltage level to a level further away from the source voltage level can increase the gate-to-source voltage, which can again decrease the drain-to-source resistance of the MOSFET.

[0144] Additionally, in example configurations where the transistor circuit contains one or more MOSFETs, an effective gate-to-source voltage with an associated effective voltage level can be included. In configurations where the transistor circuit contains a single MOSFET, the effective gate-to-source voltage is the gate-to-source voltage of the single MOSFET, and the associated effective voltage level is the voltage level of the gate-to-source voltage of the single MOSFET. In configurations where the transistor circuit contains multiple MOSFETs, the effective gate-to-source voltage is or is a combination of the gate-to-source voltages of the multiple MOSFETs, and the associated effective voltage level is a combination, e.g., a sum of the voltage levels of the gate-to-source voltages.

[0145] The decoder controller 412 can be configured to set and / or control the setting of the associated resistor of the variable-resistance bit-line circuit 418. Specifically, the decoder controller 412 can be configured to output the bit-line control signal CTRL_BL at a level, such as a voltage level, that sets the associated resistor of the variable-resistance bit-line circuit 418 to a resistance level and / or causes it to be set to a level corresponding to the level of the CTRL_BL bit-line control signal. Additionally, the decoder controller 412 can be configured to set and / or control the setting of the associated resistor by adjusting the level, such as the voltage level, of the CTRL_BL bit-line control signal that it outputs to the variable-resistance bit-line circuit 418.

[0146] In configurations where the variable-resistance bit-line circuit 418 contains or is configured as a transistor circuit, the decoder controller 412 can operate as a bias circuit or function as one configured to bias the transistor circuit. The decoder controller 412 can bias the transistor by outputting and / or applying one or more voltages of the bit-line control signal CTRL_BL to one or more input terminals of the one or more transistors in the transistor circuit. In certain configurations containing one or more MOSFETs, the input terminal is a gate terminal, and the decoder controller 412 can output the bit-line control signal CTRL_BL as one or more gate voltages that bias one or more gate terminals of the one or more MOSFETs.If the transistor circuit contains, for example, a single MOSFET, the decoder controller 412, acting as a bias circuit, can adjust and / or control the resistance of the transistor circuit by applying a gate voltage at a specific voltage level to a gate terminal of the single MOSFET. Additionally, the decoder controller 412 can adjust the resistance of the variable-resistance bitline circuit 418 by setting a voltage level of the gate voltage applied to the gate terminal of the single MOSFET. As another example, if the transistor circuit contains a large number of MOSFETs, the decoder controller 412, acting as a bias circuit, can adjust and / or control the resistance of the variable-resistance bitline circuit 418 by applying multiple gate voltages at corresponding voltage levels to several gate terminals of the multiple MOSFETs.Additionally, the decoder controller 412 can adjust the associated resistance of the variable resistance bit line circuit 418 by setting at least one voltage level of the multitude of gate voltages that it applies to the gate terminals of the multitude of MOSFETs.

[0147] Additionally, in configurations where the variable-resistance bitline circuit 418 contains or is configured as a transistor circuit, the decoder controller 412 can operate as a bias circuit by biasing the transistor circuit of the bitline decoder 404 according to a bitline bias setting. The bitline bias setting can include, indicate, and / or specify one or more voltages applied to one or more transistors of the transistor circuit, and the voltage level(s) of those voltages.The Decoder Controller 412 can bias the transistor circuit according to the bit-line bias setting by biasing one or more transistors of the circuit with one or more voltages at one or more voltage levels, as specified by the bit-line bias setting. Additionally, the Decoder Controller 412 can be configured as a biasing circuit to bias the transistor circuit with different bit-line bias settings, such as a first bit-line bias setting and a second bit-line bias setting. The first and second bit-line bias settings can differ from each other by containing at least one voltage at different voltage levels.If the decoder controller 412 biases the transistor circuit according to the first bit line bias setting, the decoder controller 412 can be configured to switch to the bias of the transistor circuit with a second bit line bias setting by changing or setting the voltage level of at least one voltage applied to the transistor circuit.

[0148] As described in detail below, the variable-resistance bitline circuit 418 can be configured during a read operation to control, at least partially, the width of a current spike or peak fraction of the memory cell current Icell that the selected memory cell MC(s) conducts when switched on, when configured in a specific state, e.g., a low-resistance state. For this purpose, during the read operation, the variable-resistance bitline circuit 418 can be configured to set its associated resistance to a high resistance level in preparation for or before the switch-on of the selected memory cell MC(s) and / or in preparation for or before a switch-on time of the selected memory cell MC(s).The variable-resistance bitline circuit 418 can be configured to maintain its associated resistance at a high level during an initial power-on period, while the selected memory cell MC(s) is initially energized and conducts a current spike of the memory cell current Icell. After the current spike reaches its maximum, the variable-resistance bitline circuit 418 can be configured to adjust its associated resistance from a high level to a low level, where the low level is lower than the high level. In some example configurations, the decoder controller 412 is configured to effect the transition from the high to the low resistance level by changing the level of the bitline control signal CTRL_BL.

[0149] If the selected memory cell MC(s) is configured in the respective state to conduct the current spike upon initial power-up, setting the associated resistance of the variable-resistance bit-line circuit 418 to the high resistance level during the current spike can result in the current spike having a minimized and / or reduced width compared to the width the current spike would have if the associated resistance of the variable-resistance bit-line circuit 418 were set to the low resistance level. However, after the current spike has occurred, setting the variable-resistance bit-line circuit 418 to the low-resistance circuit can be advantageously accelerated if the read circuit 410 can determine the logical value of the data stored in the selected memory cell MC(s), for example, by the global selected word-line voltage V. GWL_SELThe current can drop below a trigger voltage level Vtrp more quickly than if the variable-resistance bitline circuit 418 is held at the high resistance level. Additionally or alternatively, by setting the variable-resistance bitline circuit 418 to the low resistance level after the current peak has occurred, it can provide an optimized resistance level for the selected bitline path 417 for a subsequent programming operation on the selected memory cell MC(s) compared to the high resistance level.

[0150] Fig. Figure 6 shows a circuit diagram of an example configuration of the bitline circuit with variable resistance 418. Fig. 4. In the example configuration of Fig. 6 is the bitline circuit with variable resistance 418 configured as an n-channel MOSFET, which is designated as NMOS transistor N1. As in Fig. As shown in Figure 6, the drain and source terminals of the NMOS transistor N1 are coupled to the selected bit line path 417. The NMOS transistor N1 can be one of the switches that the decoder controller 412 is to turn on in order to electrically connect the global selected bit line node GBL_SEL to the selected bit line. Although in Fig. Not shown in Figure 6, for some example configurations of the bitline decoder 404, one or more other switches (e.g., transistors) may be arranged in the selected bitline path 417 between the source terminal of the NMOS transistor N1 and the global selected bitline node GBL_SEL, and / or in the selected bitline path 417 between the drain terminal of the NMOS transistor N1 and the selected bitline. In other example configurations, the source terminal may be directly connected to the global selected bitline node GBL_SEL, and / or the drain terminal may be directly connected to the selected bitline.

[0151] The NMOS transistor N1 can be configured to turn on and off. When turned on, the NMOS transistor N1 can form a conductive path between its drain and source terminals to allow a certain amount of current to flow between them and, in turn, to supply at least a portion of the global selected bit line voltage V. GBL_SEL from its source terminal to its drain terminal in the direction of the selected bit line. Furthermore, the NMOS transistor N1, when switched off, may not form a conductive path between its drain and source terminals and may itself generally be an open circuit, carrying the global selected bit line voltage V. GBL_SEL does not pass from its source terminal to its drain terminal to the selected bit line.

[0152] The NMOS transistor N1 can include a gate terminal configured to receive an NMOS gate voltage VgNT, which is a voltage of the reference to Fig. The NMOS transistor N1 can be configured to turn on and off in response to the NMOS gate voltage VgNT. Whether NMOS transistor N1 turns on or off depends on the voltage level of the NMOS gate voltage VgNT. In particular, NMOS transistor N1 can have an associated threshold voltage VtN. An example of an associated threshold voltage might be 0.5 V, although other voltage levels are possible. When the voltage level of the NMOS gate voltage VgNT provides a gate-to-source voltage across the gate and source terminals of NMOS transistor N1 that is less than the associated threshold voltage VtN, NMOS transistor N1 turns off.When the voltage level of the NMOS gate voltage VgNT provides an amount of gate-to-source voltage at the gate and source terminals of the NMOS transistor N1 that is greater than or equal to the associated threshold voltage VtN, the NMOS transistor N1 is turned on.

[0153] The decoder controller 412 is configured to control the switching on and off of the NMOS transistor N1 by controlling and / or adjusting the voltage level of the NMOS gate voltage VgNT. Generally, the decoder controller 412 decreases the magnitude of the gate-to-source voltage at the gate and source terminals of the NMOS transistor N1 by decreasing the voltage level of the NMOS gate voltage VgNT, and increases the magnitude of the gate-to-source voltage at the gate and source terminals of the NMOS transistor N1 by increasing the voltage level of the NMOS gate voltage VgNT. Additionally, the decoder controller 412 can generate the NMOS gate voltage VgNT at a specific voltage level that provides a gate-to-source voltage of the NMOS transistor N1 with the associated threshold voltage level VtN.The lower the NMOS gate voltage VgNT generated by the decoder controller 412 is from a specified voltage level, the lower the amplitude of the gate-to-source voltage of the NMOS transistor N1. Furthermore, the higher the NMOS gate voltage VgNT generated by the decoder controller 412 is above the specified voltage level, the higher the gate-to-source voltage of the NMOS transistor N1. Accordingly, the decoder controller 412 can be configured to decrease the NMOS gate voltage VgNT to reduce the magnitude of the gate-to-source voltage, and it can be configured to increase the NMOS gate voltage VgNT to increase the magnitude of the gate-to-source voltage.

[0154] Furthermore, the NMOS transistor N1 can have an associated drain-to-source resistance RdsN across its drain and source terminals. In configurations where the variable-resistance bit-line circuit 418 is configured as the NMOS transistor N1, the associated resistance of the variable-resistance bit-line circuit 418 is the drain-to-source resistance RdsN of the NMOS transistor N1. The NMOS transistor N1 can exhibit an inverse relationship between its drain-to-source resistance RdsN and its gate-to-source voltage. That is, the larger the amplitude of the gate-to-source voltage, the smaller the resistance value of its drain-to-source resistance RdsN, and the smaller the amplitude of the gate-to-source voltage, the larger the resistance value of its drain-to-source resistance RdsN.

[0155] As previously described, in configurations where the variable-resistance bitline circuit 418 is implemented as a transistor circuit with one or more MOSFETs, the transistor circuit can have an effective gate-to-source voltage. For the single-transistor configuration from Fig. 6 is the effective gate-to-source voltage of the transistor circuit, the gate-to-source voltage of the NMOS transistor N1, and the voltage level of the effective gate-to-source voltage is the voltage level of the gate-to-source voltage of the NMOS transistor N1.

[0156] During a read operation to read data from the selected memory cell MC(s) ( Fig. 4) Before a power-on time, the decoder controller 412 can generate the NMOS gate voltage VgNT at an initial voltage level, which reduces the gate-to-source voltage and, in turn, increases the drain-to-source resistance RdsN. The decoder controller 412 can maintain the NMOS gate voltage VgNT at this initial level during an initial power-on period, during which the selected memory cell MC(s) conducts a current spike of the memory cell current Icell if it is programmed to be in a specific state, e.g., a low-resistance state.By maintaining the NMOS gate voltage VgNT at the first level during the initial turn-on period, the NMOS transistor N1 has a gate-to-source voltage at the reduced voltage level, and its drain-to-source resistance RdsN is set to the high or increased resistance level during the initial turn-on period when the selected memory cell MC(s) conducts the current spike. At the end of the initial turn-on period, the decoder controller 412 can begin increasing the NMOS gate voltage VgNT from the first voltage level to a second voltage level, which in turn increases the gate-to-source voltage to an increased voltage level and decreases the drain-to-source resistance RdsN to a low or reduced resistance level.

[0157] The first voltage level, at which the decoder controller 412 generates the NMOS gate voltage VgNT, can supply a gate-to-source voltage of the NMOS transistor N1 at a reduced voltage level, configured to reduce the width of the current peak of the memory cell current Icell. The width is reduced relative to the width of a current peak that the selected memory cell MC(s) would conduct if the decoder controller 412 generated the NMOS gate voltage VgNT at the second level, so that the gate-to-source voltage is at the increased voltage level and the drain-to-source resistance RdsN is at the low or reduced resistance level during the initial turn-on time.

[0158] The initial power-on period may end before a subsequent event related to the selected memory cell MC(s) occurs. This subsequent event may be a read result acquisition event, in which the read circuit 410 generates and / or outputs a read result signal SR indicating the logic level of the data stored in the selected memory cell MC(s). When the initial power-on periods end, increasing the NMOS gate voltage VgNT, and thus increasing the gate-to-source voltage to the elevated voltage level, and decreasing the drain-to-source resistance RdsN to the lower or reduced resistance level, allows for a faster reduction of the global selected word line voltage V. GWL_SEL, and thus also that the event of the read result acquisition occurs earlier, compared to when the decoder controller 412 keeps the NMOS gate voltage VgNT at the first voltage level and thus the gate-to-source voltage at the reduced level and the drain-to-source resistance RdsN at the high or increased resistance level.

[0159] Additionally or alternatively, a subsequent event associated with the selected memory cell MC(s) can be a write operation, such as part of a read-modify-write operation as described previously. During the write operation, the selected bit line can bias the selected memory cell MC(s) with the selected bit line voltage so that the selected memory cell MC(s) can conduct a specific desired amount of current over the portion of the write period, thus configuring the selected memory cell MC(s) in a specific state (e.g., a low-impedance or high-impedance state) to store data at a desired logic level.The NMOS transistor N1 with the gate-to-source voltage at the reduced voltage level and an increased drain-to-source resistance RdsN is suitable to minimize the width of the current peak during the initial turn-on period, but may have too large a voltage drop and / or too high a drain-to-source resistance RdsN to ensure that the selected memory cell MC(s) conducts the specific desired amount of cell current during the write period.Accordingly, after the end of the initial turn-on periods, increasing the NMOS gate voltage VgNT, and thus increasing the gate-to-source voltage to the increased voltage level, and reducing the drain-to-source resistance RdsN to the low or reduced resistance level can allow a lower voltage drop across the NMOS transistor N1 and / or a larger current flow through the NMOS transistor N1 to better ensure that the selected memory cell MC(s) is able to conduct a sufficiently large cell current during the write period.

[0160] The Decoder Controller 412 can be configured to generate the NMOS gate voltage VgNT at a corresponding maximum and minimum voltage level. The Decoder Controller 412 can be configured to generate the NMOS gate voltage VgNT at the minimum voltage level to turn off the NMOS transistor N1. When generating the NMOS gate voltage VgNT at the minimum voltage level, the NMOS transistor N1 can exhibit a gate-to-source voltage at the minimum voltage level and a drain-to-source resistance RdsP at the maximum resistance level. When the gate terminal is biased at the minimum voltage level with the NMOS gate voltage, the conduction path between the source and drain terminals of the NMOS transistor N1 will accordingly have minimum conductance and / or maximum resistance.When generating the NMOS gate voltage VgNT at its maximum voltage level, the NMOS transistor N1 can exhibit a gate-to-source voltage at maximum voltage level and a drain-to-source resistance RdsP at minimum level. When biased with the NMOS gate voltage VgNT at its maximum voltage level, the NMOS transistor N1 is said to be fully turned on, as its conduction path between its source and drain terminals exhibits maximum conductance and / or minimum resistance.

[0161] In some example configurations, the maximum and minimum voltage levels can correspond to and / or be equal to the maximum and minimum supply voltage levels that result in the maximum or rail-to-rail voltage swing for the memory operation. Depending on the memory configuration, the memory chip can use 104 different maximum and minimum voltage levels for read and write operations. Additionally or alternatively, the maximum and minimum voltage levels can depend on the memory technology of the NMOS transistor N1. Similar to the one mentioned with reference to Fig. As described in section 5 for the PMOS transistor M1, two types of transistors can be used for the NMOS transistor N1: a triple-well transistor and a non-triple-well transistor. For a specific type of triple-well transistor, the minimum NMOS gate voltage level is 0 V and the maximum NMOS gate voltage level is 4.5 V. For a specific type of non-triple-well transistor, the minimum NMOS gate voltage level is 0 V and the maximum PMOS gate voltage level is 8 V. These voltage levels are only examples, and other minimum and maximum gate voltage levels applied to the NMOS transistor N1 are possible.

[0162] In some example configurations, the first NMOS gate voltage level, VgNT, which sets the gate-to-source voltage of the NMOS transistor N1 to a reduced level and the drain-to-source resistance RdsN to a high or increased level, is an intermediate voltage level between the maximum and minimum voltage levels. In certain example configurations, the first voltage level is greater than the associated threshold voltage, VtP, above the minimum voltage level and less than the maximum voltage level. In an example configuration using a non-triple-well NMOS transistor where the maximum voltage level is 8 V, the minimum voltage level is 0 V, and the threshold voltage, VtP, is 0.5 V, the first NMOS gate voltage level is 2 V.In another example configuration using a triple-well PMOS transistor with a maximum voltage of 9 V, a minimum voltage of 4.5 V, and a threshold voltage of 0.5 V, the first voltage level of the NMOS gate voltage is 2.25 V. This first voltage is an intermediate value between the maximum and minimum voltage levels. These voltage levels are only examples, and other voltage levels above a threshold voltage VtN, above the minimum voltage level, and below the maximum voltage level are possible.

[0163] If the NMOS transistor N1 is biased with the NMOS gate voltage VgNT at an intermediate voltage level between the maximum and minimum voltage levels, the NMOS transistor N1 can be considered partially switched on, since its conduction path between its source and drain terminals may lie between a maximum and a minimum conductance and / or resistance value, and some non-zero current may flow through the NMOS transistor N1.

[0164] In other example configurations, the first voltage level of the NMOS gate voltage VgNT can be the minimum voltage level that turns off the NMOS transistor N1, effectively making the NMOS transistor in the selected bit path 417 "floating". However, in at least some configurations, setting the first voltage level to the minimum voltage level that turns off the NMOS transistor N1 can cause the selected memory cell MC(s) to conduct too little cell current Icell after being turned on. This could cause the selected memory cell MC(s) to oscillate or switch between being on and off, which in turn could affect the lifetime of the selected memory cell MC(s).Conversely, it can be advantageous for the decoder controller 412 to generate the NMOS gate voltage VgNT at an intermediate voltage level, so that the NMOS transistor N1 is partially switched on, allowing the selected memory cell MC(s) to conduct at least a minimally high amount of cell current Icell to prevent the selected memory cell MC(s) from being switched off.

[0165] Additionally, in some example configurations, the second voltage level of the NMOS gate voltage VgNT, which increases the gate-to-source voltage and decreases the drain-to-source resistance RdsN, can be the maximum voltage level. This results in the gate-to-source voltage of the NMOS transistor N1 being at its maximum magnitude and the drain-to-source resistance RdsN between the drain and source terminals being at its minimum level. In other example configurations, the second level is lower than the maximum voltage level but still higher than the first voltage level, providing an increased gate-to-source voltage level and / or a decreased drain-to-source resistance level.

[0166] As with the one relating to Fig. In the PMOS transistor configuration described in Section 5, the second voltage level of the NMOS gate voltage VgNT can be the level of the NMOS gate voltage VgNT at the time a subsequent event associated with the selected memory cell MC(s) occurs or begins. In some example configurations, there can be multiple second voltage levels, since the second voltage level at which the NMOS gate voltage VgNT is when the read result capture event occurs may be different (e.g., lower) than the second voltage level at which the NMOS gate voltage VgNT is when the write operation begins. As an illustrative example, at the end of the initial power-on period, the decoder controller 412 can begin increasing the NMOS gate voltage VgNT from the first voltage level.When the read result acquisition event occurs, the decoder controller 412 can generate the NMOS gate voltage VgNT at a given voltage level higher than the first voltage level. The decoder controller 412 can further increase the level of the NMOS gate voltage VgNT so that, at a later time when the write period begins, the NMOS gate voltage VgNT is at a voltage level higher than both the first voltage level and the given voltage level at which the NMOS gate voltage VgNT was at the time of the read result acquisition event. In other configurations, the second voltage level can be a single voltage level reached at the time of the acquisition event, and the decoder controller 412 can be configured to maintain the NMOS gate voltage VgNT at the second voltage level from the time of the acquisition event for at least part of the write period.In both cases, the decoder controller 412 can be configured to begin increasing the NMOS gate voltage VgNT some time after the maximum of the peak fraction of the cell current Icell and before the occurrence of at least one subsequent event associated with the selected memory cell MC(s), so that until the subsequent event occurs, the NMOS transistor N1 has a gate-to-source voltage at a higher voltage level and a drain-to-source resistance at a lower resistance level than during the initial turn-on period when it conducted the current peak.

[0167] Additionally or alternatively, the 412 decoder controller can, at least for some example configurations, increase the NMOS gate voltage VgNT from the first voltage level to the second voltage level, so that until the subsequent event associated with the selected memory cell MC(s) occurs, the drain-to-source resistance RdsP experiences at least a minimal change (e.g., a minimal decrease) in resistance level. In some example configurations, the change in resistance level can be on the order of kiloohms (kΩ), e.g., at least 1 kΩ. In certain example configurations, the change in resistance level can be a decrease on the order of 4 kΩ or 5 kΩ, as non-limiting examples.

[0168] An example of a read operation to read data from the selected memory cell MC(s), followed by an example write operation to write data to the selected memory cell MC(s), will now be given with reference to the Fig. 4-7 described. Fig. Figure 7 shows a time or timing diagram of certain signals and voltages, which are generated using the exemplary reading circuit from Fig. 4 were generated during the exemplary read and write operations. The timing diagram further shows the cell current Icell as a function of time during the read and write operations. For the read operation portion of the timing diagram, the waveform of the cell current Icell can be an indication of the cell current Icell that the selected memory cell MC(s) can draw or receive when programmed in a state that causes the selected memory cell MC(s) to conduct the cell current Icell at an amplitude level greater than zero or greater than the leakage current when biased with the read voltage difference at the predetermined read voltage difference level.An example memory technology could be PCM or ReRAM or another similar two-terminal and / or resistance memory technology, where the memory element of the memory cell is programmed in a low-impedance state such that when the predetermined read voltage differential level exceeds the total or common threshold voltage of the memory element and the selected element, the selected memory cell MC(s) responds by first conducting a current spike or peak fraction 702 of the memory cell current Icell, which rises to a peak value and then decays to a relatively steady, non-zero value for the remaining duration of the read operation. For the write portion of the timing diagram, the waveform of the cell current Icell can indicate the cell current Icell that the selected memory cell MC(s) draws or discharges.can record when it is biased with a write voltage difference that causes the selected memory cell MC(s) to conduct the cell current Icell with a fast back edge, for example to program the selected memory cell MC(s) in a high-impedance state.

[0169] Furthermore, the information relating to Fig. 7 described exemplary read and write operations with the word line circuit with variable resistance 416, which is a PMOS transistor M1 from Fig. 5 is configured, and with the variable resistance bit line circuit 418, which is configured as an NMOS transistor N1 from Fig. 6 is configured, as described. Accordingly, it shows Fig. 7. The word line control signal CTRL_WL, which is applied to the variable-resistance word line circuit 416 as the PMOS gate voltage VgPT, and the bit line control signal CTRL_BL, which is applied to the variable-resistance bit line circuit 416 or 418 as the NMOS gate resistance voltage VgNT. Additionally, the PMOS and NMOS gate voltages VgPT and VgNT are described with reference to the PMOS and NMOS transistors M1 and N1 in a non-triple-well configuration, although similar voltage waveforms may be applicable to configurations with triple-well transistors.

[0170] Additionally, the exemplary read operation is described as being executed over four periods, including a bit line setting period, a word line setting period, a memory cell response period, and a read period. Other ways of dividing an exemplary read operation into periods are also possible. Furthermore, it is shown that the write operation following the read operation takes place during a write period that follows the read period of the read operation.

[0171] At the beginning of the read operation (before the start of the bit line setting period), the circuit for carrying out the read operation may be in a standby mode, and the bit line decoder 404 sets the bit lines involved in or associated with the read operation to a predetermined, unselected bit line level or bit line voltage level V. BLU,and the word line decoder 402 sets the word lines involved in or associated with the reading process to a predetermined, unselected word line level or voltage level V. WLU Furthermore, the decoder controller 412 can be used in the Fig. In the read operation shown in Figure 7, before the start of the bitline setting period, the decoder controller 412 first outputs the PMOS gate voltage VgPT at a minimum gate voltage level Vgmin, thereby fully turning on the PMOS transistor M1. With triple-well technology, the decoder controller 412 can alternatively output the PMOS gate voltage VgPT at a maximum voltage level Vgmax to turn off the PMOS transistor M1. This difference arises because the decoder controller 412 is configured to keep non-triple-well PMOS transistors on during standby mode, while it is configured to keep triple-well PMOS transistors off during standby mode. Additionally, before the start of the bitline setting period, the decoder controller 412 can first output the NMOS gate voltage at the maximum voltage level Vgmax to fully turn on the NMOS transistor N1.

[0172] During the bit line setting period, the bit line decoder 404 sets the selected bit line voltage V. BL_SEL the selected bit line to the predetermined selected bit line read voltage level V BL_RD or sets them initially. For this purpose, the bit line voltage generator 408 can set the selected bit line voltage V at the beginning or in an initial section of the bit line setting period. BL_SEL low to the selected bit line read voltage level V BL_RD drive by increasing the selected bit line voltage V BL_SEL from the unselected bit line level V BLU on the selected bit line read voltage level V BL_RD transitions. When the NMOS transistor N1 is fully switched on, the selected current path 416 can supply the selected bit line voltage V. BL_SEL with the selected bit line read voltage level V BL_RDto the selected bit line, which in turn can lead to the selected bit line having a voltage level of the selected bit line voltage V GBL_SEL from the unselected bit line level V BLU on the selected bit line read voltage level V BL_RD reduced accordingly.

[0173] The word line decoder 402 sets the selected word line voltage V during the word line setting period. WL_SEL the selected word line to the specified chosen word line reading voltage level V WL_RD For this purpose, the word line voltage generator 406 can set the globally selected word line voltage V at the beginning of the word line setting period. GWL_SEL from the unselected word line level V WLU on the selected word line reading voltage level V WL_RD Activate and begin increasing them. The selected word line path 414 can increase the selected word line voltage V. GWL_SELto the selected word line, which can lead to the selected word line voltage V WL_SEL from the unselected word line level V WLU on the selected word line reading voltage level V WL_RD increases. As in Fig. As shown in 7, the selected word line voltage V can be WL_SEL from the unselected word line level V WLU begin with a certain delay compared to the time at which the globally selected word line voltage V GWL_SEL from the unselected word line level V WLU begins to rise. The delay may be due to the selected word line voltage V. WL_SEL It only begins to rise when the globally selected word line voltage V WL_SEL or V GWL_SEL exhibits a threshold voltage level above the voltage level of the PMOS gate voltage VgPT. The delay with which the selected word line voltage V WL_SELThe process of how the rate of increase begins is described in more detail below. Furthermore, as described in Fig. 7 shown, the global selected word line voltage V GWL_SEL and the selected word line voltage V WL_SEL despite the delay, the selected word line reading voltage level V is reached at approximately the same time. WL_RD to reach or rise to this level, which marks the end of the word-lead setting period.

[0174] If the selected word line voltage V WL_SEL the selected word line reading voltage level V WL_RDOnce the target voltage is reached, the corresponding read voltage difference across the selected memory cell MC(s) can be at the predetermined read voltage difference level, thus initiating the response period of the memory cell. The memory cell response period is the time span during which the selected memory cell MC(s) behaves or responds in a specific way in response to the read voltage difference across the selected memory cell, which is at the predetermined read voltage difference level. In particular, if the selected memory cell MC(s) is programmed in a high-impedance state, then the read voltage difference at the predetermined read voltage difference level may be below the overall threshold voltage of the selected memory cell MC(s).In this case, the selected memory cell MC(s) can remain switched off at the beginning and / or during the memory cell response time, and no memory cell current Icell will flow through the selected memory cell MC(s). Alternatively, if the selected memory cell is programmed in a low-impedance state, the read voltage difference at the predetermined read voltage difference level can exceed the total threshold voltage of the selected memory cell MC(s). In this case, the selected memory cell MC(s) can switch on or trigger at the beginning of the memory cell response period. This latter case, where the selected memory cell is in a low-impedance state and switches on, is shown in the timing diagram. Fig. 7 shown.

[0175] If the selected memory cell MC(s) is programmed in the low-impedance state and turns on at the beginning of the memory cell response period, the selected memory cell can immediately or rapidly draw, absorb, or conduct a relatively large amount of memory cell current Icell. Otherwise, if the selected memory cell initially turns on or triggers, the selected memory cell conducts a current spike (or spike fraction) 702, which represents a current intensity over an instantaneous period during which the memory cell current Icell increases from zero or substantially zero to a current maximum. Upon reaching the maximum of the current spike 702, the amplitude of the memory cell current Icell through the selected memory cell MC(s) begins to decrease or fall during the memory cell response time until the magnitude of the memory cell current Icell reaches a relatively constant decreased value.The portion of the memory cell current Icell that exhibits a peak upon initial activation of the selected memory cell MC(s) can be referred to as a peak section 702 of the memory cell current Icell, and the portion of the memory cell current Icell that falls from a peak level of the peak section to the constant reduced level can be referred to as a decay section 704 of the memory cell current Icell. The peak and decay components 702 and 704 of the memory cell current Icell are described in more detail below.

[0176] Furthermore, as in Fig. Figure 4 shows that the reading circuit 410 is coupled with the globally selected word line node GWL_SEL and configured to display the globally selected word line voltage V. WL_SELto capture, recognize, and / or receive. At the end of the memory cell response period, the read operation can transition into the read period, during which the read circuit 410 can be configured to monitor the voltage level of the global selected word line voltage V. WL_SEL to capture or detect or otherwise measure the global selected word line voltage V WL_SELto use to identify a logical level of the data stored in the selected memory cell MC(s). In response to the identification, the read circuit 410 can be configured to output a read result signal SR indicating the logical level of the data stored in the selected memory cell MC(s). The read circuit 410 can be configured to output the read result signal SR to the read controller or word line path 414, or to another circuit component located on or off the memory die 104.

[0177] During the read period, the read circuit 410 can be configured to monitor the voltage level of the global selected word line voltage V. GWL_SELto compare with a trigger voltage level Vtrp to identify the logical level of the data stored in the selected memory cell MC(s). To determine the voltage level of the global selected word line voltage V GWL_SEL Compared to the trigger voltage level Vtrp, the read circuit 410 can be configured to react differently depending on whether the voltage level of the global selected word line voltage V GWL_SEL above or below the trip voltage level Vtrp. For example, if the global selected word line voltage V is above or below the trip voltage level during the read period. GWL_SEL If the trigger voltage level Vtrp is above the trigger voltage level, the read circuit 410 can be configured to maintain a level (e.g., a voltage level) of the read result signal SR at an initial (e.g., high) level. On the other hand, if the global selected word line voltage V GWL_SELIf the voltage is below the trigger voltage Vtrp, the read circuit 410 can be configured to lower the level of the read result signal SR from the first level to a second (low) level. The read result signal SR at the first (high) level can indicate a first logical level or value of the data stored in the selected memory cell MC(s), and the read result signal SR at the second (low) level can indicate a second logical level or value of the data stored in the selected memory cell MC(s) that differs from the first logical level.

[0178] Whether the voltage level of the global selected word line voltage V GWL_SELWhether the voltage at the beginning of the read period is above or below the trigger level can depend on whether the selected memory cell MC(s) remained switched on or off in response to the read voltage difference at the specified read voltage difference level at the beginning of the memory cell response period. If the selected memory cell MC(s) is programmed in the high-impedance state, it can remain switched off and, as a result, be prevented from drawing the memory cell current Icell. If the selected memory cell MC(s) remains switched off during the memory cell response period, the voltage level of the global selected word line voltage can remain at a relatively constant level or decrease by a relatively small amount, so that it is above the trigger level Vtrp at the beginning of the read period.

[0179] On the other hand, if the selected memory cell MC(s) is programmed in the low-impedance state, the selected memory cell MC(s) can turn on (or trigger) and, in response, pull the current memory cell I-cell, as described previously. When the selected memory cell MC(s) turns on, the amount of the memory cell current I-cell, which the selected memory cell MC(s) is configured to conduct, can cause a current to drop from the globally selected word line node GWL_SEL, which in turn can cause the voltage level of the globally selected word line voltage V to drop. GWL_SEL compared to when the selected memory cell MC(s) has not been activated, it decreases. Although the global selected word line voltage V GWL_SELDue to an effective capacity provided by the globally selected word line node GWL_SEL and the word line decoder 402, it may not decrease at nearly the same rate as the voltage level of the selected word line voltage V. WL_SEL as it drops, the global selected word line voltage V can GWL_SEL however, they should fall below the trigger voltage level Vtrp by the start of the reading period.

[0180] Fig. Figure 7 further shows a write operation performed during a write period following the read period. At the beginning of the write period, the word line voltage generator 406 can set the globally selected word line voltage V. GWL_SEL to a programmed word line voltage level V WL_PGincrease, and the selected memory cell MC(s) can begin to conduct the cell current Icell at an increased amount compared to the relatively steadily decreasing amount that the selected memory cell MC(s) conducted during the read period. For example, the relatively steadily decreasing amount that the selected memory cell MC(s) conducts during the read period may be in the range of about 30-40 microamperes (µA), and at the beginning of the write period, the amount of cell current Icell that the selected memory cell MC(s) conducts may be in the range of about 100-110 µA. Additionally, the word line and bit line voltage generators 406, 408 move or change in the Fig. In the example write operation shown in section 7, at the end of the write period, the globally selected word and bit line voltages V are applied. GWL_SEL , V GBL_SELThe voltage level quickly drops to approximately the same level, so that the voltage across the selected memory cell MC(s) is 0 V. This rapid movement or change in voltage levels causes the selected memory cell MC(s) to quickly cease conducting current, which is referred to as the fast fall-off of the memory cell current Icell. The selected memory cell MC(s), which conducts a fast fall-off of the memory cell current from approximately 100 µA to 0 µA, can program the selected memory cell MC(s) into the high-impedance state.

[0181] Referring back to the read operation, it is possible that the selected memory cell MC(s), if programmed in the low-impedance state, conducts a current spike 702 of the cell current Icell during initial power-up at the beginning of the memory cell response period, as described previously. The time marking the beginning of the memory cell response period can be called the power-on time and is in Fig. Figure 7 is represented as occurring at time t2. The current peak 702 can be considered instantaneous, and upon reaching a maximum, the cell current can begin to decrease towards a relatively constant lower level. The width of the current peak can be the time period required by the decay phase or section 704 to fall to a predetermined current level Ipdt.

[0182] In some example read operations, the NMOS gate voltage VgNT can initially be set to the maximum gate voltage level Vgmax at the beginning of the read operation and / or before the bit line setting period, and remain at the maximum gate voltage level Vgmax for the duration of the read operation. Similarly, the PMOS gate voltage VgPT can initially be set to the minimum gate voltage level Vgmin at the beginning of the read operation and / or before the bit line setting period, and remain at the minimum gate voltage level Vgmin for the duration of the read operation.

[0183] As previously described, the NMOS gate voltage VgNT at the maximum voltage level Vgmax can configure the NMOS transistor N1 to exhibit minimum resistance. Similarly, the PMOS gate voltage VgPT at the minimum voltage level Vgmin can configure the PMOS transistor M1 to exhibit minimum resistance. If the PMOS and NMOS transistors M1 and N1 are configured with their respective resistances set to minimum resistance levels when the selected memory cell MC(s) is turned on and current spike 702 is conducting, the current spike 702 may have a width large enough to increase the likelihood of causing a read error or a write error.

[0184] To reduce the probability, the decoder controller 412 can, after biasing the gate terminal of the NMOS transistor N1 with the NMOS gate voltage VgNT to the maximum gate voltage level Vgmax, set the selected bit line voltage V. BL_SEL on the selected bit line voltage level V BL_RD The NMOS spike control gate voltage level VgSCN can be reduced at time t1 before the switch-on time at time t2. This level can correspond to the first voltage level of the NMOS gate voltage VgNT, and thus to the gate-to-source voltage at a reduced level and the drain-to-source resistance RdsN at a high or increased resistance level, as previously described with reference to... Fig. 6 described. In some example configurations, the NMOS spike control gate voltage level VgSCN can be an intermediate voltage between the maximum gate voltage level Vgmax and the minimum gate voltage level Vgmin. In other example configurations, the NMOS spike control gate voltage level VgSCN is the minimum gate voltage level Vgmin that turns off NMOS transistor N1 and allows NMOS transistor N1 to float in the selected bit path 417.

[0185] Furthermore, at time t1 before the power-on time, the decoder controller 412 can increase the PMOS gate voltage VgPT from the minimum gate voltage Vgmax to a PMOS spike control gate voltage VgSCN. The PMOS spike control gate voltage VgSCN can correspond to the first voltage level of the PMOS gate voltage VgPT, and thus to the gate-to-source voltage at the reduced level and the drain-to-source resistance RdsP at the high or increased resistance level, as previously described with reference to Fig. 5 described. Furthermore, the PMOS spike control gate voltage VgSCN can be an intermediate voltage level between the maximum voltage level Vgmax and the minimum voltage level Vgmin.

[0186] The Decoder Controller 412 can be configured to maintain the PMOS gate voltage VgPT at the PMOS spike control gate voltage VgSCP and the NMOS gate voltage VgNT at the NMOS spike control gate voltage VgSCN during the word line setting period and up to an initial turn-on time period, which can be considered a sub-period of the memory cell response period. The initial turn-on period can begin at time t2 and end at a later time t3 when the memory cell current Icell decays to a threshold. In some configurations, the subsequent time t3 can be a predetermined time that the Decoder Controller 412 identifies as the end of the initial turn-on period, regardless of whether the cell current Icell actually decays to the threshold.

[0187] By setting the PMOS and NMOS gate voltages VgPT, VgNT to their respective PMOS and NMOS spike control gate voltage levels VgSCP, VgSCN, increased resistances can occur in the selected word line and bit line paths 414 and 417, respectively. This, in turn, can reduce the width of the current spike 702 compared to the case where the PMOS and NMOS gate voltages VgPT, VgNT maintain their gate voltages at the minimum and maximum gate voltage levels Vgmin, Vgmax, respectively. This, in turn, can decrease or minimize the probability that the current spike 702 causes a read error or a write error.

[0188] The timing diagram from Fig. Figure 7 shows the change of the PMOS and NMOS gate voltages VgPT, VgNT to their respective PMOS and NMOS spike control gate voltage levels VgSCP, VgSCN at the same time t1. In other example configurations, the PMOS and NMOS gate voltages VgPT, VgNT may change at different times. Regardless of whether the PMOS and NMOS gate voltages VgPT, VgNT change to their respective PMOS and NMOS spike control gate voltage levels VgSCP, VgSCN simultaneously or at different times, it can be advantageous for the gate voltages to change before the word line setting period begins and the globally selected word line voltage V is reached. GWL_SEL in the direction of the selected word line voltage level V read WL_RD increases so that the selected memory cell MC(s) does not switch on and conduct the current spike before the PMOS and NMOS transistors M1, N1 are set to their high resistance levels.

[0189] Although Fig. Figure 7 shows both the PMOS and NMOS gate voltages VgPT, VgNT, which switch to their respective PMOS and NMOS spike control gate voltage levels VgSCP, VgSCN; in other example configurations, only one of the gate voltages may change. In other example configurations, the decoder controller 412 can set the PMOS and NMOS gate voltages VgPT, VgNT such that the PMOS gate voltage VgPT switches to the PMOS spike control gate voltage level VgSCP before the power-on time, while the NMOS gate voltage VgNT remains at the maximum gate voltage level Vgmax, or the NMOS gate voltage VgNT can switch to the NMOS spike control gate voltage level VgSCN before the power-on time, while the PMOS gate voltage VgPT remains at the minimum gate voltage level Vgmin.

[0190] Furthermore, as previously described, the selected word line voltage V WL_SELa certain delay at the start of the rise of the set word line period compared to the unselected word line voltage level V WLU learn. In particular, the selected word line voltage V must be WL_SEL only begin to rise when the global selected word line voltage V GWL_SEL The PMOS gate voltage rises to a threshold voltage level above the PMOS gate voltage VgPT at the PMOS spike control gate voltage level VgSCP. Accordingly, the delay is greater the higher the PMOS spike control gate voltage level VgSCP is, and the longer the word line setting period and turn-on time. Consequently, setting the PMOS gate voltage VgPT to the PMOS spike control gate voltage level VgSCP can represent a trade-off by lengthening the word line setting period to generate a gate bias that reduces the width of the current spike 702.

[0191] In response to the end of the initial turn-on time at time t3, the decoder controller 412 can also be configured to increase the NMOS gate voltage VgNT from the NMOS spike control gate voltage level VgSCN back to the maximum gate voltage level Vgmax in order to reduce the drain-to-source resistance level RdsN of the NMOS transistor N1. Additionally, the decoder controller 412 can be configured to decrease the PMOS gate voltage VgPT from the PMOS spike control gate voltage level VgSCP back to the minimum gate voltage level Vgmin in order to reduce the drain-to-source resistance level RdsP of the PMOS transistor M1.

[0192] By changing the NMOS and PMOS gate voltages VgNT, VgPT, an event for capturing the read result can occur faster than if the NMOS and PMOS gate voltages remain at their respective spike control gate voltage levels VgSCN, VgSCP. Fig. Figure 7 shows the read result acquisition event at time t4, when the read result signal SR output by the read circuit 410 falls below the trigger voltage level Vtrp, and thus the voltage level drops. The read result acquisition event can mark the time at which a circuit, such as a read controller or the logic control circuit 154, Fig. 2B, can sample, record, or identify the voltage level of the read result signal SR in order to determine the logic level of the data stored in the selected memory cell MC(s). In the Fig. In the read operation shown in Figure 7, the NMOS gate voltage VgNT rises to the maximum gate voltage level Vgmax at a much faster rate than the rate at which the PMOS gate voltage VgPT decreases to the minimum gate voltage level Vgmin. The PMOS gate voltage VgPT can decrease at a desired rate, allowing the read result acquisition event to occur more quickly (e.g., the global selected word line voltage V). GWL_SEL (below the trigger voltage level Vtrp), as if the PMOS gate voltage VgPT remains at the PMOS spike control gate voltage level VgSCP, but does not decrease too rapidly in order to avoid an excessive amount of cell current Icell flowing through the selected memory cell MC(s) while the memory cell current Icell is still decreasing.

[0193] Additionally, as previously described, the selected memory cell MC(s) can conduct cell current during the write period at or around a specific current value greater than the value it conducts during the memory cell's respond and read periods. By increasing the NMOS gate voltage VgNT to the maximum gate voltage level Vgmax and decreasing the PMOS gate voltage VgPT to the minimum gate voltage level Vgmin at the beginning of the write period, the PMOS and NMOS transistors M1 and N1 can be configured with low resistance levels, which are better suited than high resistance levels for biasing the selected word lines and bit lines and allowing the specified current value to flow through the selected memory cell MC(s) during the write period.

[0194] Fig. Figure 8 is a circuit diagram of another example configuration of the word line circuit with variable resistance 416. Fig. 4. How to configure it in Fig. 5 is the word line circuit with variable resistance 416 implemented as a transistor circuit.

[0195] Instead of a single PMOS transistor configuration as in Fig. 5 contains the configuration in Fig. However, two PMOS transistors M1 and M2 are connected in parallel. The first PMOS transistor M1 is configured to receive a first PMOS gate voltage VgPT1 from the decoder controller 412, and the second PMOS transistor M2 is configured to receive a second PMOS gate voltage VgPT2 from the decoder controller 412. The first PMOS transistor M1 can be optimally dimensioned, e.g., by having an optimal gate width to minimize the width of the current spike 702, and the second PMOS transistor M2 can be optimally dimensioned, e.g., by having an optimal gate width, for write operations. Accordingly, the second PMOS transistor M2 can have a larger size, e.g., a larger gate width, than the first PMOS transistor. An effective gate-to-source voltage of the transistor circuit from Fig. 8 can contain a combination, e.g. a sum, of the gate-to-source voltages of the first and second PMOS transistors.

[0196] Fig. Figure 10 shows an example timing diagram of the gate voltages VgPT1, VgPT2 applied to the gate terminals of the first and second PMOS transistors M1, M2. The other voltage and current curves, which correspond to the timing diagram, are shown below. Fig. Seven things that are common to each other have been omitted for the sake of clarity. As in Fig. As shown in Figure 10, the PMOS gate voltage VgPT1 applied to the first PMOS transistor M1 is always maintained at the minimum gate voltage level Vgmin to keep the first PMOS transistor M1 fully switched on during read and write operations. However, at time t1 before the switch-on time, the decoder controller 412 can output the second PMOS gate voltage VgPT2 at the maximum gate voltage level Vgmax to switch off the second PMOS transistor M2, which is optimized for the events after the initial switch-on period. Setting the second PMOS gate voltage VgPT2 to the maximum gate voltage level Vgmax can result in a reduced effective gate-to-source voltage level for the transistor circuit and an increased effective or equivalent resistance level for both PMOS transistors M1 and M2.Subsequently, in response to the initial turn-on time, which ends at time t3, the decoder controller 412 can begin to reduce the second PMOS gate voltage VgPT2 back to the minimum gate voltage level Vgmin in order to turn on the second PMOS transistor M2, which in turn increases the effective gate-to-source voltage to a higher level and reduces the effective or equivalent resistance of the two PMOS transistors M1, M2.

[0197] Fig. Figure 9 is a circuit diagram of another example configuration of the bitline circuit with variable resistance 418. Fig. 4. How to configure it in Fig. In diagram 6, the bitline circuit with variable resistor 418 is configured as a transistor circuit. Instead of a single NMOS transistor configuration as in Fig. 6 contains the configuration in Fig. 9. However, two NMOS transistors N1 and N2 are connected in parallel. The first NMOS transistor N1 is configured to receive a first NMOS gate voltage VgNT1 from the decoder controller 412, and the second NMOS transistor N2 is configured to receive a second NMOS gate voltage VgNT2 from the decoder controller 412. The first NMOS transistor N1 can be optimally dimensioned, e.g., by having an optimal gate width to minimize the width of the current spike 702, and the second NMOS transistor N2 can be optimally dimensioned for write operations, e.g., by having an optimal gate width. Accordingly, the second NMOS transistor N2 can have a larger size, e.g., a larger gate width, than the first NMOS transistor N2. An effective gate-to-source voltage of the transistor circuit from Fig. 9 can contain a combination, e.g. a sum, of the gate-to-source voltages of the first and second NMOS transistors.

[0198] Referring back to Fig. 10. The NMOS gate voltage VgNT1 applied to the first NMOS transistor N1 is always held at the maximum gate voltage level Vgmax to keep the first NMOS transistor N1 fully switched on during read and write operations. However, at time t1 before the switch-on time, the decoder controller 412 can output the second NMOS gate voltage VgNT2 at the minimum gate voltage level Vgmin to switch off the second NMOS transistor N2, which is optimized for the events after the initial switch-on period. Setting the second NMOS gate voltage VgNT2 to the minimum gate voltage level Vgmin can result in a reduced effective gate-to-source voltage level of the transistor circuit and an increased effective resistance level of the two NMOS transistors N1 and N2.Subsequently, in response to the initial turn-on time period, which ends at time t3, the decoder controller 412 can begin to increase the second NMOS gate voltage VgNT2 back to the maximum gate voltage level Vgmax in order to turn on the second NMOS transistor N2, which in turn increases the effective gate-to-source voltage to a higher level and reduces the effective or equivalent resistance of the two NMOS transistors N1, N2.

[0199] A means for supplying a voltage for biasing a memory cell during a read operation for reading data from the memory cell can, in various embodiments, select the word line path 414, which provides the global selected word line voltage V. GWL_SEL to the selected word line, or the selected bit line path 417, which supplies the global selected bit line voltage V GBL_SELto the selected bit line, or similar. Other embodiments may include similar or equivalent means for supplying a voltage to bias a memory cell.

[0200] A means for setting a resistance to a high resistance level can, in various embodiments, be the individual PMOS transistor M1 ( Fig. 5), two PMOS transistors M1, M2 connected in parallel ( Fig. 8), the single NMOS transistor N1 ( Fig. 6) or two NMOS transistors N1, N2 connected in parallel ( Fig. 9), the decoder controller 412 or similar, other logic hardware and / or executable code stored on a computer-readable medium. Other embodiments may include similar or equivalent means for adjusting a resistor to a high resistance level.

[0201] A means of changing a resistance to a low resistance level can, in various embodiments, be the individual PMOS transistor M1 ( Fig. 5), two PMOS transistors M1, M2 connected in parallel ( Fig. 8), the single NMOS transistor N1 ( Fig. 6) or two NMOS transistors N1, N2 connected in parallel ( Fig. 9), the decoder controller 412 or similar, other logic hardware and / or executable code stored on a computer-readable medium. Other embodiments may include similar or equivalent means for adjusting a resistor to a high resistance level.

[0202] The foregoing detailed description is intended to illustrate selected forms that the invention can take, and not to define the invention. Only the following claims, including all equivalent embodiments, are intended to define the scope of the claimed invention. Finally, it should be noted that each aspect of each of the preferred embodiments described herein may be used alone or in combination with one or more others.

Claims

[1] Circuit, comprising: a memory field or array (104, 400) comprising a plurality of memory cells; a path (414, 417) configured to supply a voltage for biasing one memory cell (MC) of the plurality of memory cells, wherein the path comprises: a variable resistance circuit (416) configured to: before switching on the memory cell (MC), an associated resistor is set to a high resistance level; and in response to an end time of an initial power-on period, to adjust the associated resistance from a high resistance level to a low resistance level, wherein the initial power-on period extends from a power-on time (t2) to the end time (t3) that precedes a read result acquisition event of the read operation. [2] Circuit according to claim 1, wherein the circuit with variable resistance (416) comprises a transistor (M1, N1) configured to to receive an input voltage; and in response to receiving the input voltage, the associated resistor should be adjusted to the high resistance level. [3] Circuit according to claim 2, wherein the transistor (M1, N1) is configured to adjust the associated resistance from the high resistance level to the low resistance level in response to a change in the voltage level of the input voltage. [4] Circuit according to claim 2, wherein the transistor (M1, N1) is configured to adjust the associated resistance to the high resistance level in response to the reception of the input voltage at an intermediate voltage level. [5] Circuit according to claim 2, wherein the transistor (M1, N1) is configured to adjust the associated resistance to the high resistance level in response to receiving the input voltage at a minimum voltage level. [6] Circuit according to claim 2, further comprising a word line decoder (402) comprising the transistor. [7] Circuit according to claim 2, further comprising a bit line decoder (404) comprising the transistor. [8] Circuit according to claim 1, wherein the path (414, 417) comprises a first path, the voltage comprises a first voltage, the variable resistance circuit comprises a first variable resistance circuit, the associated resistance comprises a first associated resistance, the high resistance level comprises a first high resistance level, the low resistance level comprises a first low resistance level, and wherein the circuit further comprises: a second path configured to supply a second voltage for biasing the memory cell, wherein the second path comprises: a second circuit with variable resistance, configured to to set a second associated resistor to a second high resistance level before the memory cell is switched on; and In response to the end time of the first on-time period, the second associated resistance is adjusted from the second high resistance level to a second low resistance level. [9] Circuit according to claim 1, wherein the circuit with variable resistance is configured to set the associated resistance to the high resistance level before a word line selection period of a read operation to read data from the memory cell. [10] Circuit according to claim 1, wherein the variable resistance circuit comprises a pair of transistors (M1, M2; N1, N2) connected in parallel, wherein one of the transistors of the pair is configured to turn off in order to adjust the associated resistance to the high resistance level, and wherein both transistors of the pair are configured to turn on in order to adjust the associated resistance from the high resistance level to the low resistance level. [11] Circuit, comprising: a memory field or array (104, 400) comprising a plurality of memory cells; a voltage generator (406, 408) configured to generate a voltage during a read operation to read data from one memory cell (MC) of the plurality of memory cells; a transistor circuit (416, 418) configured to to receive the tension; and to forward the voltage to a bias line coupled to the memory cell (MC); a bias circuit configured to to bias the transistor circuit according to an initial bias setting during a bias line setting period before a switch-on time at which the memory cell conducts a spike or peak component of a memory cell current; and to switch to biasing the transistor circuit according to a second bias setting temporally after the peak component and before a read result acquisition time of the read operation, wherein at the read result acquisition time a read circuit (410) generates and / or outputs a read result signal that indicates the logical level of the data stored in the selected memory cell. [12] Circuit according to claim 11, wherein the transistor circuit comprises a p-channel metal oxide semiconductor field-effect transistor, PMOS transistor,(M1, M2), and wherein the bias circuit is configured to switch to the bias voltage of the PMOS transistor according to the second bias setting by lowering a gate voltage applied to the PMOS transistor from a first voltage level to a second voltage level. [13] Circuit according to claim 12, wherein the first voltage level comprises an intermediate voltage level. [14] Circuit according to claim 12, wherein the PMOS transistor comprises one of a plurality of transistors of a word line decoder. [15] Circuit according to claim 11, wherein the transistor circuit comprises an n-channel metal oxide semiconductor field-effect transistor, NMOS transistor (N1, N2), and wherein the bias circuit is configured to bias the NMOS transistor according to the second bias setting by increasing a gate voltage applied to the NMOS transistor from a first voltage level to a second voltage level. [16] Circuit according to claim 15, wherein the NMOS transistor comprises one of a plurality of transistors of a word line decoder. [17] System encompassing: a memory field or array (104, 400) comprising a plurality of memory cells; a word line coupled to a memory cell (MC) of the plurality of memory cells, wherein the memory cell is configured to conduct a peak fraction of a memory cell current when the memory cell turns on during the read operation; a bit line coupled to the memory cell; a word line decoder configured to set a word line voltage on the word line; a bitline decoder (404) configured to set a bitline voltage on the bitline; and a decoder controller (412) that is configured to prior to the occurrence of the peak component (702), to set a first effective gate-to-source voltage of a first transistor circuit in the word line decoder and a second effective gate-to-source voltage of a second transistor circuit in the bit line decoder to reduced voltage levels, the reduced voltage levels being configured to reduce a width of the peak component; and After the occurrence of a peak fraction maximum, the first effective gate-to-source voltage and the second effective gate-to-source voltage are increased from their respective reduced voltage levels to their respective increased voltage levels configured for a subsequent event associated with the memory cell, wherein the subsequent event is a read result acquisition event in which a read circuit (410) generates and / or outputs a read result signal indicating the logical level of the data stored in the selected memory cell. [18] System according to claim 17, wherein the decoder controller (412) is configured to increase a gate voltage in order to increase the second effective gate-to-source voltage of the second transistor circuit. [19] System according to claim 17, wherein the decoder controller (412) is configured to decrease a gate voltage in order to increase the first effective gate-to-source voltage of the first transistor circuit. [20] System according to claim 17, wherein the respective reduced voltage levels correspond to a corresponding intermediate voltage level. [21] Procedures, including: Supplying a voltage to a bias line coupled to a storage cell via a path; Pre-biasing a transistor of the path with a gate voltage to a first gate voltage level before switching on the memory cell with a decoder controller; and Pre-biasing the transistor with the gate voltage to a second gate voltage level increasing the gate-to-source voltage of the transistor, by means of the decoder controller in response to the detection of an end time of a first turn-on time span extending from a turn-on time (t2) to the end time (t3) preceding a read result acquisition event of the read operation.

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