Method and apparatus for offset correction in SAR-ADC with DAC with reduced capacitor array

Abstract

A method for offset correction in a successive approximation register (SAR) analog-to-digital converter (ADC) using a reduced-capacitor array digital-to-analog converter (DAC); the method comprises the following steps: coupling the positive and negative inputs (Vinp; Vinn) of a SAR ADC; determining a digital representation of an offset voltage of the SAR ADC; storing the digital representation of the offset voltage in an offset register; configuring the reduced-capacitor array DAC, which has a plurality of offset correction capacitors (202; 504), with the stored digital representation of the offset voltage to provide an offset correction voltage; decoupling the positive and negative inputs (Vinp; Vinn) of the SAR ADC; coupling a differential voltage to the positive and negative inputs (Vinp; Vinn) of the SAR ADC;and performing a SAR conversion of the differential voltage while coupling with the offset correction voltage from the reduced capacitor array DAC, wherein the plurality of offset correction capacitors (202; 504) comprises N positive offset correction capacitors (202p; 504p) with coupled top plates forming a node Vx and N negative offset correction capacitors (202n; 504n) with coupled top plates forming a node Vy, where N is the number of offset voltage correction bits of the reduced capacitor array DAC, and wherein the method further comprises: selectively coupling bottom plates of the N positive offset correction capacitors (202p; 504p) and the N negative offset correction capacitors (202n; 504n) to a common-mode voltage Vcm, a scaled positive reference voltage Vrefp / 2m or a scaled negative reference voltage Vrefn / 2m, where m is a positive integer.;

Description

RELATED PATENT APPLICATION

[0001] This application claims precedence over serial number 62 / 578,608 of the jointly owned preliminary US patent application; filed on October 30, 2017; entitled “Method for Offset Correction in SAR ADC with Reduced Capacitor Array DAC” by Anders Vinje and Ivar L⌀kken; and is hereby incorporated herein by reference for all purposes. TECHNICAL AREA OF INVENTION

[0002] The present disclosure relates to analog-to-digital converters (ADCs) and in particular to offset correction in successive approximation register (SAR) ADCs with reduced capacitor array digital-to-analog conversion (DAC). BACKGROUND OF THE INVENTION

[0003] A SAR analog-to-digital converter (ADC) is a type of analog-to-digital converter that converts a continuous analog waveform into discrete digital representations by performing a binary search to converge on the nearest quantization level of each sampled value of the analog waveform, which then provides a digital representation of that value. SAR ADCs are among the most popular ADC architectures and can be used, for example, in microcontrollers.

[0004] An ADC is generally expected to perform offset-free measurements. Offset calibration methods include digital offset correction in post-processing, analog offset correction using an offset compensation comparator, and hybrid digital / analog offset correction using a dedicated compensation digital-to-analog converter (DAC). Digital correction is the simplest but has a fundamental limitation: it restricts the ADC's signal range. Analog correction using an offset-compensated comparator or hybrid correction using a dedicated correction DAC is therefore widely used but significantly increases circuit complexity.

[0005] Some offset calibration solutions include digital offset correction during post-processing, analog offset correction using an offset compensation comparator, and hybrid digital / analog offset correction using a dedicated compensation DAC. Digital correction can be simple, but it has a fundamental limitation: it restricts the signal range of the ADC. Analog correction using an offset-compensated comparator or hybrid correction using a dedicated correction DAC can be used, but these approaches can significantly increase circuit complexity.

[0006] Fig. Figure 1 shows three state-of-the-art methods for performing an offset correction. Fig. Figure 1(a) shows a circuit for digital offset correction. Digital offset correction during post-processing of the output data is the simplest method, but it limits the range of the ADC because it shifts the entire ADC transfer function and thus changes its saturation limits. This can involve measuring the offset and digitally compensating for it during post-processing.

[0007] Fig. Figure 1(b) shows a circuit for analog offset correction. A fully analog offset correction using an offset-compensated comparator avoids the problem of the digital offset correction method mentioned above and is commonly used, for example, in the SAR ADC for a microcontroller. Analog correction does not restrict the operating range of the ADC. This can be achieved with additional clock cycles running in the background. However, this significantly increases the complexity of the comparator and often considerably increases its area for integrated circuits.

[0008] Fig. Figure 1(c) shows a circuit for hybrid analog / digital offset correction. This method uses hybrid (analog / digital) correction with a separate correction DAC, allowing the offset to be subtracted after measurement and storage. This also does not limit the operating range of the ADC, but increases complexity due to the need for a dedicated correction DAC. The hybrid correction can involve measuring the offset and compensating it in the analog domain using the correction DAC. SUMMARY

[0009] Therefore, a hybrid analog / digital correction method and a device for SAR-ADCs are needed that utilize a capacitor-reduced DAC topology to provide offset correction without requiring a dedicated compensation DAC.

[0010] According to one embodiment, a method for offset correction of a successive approximation register (SAR) analog-to-digital converter (ADC) using a reduced-capacitor array digital-to-analog converter (DAC) may comprise the following steps: coupling the positive and negative inputs of a SAR ADC; determining a digital representation of an offset voltage of the SAR DAC; storing the digital representation of the offset voltage in an offset register; configuring a reduced-capacitor array DAC, which may include a plurality of offset correction capacitors, with the stored digital representation of the input offset voltage to provide an offset correction voltage; decoupling the positive and negative inputs of the SAR ADC; coupling a differential voltage to the positive and negative inputs of the SAR ADC.and performing a SAR conversion of the differential voltage during coupling with the offset correction voltage from the reduced capacitor array DAC.

[0011] According to another embodiment of the method, the plurality of offset correction capacitors can be coupled to a plurality of reference voltages selected by the digital representation of the offset voltage stored in the offset register. According to another embodiment of the method, the plurality of reference voltages in the voltage range from Vrefp to Vrefn can be binary weighted. According to another embodiment of the method, a common-mode voltage Vcm can be approximately equal to (Vrefp + Vrefn) / 2. According to another embodiment of the method, the plurality of reference voltages can be provided from a series of resistor voltage dividers coupled between Vrefp and Vrefn.According to another embodiment of the method, the plurality of offset correction capacitors can comprise N positive offset correction capacitors having coupled upper plates forming a node Vx, and N negative offset correction capacitors having coupled upper plates forming a node Vy, where N can be the number of offset voltage correction bits of the reduced capacitor array DAC.

[0012] According to another embodiment of the method, N can be five (5) and can further comprise the following steps: coupling a lower plate of a first positive offset correction capacitor selectively to Vcm, Vrefp / 2 or Vrefn / 2; coupling a lower plate of a first negative offset correction capacitor selectively to Vcm, Vrefn / 2 or Vrefp / 2; coupling a lower plate of a second positive offset correction capacitor selectively to Vcm, Vrefp / 4 or Vrefn / 4; coupling a lower plate of a second negative offset correction capacitor selectively to Vcm, Vrefn / 4 or Vrefp / 4; coupling a lower plate of a third positive offset correction capacitor selectively to Vcm, Vrefp / 8 or Vrefn / 8; Coupling of a lower plate of a third negative offset correction capacitor optionally with Vcm, Vrefn / 8 or Vrefp / 8; coupling of a lower plate of a fourth positive offset correction capacitor optionally with Vcm, Vrefp / 16 or Vrefn / 16;Coupling a lower plate of a fourth negative offset correction capacitor optionally to Vcm, Vrefn / 16 or Vrefp / 16; coupling a lower plate of a fifth positive offset correction capacitor optionally to Vcm, Vrefp / 32 or Vrefn / 32; and coupling a lower plate of a fifth negative offset correction capacitor optionally to Vcm, Vrefn / 32 or Vrefp / 32, thereby generating the offset compensation voltage.

[0013] According to another embodiment of the method, N can be six (6) and can further comprise the following steps: coupling an upper plate of a sixth positive offset correction capacitor to node Vx; coupling an upper plate of a sixth negative offset correction capacitor to node Vy; coupling a lower plate of the sixth positive offset correction capacitor optionally to Vcm, Vrefp or Vrefn; and coupling a lower plate of the sixth negative offset correction capacitor optionally to Vcm, Vrefn or Vrefp, thereby doubling the voltage offset correction range.

[0014] According to a further embodiment of the method, it may include the step of coupling the lower plates of the positive and negative offset correction capacitors to the common-mode voltage Vcm during a sampling phase of the SAR-ADC. According to a further embodiment of the method, it may include the step of disabling the offset compensation voltage. According to a further embodiment of the method, it may include the step of performing an offset correction at startup. According to a further embodiment of the method, it may include the step of periodically performing an offset correction. According to a further embodiment of the method, the SAR-ADC may be a differential-input SAR-ADC.

[0015] According to another embodiment, a method for correcting an offset voltage in an analog-to-digital converter (ADC) may comprise the following steps: coupling inputs of an ADC to generate an offset voltage; converting the offset voltage into a digital representation thereof; storing the digital representation of the offset voltage in an offset register; deriving an offset compensation voltage from the stored digital representation of the offset voltage in the offset register; receiving an analog input voltage; correcting the offset voltage by scaling the voltage of a least significant bit; and converting the analog input voltage into a digital output value. According to a further embodiment, the SAR ADC may be a differential input SAR ADC.

[0016] According to yet another embodiment, an analog-to-digital converter (ADC) can include a circuit configured to: couple inputs of an ADC to generate an offset voltage; convert the offset voltage into a digital representation thereof; store the digital representation of the offset voltage in an offset register; derive an offset compensation voltage from the stored digital representation of the offset voltage in the offset register; receive an analog voltage; convert the analog voltage into a digital value; and clean up the offset voltage by scaling reference voltages to a digital-to-analog converter (DAC) with a reduced capacitor array, which is assigned to a least significant bit of the ADC. According to yet another embodiment, the ADC can be part of an integrated microcontroller circuit.

[0017] According to yet another embodiment, an offset correction device in a successive approximation register (SAR) analog-to-digital converter (ADC) using a reduced capacitor array digital-to-analog converter (DAC) may comprise: a SAR ADC having: inputs for a positive voltage Vinp and a negative voltage Vinn, a positive reference voltage Vrefp and a negative reference voltage Vrefn, and a common-mode voltage Vcm; a first plurality of binary weighted capacitors with top plates coupled to form a node Vx; a second plurality of binary weighted capacitors with top plates coupled to form a node Vy; a plurality of first switches suitable for selectively coupling the bottom plates of the first plurality of binary weighted capacitors to the voltages Vrefp, Vrefn, Vcm, and Vinp;a plurality of second switches suitable for selectively coupling the lower plates of the second plurality of binary-weighted capacitors to the voltages Vrefp, Vrefn, Vcm and Vinn; a reduced capacitor array DAC comprising: N positive offset correction capacitors with top plates coupled to node Vx, N negative offset correction capacitors with top plates coupled to node Vy, a plurality of third switches suitable for selectively coupling the lower plates of the N positive offset correction capacitors to Vcm and a plurality of scaled voltage references Vrefp / 2; m and Vrefn / 2 m are adapted, where m can be a positive integer; and a plurality of fourth switches for selectively coupling lower plates of the N negative offset correction capacitors with Vcm and the plurality of scaled voltage references Vrefn / 2 m and Vrefp / 2 mare suitable, where m can be a positive integer.

[0018] According to another embodiment, N can be five (5) and the embodiment includes: the lower plate of a first positive offset correction capacitor can optionally be coupled to Vcm, Vrefp / 2 or Vrefn / 2; the lower plate of a first negative offset correction capacitor can optionally be coupled to Vcm, Vrefn / 2 or Vrefp / 2; the lower plate of a second positive offset correction capacitor can optionally be coupled to Vcm, Vrefp / 4 or Vrefn / 4; the lower plate of a second negative offset correction capacitor can optionally be coupled to Vcm, Vrefn / 4 or Vrefp / 4; the lower plate of a third positive offset correction capacitor can optionally be coupled to Vcm, Vrefp / 8 or Vrefn / 8; The lower plate of a third negative offset correction capacitor can optionally be coupled to Vcm, Vrefn / 8 or Vrefp / 8;The lower plate of a fourth positive offset correction capacitor can optionally be coupled to Vcm, Vrefp / 16 or Vrefn / 16; the lower plate of a fourth negative offset correction capacitor can optionally be coupled to Vcm, Vrefn / 16 or Vrefp / 16; the lower plate of a fifth positive offset correction capacitor can optionally be coupled to Vcm, Vrefp / 32 or Vrefn / 32; and the lower plate of a fifth negative offset correction capacitor can optionally be coupled to Vcm, Vrefn / 32 or Vrefp / 32, thereby generating the offset compensation voltage.

[0019] According to another embodiment, N can be six (6), and the embodiment can additionally include: the upper plate of a sixth positive offset correction capacitor can be coupled to node Vx; the upper plate of a sixth negative offset correction capacitor can be coupled to node Vy; the lower plate of the sixth positive offset correction capacitor can optionally be coupled to Vcm, Vrefp, or Vrefn; and the lower plate of the sixth negative offset correction capacitor can optionally be coupled to Vcm, Vrefn, or Vrefp; thereby doubling the voltage offset correction range. According to another embodiment of the method, the SAR ADC can be a differential input SAR ADC. List of characters

[0020] A more complete understanding of the present disclosure can be obtained by referring to the following description in conjunction with the accompanying drawings, wherein: Fig. 1 schematic diagrams of three state-of-the-art methods for carrying out offset correction are illustrated; Fig. 2 a schematic diagram of a DAC with a reduced capacitor array according to embodiments of the present disclosure illustrates; Fig. 2A illustrates a schematic diagram of a resistance voltage divider to provide reference voltages for the Fig. to scale the DAC shown in 2 with a reduced capacitor array according to embodiments of the present disclosure; Fig. 3 a schematic diagram of the in Fig. Figure 2 illustrates the capacitor-reduced DAC when used during sampling as a sample-and-hold (S / H) and offset correction DAC according to specific exemplary embodiments of this disclosure; Fig. 4 A schematic diagram of a switching control logic for coupling offset correction capacitors to inputs and reference voltages according to specific exemplary embodiments of this disclosure is illustrated; Fig. 5 a schematic diagram of a circuit for doubling the offset correction range according to specific exemplary embodiments of this disclosure is illustrated; and Fig. Figure 6 illustrates a schematic flowchart for the operation of an ADC with hybrid offset calibration according to specific exemplary embodiments of this disclosure.

[0021] While the present disclosure is open to various modifications and alternative forms, specific exemplary embodiments thereof have been shown in the drawings and are described in detail here. It is understood, however, that the description of specific exemplary embodiments herein is not intended to limit the disclosure to the forms disclosed herein. DETAILED DESCRIPTION

[0022] Embodiments of the present disclosure include a hybrid analog / digital correction that utilizes a capacitor-reduced DAC topology to enable offset correction without requiring a dedicated compensation DAC. Embodiments of the present disclosure may employ a DAC topology referred to as a capacitor-reduced DAC. Some ADCs are not calibrated because they only handle relative measurements and offsets, and absolute gain is not important. Embodiments of the present disclosure may adapt the topology architecture for general microcontroller use. Accordingly, embodiments of the present disclosure may include the option to calibrate the ADC's offset and gain, or not.According to embodiments of the present disclosure, the proposed solution provides a hybrid digital / analog offset correction without limiting the working range of the ADC and eliminates the need for a separate correction DAC.

[0023] The capacitor-reduced DAC topology circuit disclosed and claimed herein can be easily implemented in an integrated circuit device, such as, but not limited to, a mixed-signal microcontroller (both analog and digital circuits).

[0024] With reference to the drawings, the details of exemplary embodiments are schematically illustrated. Identical elements in the drawings are represented by the same numbers, and similar elements are represented by the same numbers with a different lowercase suffix.

[0025] With reference to Fig. Figure 2 illustrates a schematic diagram of a reduced-capacitor array DAC according to embodiments of the present disclosure. ADCs used with a reduced-capacitor array DAC can be more efficient than a split-capacitor array. The reduced-capacitor array for a 12-bit Vcm-based differential-input SAR ADC is shown in Fig. Figure 2 shows a charge redistribution ADC with a capacitive DAC. Instead of scaling the lower bits using dedicated scaling capacitors, they are scaled by dividing the reference voltage and using the scaled reference voltages ( Fig. 2A) scales to generate a charge relationship of Q = C * · V, which is equivalent to charge redistribution operation. By scaling V instead of C, unit capacitors can be used, which are relatively large yet achieve a small overall capacitance. This is advantageous for the area, power consumption, and load that the capacitor array presents for the input signal and reference voltage buffer.

[0026] To maintain a correct transfer function for the ADC, where the MSB should represent half of the total signal range, the input in the Fig. The two DACs shown are sampled with only twice the capacitance of the MSB, or 64. Co. The remaining five capacitors, which operate with scaled references, have both sides connected to Vcm during sampling, meaning they are free of charge.

[0027] In Fig. Figure 2 shows that in the sampling phase, the input is sampled at 64Co (all sampling capacitors are coupled together: 32Co + 16Co + 8Co + 4Co + 2Co + Co + Co), while the capacitors for the five lowest bits are connected to Vcm, thus leaving them uncharged. When the ADC transitions from the sampling phase to the MSB decision phase, the input sampling capacitors are switched to Vcm, shifting the input voltages to nodes Vx and Vy through charge redistribution. The ADC then makes the MSB decision depending on whether Vx > Vy or Vx > Vy. <Vy. Die 32 . Co-Kondensatoren werden dann abhängig von der MSB-Entscheidung auf Vrefp / Vrefn oder Vrefn / Vrefp geschaltet, und dann werden Vx und Vy erneut ausgewertet, um die Entscheidung MSB-1 zu erhalten. Dieser Prozess wird fortgesetzt, bis die sukzessive Approximation der Analog-Digital-Wandlung abgeschlossen ist und alle Bits konvertiert sind.

[0028] However, since the capacitors for the five lower bits are not used during sampling, it is possible to use them to perform a five-bit offset correction. If these capacitors are held at their split Vrefp voltages on the Vx side and at split Vrefn voltages on the Vy side, the difference between Vx and Vy is shifted upwards by 32 LSBs. And if they are switched in the opposite direction, the difference between Vx and Vy is shifted downwards by 32 LSBs. This means that if the switching of these five capacitors is controlled during the sampling phase, we get a free 5-bit offset correction DAC with a resolution of ±1 LSB. This means that we only need one 5-bit offset memory register to control these five bits during sampling to obtain a 5-bit offset correction, as shown in Fig. 3. Conceptually shown. With correct measurement, the offset can thus be reduced to ± 1 LSB.

[0029] During the sampling phase, the LSB section of the DAC can be connected to reference voltages instead of Vcm to shift the transfer function. Connecting a unit element pair to the positive / negative reference shifts the transfer function up by one LSB, and conversely, connecting it to the negative / positive reference shifts it down by one LSB. The offset can be measured and then stored in a register used to control the LSB section during sampling. The capacitor pairs are connected to either the positive / negative or negative / positive reference depending on the result stored in the offset storage register. Thus, the LSB section can function as a compensation DAC without adding any analog circuitry. The switching control logic and the offset storage register are the only additional circuitry required.

[0030] With reference to Fig. 3 is a schematic diagram of the in Fig. The capacitor-reduced DAC shown in Figure 2 is illustrated when used as a sample-and-hold (S / H) and offset-correction DAC during sampling, according to specific exemplary embodiments of this disclosure. The capacitors 202 , which feature the offset compensation ADC, can be used with either positively or negatively scaled reference voltages, depending on the required offset compensation direction ( Fig. 2A) be coupled.

[0031] With reference to Fig. Figure 4 shows a schematic diagram of a switching control logic for coupling offset correction capacitors to inputs and reference voltages according to specific exemplary embodiments of this disclosure. This can be an implementation of the switching control for the offset correction DAC. Here, the input signal `offscorr` is used to turn the offset correction on or off. When the offset correction is off (`offscorr` = 0), the control is as usual (in a capacitor-reduced DAC without any offset correction), with the capacitors connected to Vcm during both the sampling phase (`samp` = 1`) and the Vcm phase (`scm` = 1), and the capacitors being switched to Vrefp / Vrefn or Vrefn / Vrefp during the bit decision phase, depending on the result of the previous decision (`sref` high or low).When offset correction is enabled (offscorr = 1), the capacitors are connected to Vrefp / Vrefn or Vrefn / Vrefp instead of Vcm when samp = 1, depending on the value of reg(i), which is the i-th bit of the offset memory register. This means that with five such switches and a 5-bit offset memory register, the values ​​in... Fig. The control shown in Figure 3 can be implemented. The additional cost compared to a switching control logic without offset correction is three 2:1 multiplexers, one AND gate, and one inverter per bit calibration. Additionally, a 5-bit register can be used to store the offset bit control configuration. According to the teachings of this revelation, no additional analog hardware is required.

[0032] With reference to Fig. Figure 5 shows a schematic diagram of a circuit for doubling the offset correction range according to specific exemplary embodiments of this disclosure. The offset correction range can be doubled by adding an additional capacitor element on each side, e.g., Co 504p and Co 504n It is also possible, and considered here, to extend the offset calibration range in analog hardware at very low cost. Since the part of the DAC used for offset correction employs scaled references, only one additional capacitor element needs to be connected to the full reference voltage Vref to double the offset correction range. Adding two cocapacitors connected to the full references Vrefp and Vrefn thus provides another bit of calibration. Extending the offset correction range from ±32 LSBs to ±64 LSBs is described in [reference to be added]. Fig. Figure 5 is shown. The resolution remains ± 1 LSB, which represents the basic resolution of this correction scheme.

[0033] With reference to Fig. Figure 6 shows a schematic flowchart for the operation of an ADC with hybrid offset calibration according to specific exemplary embodiments of this disclosure. As with digital calibration or a conventional hybrid calibration scheme, an ADC conversion is required to measure the offset and store it in the offset memory register. This means that the ADC must be taken offline for a conversion period to perform an offset measurement. Typically, the offset is measured at startup, and if an offset adjustment is needed at that time, it is performed then. Updated offset measurements and offset adjustments to compensate for circuit drift, such as temperature variations, can be performed at predetermined intervals. If no offset calibration is required, the functionality can simply be disabled.An offset measurement is typically performed by shorting the ADC inputs, and a dedicated offset calibration signal can be used to ensure that the result is loaded into the offset measurement register. The offset measurement register can then be used to control the DAC switches. Fig. 4) to control when normal SAR analog-to-digital conversions are subsequently performed.

[0034] The offset calibration process begins with step 610 . At system startup or at regular intervals, e.g. to compensate for component temperature drift, in step 612 An offset calibration bit level must be determined. If the calibration bit is not set to "Offset Calibration", then in step 624 A normal ADC conversion was performed. After each ADC conversion in step 624 It is checked whether in step 626Offset calibration has been activated. If the calibration bit is not set to "Offset calibration", then in step 624 Another ADC conversion was performed.

[0035] However, if in step 612 or 626 If it is determined that the calibration bit is set to "offset calibration", the following occurs in step 614 An offset measurement was performed with the ADC inputs short-circuited. In step 616 The result of the offset measurement is stored in an offset storage register. In step 618 Regular SAR-ADC conversions are performed using the offset calibration DAC capacitors, which are coupled to the corresponding selected reference voltages (from the offset storage register). In step 620 The offset calibration bit level is checked. If offset calibration has been disabled, then return to step 624If the offset calibration bit is still enabled, then return to step 614 , to perform a new offset calibration before the next SAR-ADC conversion is executed.

[0036] It is considered, and within the scope of protection of this disclosure, that the offset-compensating SAR ADC can be implemented with bit cells to control the DAC switching according to embodiments of this disclosure. This can include adding logic to bit cells of the LSB portion to switch to positive or negative references during sampling. This can include three 2:1 multiplexers and an additional inverter in each bit cell. This can enable or disable the correction. Furthermore, there can be a storage register for the N-bit correction, which contains a plurality (N) of digital decimation filter (DDF) or digital signal processing (DSP) filters that can be used in high-resolution ADCs. Thus, an N-bit offset-correcting DAC can be realized.

[0037] Fig. 10 illustrates simulation results of embodiments of the present disclosure. Fig.Figure 10 illustrates a simulated offset (transistor level) with correction on and off.

[0038] Embodiments of the present disclosure can enable hybrid offset correction without a dedicated compensation DAC. Embodiments of the present disclosure can correct the offset to + / - 1 LSB. Embodiments of the present disclosure do not limit the input operating range of the ADC. Embodiments of the present disclosure do not require any additional analog circuitry. Embodiments of the present disclosure can measure and store offset compensation values ​​required to compensate for offsets during analog-to-digital conversion. This can be done at startup or at repeated intervals.

[0039] The present disclosure has been described in relation to one or a multitude of embodiments, and it is understood that many equivalents, alternatives, variations, and modifications, apart from those expressly stated, are possible and fall within the scope of the disclosure. While the present disclosure is accessible for various modifications and alternative forms, specific exemplary embodiments thereof have been shown in the drawings and are described here in detail. However, it is understood that the description of specific exemplary embodiments herein is not intended to limit the disclosure to the particular embodiments disclosed herein.

Claims

[1] Method for offset correction in a successive approximation register (SAR) analog-to-digital converter (ADC) using a reduced capacitor array digital-to-analog converter (DAC), the method comprising the following steps: Combining the positive and negative inputs of a SAR-ADC; Determining a digital representation of an offset voltage of the SAR-DAC; Storing the digital representation of the offset voltage in an offset register; Configuring a reduced capacitor array DAC featuring a large number of offset correction capacitors with the stored digital representation of the input offset voltage to provide an offset correction voltage; Decoupling of the positive and negative inputs of the SAR-ADC; Coupling a differential voltage to the positive and negative inputs of the SAR-ADC; and Performing a SAR conversion of the differential voltage during coupling with the offset correction voltage from the reduced capacitor array DAC. [2] Method according to claim 1, wherein the plurality of offset correction capacitors is coupled to a plurality of reference voltages selected by the digital representation of the offset voltage stored in the offset register. [3] Method according to claim 2, wherein the plurality of reference voltages is binary weighted from Vrefp to Vrefn voltages. [4] Method according to claim 3, wherein a common-mode voltage Vcm is approximately equal to (Vrefp + Vrefn) / 2. [5] Method according to one of claims 3 to 4, wherein the plurality of reference voltages is provided by a series-connected resistance voltage divider coupled between Vrefp and Vrefn. [6] Method according to any one of claims 1 to 5, wherein the plurality of offset correction capacitors comprises N positive offset correction capacitors with upper plates coupled together and forming a node Vx and N negative offset correction capacitors with upper plates coupled together and forming a node Vy, wherein N is the number of offset voltage correction bits of the reduced capacitor array DAC. [7] Method according to claim 6, wherein N is equal to five (5) and the method further comprises the steps: Coupling a lower plate of a first positive offset correction capacitor optionally with Vcm, Vrefp / 2 or Vrefn / 2; Coupling a lower plate of a first negative offset correction capacitor optionally with Vcm, Vrefn / 2 or Vrefp / 2; Coupling a lower plate of a second positive offset correction capacitor optionally with Vcm, Vrefp / 4 or Vrefn / 4; Coupling a lower plate of a second negative offset correction capacitor optionally with Vcm, Vrefn / 4 or Vrefp / 4; Coupling a lower plate of a third positive offset correction capacitor optionally with Vcm, Vrefp / 8 or Vrefn / 8; Coupling a lower plate of a third negative offset correction capacitor optionally with Vcm, Vrefn / 8 or Vrefp / 8; Coupling a lower plate of a fourth positive offset correction capacitor optionally with Vcm, Vrefp / 16 or Vrefn / 16; Coupling a lower plate of a fourth negative offset correction capacitor optionally with Vcm, Vrefn / 16 or Vrefp / 16; Coupling a lower plate of a fifth positive offset correction capacitor optionally with Vcm, Vrefp / 32 or Vrefn / 32; and Coupling a lower plate of a fifth negative offset correction capacitor optionally to Vcm, Vrefn / 32 or Vrefp / 32, thereby generating the offset compensation voltage. [8] Method according to claim 6, wherein N is equal to six (6) and further comprising the steps: Coupling an upper plate of a sixth positive offset correction capacitor to node Vx; Coupling an upper plate of a sixth negative offset correction capacitor to node Vy; Coupling a lower plate of the sixth positive offset correction capacitor optionally to Vcm, Vrefp or Vrefn; and Coupling a lower plate of the sixth negative offset correction capacitor optionally to Vcm, Vrefn or Vrefp, thereby doubling the voltage offset correction range. [9] Method according to any one of claims 1 to 8, further comprising the step of coupling the lower plates of the positive and negative offset correction capacitors to the common-mode voltage Vcm during a sampling phase of the SAR-ADC. [10] Method according to any one of claims 1 to 9, further comprising the step of disabling the offset compensation voltage. [11] Method according to any one of claims 1 to 10, further comprising the step of performing an offset correction at startup. [12] Method according to any one of claims 1 to 11, further comprising the step of periodically performing an offset correction. [13] Method according to any one of claims 1 to 12, wherein the SAR-ADC is a differential input SAR-ADC. [14] Method for correcting an offset voltage in an analog-to-digital converter (ADC) comprising the following steps: Combining the inputs of an ADC to generate an offset voltage; converting the offset voltage into a digital representation of it; Storing the digital representation of the offset voltage in an offset register; Deriving an offset compensation voltage from the stored digital representation of the offset voltage stored in the offset register; Receiving an analog input voltage; Correcting the offset voltage by scaling the voltage of a least significant bit; and Converting the analog input voltage into a digital output value. [15] Method according to claim 14, wherein the SAR-ADC is a differential input SAR-ADC. [16] Analog-to-digital converter (ADC) comprising a circuit configured to: perform one of the methods according to claims 1 to 15.