SILICON CARBIDE SEMICONDUCER UNIT

Abstract

Silicon carbide semiconductor unit (704, 708 to 714) comprising an elemental region (RE) and a non-elemental region (RN) which is arranged outside the elemental region (RE) in a top view, wherein the silicon carbide semiconductor unit (704, 708 to 714) comprises: - a silicon carbide semiconductor substrate (11) extending across the elemental region (RE) and the non-elemental region (RN); - a drift layer (10) arranged on the silicon carbide semiconductor substrate (11), consisting of silicon carbide and exhibiting a first conductivity type; - a base region (7) located in the element region (RE) on the drift layer (10) and having a second conductivity type that differs from the first conductivity type; - a source region (8) located in the element region (RE), located on the base region (7) and exhibiting the first conductivity type; - a first trench (12) which has a lateral surface penetrating the source area (8) and the base area (7), as well as a bottom surface; - a gate insulating layer (2) arranged on the lateral surface and on the bottom surface of the first trench (12); - a gate electrode (1) arranged through the gate insulating layer (2) in the first trench (12); - a first relaxation area (3) located below the first trench (12), in contact with the drift layer (10) and exhibiting the second conductivity type; - a source contact electrode (4) that is electrically connected to the source region (8) and the first relaxation region (3); - a gate contact electrode (14) located in the non-element region (RN) and electrically connected to the gate electrode (1); - at least one defect region (108) which is located below the gate contact electrode (14) at least in the non-element region (RN), located below the gate contact electrode (14) on the drift layer (10), has the first conductivity type and a higher defect concentration of the first conductivity type than a defect concentration of the first conductivity type of the drift layer (10); - at least a second trench (112) which has a lateral surface that penetrates the at least one fault area (108) and a bottom surface; and - at least a second relaxation area (103) located below the at least one second trench (112), in contact with the drift layer (10) and exhibiting the second conductivity type, - wherein the silicon carbide semiconductor unit (704, 708 to 714) has a contact area (RC) in a top view between the elemental area (RE) and the non-elemental area (RN), in which a region of the at least one defect area (108) is arranged and in which a third trench (212) is arranged, and the at least one defect area (108) and the source contact electrode (4) are electrically connected in the contact area (RC), and - wherein the silicon carbide semiconductor unit (704, 708 to 714) further comprises a third relaxation region (203) arranged below the third trench (212), electrically connected to the source contact electrode (4) and the at least one second relaxation region (103), and exhibiting the second conductivity type, wherein the element region (RE) is a region in which a cell is arranged which functions as a transistor, and the non-element region (RN) is a region in which the gate contact electrode (14) is arranged to supply a desired voltage to the gate electrode from the outside.

Description

TECHNICAL AREA

[0001] The present invention relates to a silicon carbide semiconductor unit. STATE OF THE ART

[0002] A vertical power semiconductor unit is frequently used as a switching element in an inverter circuit or similar device, and in particular, a vertical power semiconductor unit with a metal-oxide-semiconductor (MOS) structure is often used. Typically, an insulated-gate bipolar transistor (IGBT) and a metal-oxide-semiconductor field-effect transistor (MOSFET) are employed.

[0003] For example, publication WO 2010 / 098294A1 (Patent Document 1) discloses a MOSFET, and Japanese patent application publication JP 2004-273647A (Patent Document 2) discloses an IGBT. Patent Document 1 specifically discloses a vertical n-channel MOSFET using silicon carbide (SiC) as the semiconductor material. Furthermore, publication WO 2012 / 077617A1 (Patent Document 3) discloses a trench-gate MOSFET for the purpose of further reducing the voltage drop of a vertical n-channel MOSFET using silicon carbide.

[0004] The n-channel MOSFET has an n-type drift layer and a p-type trough located on the n-type drift layer. When the MOSFET switches from an on-state to an off-state, the drain voltage of the MOSFET, i.e., the voltage at the drain electrode, increases sharply from nearly zero volts to several hundred volts. In this case, a displacement current is generated by a parasitic capacitance present between the p-type trough and the n-type drift layer. A displacement current generated on the drain electrode side flows to the drain electrode, and a displacement current generated on the source electrode side flows through the p-type trough to the source electrode.

[0005] In this vertical n-channel MOSFET, in addition to the p-type well that forms the MOSFET cell (which effectively functions as the MOSFET), further p-type wells are typically arranged in an outer peripheral region of the chip. Examples of such additional p-type wells include one positioned directly below a gate contact. These p-type wells in the outer peripheral region usually have a significantly larger cross-sectional area in the horizontal plane (area in the plane layout) than the p-type well in the MOSFET cell. Consequently, the aforementioned displacement current in the p-type wells in the outer peripheral region must travel a long path before reaching the source electrode.

[0006] The p-type depressions thus exhibit high electrical resistance as current paths for the displacement current. As a result, an unacceptably high potential drop can occur in the p-type depressions. Consequently, a relatively high potential difference relative to the source potential is generated in the p-type depressions at a position in the plane far removed from a position connected to the source electrode. This can raise concerns regarding the occurrence of dielectric breakdown due to the potential difference.

[0007] In recent years, a semiconductor device using silicon carbide with a band gap approximately three times that of silicon, the most common semiconductor material, has been used as a switching element in inverter circuits, and in particular, an n-channel MOSFET has been employed. The use of a semiconductor with a large band gap allows for a reduction in inverter circuit losses. To further reduce losses, it is necessary to drive the switching element at a higher speed.

[0008] In other words, reducing losses requires further increasing dV / dt, which represents a variation of the drain voltage V with respect to time t. In such a case, the displacement current flowing through a parasitic capacitance into the p-type well is also increased. Furthermore, performing a treatment to reduce electrical resistance by doping is more difficult with silicon carbide than with silicon. Thus, when silicon carbide is used, there is a tendency for the p-type well to exhibit a high parasitic resistance. Such a high parasitic resistance can easily lead to a large potential drop in the p-type well. Under these circumstances, as described above, the use of silicon carbide can raise greater concerns regarding the aforementioned dielectric lag.

[0009] In the technology described above, according to patent WO 2010 / 098 294 A1 (Patent Document 1), a low-resistance p-type semiconductor layer is arranged on the entire upper surface or on a portion of the upper surface of the p-type well, which is positioned below the gate contact point in the outer peripheral region. This enables a reduction of the voltage distribution in the p-type well due to a potential drop that occurs when a displacement current flows in the p-type well located below the gate contact point.

[0010] Consequently, the potential difference between the p-type depression and the gate electrode is reduced. Consequently, the breakdown of a gate insulating layer is reduced.

[0011] In contrast, the technology described in patent WO 2011 / 007387A1 (patent document 4) employs a low-resistance n-type semiconductor layer covering the entire upper surface or a portion of the upper surface of a p-type well located below the gate contact point in the outer peripheral region. This further reduces the voltage distribution within the p-type well due to potential drop, which occurs when a displacement current flows in the p-type well below the gate contact point, compared to a case where a low-resistance p-type semiconductor layer is used. This reduces the potential difference between the p-type well and the gate electrode, thereby reducing the risk of gate insulation breakdown.

[0012] Patent document US 2013 / 0306983A1 (Patent Document 5) describes a semiconductor device comprising a wide-bandgap semiconductor layer having a gate trench with a side wall and a bottom wall, a gate insulating film formed on the side wall and bottom wall of the gate trench, and a gate electrode embedded in the gate trench to face the semiconductor layer through the gate insulating film, while the semiconductor layer includes a source region of a first conductivity type formed to be exposed on the side of a front face of the semiconductor layer to partially form the side wall of the gate trench, and a body region of a second conductivity type formed on one side of the source region closer to a rear face of the semiconductor layer to be in contact with the source region to partially form the side wall of the gate trench.a drift region of a first conductivity type formed on one side of the body region closer to the back of the semiconductor layer to contact the body region to form the bottom wall of the gate trench, and a first breakdown voltage holding region of a second conductivity type formed selectively at a boundary region of the gate trench where the side wall and the bottom wall intersect in a sub-region of the gate trench.

[0013] Patent document US 2017 / 0012121A1 (Patent Document 6) describes a technique in which higher dielectric strength can be achieved using a barrier layer that spreads rapidly within a circumferential region. A semiconductor device has an element region containing a gate-insulated switching element and a circumferential region adjacent to the element region. First and second trenches are provided in the circumferential region. A front surface region of the second conductivity type is provided between the first and second trenches. First and second bottom surface regions of the second conductivity type are provided in areas of the bottom surfaces of the first and second trenches. First and second side surface regions of the second conductivity type, connecting the front surface region and the first or second bottom surface region, are provided along the side surfaces of the first and second trenches.Regions with low area density are included, at least in parts of the first and second side area regions.

[0014] Patent document US 2020 / 0243641A1 (Patent Document 7) describes a semiconductor device comprising a semiconductor layer of a first conductivity type with a first principal surface on one side and a second principal surface on the other side, a gate-trough structure with a gate-trough formed in the first principal surface of the semiconductor layer and a gate electrode embedded in the gate-trough via a gate-insulating layer, a source-trough structure with a source-trough formed deeper than and at a distance from the gate-trough in the first principal surface of the semiconductor layer, a source electrode embedded in the source-trough, and a deep-embedding region of a second conductivity type formed in a region of the semiconductor layer along the source-trough, wherein the ratio of a source-trough depth to a gate-trough depth is not less than 1.5 is and not more than 4.0, a body region of the second conductivity type formed in a region of a surface layer section of the first principal surface of the semiconductor layer between the gate trench and the source trench, a source region of the first conductivity type formed in a surface layer section of the body region, and a drain electrode connected to the second principal surface of the semiconductor layer, DOCUMENTS ON THE STATE OF THE TECHNOLOGY Patent documents Patent document 1: WO 2010 / 098 294 A1 Patent document 2: JP 2004 - 273 647 A Patent document 3: WO 2012 / 077 617 A1 Patent document 4: WO 2011 / 007 387 A1 Patent document 5: US 2013 / 0 306 983 A1 Patent document 6: US 2017 / 0 012 121 A1 Patent document 7: US 2020 / 0 243 641 A1 SHORT DESCRIPTION Problem to be solved with the invention

[0015] A planar MOSFET and a trench MOSFET typically have different configurations of their outer peripheral regions (more generally, their "non-element regions"). The technologies described above in WO 2010 / 098 294 A1 and WO 2011 / 007 387 A1 refer to a planar MOSFET and are therefore not necessarily applicable to the trench type.

[0016] The present invention was conceived to solve the problem described above and has the objective of providing a silicon carbide semiconductor unit with a trench by which an element breakdown at the time of switching can be reduced by reducing a potential drop that occurs when a displacement current flows. Means to solve the problem

[0017] The problem underlying the invention is solved by the silicon carbide semiconductor unit with the features of independent claim 1. Advantageous embodiments of the invention are specified in dependent claims 2 and 9. Effects of the invention

[0018] According to the present invention, the defect region on the drift layer is included as part of a path for a displacement current flowing through the second relaxation region in the non-element region at the time of high-speed switching of the silicon carbide semiconductor unit. This reduces the effective sheet resistance for the displacement current.

[0019] Consequently, the magnitude of the potential drop due to the displacement current is reduced. Consequently, the voltage between a potential of the second relaxation region and a gate potential is reduced due to the potential drop. Consequently, the dielectric breakdown between the second relaxation region and a region exhibiting the gate potential is reduced.

[0020] These and other objectives, features, aspects and advantages of the present invention will become even clearer from the following detailed description of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The figures show: Fig. 1 a top view schematically representing a configuration of a silicon carbide unit according to a first embodiment of the present invention; Fig. 2 a schematic partial cross-sectional view along a line II-II according to Fig. 1; Fig. 3 a schematic partial cross-sectional view along a line III-III according to Fig. 1; Fig. 4 a schematic partial cross-sectional view along a line IV-IV according to Fig. 1; Fig. 5 a cross-sectional partial view showing a configuration of a silicon carbide unit according to a modification of the first embodiment of the present invention along a line VV according to Fig. 6 schematically represents; Fig. 6 a perspective cross-sectional partial view schematically representing a configuration of the silicon carbide unit according to the modification of the first embodiment of the present invention without a partial configuration on the side of an upper surface; Fig. 7 a top view schematically representing a configuration of a silicon carbide unit according to a second embodiment of the present invention; Fig. 8 a schematic partial cross-sectional view along a line VIII-VIII according to Fig. 7; Fig. 9 a partial cross-sectional view of a configuration of a silicon carbide unit according to a third embodiment of the present invention, which is in a cross-section similar to that along line VIII-VIII according to Fig. 7 is shown; Fig. 10 a partial cross-sectional view of a configuration of a silicon carbide unit according to a fourth embodiment of the present invention, which is in a cross-section similar to that along line VIII-VIII according to Fig. 7 is shown; Fig. 11 a partial cross-sectional view showing a configuration of a silicon carbide unit according to a fifth embodiment of the present invention in a non-element region; Fig. 12 a partial cross-sectional view of a configuration of a silicon carbide unit according to a sixth embodiment of the present invention, which is in a cross-section similar to that along line VIII-VIII according to Fig. 7 is shown; Fig. 13 a partial cross-sectional view of a configuration of a silicon carbide unit according to a seventh embodiment of the present invention, which is in a cross-section similar to that along line VIII-VIII according to Fig. 7 is shown; Fig. 14 a partial cross-sectional view showing a configuration of a silicon carbide unit according to an eighth embodiment of the present invention in a non-element region; Fig. 15 a partial cross-sectional view of a configuration of a silicon carbide unit according to a ninth embodiment of the present invention, which is in a cross-section similar to that along line VIII-VIII according to Fig. 7 is shown; Fig. 16 a partial top view showing a configuration of a silicon carbide semiconductor layer of a silicon carbide unit according to a tenth embodiment of the present invention in a non-element region; Fig. 17 a partial cross-sectional view along a line XVII-XVII according to Fig. 16; Fig. 18 a partial cross-sectional view along a line XVIII-XVIII according to Fig. 16; Fig. 19 a partial top view of a configuration of a silicon carbide semiconductor layer of a silicon carbide unit according to an eleventh embodiment of the present invention in a non-element region when viewed from an angle similar to that shown in the Fig. 16; Fig. 20 a partial top view of a configuration of a silicon carbide semiconductor layer of a silicon carbide unit according to a twelfth embodiment of the present invention in a non-element region when viewed from an angle similar to that shown in the Fig. 16; Fig. 21 a partial cross-sectional view showing a configuration of a silicon carbide unit according to a thirteenth embodiment of the present invention in a non-element region; Fig. 22 a partial cross-sectional view of a configuration of a silicon carbide unit according to a fourteenth embodiment of the present invention, which is in a cross-section similar to that along line VIII-VIII according to Fig. 7 is shown. DESCRIPTION OF EXECUTION FORMS

[0022] Embodiments of the present invention are described below with reference to the drawings. It should be noted that the same or equivalent areas in the following drawings are designated by the same reference numerals and their description is not repeated. First embodiment configuration

[0023] Fig. Figure 1 is a top view schematically illustrating a configuration of a MOSFET 701 (silicon carbide semiconductor unit) according to a first embodiment. In a top view, the MOSFET 701 has an elemental region RE and a non-elemental region RN. The elemental region RE includes a region in which gate-electrode controlled channels are arranged, and it is typically a region in which a MOSFET cell is arranged, effectively functioning as a MOSFET.

[0024] The non-element region RN is located outside the element region RE and includes a region in which a gate contact electrode 14 is arranged to supply a desired voltage to the gate electrode from the outside. A wire made of a metal, such as aluminum, is connected to the gate contact electrode 14 by ultrasonic bonding or similar means. The non-element region RN may include a terminal area of ​​the MOSFET 701.

[0025] Fig. 2 and Fig. 3 represent different partial cross-sections in the element area RE along a line II-II or a line III-III according to Fig. 1 schematically represented. Fig. 4 represents a partial cross-section in the non-element area RN along a line IV-IV according to Fig. 1 schematically represents. It should be noted that in these cross-sectional representations and further cross-sectional representations to be described later, areas exhibiting a p-type (a second conductivity type) are dotted.

[0026] The MOSFET 701 comprises the following: a substrate 11 (a silicon carbide semiconductor substrate), an epitaxial layer 30 (a silicon carbide semiconductor layer), a gate insulating layer 2, a gate electrode 1, a gate contact electrode 14, a source contact electrode 4, a drain electrode 104, an intermediate insulating layer 5, and an insulator region 102. The epitaxial layer 30 comprises the following: a drift layer 10, a base region 7, a source region 8, an impurity region 108, a high-concentration region 6, a first relaxation region 3, a second relaxation region 103, and a junction region 9. A first trench 12 ( Fig. 2 and Fig. 3) and a second trench 112 ( Fig. 4) ordered.

[0027] Substrate 11 extends across the elemental region RE and the non-elemental region RN. Substrate 11 is of the n-type (first conductivity type). The epitaxial layer 30 is placed on substrate 11 by epitaxial growth and extends across the elemental region RE and the non-elemental region RN.

[0028] The drift layer 10 is arranged on the substrate 11 such that it extends across the elemental region RE and the non-elemental region RN. The drift layer 10 consists of silicon carbide. The drift layer 10 is of the n-type and has a donor concentration of 1 × 10 14 cm -3 up to 1 × 10 17 cm -3 It is preferred that the donor concentration of the drift layer 10 is lower than the donor concentration of the substrate 11.

[0029] The base region 7 is located in the element region RE and is situated on the drift layer 10. The base region 7 exhibits a p-type (a second conductivity type that differs from the first conductivity type) and preferably has an acceptor concentration of 1 × 10 14 cm -3 up to 1 × 10 18 cm -3 It should be noted that the acceptor concentration and the thickness of base region 7 do not need to be uniform. Source region 8 is located within element region RE and is positioned on top of base region 7.

[0030] Source region 8 is of the n type, has a donor concentration that is higher than the donor concentration of drift layer 10, and in particular has a donor concentration of 1 × 10 18 cm -3 up to 1 × 10 20 cm -3The high-concentration region 6 is located in the element region RE, penetrates the source region 8, and extends to the base region 7. The high-concentration region 6 is p-type, has an acceptor concentration higher than that of the base region 7, and specifically has an acceptor concentration of 1 × 10 19 cm -3 up to 1 × 10 21 cm -3 on.

[0031] As in Fig. As shown in Figure 2, in the present embodiment a plurality of first trenches 12 are arranged at intervals within the element area RE. It should be noted that the plurality of first trenches 12 are like those shown in Figure 2. Fig. The two structures shown in the diagram can be connected to each other in a specific cross-section in the plane layout. The first trench 12 has a lateral surface and a bottom surface. The lateral surface of the first trench 12 penetrates the source region 8 and the base region 7. The lateral surface of the first trench 12 extends in the cross-section according to Fig. 2 up to drift layer 10.

[0032] In this way, the cross-section is calculated according to Fig. Two channels of the MOSFET are configured. The first relaxation region 3 is located below the first trench 12 and is in contact with the drift layer 10. Typically, the first relaxation region 3 is in contact with the bottom surface of the first trench 12. The first relaxation region 3 is of the p-type and preferably has an acceptor concentration of 1 × 10 14 cm -3 up to 1 × 10 18 cm -3 on.

[0033] It should be noted that the acceptor concentration and the thickness of the first relaxation region 3 do not need to be uniform. The gate insulating layer 2 is located on the lateral surface and on the bottom surface of the first trench 12. At least one portion of the gate electrode 1 is located within the first trench 12 through the gate insulating layer 2.

[0034] The source contact electrode 4 is electrically connected to the source region 8 and the high-concentration region 6 via an ohmic or Schottky junction. To achieve this electrical connection, the source contact electrode 4 is in contact with the high-concentration source region 8 and region 6. It should be noted that a portion of the source contact electrode 4 may be silicified to facilitate contact with the high-concentration source region 8 and region 6.

[0035] In other words, the source contact electrode 4 can have a silicide layer in contact with the source region 8 and the region 6 at a high concentration. The source contact electrode 4 is separated from the gate electrode 1 by the intermediate insulating layer 5. The source contact electrode 4 is electrically connected to the first relaxation region 3. In the present embodiment, the source contact electrode 4 is connected to the first relaxation region 3, which is p-type, only by a p-type semiconductor region. As shown in Fig. As shown in Figure 3, the source contact electrode 4 is connected to the first relaxation region 3, in particular via the high-concentration region 6, the base region 7, and the connection region 9. To achieve such an electrical connection in a region between the base region 7 and the bottom surface of the first trench 12, the connection region 9 is arranged adjacent to the lateral surface of the first trench 12.

[0036] As described above, the compound region 9 is of the p-type and preferably has an acceptor concentration of 1 × 10 14 cm -3 up to 1 × 10 18 cm -3 It should be noted that the acceptor concentration and the thickness of the compound area 9 do not have to be uniform. In the plane layout, a plurality of compound areas 9 can be arranged separately from one another. Although in Fig. 3. If the connection area 9 is arranged on both sides of the first trench 12, it is also possible that the connection area 9 is arranged only on one of the two sides.

[0037] Furthermore, the arrangement of one connection area 9, which is located on one side of the first trench 12, and the arrangement of the other connection area 9, which is located on the other side of the first trench 12, can differ in the longitudinal direction of the first trench 12.

[0038] The gate contact electrode 14 is located in the non-element region RN and is electrically connected to the gate electrode 1 via an ohmic or Schottky junction. To achieve this electrical connection, the gate electrode 1 has, for example, a region extending from the element region RE to the non-element region RN, and this extending region is in contact with the gate contact electrode 14 in the non-element region RN. In this way, an ohmic or Schottky contact is established between the gate contact electrode 14 and the gate electrode 1.

[0039] The defect region 108 is located at least in the non-element region RN and is situated on the drift layer 10. The defect region 108 is of the n type and has a donor concentration that is higher than the donor concentration of the drift layer 10. In particular, the donor concentration of the defect region 108 is equal to 1 × 10 18 cm -3 up to 1 × 10 20 cm -3 and can be equal to or different from the donor concentration of the source region 8. The impurity region 108 is separated from the gate contact electrode 14 by the intermediate insulating layer 5. It should be noted that, in the present embodiment, it is preferred that the impurity region 108 is electrically connected to the source contact electrode 4; however, the impurity region 108 can also be isolated from the source contact electrode 4.

[0040] Furthermore, it is preferred that the impurity region 108 is electrically connected to the first relaxation region 3; however, the impurity region 108 can also be isolated from the first relaxation region 3. It should be noted that if the impurity region 108 is isolated from the source contact electrode 4, a displacement current flowing from the second relaxation region 103 via the drift layer 10 to the impurity region 108 can flow through a certain capacitance into any of the electrodes described above or can flow again through a pn junction capacitance into the second relaxation region 103.

[0041] The second trench 112 ( Fig. 4) is located in the non-element area RN. The second trench 112 has a lateral surface and a bottom surface. The lateral surface of the second trench 112 penetrates the fault area 108 and extends to the drift layer 10. The second trench 112 can have a depth that is the same as the depth of the first trench 12. As in Fig. As shown in Figure 4, in the present embodiment a plurality of second trenches 112 are arranged at intervals. It should be noted that the plurality of second trenches 112 are like those in Fig. The four elements shown in a specific cross-section can be connected to each other in the plane layout.

[0042] The second relaxation region 103 is located below the second trench 112 and is in contact with the drift layer 10. Typically, the second relaxation region 103 is in contact with the bottom surface of the second trench 112. The second relaxation region 103 is of the p-type and preferably has an acceptor concentration of 1 × 10 14 cm -3 up to 1 × 10 18 cm -3 It should be noted that the acceptor concentration and the thickness of the second relaxation region 103 need not be uniform. The second relaxation region 103 can have an acceptor concentration that is the same as the acceptor concentration of the first relaxation region 3.

[0043] It should be noted that, in the present embodiment, it is preferred that the second relaxation area 103 is electrically connected to the source contact electrode 4; however, the second relaxation area 103 can also be insulated from the source contact electrode 4. Furthermore, it is preferred that the second relaxation area 103 is electrically connected to the first relaxation area 3; however, the second relaxation area 103 can also be insulated from the first relaxation area 3. Finally, the second relaxation area 103 can be directly connected to the first relaxation area 3.

[0044] The insulator area 102 is arranged in and fills the second trench 112. In the present embodiment, the second trench 112 is filled with only one insulator. The materials of the insulator area 102 need not be uniform. For example, a region of the insulator area 102, which faces the side surface and the bottom surface of the second trench 112, consists of a material that is the same as a material of the gate insulating layer 2 ( Fig. 2), and another area of ​​the insulator area 102, which fills the second trench 112 through the aforementioned area, consists of a material which is the same as a material of the intermediate insulating layer 5.

[0045] The drain electrode 104 is on a surface (a lower surface according to Fig. 2 to Fig. 4) of the substrate 11, which faces a surface on which the drift layer 10 is arranged. In this way, the drain electrode 104 is electrically connected to the n-type drift layer 10 via the substrate 11, which has the same n-type structure. In particular, at least one interface layer (in the present embodiment, two interface layers) forming an ohmic junction or an interface layer forming a Schottky junction is arranged between the drain electrode 104 and the drift layer 10. It should be noted that the interface region between the drain electrode 104 and the drift layer 10 may contain a silicide.

[0046] It should be noted that in the present embodiment, the first conductivity type is the n-type and the second conductivity type is the p-type. However, as a modification, these conductivity types can also be reversed. In such a case, the terms "donor concentration" and "acceptor concentration" used in the preceding description with regard to impurity concentrations should be interchanged. Furthermore, the Fig. The layer layout shown is for illustrative purposes only, and any arrangement can be used in the layer layout for the non-element area RN. Effects

[0047] According to the present embodiment, the defect region 108 on the drift layer 10 is included as a path for a displacement current flowing through the second relaxation region 103 in the non-element region RN at the time of switching of the MOSFET 701 at a high speed ( Fig. 4) This reduces the effective surface resistance to the displacement current. Consequently, the magnitude of the potential drop due to the displacement current is reduced.

[0048] Consequently, the voltage between the potential of the second relaxation region 103 and a gate potential is reduced due to the potential drop. Therefore, dielectric breakdown between the second relaxation region 103 and a region exhibiting a gate potential, i.e., the gate contact electrode 14, is reduced.

[0049] In particular, a displacement current flows at the time of switching off due to a forward current in the pn junction between the second relaxation region 103 and the drift layer 10 mainly in one direction from the second relaxation region 103 to the defect region 108.

[0050] At the time of switching on, a displacement current flows through the pn junction capacitance between the second relaxation region 103 and the drift layer 10, primarily in one direction from the defect region 108 to the second relaxation region 103.

[0051] These displacement currents experience a low surface resistance due to a high concentration of defects in the defect area 108, and such a low surface resistance allows the displacement currents to flow through the defect area 108 with a low potential drop. modification

[0052] Fig. Figure 5 is a partial cross-sectional view showing a configuration of a MOSFET 701V (silicon carbide unit) according to a modification of the first embodiment along a line VV according to Fig. 6 schematically represents. Fig. Figure 6 is a perspective cross-sectional partial view that schematically represents a configuration of the MOSFET 701V without a partial configuration on the side of an upper surface.

[0053] To establish an electrical connection between the source contact electrode 4 and the first relaxation region 3, a p-type semiconductor region, such as the connection region 9, connects the source contact electrode 4 and the first relaxation region 3 in the MOSFET 701 ( Fig. 3) In this modification ( Fig. 5) However, the source contact electrode 4 is in contact with the first relaxation region 3. As a result of this contact, an ohmic junction or a Schottky junction is arranged between the source contact electrode 4 and the first relaxation region 3.

[0054] This contact is achieved by a configuration in which a contact 15, extending in the intermediate insulating layer 5, is positioned in the source contact electrode 4 such that it reaches up to the first relaxation region 3. The contact 15 can be located in a groove situated in the epitaxial layer 30. The groove can be located in the element region RE and can be integrated with the first groove 12, as shown in the drawing.

[0055] It should be noted that in the Fig. In the cross-section shown in Figure 5, a plurality of first relaxation areas are separated from each other, but these are connected to each other in the plane layout. Second embodiment

[0056] Fig. Figure 7 is a top view schematically illustrating a configuration of a MOSFET 702 (silicon carbide semiconductor unit) according to a second embodiment. In the top view, the MOSFET 702 has a contact region RC between the element region RE and the non-element region RN.

[0057] Fig. 8 is a schematic partial cross-sectional view along a line VIII-VIII according to Fig. 7. In the present embodiment, a third groove 212 is arranged in the epitaxial layer 30 at least in a region of the contact area RC. The third groove 212 has a lateral surface and a bottom surface. The third groove 212 has a depth that is the same as the depth of the first groove 12.

[0058] The MOSFET 702 has a third relaxation region 203 located in the contact region RC. Specifically, the third relaxation region 203 is located below the third trench 212 and is in contact with the drift layer 10. Typically, the third relaxation region 203 is in contact with the bottom surface of the third trench 212. The third relaxation region 203 is of the p-type. The third relaxation region 203 can have an acceptor concentration that is the same as the acceptor concentration of the first relaxation region 3.

[0059] The third relaxation area 203 is electrically connected to the second relaxation area 103. In particular, the third relaxation area 203 has the cross-section according to Fig. The third relaxation area 203 is separated from the second relaxation area 103, but is connected to the second relaxation area 103 in the plane layout. It should be noted that it is preferred that the third relaxation area 203 be connected to the first relaxation area 3 in the plane layout, but the third relaxation area 203 does not have to be connected to the first relaxation area 3.

[0060] The third relaxation area 203 is electrically connected to the source contact electrode 4. To achieve this electrical connection, the source contact electrode 4 typically has a contact 215 in the third trench 212, which extends into the intermediate insulating layer 5 and reaches up to the third relaxation area 203.

[0061] If contact 215 is in contact with the third relaxation region 203, the source contact electrode 4 and the third relaxation region 203 are connected by an ohmic junction or a Schottky junction. It should be noted that the source contact electrode 4 may contain a silicide in the junction region between the source contact electrode 4 and the third relaxation region 203.

[0062] The above configuration enables an electrical connection of the second relaxation region 103 with the source contact electrode 4. In particular, the second relaxation region 103, which has the p-type, is connected to the source contact electrode 4 only by the third relaxation region 203, which has the p-type.

[0063] It should be noted that a region of the gate electrode 1 and a region of the gate contact electrode 14 can be arranged in contact with each other in the third trench 212. In this way, an electrical connection between the gate electrode 1 and the gate contact electrode 14 is achieved.

[0064] The configuration, with the exception of that described above, is essentially the same as the configuration of the first embodiment described above, and thus the same or corresponding elements are designated by the same reference numerals, and a description thereof is not repeated.

[0065] According to the present embodiment, the second relaxation region 103 is connected to the source contact electrode 4 via the third relaxation region 203. This ensures that a displacement current flowing at high speed in the second relaxation region 103 during switching is sufficiently directed towards or away from the source contact electrode 4. Consequently, the magnitude of the potential drop due to the displacement current is further reduced.

[0066] Consequently, the voltage between the potential of the second relaxation region 103 and a gate potential is further reduced due to the potential drop. Therefore, dielectric breakdown between the second relaxation region 103 and a region exhibiting the gate potential, i.e., the gate contact electrode 14, is more reliably prevented.

[0067] It should be noted that this in Fig. The plane layout shown in Figure 7 is merely illustrative and any arrangement for the non-element region RN can be used in this layout. Furthermore, the configuration for achieving an electrical connection between the source contact electrode 4 and the second relaxation region 103 is not limited to the one shown in Figure 7. Fig. The configuration shown is limited to 8, and these can, for example, be in contact with each other. Third embodiment

[0068] Fig. Figure 9 is a partial cross-sectional view of a configuration of a MOSFET 703 (silicon carbide semiconductor unit) according to a third embodiment, which is shown in a cross-section similar to that along line VIII-VIII according to Fig. 7 is shown. In the top view (see Fig. 7) The MOSFET 703 has a contact area RC between the element area RE and the non-element area RN, in which an area of ​​the defect area 108 ( Fig. 9) is arranged. In the contact area RC, the defect area 108 and the source contact electrode 4 are electrically connected. To achieve this electrical connection, the source contact electrode 4 typically has a contact 115 in the contact area RC, which extends into the intermediate insulating layer 5 and reaches up to the defect area 108.

[0069] If contact 115 is in contact with the defect area 108, an ohmic junction or a Schottky junction is arranged between the source contact electrode 4 and the defect area 108. In this way, the defect area 108 and the source contact electrode 4 are electrically connected in the contact area RC. It should be noted that contact 215 ( Fig. 8: second embodiment) is not arranged in the present embodiment.

[0070] The configuration, with the exception of that described above, is essentially the same as the configuration of the first or second embodiment described above, and thus the same or corresponding elements are designated by the same reference numerals, and a description thereof is not repeated.

[0071] According to the present embodiment, the defect area 108 is electrically connected to the source contact electrode 4. This ensures that a displacement current flowing at high speed in the defect area 108 during switching is sufficiently directed towards or away from the source contact electrode 4. Consequently, the magnitude of the potential drop due to the displacement current is further reduced.

[0072] Consequently, the voltage between the potential of the second relaxation region 103 and a gate potential is further reduced due to the potential drop. Therefore, dielectric breakdown between the second relaxation region 103 and a region exhibiting the gate potential, i.e., the gate contact electrode 14, is more reliably prevented. Fourth embodiment

[0073] Fig. Figure 10 is a partial cross-sectional view of a configuration of a MOSFET 704 (silicon carbide semiconductor unit) according to a fourth embodiment, which is shown in a cross-section similar to that along line VIII-VIII according to Fig. Figure 7 is shown. In the MOSFET 704, both contact 215 described in the second embodiment and contact 115 described in the third embodiment are arranged. This configuration produces the effects of both the second and third embodiments. Fifth embodiment

[0074] Fig. Figure 11 is a partial cross-sectional view showing a configuration of a MOSFET 705 (silicon carbide semiconductor unit) according to a fifth embodiment in the non-element region RN. The MOSFET 705 has, instead of the insulator region 102 ( Fig. 4: first embodiment) an insulating layer 202 on the inner surface and a region 101 with low resistance.

[0075] The insulating layer 202 on the inner surface is arranged on the side surface and on the bottom surface of the second trench 112. The material for the insulating layer 202 on the inner surface can be the same material as that of the gate insulating layer 2 ( Fig. 2: first embodiment).

[0076] The low-resistance region 101 is located in the second groove 112 on the inner surface by the insulating layer 202. The low-resistance region 101 is electrically insulated from the gate contact electrode 14 by the intermediate insulating layer 5. The low-resistance region 101 consists of a metal or a doped semiconductor. In this way, the low-resistance region 101 exhibits a low specific electrical resistance. The material for the low-resistance region 101 can be the same material as that of the gate electrode 1 ( Fig. 2: first embodiment).

[0077] It should be noted that, with the exception of those described above, the configuration is essentially the same as that of the first to fourth embodiments described above, and thus the same or corresponding elements are designated with the same reference numerals, and a description thereof is not repeated. Furthermore, the present embodiment produces essentially the same effects as those of the first to fourth embodiments described above. Sixth embodiment

[0078] Fig. Figure 12 is a partial cross-sectional view of a configuration of a MOSFET 706 (silicon carbide unit) according to a sixth embodiment, which is in a cross-section similar to that along line VIII-VIII according to Fig. Figure 7 is shown. The MOSFET 706 has a contact 215 similar to that in the second embodiment ( Fig. 8) and has an insulating layer 202 on the inner surface and a low-resistance region 101 similar to those in the fifth embodiment ( Fig. 11).

[0079] The configuration, with the exception of that described above, is essentially the same as the configuration of the first embodiment described above, and thus the same or corresponding elements are designated with the same reference numerals, and a description thereof is not repeated. The present embodiment produces essentially the same effects as those of the second and fifth embodiments described above. Seventh embodiment

[0080] Fig. Figure 13 is a partial cross-sectional view of a configuration of a MOSFET 707 (silicon carbide unit) according to a seventh embodiment, which is in a cross-section similar to that along line VIII-VIII according to Fig. Figure 7 is shown. The MOSFET 707 has a contact 115 similar to that in the third embodiment ( Fig. 9) and has an insulating layer 202 on the inner surface as well as a region 101 with a low resistance similar to those in the fifth embodiment ( Fig. 11).

[0081] The configuration, with the exception of that described above, is essentially the same as the configuration of the first embodiment described above, and thus the same or corresponding elements are designated with the same reference numerals, and a description thereof is not repeated. The present embodiment produces essentially the same effects as those of the third and fifth embodiments described above. Eighth embodiment

[0082] Fig. Figure 14 is a partial cross-sectional view showing a configuration of a MOSFET 708 (silicon carbide semiconductor unit) according to an eighth embodiment in the non-element region RN. The MOSFET 708 has a connection region 109. The connection region 109 is located adjacent to the lateral surface of the second trench 112 and is connected to the second relaxation region 103 and the defect region 108. The connection region 109 is of the p-type and preferably has an acceptor concentration of 1 × 10⁻⁶. 14 cm -3 up to 1 × 10 18 cm -3 It should be noted that the MOSFET 708, as in Fig. 11 shows a cross-section in which the connection area 109 is not located.

[0083] Although the connection area 109 in Fig. If the connection area 109 is arranged on both sides of the second trench 112, it is also possible that the connection area 109 is arranged on only one of these two sides. Furthermore, the arrangement of one connection area 109, which is arranged on one side of the second trench 112, and the arrangement of the other connection area 109, which is arranged on the other side of the second trench 112, may differ in the longitudinal direction of the second trench 112. The acceptor concentration and the thickness of the connection area 109 need not be uniform.

[0084] It should be noted that, with the exception of those described above, the configuration is essentially the same as the configuration of the first to fourth embodiments described above, and thus the same or corresponding elements are designated with the same reference numerals, and a description thereof is not repeated. Furthermore, the connection area 109 ( Fig. 14) as a modification in the fifth to seventh embodiments ( Fig. 11 to Fig. 13) are used, which have the insulating layer 202 on the inner surface and the area 101 with low resistance.

[0085] According to the present embodiment, the junction 109 is arranged between the second relaxation region 103 and the defect region 108. This allows a displacement current to flow effectively between the relaxation region 103 and the defect region 108 at high speed when the MOSFET 708 is switched on. At the time of switch-off, a displacement current flows primarily from the second relaxation region 103 through the junction 109 to the defect region 108 due to a forward current in the pn junction between the junction 109 and the defect region 108.

[0086] At the time of switch-on, a displacement current flows through the pn junction capacitance between the connection area 109 and the fault area 108, primarily from the fault area 108 through the connection area 109 to the second relaxation area 103. These displacement currents can flow with a small potential drop due to the arrangement of the connection area 109. Ninth embodiment

[0087] Fig. Figure 15 is a partial cross-sectional view of a configuration of a MOSFET 709 (silicon carbide unit) according to a ninth embodiment, which is in a cross-section similar to that along line VIII-VIII according to Fig. Figure 7 shows the MOSFET 709 having a contact 115 and a contact 215 similar to those in the fourth embodiment ( Fig. 10) and has an insulating layer 202 on the inner surface and a region 101 with a low resistance similar to those in the fifth embodiment ( Fig. 11).

[0088] The configuration, with the exception of that described above, is essentially the same as the configuration of the first embodiment described above, and thus the same or corresponding elements are designated with the same reference numerals, and a description thereof is not repeated. The present embodiment produces essentially the same effects as those of the fourth and fifth embodiments described above. Tenth embodiment

[0089] Fig. Figure 16 is a partial top view showing a configuration of the epitaxial layer 30 of a MOSFET 710 (silicon carbide unit) according to a tenth embodiment in the non-element region RN. Fig. 17 and Fig. 18 are partial cross-sectional views along a line XVII-XVII or a line XVIII-XVIII according to Fig. 16.

[0090] In the present embodiment, a plurality of second trenches 112 are arranged at intervals. In particular, in the figure, each of them extends in the vertical direction, and they are separated from each other in the horizontal direction. As in Fig. As shown in Figure 18, in the present embodiment such a plurality of areas are connected to the third trench 212. As a result of this configuration, the second relaxation area 103 is connected to the third relaxation area 203.

[0091] In the non-element area RN, the defect area is 108 ( Fig. 16) each arranged between the second trenches 112. A plurality of fault areas 108 are separated from one another. Each of these is electrically connected, for example, by the contact 115 to the source contact electrode 4 ( Fig. 17). The contact 115 can extend continuously along the horizontal direction according to Fig. 16. extend in such a way that it extends over these, or may have a plurality of separate areas.

[0092] The second relaxation zones 103 are each arranged below the second trench 112, specifically on its bottom surface. In this way, the majority of the second relaxation zones 103 are separated from one another, as shown in Fig. 16 shown. Fig. 16 each of them extends in the vertical direction, and in the horizontal direction they are separated by the drift layer 10 (in Fig. 16 (not shown) immediately below the fault area 108 separated from each other.

[0093] The second relaxation areas 103 are each, for example, through contact 215 ( Fig. 18) electrically connected to the source contact electrode 4. The contact 215 can extend continuously along the horizontal direction according to Fig. 16 extend or may have a plurality of separate areas.

[0094] It should be noted that, with the exception of those described above, the configuration is essentially the same as the configuration of the first to fourth embodiments described above, and thus the same or corresponding elements are designated with the same reference numerals, and a description thereof is not repeated. Furthermore, the configuration shown in the present embodiment can be considered a modification of the fifth to seventh embodiments ( Fig. 11 to Fig. 13) are used, which have the insulating layer 202 on the inner surface and the area 101 with a low resistance instead of the insulator area 102.

[0095] According to the present embodiment, as in Fig. As shown in Figure 16, a simple layer layout can be used as the layer layout of the non-element area RN. In particular, a line and space layer layout can be used, which has an arrangement in one direction (the horizontal direction in Figure 16). Fig. 16). This enables an improvement in the reliability of the MOSFET. Eleventh embodiment

[0096] Fig. Figure 19 is a partial top view of a configuration of the epitaxial layer 30 of a MOSFET 711 (silicon carbide unit) according to an eleventh embodiment in the non-element region RN when viewed from an angle similar to that shown in Figure 19. Fig. 16. In the MOSFET 711, the fault area 108 has a plurality of extending fault areas 108X and at least one interconnecting fault area 108Y.

[0097] The majority of extending defect regions 108X are separate from one another, and each extends in one direction (the vertical direction in the figure). The connecting defect region 108Y connects adjacent majority of extending defect regions 108X. It should be noted that the connecting defect region 108Y can be located in at least one region of adjacent pairs of extending defect regions 108X.

[0098] The configuration, with the exception of that described above, is essentially the same as the configuration of the tenth embodiment or its modification described above, and thus the same or corresponding elements are designated by the same reference numerals, and a description thereof is not repeated.

[0099] According to the present embodiment, the connection fault area 108Y is arranged in the fault area 108, forming a path for the displacement current as well as the second relaxation area 103. This reduces the uneven distribution of a displacement current that flows at high speed in the second relaxation area 103 in the non-element area RN at the time of switching.

[0100] Consequently, the uneven distribution of the potential drop along the second relaxation region 103 is reduced. Consequently, the local increase in voltage between the second relaxation region 103 and the gate contact electrode 14 due to the potential drop is reduced. Consequently, dielectric breakdown between the second relaxation region 103 and the gate contact electrode 14 is more reliably reduced. Twelfth embodiment

[0101] Fig. Figure 20 is a partial top view of a configuration of the epitaxial layer 30 of a MOSFET 712 (silicon carbide unit) according to a twelfth embodiment in the non-element region RN when viewed from an angle similar to that shown in Figure 20. Fig. 16. In MOSFET 712, the second relaxation region 103 has a plurality of extending relaxation regions 103X and at least one connecting relaxation region 103Y. The plurality of extending relaxation regions 103X are separate from one another, and each extends in one direction (the vertical direction in the figure). The connecting relaxation region 103Y connects adjacent members of the plurality of extending relaxation regions 103X. It should be noted that the connecting relaxation region 103Y can be located in at least one region of adjacent pairs of extending relaxation regions 103X.

[0102] The configuration, with the exception of that described above, is essentially the same as the configuration of the tenth embodiment or its modification described above, and thus the same or corresponding elements are designated by the same reference numerals, and a description thereof is not repeated.

[0103] According to the present embodiment, the connection relaxation region 103Y is arranged within the second relaxation region 103. This reduces the uneven distribution of a displacement current flowing in the non-element region RN at the time of high-speed switching within the second relaxation region 103. Consequently, the uneven distribution of the potential drop along the second relaxation region 103 is reduced.

[0104] Consequently, a local increase in voltage between the second relaxation region 103 and the gate contact electrode 14 is reduced due to the potential drop. Therefore, a dielectric breakdown between the second relaxation region 103 and the gate contact electrode 14 is more reliably reduced. Thirteenth embodiment

[0105] Fig. Figure 21 is a partial cross-sectional view showing a configuration of a MOSFET 713 (silicon carbide unit) according to a thirteenth embodiment in the non-element region RN. The MOSFET 713 has a configuration in which a defect region 107, which has the p-type, corresponds to the configuration of the eighth embodiment ( Fig. 14) is added. The defect area 107 is located on the drift layer 10 at a position immediately below the defect area 108.

[0106] In other words, in the present embodiment, the defect region 108 is arranged above the drift layer 10, with the defect region 107 being inserted between the defect region 108 and the drift layer 10. The connecting region 109 connects the second relaxation region 103 and the defect region 107. It is preferred that the defect region 107 has an acceptor concentration of 1 × 10 14 cm -3 up to 1 × 10 18 cm -3 exhibits. It should be noted that the acceptor concentration and the thickness of the defect area 107 need not be uniform.

[0107] The configuration, with the exception of that described above, is essentially the same as the configuration of the first to fourth embodiments or the tenth to twelfth embodiments described above, and thus the same or corresponding elements are designated with the same reference numerals, and a description thereof is not repeated. Furthermore, the defect area 107 can be considered a modification in the fifth to seventh embodiments ( Fig. 11 to Fig. 13) are used, which have the insulating layer 202 on the inner surface and the area 101 with a low resistance instead of the insulator area 102.

[0108] According to the present embodiment, the arrangement of the impurity region 107 causes a displacement current to flow effectively at high speed between the second relaxation region 103 and the impurity region 108 at the time the MOSFET 713 switches on. At the time of switch-off, a displacement current flows due to a forward current in the pn junction between the impurity region 107 and the impurity region 108, primarily from the second relaxation region 103 through the junction region 109 and the impurity region 107 to the impurity region 108.

[0109] At the time of switch-on, a displacement current flows through the pn junction capacitance between the fault region 107 and the fault region 108, primarily from the fault region 108 through the fault region 107 and the connection region 109 to the second relaxation region 103. These displacement currents can flow with a small potential drop due to the arrangement of the fault region 107. Fourteenth embodiment configuration

[0110] Fig. Figure 22 is a partial cross-sectional view of a configuration of a MOSFET 714 (silicon carbide unit) according to a fourteenth embodiment, which is in a cross-section similar to that along line VIII-VIII according to Fig. 7 is shown.

[0111] In the MOSFET 714, the defect region 108 has a sub-region 108N, which is located in the non-element region RN, and a sub-region 108C, which is located in the contact region RC. The sub-region 108N and the sub-region 108C have the cross-section shown in the diagram. Fig. 22 separate from each other, but are connected in the plane layout. The defect area 107 has a sub-area 107N, which is located in the non-element area RN, and a sub-area 107C, which is located in the contact area RC. The sub-area 107N and the sub-area 107C are in the cross-section according to Fig. 22 separate from each other, but are connected in the layer layout.

[0112] The epitaxial layer 30 in the contact region RC exhibits a high-concentration region 106. This high-concentration region 106 penetrates subregion 108C and extends to subregion 107C. The high-concentration region 106 is p-type, exhibits an acceptor concentration higher than that of the defect region 107, and specifically has an acceptor concentration of 1 × 10 19 cm -3 up to 1 × 10 21 cm -3 The acceptor concentration of range 106 with a high concentration can be the same as the acceptor concentration of range 6 with a high concentration.

[0113] Subregion 108C is electrically connected to the source contact electrode 4. To achieve this electrical connection, the source contact electrode 4 typically has a contact 315 in contact region RC, which extends into the intermediate insulating layer 5 and reaches to subregion 108C. When contact 315 is in contact with subregion 108C, an ohmic junction or a Schottky junction is formed between the source contact electrode 4 and subregion 108C. According to this structure, the source contact electrode 4 is connected to subregion 108N via subregion 108C. In this way, the entire defect region 108 is electrically connected to the source contact electrode 4.

[0114] The high-concentration region 106 is electrically connected to the source contact electrode 4. To achieve this electrical connection, the source contact electrode 4 typically has a contact 315 in contact region RC, which extends into the intermediate insulating layer 5 and reaches up to the high-concentration region 106. When the contact 315 is in contact with the high-concentration region 106, an ohmic junction or a Schottky junction is formed between the source contact electrode 4 and the high-concentration region 106.

[0115] According to this structure, the source contact electrode 4 is connected to the second relaxation region 103, which is also p-type, via the high-concentration region 106, the subregion 107C, and the connection region 109, all of which have the same p-type structure. In this way, the second relaxation region 103 is electrically connected to the source contact electrode 4.

[0116] It should be noted that, with the exception of those described above, the configuration is essentially the same as the configuration of the thirteenth embodiment or its modification described above, and thus the same or corresponding elements are designated by the same reference numerals, and a description thereof is not repeated. Effects

[0117] According to the present embodiment, the source contact electrode 4 is electrically connected to the defect area 108 and the second relaxation area 103. This ensures that a displacement current flowing at high speed in the second relaxation area 103 during switching is sufficiently directed towards or away from the source contact electrode 4. Consequently, the magnitude of the potential drop due to the displacement current is further reduced.

[0118] Consequently, the voltage between the potential of the second relaxation region 103 and a gate potential is further reduced due to the potential drop. Therefore, dielectric breakdown between the second relaxation region 103 and a region exhibiting the gate potential, i.e., the gate contact electrode 14, is more reliably prevented.

[0119] In particular, the impurity region 108 is electrically connected to the source contact electrode 4. Thus, a displacement current generated in the impurity region 108 at the time of high-speed switching can easily flow towards or away from the source contact electrode 4. Furthermore, the second relaxation region 103 is electrically connected to the source contact electrode 4. Thus, a displacement current generated in the second relaxation region 103 at the time of high-speed switching can easily flow towards or away from the source contact electrode 4. REFERENCE MARK LIST RC contact area RE Element Area RN Non-Element Area 1 Gate electrode 2 Gate insulating layer 3 first relaxation area 4 Source contact point electrode 5 Intermediate insulating layer 6,106 area with a high concentration 7 Basic Area 8 Source area 109 Connection area 10 Drift layer 11 Substrate (silicon carbide semiconductor substrate) 12 first trench 14 Gate contact electrode 30 epitaxial layer 101 area with low resistance 102 Insulator area 103 second relaxation area 104 Drain electrode 107 Fault area 112 second trench 202 Insulating layer on the inner surface 203 third relaxation area 212 third trench 701 to 714, 701V MOSFET (silicon carbide semiconductor unit)

Claims

[1] Silicon carbide semiconductor unit (704, 708 to 714) comprising an elemental region (RE) and a non-elemental region (RN) which is arranged outside the elemental region (RE) in a top view, wherein the silicon carbide semiconductor unit (704, 708 to 714) comprises: - a silicon carbide semiconductor substrate (11) extending across the elemental region (RE) and the non-elemental region (RN); - a drift layer (10) arranged on the silicon carbide semiconductor substrate (11), consisting of silicon carbide and exhibiting a first conductivity type; - a base region (7) located in the element region (RE) on the drift layer (10) and having a second conductivity type that differs from the first conductivity type; - a source region (8) located in the element region (RE), located on the base region (7) and exhibiting the first conductivity type; - a first trench (12) which has a lateral surface penetrating the source area (8) and the base area (7), as well as a bottom surface; - a gate insulating layer (2) arranged on the lateral surface and on the bottom surface of the first trench (12); - a gate electrode (1) arranged through the gate insulating layer (2) in the first trench (12); - a first relaxation area (3) located below the first trench (12), in contact with the drift layer (10) and exhibiting the second conductivity type; - a source contact electrode (4) that is electrically connected to the source region (8) and the first relaxation region (3); - a gate contact electrode (14) located in the non-element region (RN) and electrically connected to the gate electrode (1); - at least one defect region (108) which is located below the gate contact electrode (14) at least in the non-element region (RN), located below the gate contact electrode (14) on the drift layer (10), has the first conductivity type and a higher defect concentration of the first conductivity type than a defect concentration of the first conductivity type of the drift layer (10); - at least a second trench (112) which has a lateral surface that penetrates the at least one fault area (108) and a bottom surface; and - at least a second relaxation area (103) located below the at least one second trench (112), in contact with the drift layer (10) and exhibiting the second conductivity type, - wherein the silicon carbide semiconductor unit (704, 708 to 714) has a contact area (RC) in a top view between the elemental area (RE) and the non-elemental area (RN), in which a region of the at least one defect area (108) is arranged and in which a third trench (212) is arranged, and the at least one defect area (108) and the source contact electrode (4) are electrically connected in the contact area (RC), and - wherein the silicon carbide semiconductor unit (704, 708 to 714) further comprises a third relaxation region (203) arranged below the third trench (212), electrically connected to the source contact electrode (4) and the at least one second relaxation region (103), and exhibiting the second conductivity type, wherein the element region (RE) is a region in which a cell is arranged which functions as a transistor, and the non-element region (RN) is a region in which the gate contact electrode (14) is arranged to supply a desired voltage to the gate electrode from the outside. [2] Silicon carbide semiconductor unit (704, 708, 710, 713, 714) according to claim 1, wherein the at least one second trench (112) is filled with an insulator. [3] Silicon carbide semiconductor unit (709) according to claim 1 or 2, further comprising: - an insulating layer (202) on the inner surface, arranged on the lateral surface and on the bottom surface of at least one second trench (112); and - a low-resistance region (101) located in at least the second trench (112) by the insulating layer (202) on the inner surface, electrically insulated from the gate contact electrode (14) and consisting of a metal or a doped semiconductor. [4] Silicon carbide semiconductor unit (708, 713, 714) according to any one of claims 1 to 3, further comprising: a connecting area (109) which is located on the lateral surface of the at least one second trench (112), has the second conductivity type and connects the at least one second relaxation area (103) and the at least one fault area (108). [5] Silicon carbide semiconductor unit (710) according to any one of claims 1 to 4, - wherein the at least one second relaxation area (103) has a plurality of second relaxation areas (103) and the plurality of second relaxation areas (103) are arranged such that they are separated from each other, and - wherein at least one fault area (108) has a plurality of fault areas (108) and the plurality of fault areas (108) are arranged such that they are separated from each other. [6] Silicon carbide semiconductor unit (711) according to any one of claims 1 to 4, - wherein the at least one second relaxation area (103) has a plurality of second relaxation areas (103) and the plurality of second relaxation areas (103) are arranged such that they are separated from each other, and - wherein the at least one fault area (108) has a plurality of extending fault areas (108X) that are separate from each other and a connecting fault area (108Y) that connects adjacent of the plurality of extending fault areas (108X). [7] Silicon carbide semiconductor unit (712) according to any one of claims 1 to 4, - wherein at least one fault area (108) has a plurality of fault areas (108) and the plurality of fault areas (108) are arranged such that they are separated from each other, and - wherein the at least one second relaxation area (103) has a plurality of extending relaxation areas (103X) that are separate from each other and a connecting relaxation area (103Y) that connects adjacent of the plurality of extending relaxation areas (103X). [8] Silicon carbide semiconductor unit (704, 709, 710) according to any one of claims 1 to 7, wherein the first trench (12) and the at least one second trench (112) have the same depth. [9] Silicon carbide semiconductor unit (710) according to any one of claims 1 to 8, wherein the at least one second trench (112) has a plurality of second trenches (112) and the plurality of second trenches (112) is arranged in the non-element region (RN).

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