Semiconductor component with a stress compensation layer and method for manufacturing a semiconductor component

Abstract

Semiconductor device (10, 15) comprising: a conductive layer (130) over a semiconductor body (100, 125), an insulating layer (150) adjacent to a main surface (140) of the conductive layer (130) as well as a first stress compensation layer (170) adjacent to a main surface of the insulating layer (150) facing away from the conductive layer, which has a defined first stress, wherein the first stress compensation layer (170) has the same type of stress as the adjacent insulating layer (150).

Description

BACKGROUND

[0001] Semiconductor devices, such as optoelectronic semiconductors, typically contain passivation layers that electrically insulate the components and provide protection against environmental influences. A key reliability characteristic of a semiconductor device is the durability of this passivation layer, which must withstand further processing and the associated mechanical, thermal, and electrical stresses.

[0002] Other semiconductor devices are known, for example, from publications US 2015 / 0 048 484 A1, US 2015 / 0 194 481 A1, US 8 969 109 B1 and US 2010 / 0 051 995 A1.

[0003] Document US 2015 / 0048484A1 relates to a semiconductor device comprising a Group III-V semiconductor substrate, circuit elements in and on the substrate, a first metal layer above the substrate, and an interlayer dielectric (ILD) layer. The ILD layer defines a via extending to the first metal layer. Above the ILD layer are a thick second metal layer and a passivation layer. The second metal layer includes a connection extending through the via to contact with the first metal layer. The second metal layer is structured to define at least one conductor. The passivation layer covers the second metal layer and the interlayer dielectric and includes stacked regions of dielectric material.Areas under tensile stress alternate with areas under compressive stress, so that the passivation layer is subject to a net compressive stress.

[0004] Document US 2015 / 0194481A1 describes a semiconductor structure and a method for its fabrication. The semiconductor structure comprises a substrate, a stacked strip structure, and a tensile strip. The stacked strip structure is formed vertically on the substrate and is subject to compressive stress. It includes multiple conductive strips and multiple insulating strips, the conductive and insulating strips being interwoven. The tensile strip is formed on top of the stacked strip structure and is subject to tensile stress.

[0005] Document US 8,969,109 B1 relates to a method for manufacturing a light-emitting diode (LED) in which a first tensile stress level is determined, which is to be applied to a base substrate with multiple quantum well layers in order to adjust the band gap of the base substrate to a predetermined band gap. The first tensile stress level is generated in the base substrate by forming a tensile stress layer on the base substrate.

[0006] Document US 2010 / 0051995A1 describes a method for manufacturing a semiconductor light-emitting device, which includes depositing a semiconductor light-emitting device onto a mounting element. The semiconductor light-emitting device comprises a stacked structural unit with a first semiconductor layer, a second semiconductor layer, and a light-emitting layer arranged between the first and second semiconductor layers; a first electrode provided on a major surface of the stacked structural unit for contact with the first semiconductor layer; a second electrode provided on the major surface of the stacked structural unit for contact with the second semiconductor layer; and a dielectric stacked film provided on the major surface of the first and second semiconductor layers.which is not covered by the first and second electrodes, and which is formed from stacked dielectric films with different refractive indices and comprises a protruding section erected on at least one section of an edge of at least one of the first and second electrodes. The fastening element comprises a connecting element that is connected to at least one of the first and second electrodes. The method further comprises connecting the connecting element to at least one of the first and second electrodes using the protruding section as a guide.

[0007] The present invention is based on the objective of providing an improved semiconductor device and an improved method for manufacturing a semiconductor device.

[0008] According to the present invention, the problem is solved by the subject matter or the method of the independent claims. SUMMARY

[0009] A semiconductor device comprises a conductive layer over a semiconductor body, an insulating layer adjacent to the conductive layer, and a first stress compensation layer adjacent to the insulating layer. The stress compensation layer exhibits a defined first stress. For example, an absolute value of the stress is greater than a predetermined limit.

[0010] According to further embodiments, a semiconductor device comprises a conductive layer over a semiconductor body and a first stress compensation layer adjacent to the conductive layer. The stress compensation layer exhibits a defined first stress. For example, an absolute value of the stress is greater than a predetermined limit.

[0011] The initial stress can be set by adjusting deposition parameters. For example, compressive stress can be generated by increasing the RF power and pressure during deposition. Conversely, tensile stress can be generated by decreasing the pressure and RF power during deposition. In particular, stable stress can be achieved during PECVD deposition due to the high temperature involved (approximately 300°C).

[0012] For example, the first stress can be matched to the stress of a layer located between the stress compensation layer and the semiconductor body. "Matched" in this context means that the stress has the same sign. Furthermore, the magnitude of the stress is of a similar order of magnitude, i.e., it has the same or a comparable order of magnitude. If this layer exhibits tensile stress, for example, the first stress can also be tensile stress. If this layer exhibits compressive stress, the first stress can also be compressive stress. The layer located between the stress compensation layer and the semiconductor body can be either an insulating or a conductive layer.

[0013] For example, the first stress compensation layer contains or consists of silicon oxide. The first strain can be a compressive strain. The semiconductor device can further include a second stress compensation layer with a defined second strain, which is arranged above the first stress compensation layer.

[0014] The semiconductor device can also contain a third stress compensation layer with a defined third strain, which is arranged above the second stress compensation layer.

[0015] According to various embodiments, the first stress can be a tensile stress. The second stress can be a compressive or a tensile stress. The third stress can be a compressive stress.

[0016] In the presence of a second stress compensation layer, the initial stress of the first stress compensation layer can be selected based on the stress of the adjacent insulating or conductive layer. If the adjacent insulating or conductive layer exhibits compressive stress, then the first stress compensation layer will also exhibit compressive stress. If the adjacent insulating or conductive layer exhibits tensile stress, then the first stress compensation layer will also exhibit tensile stress. The second stress compensation layer can exhibit a stress opposite to that of the first.

[0017] The semiconductor device can also include a first stress-relief layer between the first and second stress-compensation layers. In this stress-relief layer, the absolute value of the stress can be less than a predetermined limit. Furthermore, the semiconductor device can include a second stress-relief layer between the second and third stress-compensation layers, in which the absolute value of the stress is also less than the predetermined limit.

[0018] For example, the semiconductor body can be a semiconductor chip, and the conductive layer can be suitable for connecting components of the semiconductor chip with an electrical connection. The semiconductor device can further comprise a substrate, in which the semiconductor chip is mounted onto the substrate via the conductive layer.

[0019] For example, the semiconductor chip could be an LED chip with a first semiconductor layer of one conductivity type and a second semiconductor layer of a second conductivity type. The conductive layer could be electrically connected to either the first or second semiconductor layer. The insulating layer and the stress compensation layer could be components of a passivation layer stack.

[0020] For example, the LED chip can be designed to emit electromagnetic radiation via a first primary surface of the LED chip. Terminals for connecting the first and second semiconductor layers can be located on a second primary surface of the LED chip.

[0021] According to further embodiments, the semiconductor chip can be a laser chip with a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type. The conductive layer can be electrically connected to the first semiconductor layer. The insulating layer and the stress compensation layers can be arranged between the conductive layer and the first semiconductor layer.

[0022] A method for manufacturing a semiconductor device includes forming a conductive layer, forming an insulating layer adjacent to the conductive layer, and forming a first stress compensation layer, which has a defined first strain, over the insulating layer.

[0023] For example, the initial tension can be adjusted by setting the separation parameters.

[0024] The procedure can further include the formation of a first relaxation layer adjacent to the first stress compensation layer, wherein an absolute value of tension in the first relaxation layer is less than a predetermined limit, and the formation of a second stress compensation layer with a defined second tension adjacent to the first relaxation layer.

[0025] The procedure can also include the formation of a second relaxation layer adjacent to the second stress compensation layer, wherein an absolute value of the tension of the second relaxation layer is less than a predetermined limit. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings serve to illustrate exemplary embodiments of the invention. The drawings depict these embodiments and, together with the description, explain them. Further exemplary embodiments and many of the intended advantages will become apparent from the detailed description below. The elements and structures shown in the drawings are not necessarily drawn to scale. Identical reference numerals refer to identical or corresponding elements and structures. Fig. Figure 1A shows a cross-sectional view through parts of a semiconductor device according to embodiments. Fig. Figure 1B shows a cross-sectional view through parts of a semiconductor device according to further embodiments. Fig. Figure 1C shows a cross-sectional view through a part of a semiconductor device according to further embodiments. Fig. Figure 1D shows a cross-sectional view through parts of a semiconductor device according to further embodiments. Fig. Figure 1E shows a cross-sectional view through parts of a semiconductor device according to further embodiments. Fig. Figure 2A shows a cross-sectional view through parts of a semiconductor device when arranged on a support element. Fig. Figure 2B shows a cross-sectional view through parts of an optoelectronic semiconductor device according to embodiments in conjunction with a support element. The Fig. Figures 2C to 2E show cross-sectional views of optoelectronic semiconductor devices according to further embodiments. Fig. Figure 3A shows a cross-sectional view through parts of an optoelectronic semiconductor device according to embodiments. Fig. Figure 3B shows a cross-sectional view through parts of an optoelectronic semiconductor device according to further embodiments. Fig. 4A summarizes a method according to embodiments. Fig. 4B summarizes a method according to further embodiments. DETAILED DESCRIPTION

[0027] The following detailed description refers to the accompanying drawings, which form part of the disclosure and show specific embodiments for illustrative purposes. In this context, directional terminology such as "top," "bottom," "front," "back," "over," "on," "in front," "behind," "front," "back," etc., refers to the orientation of the figures just described. Since the components of the embodiments can be positioned in different orientations, the directional terminology serves only for explanation and is in no way restrictive.

[0028] The description of the embodiments is not limiting, as other embodiments exist and structural or logical modifications can be made without deviating from the scope defined by the claims. In particular, elements of the embodiments described below can be combined with elements of other described embodiments, unless the context indicates otherwise.

[0029] The terms "wafer" or "semiconductor substrate" used in the following description can encompass any semiconductor-based structure that has a semiconductor surface. Wafer and structure are to be understood as including doped and undoped semiconductors, epitaxial semiconductor layers, optionally supported by a substrate, and other semiconductor structures. For example, a layer of a first semiconductor material may be grown on a growth substrate of a second semiconductor material or of an insulating material, such as sapphire. Depending on the intended use, the semiconductor may be based on a direct or an indirect semiconductor material.Examples of semiconductor materials particularly suitable for generating electromagnetic radiation include, in particular, nitride semiconductor compounds, which can generate, for example, ultraviolet, blue, or longer-wavelength light, such as GaN, InGaN, AlN, AlGaN, AlGaInN; phosphide semiconductor compounds, which can generate, for example, green or longer-wavelength light, such as GaAsP, AlGaInP, GaP, AlGaP; and other semiconductor materials such as AlGaAs, SiC, ZnSe, GaAs, ZnO, Ga₂O₃, diamond, hexagonal BN, and combinations of these materials. The stoichiometric ratio of the ternary compounds can vary. Further examples of semiconductor materials include silicon, silicon-germanium, and germanium. In the context of this description, the term "semiconductor" also includes organic semiconductor materials.

[0030] The term "substrate" generally includes insulating, conductive, or semiconductor substrates.

[0031] The terms "lateral" and "horizontal," as used in this description, are intended to describe an orientation or alignment that is essentially parallel to a first surface of a substrate or semiconductor body. This could be, for example, the surface of a wafer, a die, or a chip.

[0032] The horizontal direction can, for example, lie in a plane perpendicular to a growth direction when layers are growing.

[0033] The term “vertical”, as used in this description, is intended to describe an orientation that is essentially perpendicular to the first surface of the substrate or semiconductor body.

[0034] The vertical direction can, for example, correspond to a growth direction when layers are built up.

[0035] Where terms such as "have," "contain," "comprise," "exhibit," and the like are used here, they are open terms that indicate the presence of the elements or characteristics mentioned, but do not exclude the presence of further elements or characteristics. The indefinite and definite articles include both the plural and the singular, unless the context clearly indicates otherwise.

[0036] In the context of this description, the term "electrically connected" means a low-resistance electrical connection between the connected elements. The electrically connected elements do not necessarily have to be directly connected to each other. Other elements can be arranged between electrically connected elements. The term "electrically connected" also includes tunnel contacts between the connected elements.

[0037] In the context of this description, layers exhibiting stress, such as tensile or compressive stress, are specifically described. Generally, stress can be positive or negative, i.e., tensile or compressive. Within the scope of this description, stress refers to a stress that leads to the bending of a suitable substrate material, such as a test wafer, when a corresponding layer is applied to it. In the case of tensile stress, the substrate material with the applied layer assumes a bowl-like or concave shape. In the case of compressive stress, the substrate material with the applied layer assumes a convex shape.

[0038] In the context of this description, the term "defined stress" refers to a stress that is intentionally introduced and whose absolute value is greater than a predetermined limit. For example, a defined stress can be specifically adjusted by setting deposition parameters.

[0039] For example, stress can be measured by measuring wafer deflection on a test wafer. A wafer is stress-free at a pressure between -25 MPa and +25 MPa. If the stress is greater than 25 MPa, it is referred to as tensile stress; if it is less than -25 MPa, it is referred to as compressive stress. Accordingly, a stress compensation layer with tensile stress on a test wafer results in a stress greater than 25 MPa. A stress compensation layer with compressive stress results in a stress less than -25 MPa on a test wafer.

[0040] A relaxation layer on a test wafer results in a stress between -25 MPa and +25 MPa.

[0041] Fig. Figure 1A shows a cross-sectional view through parts of a semiconductor device 10. A conductive layer 130 is arranged over a semiconductor body 100. The conductive layer can be, for example, a metallic layer, such as a layer containing Ni, Zn, Al, Ti, W, or other metals commonly used for metallization in semiconductor devices. The semiconductor body 100, 125 can be, for example, any semiconductor body, such as a semiconductor substrate with semiconductor layers deposited or applied to it. The layers need not necessarily be single-crystal; they can also be amorphous or polycrystalline. The semiconductor body 100, 125 can also contain semiconductor layers without a semiconductor substrate or any other substrate. Other non-semiconductor layers, such as insulating or conductive layers, can be included in the semiconductor body.

[0042] The semiconductor body 100 can, in particular, be a semiconductor chip 125 containing special functional components such as active or passive components, electronic or optoelectronic devices. Examples include, but are not limited to, switching devices, power semiconductor devices, light-receiving devices such as sensors or solar cells, and light-emitting devices such as LEDs or lasers.

[0043] The conductive layer can be formed over a second main surface 120 of the semiconductor body 100, 125 and, for example, be in direct contact with the second main surface. According to further embodiments, additional intermediate layers can also be arranged between the second main surface of the semiconductor body and the conductive layer. An insulating layer 150 borders the conductive layer 130. The insulating layer can, in particular, form part of a passivation layer or a stack of passivation layers. In addition to its insulating properties, such a passivation layer serves as a diffusion barrier against gases, for example, corrosive gases such as water vapor. Examples of the insulating layer include silicon nitride, aluminum oxide, niobium oxide, and silicon oxynitride. For example, the insulating layer can be chemically inert and cause the passivation layer to adhere to the conductive layer.For example, the insulating layer may be subject to tensile stress. This can be a consequence of the manufacturing process of the insulating layer over the conductive layer.

[0044] A first stress compensation layer 170 is arranged adjacent to a first main surface 160 of the insulating layer 150. The first stress compensation layer 170 has a defined first strain. For example, the first stress compensation layer 170 can be a silicon oxide layer. For example, the silicon oxide layer can be TEOS-based, i.e., grown by a deposition process, for example a PECVD process (plasma-enhanced chemical vapor deposition), using TEOS (tetraethyl orthosilicate).

[0045] The first stress can, for example, be a compressive stress. For example, a compressive stress in the first stress compensation layer 170 can compensate for a tensile stress that is present in the insulating layer 150 due to the manufacturing process and is uncontrolled.

[0046] In the context of the present application, the term "over" in relation to deposited layers refers to a distance to a reference layer. For example, when describing a stress compensation layer stack, the feature that a first layer is arranged "over" a second layer means that the first layer has a greater distance to the conductive layer 130 of the semiconductor device than the second layer. Accordingly, the term "over" cannot be suitable to describe a deposition sequence.

[0047] For example, according to embodiments, the insulating layer 150 and the first stress compensation layer 170 can be arranged between semiconductor body 100, 125 and conductive layer 130.

[0048] Fig. Figure 1B shows a cross-section through a portion of a semiconductor device according to further embodiments. In contrast to the semiconductor device in Fig. 1A here represents the first stress of the first stress compensation layer 170, a tensile stress. Furthermore, the semiconductor device 10 or the stress compensation layer stack 165 additionally comprises a second stress compensation layer 175, which is arranged above the first stress compensation layer 170.

[0049] According to embodiments, the second stress compensation layer 175 can be compression-stressed. The tension of the second stress compensation layer 175 can thus be opposite to the tension of the first stress compensation layer 170. The second stress compensation layer 175 can be directly adjacent to the first stress compensation layer 170. According to further embodiments, a first relaxation layer 180 can be arranged between the first and second stress compensation layers 170, 175. The relaxation layer can be a layer in which the absolute value of a stress is less than a predetermined limit. For example, this limit can be 25 MPa. The compensation layer stack can further comprise a second relaxation layer 185 arranged above the second stress compensation layer 175.The presence of the relaxation layer 180 between the first and second stress compensation layers 170, 175 further increases the stability of the compensation layer stack 165. Because the first stress compensation layer 170 has the same type of tension as the insulating layer 150, mechanical and thermal stresses can be compensated for particularly gently, resulting in a stable combination of the compensation layer stack and the insulating layer, and thus making the semiconductor device particularly reliable.

[0050] According to the embodiments described in this description, the stress compensation layer and, optionally, the stress relief layers can each contain or consist of silicon oxide, for example, TEOS-based silicon oxide. Other examples of materials include silicon nitride, aluminum oxide, or zirconium oxide. For example, aluminum oxide or zirconium oxide can be deposited using ALD processes. The stress compensation layers exhibit a defined stress. The stress compensation layers and stress relief layers form a stress compensation layer stack 165. The combination of the stress compensation layer stack 165 and an insulating layer 150 together forms a passivation layer stack 155, which is suitable for mechanically, electrically, and chemically protecting the underlying semiconductor device or the adjacent conductive layer.For example, the passivation layer stack 155 forms a diffusion barrier against corrosive gases such as water vapor.

[0051] Fig. Figure 1C shows a cross-sectional view of a portion of a semiconductor device according to further embodiments. In addition to the ones shown in Fig. In the layers shown in Figure 1B, the stress compensation layer stack 165 further comprises a third stress compensation layer 177, which is arranged above the second relaxation layer 185. The third stress compensation layer 177 exhibits, for example, tension with the same sign as the second stress compensation layer 175. The third stress compensation layer is pressure-stressed. Furthermore, the stress compensation layer stack 165 additionally includes a relaxation layer 187, which is arranged above the third stress compensation layer 177.

[0052] Fig. Figure 1D shows a portion of a semiconductor device according to further embodiments. In contrast to the semiconductor device in Fig. 1C here is the tension of the second stress compensation layer 175, a tensile stress.

[0053] Fig. Figure 1E shows a portion of a semiconductor device according to further embodiments. In contrast to the embodiment shown in Fig. In the embodiments shown in Figure 1A, the insulating layer 150 is omitted, and the first stress compensation layer 170 is directly adjacent to the conductive layer 130. The other components of the device are as described with reference to Fig. 1A described. For example, the first stress compensation layer 170 exhibits the same type of tension as the adjacent conductive layer. If the conductive layer 130 is compression-stressed, then the first stress compensation layer 170 is also compression-stressed. If the conductive layer 130 is tension-stressed, then the first stress compensation layer 170 is also tension-stressed. According to further embodiments, additional stress compensation layers and, optionally, relaxation layers can be provided, as described with reference to the Fig. Described as 1B to 1D, they are arranged above the first stress compensation layer 170.

[0054] In the described embodiments, the total thickness of the stress compensation layer is slightly more than 500 nm, for example, 500 to 1000 nm. The thickness of the individual layers is approximately 120 to 200 nm, for example, 150 to 180 nm. The insulating layer 150 can, for example, have a thickness of more than 200 nm, for example, more than 300 nm, for example, 300 to 400 nm. For example, the thickness of the insulating layer can be less than 1000 nm.

[0055] Overall, it has been shown that it is advantageous to arrange a tensile-stressed first stress compensation layer 170 adjacent to a tensile-stressed insulating layer 150. In this way, the pressure within the stress compensation layer stack 165 can adapt to the tensile stress of the adjacent insulating layer 150. Furthermore, the use of the stress relief layers 180, 185, 187 can achieve greater stability of the deposited layer stack and thus increase the reliability of the semiconductor device.

[0056] Due to the differently stressed layers of the stress compensation layer stack 165, the resulting passivation layer stack 155 can compensate for thermal and mechanical stresses of opposite polarity (extension, contraction). Such thermal and mechanical stresses can occur, in particular, when soldering processes are performed on the semiconductor device. More precisely, the temperature increase associated with a soldering process leads to the generation of stresses within the semiconductor device. By constructing the stress compensation layer stack in the manner described, the stress on the chip can be reduced, thereby improving the reliability of the semiconductor device. Similarly, its robustness against mechanical loads is increased.

[0057] For example, a semiconductor device 10 can be equipped with the described stress compensation layer stack 165, as is used, for example, in the Fig. As shown in Figures 1A to 1D, the semiconductor chip also includes a support element 205. The support element can be applied to one side of an insulation layer stack 221, 226 of the semiconductor chip. The insulation layer stack 221, 226 can include the stress compensation layer stack 165.

[0058] Fig. Figure 2A shows a schematic cross-sectional view of a semiconductor chip 125 with an attached support element 205. The in Fig. The semiconductor device shown in Figure 2A comprises a semiconductor chip, for example, with a semiconductor substrate 230. Various components of the semiconductor device, such as conductive traces, doped areas, active and passive components, resistors, transistors, etc., can be formed in the semiconductor chip 125. The semiconductor chip 125 comprises, for example, a first contact surface 220, which is connected via a contact material 228 to a first component 232 of the semiconductor chip 125. The first contact surface 220 can be connected to a first contact area 206 of the substrate 205. The semiconductor chip 125 also comprises a second contact surface 225, which can be connected, for example, via a contact material 229 to a second contact area 207 of a substrate 205. The second contact surface 225 is, for example, connected to a second component of the semiconductor chip 125.

[0059] For example, a first insulating layer stack 221 is arranged between the semiconductor substrate 230 and the first contact surface 220. The first insulating layer stack 221 can include an insulating layer 150 as discussed above, as well as the stress compensation layer stack 165. For example, the first insulating layer stack 221 can passivate the semiconductor substrate with the components arranged therein.

[0060] Furthermore, a second insulation layer stack 226 can be arranged between the second connection surface 225 and the support element 205. The described compensation layer stack 165, which in relation to the Fig. The compensation layer stack 165, as described in sections 1A to 1D and forming part of the insulation layer stack 221, can therefore be arranged both between the semiconductor substrate and the metallic layer. According to further embodiments, the described compensation layer stack 165 can also be arranged between the metallic layer and an adjacent support element.

[0061] The support element 205 can, for example, also be a semiconductor substrate, for instance with semiconductor components arranged therein. According to further embodiments, however, it can also be a printed circuit board onto which the semiconductor substrate 230 with the components contained therein is soldered. If the semiconductor substrate 230 with the components formed therein is brought into contact with the support element 205 and subsequently heated, a strong thermal and thus associated mechanical stress arises within the semiconductor device. Because the semiconductor device 10 contains stress compensation layers as described, these stresses can be compensated.

[0062] The in Fig. The semiconductor device 10 shown in Figure 2A can be any semiconductor device, such as a switching device (e.g., for logic applications) or an optoelectronic device (e.g., a solar cell). For example, the semiconductor device 10 may not have an outer casing but may be designed to be soldered directly onto the carrier element 205.

[0063] Fig. Figure 2B shows a schematic cross-sectional view of another embodiment of a semiconductor device, which is designed as an optoelectronic semiconductor device 15. The optoelectronic semiconductor device 15 comprises, for example, a transparent insulating substrate 200, which is optional and can be omitted depending on the embodiment. The substrate 200 can, for example, be a sapphire substrate. A first semiconductor layer 212, for example, of a first conductivity type, for example, n-type, is arranged over the substrate 200. A second semiconductor layer 213, for example, of a second conductivity type, for example, p-type, is arranged over the first semiconductor layer 212. For example, an active region 214 can be arranged between the first and second semiconductor layers 212, 213.The active region 214 can, for example, feature a pn junction, a double heterostructure, a single quantum well (SQW), or a multi quantum well (MQW) for radiation generation. The term "quantum well structure" here has no bearing on the dimensionality of the quantization. It thus includes, among other things, quantum wells, quantum wires, and quantum dots, as well as any combination of these layers.

[0064] The electromagnetic radiation 20 emitted by the semiconductor device 15 is emitted, for example, via a first main surface 210 of the substrate 200 or the first semiconductor layer 212. The optoelectronic semiconductor device 20 thus represents a flip-chip device in which contacts for connecting the semiconductor layers are arranged on one side of the semiconductor stack facing away from the light-emitting surface 210. A portion of a metallic layer is arranged adjacent to the second semiconductor layer 213 and forms a second contact surface 225. A portion of another metallic layer is arranged over an insulating layer stack 221 and is electrically connected to the first semiconductor layer 212 via an electrical contact material 218. For example, the first contact surface 220 can be connected to the first semiconductor layer 212 via a contact element 218.The first contact element 218 is arranged in a contact opening 219 and is insulated from the second semiconductor layer 213 by a side wall insulation 217 and the first insulation layer stack 221.

[0065] The optoelectronic semiconductor device 15 further comprises a support element 205, for example a printed circuit board or a semiconductor chip with connection areas 207, 206 arranged therein.

[0066] A second insulating layer stack 226 is arranged over an exposed surface of the second contact surface 225. The first and second insulating layer stacks 221, 226 can each contain an insulating layer 150 as discussed above, as well as the previously described stress compensation layer stack 165. The second insulating layer stack can also be omitted. When the semiconductor chip 125 is applied to the substrate 205 and subsequently heated to perform a joining or soldering process, high temperatures occur, leading to thermal and mechanical stress on the optoelectronic semiconductor device 15. Because the optoelectronic semiconductor device has an insulating layer stack 221, 226 with the described stress compensation layer stack 165, the resulting thermal and mechanical stresses can be efficiently compensated.For example, in the insulation layer stack 221, the insulating layer 150 is formed adjacent to the first contact surface 220. Similarly, in the second insulation layer stack 226, the insulating layer 150 can be formed in contact with the second contact surface 225.

[0067] The Fig. Figures 2C to 2E show cross-sectional views through further examples of optoelectronic semiconductor devices 15, in each case where the substrate 200 is arranged on a side of the optoelectronic semiconductor devices 15 facing away from a light-emitting surface or light-incidence surface. The light-emitting surface or light-incidence surface corresponds to a first main surface 105 of the optoelectronic semiconductor device 15.

[0068] The in Fig. The optoelectronic semiconductor device shown in Figure 2C comprises a first semiconductor layer 212 of a first conductivity type, for example, n- or p-type, a second semiconductor layer 213 of a second conductivity type, for example, p- or n-type, and optionally an active region 214 as described above. The active region 214 can be arranged between the first semiconductor layer 212 and the second semiconductor layer 213. A converter 215 can, for example, be arranged above the second semiconductor layer 213. A second contact surface 225 made of electrically conductive material is electrically connected to the second semiconductor layer 213. For example, the second contact surface 225 can be arranged on a side of the second semiconductor layer 213 facing away from the first semiconductor layer 212.The second contact surface can be located in the region of the first main surface 105 of the optoelectronic semiconductor device. A first contact surface 220, made of electrically conductive material, is electrically connected to the first semiconductor layer 212 and is located on a side of the first semiconductor layer 212 facing away from the second semiconductor layer 213. The stack of first and second semiconductor layers can, for example, be arranged over a substrate 200, which can be made of, for example, an insulating material, a conductive material, or a semiconductor material. The substrate 200 can, for example, be mounted on a support element 205. For example, one or more conductive traces 208 can be arranged in or over the support element 205. The conductive traces 208 can be made of an electrically conductive material.

[0069] According to embodiments, a first stack of insulating layers 221 can be arranged adjacent to the first contact surface 220. For example, it can be arranged between the first contact surface 220 and the substrate 200. For example, the first stack of insulating layers 221 can be approximately the same size as the first contact surface 220 and may not extend over the entire lateral extent of the substrate. According to further embodiments, it can extend over the entire lateral extent of the substrate 200.

[0070] Furthermore, a second stack of insulating layers 226 can be arranged between the substrate 200 and the support element 205. For example, the second stack of insulating layers 226 can border the conductor track 226 at least section by section.

[0071] The first and second insulation layer stacks 221, 226 can each contain an insulating layer 150 as discussed above, as well as the stress compensation layer stack 165 described above.

[0072] Fig. Figure 2D shows a schematic cross-sectional view of an optoelectronic semiconductor device 15 according to further embodiments. Many components of the device are shown in the diagram. Fig. The optoelectronic semiconductor device 15 shown in 2D corresponds to those shown in Fig. 2C are shown. In contrast to Fig. 2C, the substrate 200 is insulating. The conductor track 208 is connected to the first semiconductor layer 212 via a contact element 218. A first insulating layer stack 221, as previously described, can be arranged between the conductor track 208 and the substrate 200. A second insulating layer stack 226 can be arranged between the substrate 200 and the first semiconductor layer 212. The first and second insulating layer stacks 221 and 226 can each contain an insulating layer 150, as discussed above, as well as the previously described stress compensation layer stack 165.

[0073] Fig. Figure 2E shows a schematic cross-sectional view of an optoelectronic semiconductor device 15 according to further embodiments. Many components of the device shown in Figure 2E are shown in Figure 2E. Fig. The optoelectronic semiconductor device 15 shown in Figure 2E corresponds to those shown in the Fig. 2C and Fig. are represented in 2D. Unlike Fig. The substrate 200 is insulating. Furthermore, the second contact surface 225 is arranged on one side of the first semiconductor layer 212. The contact surface 225 is connected to the second semiconductor layer 213, for example, by a contact element 224 that extends through the first semiconductor layer 212 and the active region 214. The contact element 224 can be insulated from the first semiconductor layer 212 and the active region 214 by a sidewall insulation 217. The sidewall insulation 217 can be implemented, for example, by a stack of insulating layers. For example, the first contact surface can be arranged on a side of the substrate 200 facing away from the first semiconductor layer 212. Furthermore, a second stack of insulating layers 226 can be arranged between the second contact surface 225 and the substrate 200. The first contact surface 220 can be connected to the first semiconductor layer 212 via a contact element 218.The contact element 218 can extend through the substrate 200. For example, the first contact surface 220 can be adjacent to the conductor track 208. According to embodiments, a first stack of insulating layers 221 can be arranged on a side of the substrate 200 that is adjacent to the support element 205.

[0074] The first and second insulation layer stacks 221, 226 and, if applicable, the insulation layer stack representing the side wall insulation 217 can each contain an insulating layer 150 as discussed above and the stress compensation layer stack 165 described above.

[0075] Fig. Figure 3A shows a schematic cross-sectional view of an optoelectronic device 15, which is a flip-chip LED chip. A second primary surface 302 of a transparent substrate 300 is roughened, for example, to increase the light extraction efficiency of the optoelectronic semiconductor device. A first primary surface 301 of the transparent substrate 300 serves as the light emission surface of the optoelectronic semiconductor device. A second semiconductor layer 307, for example, of the second conductivity type, such as n-type, is arranged over the second primary surface 302 of the substrate 300. A first semiconductor layer 305 of the first conductivity type, for example, p-type, is arranged over the second semiconductor layer 307. An active region 308 is arranged between the first and second semiconductor layers 305 and 307.The first semiconductor layer 305 is electrically connected to a first contact surface 312 via the mirror layer 310 and a first metal layer 311. The mirror layer 310 can, for example, contain silver. The first metal layer 311 can be made of a conventional metal for contacting the first semiconductor layer 305; specific examples include Au, Ti, Pt, or Ni. A material for the first contact surface 312 can, for example, include Ti, Cr, Al, Mo, Ni, W, AuSn, Sn, Cu, and Pt.

[0076] The second semiconductor layer 307 is connected to a second contact surface 321 via a second metal layer 320. The second metal layer 320 is arranged in a contact opening 319 formed in the first semiconductor layer 305. An electrically insulating material is arranged between the second metal layer 320 and the mirror layer 310, as well as the first metal layer 311. For example, the insulating material can comprise an insulating layer 316 and a stress compensation layer stack 318. For example, the insulating layer 316 can be structured analogously to the insulating layer 150. The insulating layer 316 can adjoin both the first and the second main surface of the second metal layer 320. According to embodiments, however, the insulating layer 316 can also be arranged on only one side of the second metal layer 320.Additionally, the stress compensation layer stack 318 can adjoin the insulating layer 316. The stress compensation layer stack 318 can be arranged similarly to the above. Fig. 1A to 1D are discussed as being trained.

[0077] According to further embodiments, a further insulating layer 314 can be arranged between the first metal layer and the stress compensation layer stack 318. For example, the further insulating layer 314 can be made of Al₂O₃. Parts of the insulating layer 314 can also be formed at other locations adjacent to the first metal layer 311.

[0078] Because the insulating material that isolates the p-contact from the n-contact contains the stress compensation layer stack 318, thermal and mechanical stresses, such as those that occur when the optoelectronic semiconductor device 15 is mounted on a suitable substrate, can be effectively compensated. As a result, the metal layer can be reliably insulated and protected, and the reliability of the optoelectronic semiconductor device can be increased.

[0079] Fig. Figure 3B shows an optoelectronic semiconductor device 15 according to further embodiments. The optoelectronic semiconductor device 15 can, for example, be implemented as a semiconductor laser. The semiconductor laser comprises, for example, a first semiconductor layer 305 of a first conductivity type, for example, p-type, and a second semiconductor layer 307 of a second conductivity type, for example, n-type. An active region 308 is arranged between the first and second semiconductor layers 305, 307. The first and second semiconductor layers 305, 307 each act as waveguide layers. In addition, a suitable first cladding layer 327 of the first conductivity type is arranged adjacent to the first semiconductor layer 305. Furthermore, a second cladding layer 329 of a second conductivity type is arranged adjacent to the second semiconductor layer 307. The second cladding layer 329 is arranged over a substrate 325.The substrate 325 can, for example, be a semiconductor substrate, such as GaN. Furthermore, a conductive layer 321, which forms a second contact surface, is arranged adjacent to one side of the substrate 325. A suitable first metal layer 311 is also arranged as a contact layer to the cladding layer 327. A first contact surface 312 is arranged adjacent to the first metal layer.

[0080] The semiconductor layer sequence can, for example, have a conventional pn junction, a double heterostructure, a single quantum well (SQW) structure, or a multiple quantum well (MQW) structure as its active region. In addition to the active region, the semiconductor layer sequence can include further functional layers and regions, such as p- or n-doped charge carrier transport layers, p- or n-doped confinement, cladding, or waveguide layers, barrier layers, planarization layers, buffer layers, protective layers, and / or electrodes, as well as combinations thereof. The electrodes can each have one or more metal layers containing Ag, Au, Sn, Ti, Pt, Pd, Rh, and / or Ni. Such structures, the active region, or the further functional layers and regions are known to those skilled in the art, particularly with regard to their construction, function, and structure, and are therefore not described in more detail here.

[0081] In addition, additional layers, such as buffer layers, barrier layers and / or protective layers, can also be arranged perpendicular to the growth direction of the semiconductor layer sequence, for example around the semiconductor layer sequence, i.e. on the side faces of the semiconductor layer sequence.

[0082] The stack consisting of the first semiconductor layer 305, the first cladding layer 327, and the first metal layer 311 is structured to form a ridge 30. More precisely, the ridge 30 is formed horizontally along a propagation direction of the generated laser radiation. In particular, such a configuration of the semiconductor layer sequence, also referred to as a "ridge structure," can be suitable, depending on its width and height and through the so-called index guidance resulting from the ridge-shaped structure and an associated refractive index step, for enabling the formation of a transverse fundamental mode in the active region. The ridge can extend, in particular, from the radiation output coupling surface to the side surface of the semiconductor layer sequence opposite the radiation output coupling surface. The radiation output coupling surface runs parallel to the cross-section shown.

[0083] According to embodiments, an insulating material is arranged between the first contact surface 312 and the semiconductor layers of the semiconductor laser. For example, the insulating material comprises an insulating layer 316 and a stress compensation layer stack 318, which, as described in relation to the Fig. 1A to 1D can be discussed. The presence of the stress compensation layer stack 318 between the first contact surface 312 and the semiconductor material allows thermal and mechanical stress, such as that which arises when the first contact surface 312 is soldered onto a suitable support element, to be effectively compensated.

[0084] In the semiconductor device shown, the stress compensation layer stack can also modify the effective refractive index of the adjacent semiconductor material due to the photoelastic effect. For example, a stress-induced anti-guiding effect can be compensated. As a result, the index guidance of the laser mode in the semiconductor laser is improved.

[0085] Fig. 4A summarizes a method according to embodiments.

[0086] A method for manufacturing a semiconductor device comprises forming (S100) a conductive layer over a semiconductor body, forming (S110) an insulating layer adjacent to the conductive layer, and forming (S120) a first stress compensation layer having a defined first strain adjacent to the insulating layer.

[0087] According to further embodiments, the method can further comprise forming (S130) a first relaxation layer adjacent to the first stress compensation layer. The method can further comprise forming (S140) a second stress compensation layer with a defined second stress adjacent to the first relaxation layer. The method can also comprise forming (S150) a second relaxation layer adjacent to the second stress compensation layer. For example, the defined first stress can be a tensile stress. The defined second stress can be a compressive stress. An absolute value of the stress of the first and second relaxation layers can each be less than a predetermined limit value.

[0088] Fig. Section 4B summarizes a method according to embodiments.

[0089] A method for manufacturing a semiconductor device comprises forming (S100) a conductive layer over a semiconductor body and forming (S120) a first stress compensation layer having a defined first strain adjacent to the conductive layer.

[0090] According to further embodiments, the method can further comprise forming (S130) a first relaxation layer adjacent to the first stress compensation layer. The method can further comprise forming (S140) a second stress compensation layer with a defined second stress adjacent to the first relaxation layer. The method can also comprise forming (S150) a second relaxation layer adjacent to the second stress compensation layer. For example, the defined first stress can be a tensile stress. The defined second stress can be a compressive stress. An absolute value of the stress of the first and second relaxation layers can each be less than a predetermined limit value.

[0091] In the described methods, the sequence of steps for forming the conductive layer, the insulating layer, and the first stress compensation layer can vary depending on the layer structure, as long as the formed layers are adjacent to the corresponding layers. For example, the first stress compensation layer can first be formed over a semiconductor body. Subsequently, the insulating layer is formed adjacent to the first stress compensation layer, and the conductive layer is formed adjacent to the insulating layer. The described effect is not, for example, tied to a specific sequence of deposition processes but rather to adjacent layers in the resulting layer stack.

[0092] Similarly, the sequence of further procedural steps is given only as an example and can be arbitrary.

[0093] For example, the stress compensation and relaxation layers can be made of silicon oxide. According to embodiments, they can be formed using a PECVD process with TEOS as the starting material.

[0094] According to embodiments, the type of tension applied to the first stress compensation layer, i.e., whether compressive or tensile, can be selected depending on the type of tension applied to the adjacent conductive or insulating layer. For example, it can be selected so that the type of tension corresponds to the type of tension applied to the adjacent conductive or insulating layer.

[0095] For example, the stress concentration of the stress compensation layers and the relaxation layers can be adjusted by modifying the deposition parameters. For instance, compressive stress can be generated by increasing the RF power and pressure during deposition. Conversely, tensile stress can be generated by decreasing the pressure and RF power during deposition. In particular, stable stress concentrations can be achieved during PECVD deposition due to the high temperature involved (approximately 300°C).

[0096] Although specific embodiments have been illustrated and described herein, those skilled in the art will recognize that the specific embodiments shown and described can be replaced by a multitude of alternative or equivalent embodiments without departing from the scope of protection of the invention. REFERENCE MARK LIST 10 Semiconductor components 15 optoelectronic semiconductor device 20 electromagnetic radiation 100 semiconductor bodies 105 First main surface of the optoelectronic semiconductor device 110 first main surface of the semiconductor body 120 second main surface of the semiconductor body 125 semiconductor chips 130 conductive layer 140 first main surface of the conductive layer 150 insulating layer 155 passivation layer stacks 160 first main surface of the insulating layer 165 stress compensation layer stacks 170 first stress compensation layer 175 second stress compensation layer 177 third stress compensation layer 180 first relaxation layer 185 second relaxation layer 187 third relaxation layer 200 substrate 205 Support element 206 first connection area 207 second connection area 208 conductor track 210 First main surface of the optoelectronic semiconductor device 212 first semiconductor layer 213 second semiconductor layer 214 active area 215 converters 217 Side wall insulation 218 Contact element 219 Contact Opening 220 first connection area 221 first insulation layer stack 224 Contact element 225 second connection surface 226 second insulation layer stack 228 Contact material 229 Contact material 230 Semiconductor substrate 232 first component of the semiconductor device 234 second component of the semiconductor device 300 substrate 301 first main surface of the substrate 302 second main surface of the substrate 305 first semiconductor layer 307 second semiconductor layer 308 active area 310 mirror layer 311 first metal layer 312 first connection surface 314 insulating layer 316 insulating layer 318 Stress compensation layer stack 319 Contact Opening 320 second metal layer 321 second connection surface 325 laser substrate 327 first mantle layer 329 second mantle layer 330 Steg

Claims

[1] Semiconductor device (10, 15) comprising: a conductive layer (130) over a semiconductor body (100, 125), an insulating layer (150) adjacent to a main surface (140) of the conductive layer (130) as well as a first stress compensation layer (170) adjacent to a main surface of the insulating layer (150) facing away from the conductive layer, which has a defined first stress, wherein the first stress compensation layer (170) has the same type of stress as the adjacent insulating layer (150). [2] Semiconductor device (10, 15) according to claim 1, wherein the first stress compensation layer (170) contains silicon oxide. [3] Semiconductor device (10, 15) according to claim 1 or 2, wherein the first stress is a compressive stress. [4] Semiconductor device (10, 15) according to claim 1, further comprising a second stress compensation layer (175) with a defined second strain, which is arranged on a side of the first stress compensation layer (170) facing away from the conductive layer (130). [5] Semiconductor device (10, 15) according to claim 4, further comprising a third stress compensation layer (177) with a defined third strain, which is arranged on a side of the second stress compensation layer (175) facing away from the conductive layer (130). [6] Semiconductor device (10, 15) according to claim 4 or 5, wherein the first strain is a tensile strain. [7] Semiconductor device (10, 15) according to one of claims 3 to 6, wherein the second strain is a compressive strain. [8] Semiconductor device (10, 15) according to claim 5 or 6, wherein the second strain is a tensile strain. [9] Semiconductor device (10, 15) according to any one of claims 5 to 8, wherein the third stress is a compressive stress. [10] Semiconductor device (10, 15) according to one of claims 4 to 9, further comprising a first relaxation layer (180) between the first and the second stress compensation layer (170, 175), wherein an absolute value of a stress is less than a predetermined limit value. [11] Semiconductor device (10, 15) according to claim 10, further comprising a second relaxation layer (185) between the second and third stress compensation layer (175, 177), wherein an absolute value of the strain is less than the predetermined limit value. [12] Semiconductor device (10, 15) comprising: a conductive layer (130) over a semiconductor body (100, 125), a first stress compensation layer (170) adjacent to the conductive layer (130), which has a defined first tension, furthermore with a second stress compensation layer (175) with a defined second tension, which is arranged on a side of the first stress compensation layer (170) facing away from the conductive layer (130), and with a first relaxation layer (180) between the first and second stress compensation layers (170, 175), in which an absolute value of tension is less than a predetermined limit. [13] Semiconductor device (10, 15) comprising: a conductive layer (130) over a semiconductor body (100, 125), an insulating layer (150) adjacent to a main surface (140) of the conductive layer (130) as well as a first stress compensation layer (170) adjacent to a main surface of the insulating layer (150) facing away from the conductive layer, which has a defined first stress, furthermore with a second stress compensation layer (175) with a defined second tension, which is arranged on a side of the first stress compensation layer (170) facing away from the conductive layer (130), and with a first relaxation layer (180) between the first and second stress compensation layers (170, 175), in which an absolute value of tension is less than a predetermined limit. [14] Semiconductor device (10, 15) according to claim 12 or 13, wherein the first strain is adapted to a strain of a layer located between the stress compensation layer (170) and the semiconductor body (100, 125). [15] Semiconductor device (10, 15) according to one of claims 12 to 14, wherein the first stress compensation layer (170) contains silicon oxide. [16] Semiconductor device (10, 15) according to one of claims 12 to 15, wherein the first strain is a compressive strain. [17] Semiconductor device (10, 15) according to one of claims 12 to 16, further comprising a third stress compensation layer (177) with a defined third strain, which is arranged on a side of the second stress compensation layer (175) facing away from the conductive layer (130). [18] Semiconductor device (10, 15) according to claim 17, further comprising a second relaxation layer (185) between the second and third stress compensation layer (175, 177), wherein an absolute value of the stress is less than the predetermined limit value. [19] Semiconductor device (10, 15) according to one of the preceding claims, wherein the semiconductor body (100) is a semiconductor chip (125) and the conductive layer (130) is suitable for connecting components of the semiconductor chip (125) with an electrical connection. [20] Semiconductor device (10, 15) according to claim 19, further comprising a carrier element (205) in which the semiconductor chip (125) is mounted on the carrier element (205) via the conductive layer (130). [21] Semiconductor device (10, 15) according to claim 19 or 20, wherein the semiconductor chip (125) is an LED chip with a first semiconductor layer (212, 305) of a first conductivity type and a second semiconductor layer (213, 307) of a second conductivity type, the conductive layer (130) is electrically connected to the first or second semiconductor layer, and the stress compensation layer (170) is part of a passivation layer stack (155). [22] Semiconductor device (10, 15) according to claim 21, wherein the LED chip is suitable to emit electromagnetic radiation (20) via a first main surface (210) of the LED chip, and Terminals (220, 225) are arranged for contacting the first and second semiconductor layers on a second main surface of the LED chip. [23] Semiconductor device (10, 15) according to claim 19, wherein the semiconductor chip is a laser chip with a first semiconductor layer (305) of a first conductivity type and a second semiconductor layer (307) of a second conductivity type, the conductive layer represents a first electrical contact surface (312) which is electrically connected to the first semiconductor layer (305), and the stress compensation layers (318) are arranged between the first electrical contact surface (312) and the first semiconductor layer (305). [24] Method for manufacturing a semiconductor device (10, 15) comprising: Formation (S100) of a conductive layer (130) over a semiconductor body (100, 125), Formation (S120) of a first stress compensation layer (170) which exhibits a defined first tension, adjacent to the conductive layer (130), where the first tension is set by adjusting separation parameters, Formation (S130) of a first relaxation layer (180) adjacent to the first stress compensation layer (170), wherein an absolute value of tension in the first relaxation layer (180) is less than a predetermined limit; and Formation (S140) of a second stress compensation layer (175) with a defined second tension adjacent to the first relaxation layer (180). [25] Method for manufacturing a semiconductor device comprising (10, 15): Formation (S100) of a conductive layer (130) over a semiconductor body (100, 125), Formation (S110) of an insulating layer (150) over a main surface (140) of the conductive layer (130) as well as Formation (S120) of a first stress compensation layer (170) which has a defined first stress, over a main surface of the insulating layer (150) facing away from the conductive layer (130), where the first tension is set by adjusting separation parameters, Formation (S130) of a first relaxation layer (180) adjacent to the first stress compensation layer (170), wherein an absolute value of tension in the first relaxation layer (180) is less than a predetermined limit; and Formation (S140) of a second stress compensation layer (175) with a defined second tension adjacent to the first relaxation layer (180). [26] Method according to claim 24 or 25, further comprising forming (S150) a second relaxation layer (185) adjacent to the second stress compensation layer (175), wherein an absolute value of the tension of the second relaxation layer (185) is less than a predetermined limit value.

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