Method for producing a semiconductor component by carrying out a plasma treatment and semiconductor component

Abstract

Method for producing a semiconductor device comprising: Performing (S100) a plasma treatment of an exposed surface of a semiconductor material (100), wherein the plasma treatment is performed with halogens and a non-volatile compound (125) is generated on the surface by the plasma treatment; Carrying out (S110) an oxygen plasma treatment after carrying out the plasma treatment with halogens; and Performing (S120) a diffusion process with dopants on the exposed surface after performing the oxygen plasma treatment.

Description

BACKGROUND

[0001] In the manufacture of semiconductor devices, doping processes are used, among other things, to provide the required functionality. For example, such doping processes can involve diffusion processes, for example, from the gas phase.

[0002] In general, attempts are being made to provide improved doping processes.

[0003] Methods for producing semiconductor components are known, for example, from the documents US 2018 / 0 097 145 A1, DE 689 26 656 T2, DE 34 37 120 A1 and US 5 757 039 A.

[0004] The present invention is based on the object of providing an improved method for producing a semiconductor component and an improved semiconductor component.

[0005] According to the present invention, this object is achieved by the method and subject matter of the independent patent claims. Advantageous further developments are defined in the dependent patent claims. SUMMARY

[0006] According to embodiments, a method for manufacturing a semiconductor device comprises performing a plasma treatment of an exposed surface of a semiconductor material with halogens, and performing a diffusion process with dopants or impurities on the exposed surface.

[0007] According to embodiments, the plasma treatment may be performed such that the exposed surface is substantially not etched.

[0008] For example, the dopants or foreign atoms can be diffused from the gas phase or from a solid.

[0009] The dopants can contain zinc. For example, the dopants can be produced by decomposing an organometallic precursor, such as diethylzinc or dimethylzinc. The plasma treatment can be carried out with fluorine, chlorine, or bromine.

[0010] The semiconductor material may be a III-V compound semiconductor material. For example, the semiconductor material contains In x Ga y Al 1-x-y P.

[0011] Quantum wells can be formed in the semiconductor material.

[0012] The method may further comprise performing an oxygen plasma treatment after performing the plasma treatment with halogens and before performing the diffusion process.

[0013] According to embodiments, the method further comprises forming a layer stack comprising a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a quantum well structure between the first semiconductor layer and the second semiconductor layer.

[0014] The process can be carried out area-selectively by forming a diffusion mask. The diffusion mask can be used for the plasma treatment and the diffusion process.

[0015] Additionally, according to embodiments, the layer stack can be structured to form a mesa. A central region of the mesa can be covered by the mask, while a mesa edge can be uncovered. The mesa structuring can occur before or after the plasma treatment and the diffusion step. For example, the mesa can be structured after performing the plasma treatment and the diffusion process. A central region of the mesa can correspond to the first part of the surface of the layer stack. A mesa edge can correspond to the second part of the surface of the layer stack. As a result, the central part of the mesa is arranged in a region of the semiconductor layer stack in which no plasma treatment and no diffusion have taken place. The region of the mesa edge, on the other hand, was subjected to a plasma treatment and a diffusion.

[0016] Further embodiments relate to a semiconductor component that can be produced by the described method. The semiconductor component can be an optoelectronic semiconductor component. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings provide an understanding of embodiments of the invention. The drawings illustrate embodiments and, together with the description, serve to explain the same. Further embodiments and many of the intended advantages will become apparent from the following detailed description. The elements and structures shown in the drawings are not necessarily drawn to scale. Like reference numerals refer to like or corresponding elements and structures. Fig. 1A and Fig. 1B each show a workpiece in the manufacture of a semiconductor device. Fig. 2 illustrates an example of an apparatus in which the method according to embodiments can be performed. Fig. 3 illustrates a method according to embodiments. DETAILED DESCRIPTION

[0018] In the following detailed description, reference is made to the accompanying drawings, which form a part of the disclosure, and in which specific embodiments are shown for purposes of illustration. In this context, directional terminology such as "top," "bottom," "front," "back," "over," "on," "in front of," "behind," "fore," "rear," etc., refers to the orientation of the figures just described. Since the components of the embodiments can be positioned in different orientations, the directional terminology is for the purpose of explanation only and is not limiting in any way.

[0019] For example, elements of embodiments described below may be combined with elements of other described embodiments, unless the context indicates otherwise.

[0020] The terms "wafer" or "semiconductor substrate" used in the following description can encompass any semiconductor-based structure having a semiconductor surface. Wafer and structure are understood to include doped and undoped semiconductors, epitaxial semiconductor layers, optionally supported by a base support, and other semiconductor structures. For example, a layer of a first semiconductor material can be grown on a growth substrate of a second semiconductor material or of an insulating material, for example, on a sapphire substrate. Depending on the intended use, the semiconductor can be based on a direct or indirect semiconductor material.Examples of semiconductor materials particularly suitable for generating electromagnetic radiation include, in particular, nitride semiconductor compounds, which can be used to generate ultraviolet, blue, or longer-wavelength light, for example, such as GaN, InGaN, AlN, AlGaN, AlGaInN, AlGaInBN; phosphide semiconductor compounds, which can be used to generate green or longer-wavelength light, for example, such as GaAsP, AlGaInP, GaP, AlGaP; and other semiconductor materials such as AlGaAs, SiC, ZnSe, GaAs, ZnO, Ga2O3, diamond, hexagonal BN, and combinations of the aforementioned materials. The stoichiometric ratio of the compound semiconductor materials can vary. Further examples of semiconductor materials can include silicon, silicon-germanium, and germanium. In the context of the present description, the term "semiconductor" also includes organic semiconductor materials.

[0021] The term “substrate” generally includes insulating, conductive or semiconductor substrates.

[0022] The terms "lateral" and "horizontal," as used in this description, are intended to describe an orientation or alignment that is substantially parallel to a first surface of a substrate or semiconductor body. This can be, for example, the surface of a wafer or a chip (die).

[0023] The horizontal direction can, for example, lie in a plane perpendicular to a growth direction when growing layers.

[0024] The term "vertical," as used in this description, is intended to describe an orientation that is substantially perpendicular to the first surface of a substrate or semiconductor body. The vertical direction may, for example, correspond to a growth direction during layer growth.

[0025] Where the terms "have," "contain," "comprise," "have," and the like are used here, these are open terms that indicate the presence of the elements or characteristics in question, but do not exclude the presence of further elements or characteristics. The indefinite and definite articles include both the plural and the singular, unless the context clearly indicates otherwise.

[0026] Fig. 1A shows a vertical cross-sectional view of a workpiece 10 during implementation of a method according to embodiments. The workpiece 10 comprises a semiconductor material 100. The semiconductor material 100 may, for example, be a III-V compound semiconductor material. The semiconductor material may, for example, include a phosphide semiconductor material. For example, the semiconductor material 100 may comprise a material of the composition In x Ga y Al 1-x-yP, where x and y can each assume values ​​between 0 and 1. According to further embodiments, the III-V compound material can also be an arsenide compound semiconductor material. For example, the semiconductor material 100 can be a material of the composition Al x Ga 1-x As, where x can take values ​​between 0 and 1.

[0027] The semiconductor material 100 may comprise different layers or regions of different materials.

[0028] According to embodiments, quantum well structures 120 can be arranged in the semiconductor material 100. The quantum well structures can be formed by arranging layers of suitable band gap and layer thickness in the semiconductor material 100. The quantum well structures can, for example, have a single quantum well (SQW) structure or a multi-quantum well (MQW) structure, for example for generating radiation. The term "quantum well structure" has no significance with regard to the dimensionality of the quantization. It thus includes, among other things, quantum wells, quantum wires, and quantum dots, as well as any combination of these layers.

[0029] For example, a mask 115 may be formed over portions of a first main surface 110 of the semiconductor material 100. The mask 115 may, for example, cover a first portion 131 of the surface of the semiconductor material 100. The mask 115 may further not cover a second portion 132 of the surface of the semiconductor material 100, such that the second portion 132 is exposed. The mask 115 may, for example, be a patterned hard mask layer, for example made of silicon oxide, silicon nitride, and other suitable materials. However, the patterned mask 115 may also be a patterned top layer of the first semiconductor layer 113, which is defined by a photoresist layer.

[0030] A method for manufacturing a semiconductor device according to embodiments comprises performing a plasma treatment of an exposed surface region 111 of a semiconductor material 100 with halogens. The exposed surface region is substantially not etched by the plasma treatment. The exposed surface region 111 corresponds to the second part 132 of the surface of the semiconductor material. The method further comprises performing a diffusion process 130 with dopants on the exposed surface.

[0031] The Fig. The workpiece 10 shown in Figure 1A is subjected to a plasma treatment, for example using the plasma treatment device shown in Fig. 2. This plasma treatment modifies the exposed surface 111 of the semiconductor material 100, resulting in a modified surface 126. For example, this modification or conditioning creates a non-volatile compound 125 on the surface, which has a catalytic effect on the subsequent process for introducing atoms from the gas phase or from the solid phase. For example, a surface coating with the process gas can form in the region of the modified surface 126, which catalyzes the subsequent process. The process parameters for the plasma treatment are selected such that the lowest possible removal rate of the semiconductor material is achieved to adequately form the described surface modification.The removal rate is at least a factor of 10, for example, at least a factor of 100, lower than for conventional plasma etching processes using etching gases such as BCl3, Cl2, or SiCl4. For example, the removal rate or etching rate can be less than 1 nm / sec. The term "essentially unetched" means that the removal rate of the semiconductor material is at least a factor of 10 lower than for these conventional plasma etching processes.

[0032] As has been discovered, the corresponding conditioning, i.e., the non-volatile compound 125, can be retained on the modified surface 126 even over a longer period of time. For example, this non-volatile compound 125 can be retained for several months, such as half a year. The non-volatile compound 125, or conditioning, also survives cleaning in an oxygen plasma. For example, cleaning in an oxygen plasma can be performed to remove the photoresist layer used for structuring before a subsequent diffusion process is carried out. Furthermore, the non-volatile compound 125 exhibits sufficient stability at elevated temperatures, such as temperatures greater than 500°C or 520°C, which can occur during a diffusion process.

[0033] According to all embodiments described here, an identical mask 115 can be used for the plasma treatment and the diffusion process.

[0034] As a result of plasma treatment with halogens, a diffusion process 130 for introducing dopants can be greatly accelerated. Furthermore, undesirable surface effects can be suppressed, resulting in improved doping homogeneity.

[0035] For example, the formation of the non-volatile compound 125 lowers the activation energy for the diffusion process, in which the atoms to be diffused are first decomposed and then penetrate into the crystal lattice.

[0036] According to embodiments, the diffusion process can be carried out from the gas phase. For example, a diffusion of zinc atoms can be carried out. A metal-organic precursor material can be used. For example, diethylzinc or dimethylzinc can be provided as the gaseous precursor material. According to further embodiments, the diffusion process can be carried out from the solid phase. For example, a suitable material, such as a zinc compound, can be vapor-deposited onto the exposed surface 111. A subsequent temperature treatment step diffuses the dopants into the semiconductor material 100. The result is the doped region 105.

[0037] Fig. 1B shows a cross-sectional view of a workpiece during implementation of a method according to further embodiments. The semiconductor material 100 comprises a first semiconductor layer 113 of a first conductivity type, for example, p-type, and a second semiconductor layer 114 of a second conductivity type, for example, n-type. A quantum well structure 120, as described above, is arranged between the first and second semiconductor layers 113, 114. For example, the quantum well structure 120 forms an active zone in which electromagnetic radiation can be generated.

[0038] The method according to embodiments as described above is performed. In particular, a plasma treatment of the exposed surface 111 of a semiconductor material 100 with halogens is performed. Furthermore, a diffusion process 130 with dopants is performed on the exposed surface 111.

[0039] In addition, the semiconductor layer stack, which includes the first and second semiconductor layers, as well as the quantum well structure, is structured into a mesa 107. The mesa etching can be performed before or after the diffusion step.

[0040] For example, the mesa etching can be performed such that a central region of the mesa, i.e., a region of the mesa that does not correspond to the mesa edge 108 and that can, for example, be enclosed by the mesa edge 108, is present in the region of the first part 131 of the surface of the layer stack. The mesa edge 108 is present in a second part 132 of the surface of the layer stack. Accordingly, the plasma treatment with halogens and a diffusion of zinc atoms or foreign atoms have taken place at the mesa edge 108 or will take place in a subsequent step. In the central region of the mesa, no plasma treatment with halogens and no diffusion of zinc atoms has taken place and will not take place in any subsequent diffusion step.

[0041] If the mesa etching takes place after performing the plasma treatment, the mask 115 can, for example, be positioned and structured such that the first part 131 of the surface of the layer stack is located at the position of a central region of the mesa 107 to be structured later. Furthermore, the second part 132 of the surface is located at the edge 108 of the mesa to be structured later.

[0042] If the mesa etching takes place before performing the plasma treatment, the mask layer 115 can be structured such that a surface 111 of the semiconductor material 100 is exposed in the region of a mesa edge 108. A central region of the mesa 107 is covered with the mask layer 115. As a result, the plasma treatment and the diffusion process take place in a region of the mesa edge 108. In a central region of the mesa 107, no plasma treatment and no diffusion process take place.

[0043] For example, the diffusion of zinc atoms can cause what is known as intermixing of quantum wells. This shifts the energy levels of the quantum wells 120 at the mesa edge 108, preventing lateral escape of charge carriers at the mesa edge. As a result, non-radiative surface recombination at the side flanks of the mesa can be avoided. In a central region of the mesa, no diffusion occurs. Experimentally, it has been determined that by performing plasma treatment with halogens, a wavelength shift of the electromagnetic radiation can be achieved after a shorter diffusion time. The wavelength shift is achieved by the intermixing of the quantum wells, i.e., the shift of the energy levels within the quantum wells as a result of the diffusion of zinc atoms. The diffusion time can be reduced, for example, to less than 1 / 10 of the original value.

[0044] For example, an improved red LED can be produced using the described method.

[0045] Fig. 2 illustrates a plasma reactor 150 in which the plasma treatment process can be carried out. A workpiece or semiconductor wafer 101, for example, is placed on a lower electrode 151 within the plasma reactor. A suitable bias voltage can be applied between the lower electrode 151 and the upper electrode 153. The lower and upper electrodes 151, 153 are each arranged in a vacuum chamber 152. The vacuum chamber 152 can be evacuated via a vacuum pump 155. Treatment gases 156 can be introduced via an inlet. A high-frequency generator 157 can be operated accordingly. In addition to the treatment gas 156, a carrier gas, for example an inert gas, can also be supplied. Furthermore, the temperature of the wafers or workpieces 10 can be adjusted. By applying a high-frequency voltage, the gas between the electrodes can be caused to glow discharge.This creates a plasma containing ions, electrons, and excited neutral particles. Under suitable process conditions, the incoming ions impact the wafer surface and lead to surface modification. Halogens such as fluorine, chlorine, or bromine can be used as reaction gases.

[0046] After this process has been carried out, and possibly after a longer waiting period, atoms from the gas phase or from the solid phase are introduced via diffusion, so that doping of the semiconductor material takes place.

[0047] According to embodiments, a cleaning step is performed in an oxygen plasma before performing the diffusion process. For example, the plasma treatment can be performed with halogens in a temperature range from room temperature to 200°C, for example, at a temperature below 100°C for a few seconds.

[0048] For example, any semiconductor components for a wide variety of applications can be manufactured using the described method. For example, optoelectronic semiconductor components based on a III-V compound semiconductor material can be manufactured using the described method.

[0049] Fig. Figure 3 summarizes a method according to embodiments. The method comprises performing (S100) a plasma treatment of an exposed surface of a semiconductor material with halogens and performing a diffusion process (S120) with dopants on the exposed surface. According to embodiments, the method may further comprise a cleaning step in an oxygen plasma (S110). This cleaning step (S110) is performed after performing the plasma treatment (S100) and before performing the diffusion process (S120). LIST OF REFERENCE SYMBOLS 10 Workpiece 100 semiconductor material 101 wafers 105 endowed area 107 Mesa 108 Mesarand 110 first main surface of the semiconductor material 111 exposed surface area 113 first semiconductor layer 114 second semiconductor layer 115 Mask 120 quantum well structure 125 non-volatile compound 126 modified surface 130 diffusion processes 131 first part of the surface 132 second part of the surface 150 plasma reactor 151 lower electrode 152 Vacuum Chamber 153 upper electrode 154 Plasma 155 Vacuum pump 156 Treatment gas 157 High-frequency generator

Claims

[1] A method for producing a semiconductor device comprising: Performing (S100) a plasma treatment of an exposed surface of a semiconductor material (100), wherein the plasma treatment is performed with halogens and a non-volatile compound (125) is generated on the surface by the plasma treatment; Carrying out (S110) an oxygen plasma treatment after carrying out the plasma treatment with halogens; and Performing (S120) a diffusion process with dopants on the exposed surface after performing the oxygen plasma treatment. [2] A method according to claim 1, wherein the dopants are diffused from the gas phase. [3] A method according to claim 1, wherein the dopants are diffused from a solid. [4] A method according to claim 2, wherein the dopants contain zinc. [5] A method according to claim 2 or 4, wherein the dopants are produced by decomposition of an organometallic precursor. [6] The process of claim 5, wherein the organometallic precursor comprises diethylzinc or dimethylzinc. [7] A process according to any one of the preceding claims, wherein the halogen plasma treatment is carried out with fluorine. [8] A process according to any one of claims 1 to 6, wherein the halogen plasma treatment is carried out with chlorine. [9] A process according to any one of claims 1 to 6, wherein the halogen plasma treatment is carried out with bromine. [10] Method according to one of the preceding claims, wherein the semiconductor material (100) is a III-V compound semiconductor material. [11] A method according to claim 9, wherein the semiconductor material In x Ga y Al 1-x-y P contains, with 0≤x≤1, 0≤y≤1 and x+y≤1. [12] Method according to one of the preceding claims, in which quantum wells are formed in the semiconductor material. [13] Method according to one of the preceding claims, wherein the semiconductor component is an optoelectronic semiconductor component. [14] A method according to any one of the preceding claims, further comprising: Forming a layer stack comprising a first semiconductor layer (113) of a first conductivity type, a second semiconductor layer (114) of a second conductivity type, and a quantum well structure (120) between the first semiconductor layer (113) and the second semiconductor layer (114); Forming a mask (115), before carrying out the plasma treatment and the diffusion process (S100, S120), by which a first part (131) of a surface of the layer stack is covered and a second part (132) of the surface of the layer stack is uncovered. [15] The method of claim 14, wherein the mask covers the first part (131) of the surface of the layer stack during the plasma treatment and during the diffusion process. [16] The method of claim 14 or 15, further comprising: Structuring the layer stack into a mesa (107). [17] Method according to claim 16, wherein the mesa is structured after performing the plasma treatment and the diffusion process (S100, S120), wherein a central region of the mesa corresponds to the first part (131) of the surface of the layer stack and a mesa edge (108) corresponds to the second part (132) of the surface of the layer stack. [18] Semiconductor component which can be produced by the method according to one of claims 1 to 17. [19] A semiconductor device according to claim 18, wherein the semiconductor device is an optoelectronic semiconductor device.

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