FLASH STORAGE ARCHITECTURE IMPLEMENTING INTERCONNECTION REDUNDANCY

Abstract

A memory architecture (100) comprising - a plurality of subarrays (110) of memory cells, - a plurality of sense amplifiers (120) connected to the subarrays (110); - a variety of original pads (OP); - at least one redundant pad (RP); - multiple data lines (DL); - a redundant register (200) connected to the plurality of original pads (OP), to the at least one redundant pad (RP) and to the plurality of data lines (DL); and - a selection circuit (300) connected to the redundant register (200), to the plurality of original pads (OP) and to the at least one redundant pad (RP) and configured to implement connection redundancy and connect the at least one redundant pad (RP) to the plurality of data lines (DL) when it is determined that an addressed original pad (OP) is defective by replacing a corresponding address of the defective original pad (OP) with an address of the at least one redundant pad (RP) using the redundant register (200).

Description

TECHNICAL FIELD

[0001] The present invention relates to a flash memory architecture and, more particularly, to a flash memory architecture implementing interconnect redundancy. STATE OF THE ART

[0002] Non-volatile memories can provide persistent data by retaining stored data when power is not applied and may include, but are not limited to, NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistance-variable memories such as phase-change random access memory (PCRAM), chalcogenide-based self-selecting memory, resistive random access memory (RRAM), 3D X-point memory (3DXP), and magnetoresistive random access memory (MRAM).

[0003] Flash memory is a type of non-volatile memory that stores stored data and is characterized by very fast access times. It can also be erased block by block, not by byte. Each erasable memory block comprises a plurality of non-volatile memory cells arranged in a matrix of rows and columns. Each cell is connected to an access line and / or multiple data lines. The cells are programmed and erased by manipulating the voltages on the access and data lines.

[0004] Non-volatile flash memory is one of the fundamental building blocks in modern electronic systems, especially for real-time operating systems (RTOS). The operation of non-volatile flash memory is managed by a controller containing embedded firmware, which performs the necessary read / write / erase operations.

[0005] Memory cells are prone to failure, particularly in very aggressive lithographic nodes. Redundancy is used to bypass defective cells and repair a memory architecture that has failed a test phase or exhibits errors in the field, for what is known as hot redundancy. The cause of the defect can be various, e.g., spent cells, defective oxides within the cell, defects in the connection to the physical cell, e.g., broken vias, a short end cap, an oxide defect, etc.

[0006] In NOR memory devices, redundancy typically occurs column-by-column. Specifically, redundancy repairs local defects by replacing a physical column containing defective cells or cells with another without defects. The redundancy columns are typically positioned at a boundary of the memory array.

[0007] The implementation of redundancy can be done by linking an address of a defective column and a new destination address of a redundant column, so that when the defective column is addressed, the storage device activates the redundancy to store / read the contents in the other redundant column which is not defective.

[0008] Currently, the technology of complex semiconductor structures known as systems-on-chips (SoCs) allows for the integration of at least one embedded non-volatile memory into the system. However, with current technologies, embedded memory becomes a large macro in an SoC, and it is not effective to increase its size to, for example, more than 128 Mbit. In other words, embedded memory currently has a minimal, non-integratable density.

[0009] In other words, embedded memory in SoCs becomes increasingly difficult to manage when the lithography node is below a technology boundary, for example below 28 nm.

[0010] US 2015 / 0363258 A1 relates to a device with an adaptive repair circuit capable of supporting various repair schemes. The invention enables faulty signal paths—particularly in connecting elements between devices or subsystems—to be dynamically compensated on the hardware side, without relying on purely software-based recovery mechanisms. For this purpose, an additional, selectively usable repair signal path is provided, which can be activated depending on a mode signal and a fault information signal. The system aims to improve the reliability and flexibility of complex semiconductor devices and systems, particularly in high-performance applications.

[0011] The connection between embedded memory and other parts of an SoC also raises fault tolerance issues related to the contact between the memory pads and the system.

[0012] Large connecting devices, such as flash memory in an SoC, also called embedded flash replacement, can therefore suffer from defects due to interconnectivity, regardless of the redundancy strategy applied to the flash memory architecture.

[0013] The presence of a defect on connected pads can completely compromise the function of the SoC with the flash memory, wasting a large amount of money because the SoC, embedded flash and package must be discarded, completely wasting the corresponding silicon costs.

[0014] Therefore, there is a need to provide a solution for defects associated with the connection pads of an embedded flash memory and a SoC, which allows to repair the already stacked device and improve the yield of a manufacturing process of such systems. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A shows a block diagram of a flash memory subarray with sense amplifiers and a boundary cell; Fig. Figure 1B shows an enlarged view of a detail of the flash memory subarray of Fig. 1A; Fig. 2A shows a redundant register implementing single-pad interconnect redundancy according to an embodiment of the present disclosure; Fig. 2A shows a redundant register implementing single-pad interconnect redundancy according to an embodiment of the present disclosure; Fig. Figure 2C shows a flash memory architecture that provides interconnect redundancy using the redundant register of Fig. 2A implemented according to an embodiment of the present disclosure; Fig. 3A and Fig. 3B show various working conditions of a selection circuit of a flash memory architecture that provides connection redundancy using the redundant register of Fig. 2A implemented according to an embodiment of the present disclosure; Fig. 4 and Fig. 5 illustrate an exemplary method for managing interconnect redundancy of a storage architecture according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] With reference to these figures, a memory architecture is disclosed herein comprising an array of memory cells, in particular a flash memory array provided with a selection circuit implementing interconnect redundancy.

[0016] The exemplary embodiment of Fig. 1A is a memory architecture 100 having a flash memory subarray 110, wherein the memory architecture includes multiple subarrays all having the same structure.

[0017] In particular, the flash memory subarray 110 is connected to a sense amplifier 120, which in turn is connected to a boundary or Jtag cell 130 capable of managing serial input and output data SIN and SOUT, as well as parallel input and output data, PIN and POUT, respectively.

[0018] The parallel output data POUT is provided to an SoC (not shown) that includes the memory architecture 100. The memory architecture 100 is connected to the SoC using any packaging techniques.

[0019] A low-signal-count interface 140 with the ability to modify the internal content of the flash memory subarray 110, in particular using functional pins and corresponding signals TDI, TDO, tms, tck, trst according to the Jtag protocol, could also be integrated in the memory architecture 100 between the sense amplifiers 120 and the SoC, which are connected to the Jtag cells 130, whose parallel outputs POUT form connection channels 150 with the SoC, as in Fig. 1B shown.

[0020] As explained in the following description, memory architecture 100 implements interconnect redundancy that can correct defects associated with the interconnects between memory architecture 100 and the SoC comprising it. The redundancy is replicated for each subarray of the memory architecture, with the subarray outputs being the interconnect channels 150 to an SoC not shown in the figures.

[0021] In particular, interconnect defects are associated with defective pads or a defective connection between pads, and the memory architecture 100 according to embodiments of the present disclosure provides redundancy for all possible defective or misconnected pads.

[0022] According to the division of a memory architecture into a plurality of subarrays, 168 pads per channel is the currently desired implementation for a flash memory architecture to be embedded in an SoC. Suitably, the present disclosure refers to a memory architecture 100 that manages one or more defects on one of the 168 pads.

[0023] To implement connection redundancy, the memory architecture 100 suitably comprises a redundant register 200, which is schematically shown in Fig. 2A. The redundant register 200 is addressed via a JTAG port in the case of factory redundancy and via the flash controller or the host in the case of on-site redundancy to properly set the redundancy, with or without the low pin count interface 140, such as a JTAG interface.

[0024] In particular, as in Fig. As shown in Figure 2A, the redundant register 200 receives for each extended page of the flash memory subarray 110 from the communication channel a bit address of an addressed memory cell of the flash memory subarray 110 that is connected to a corresponding addressed pad. This bit address is provided by a sufficient number of bits to identify the defective pad, for example, 8 bits to address 256 possible defective pads, sufficient for the embodiment of 168 pads per channel and thus capable of managing one defective pad. The pads bar for each flash memory subarray 110 is shown in Fig. 2A is designated 210.

[0025] The redundant register 200 stores the information to enable redundancy using the JTAG interface; the register can be programmed in the factory and / or by the flash controller and / or the SoC if on-field redundancy, also called "on the fly," is implemented and available. Specifically, if redundancy is implemented during operation, the JTAG and / or the SoC and / or the host can be used to program the register.

[0026] In addition, when an address bus is cached, it is used as a read address in the raw data buffers associated with the raw address buffers.

[0027] As will become clear from the following description, the redundant register 200 implements error trapping logic that is always on and compares each address used by each flash memory subarray 110 of the memory architecture 100 and the SoC that embeds it to ensure that the data is correctly routed to the SoC.

[0028] When implementing single-pad redundancy, the redundancy register 200 according to the embodiment shown in Fig. 2A includes a first section 220 which is a 1-bit redundancy flag (ON / OFF) indicating the use of redundancy, a second section 230 for storing a location or address of the pads out of 168 that are defective, and a third section 240 for storing another location or address of a spare pad used as a redundant resource.

[0029] When implementing multipad redundancy, the redundancy register 200 comprises the Fig. 2B, for up to 4 pads redundancy, a first section 220, which is a 1-bit redundancy flag (ON / OFF) indicating the use of redundancy; a second section 230 with 4 (in the example described here) groups of bits for storing four locations or addresses of the 168 pads that are defective (for example, each group contains 8 bits to address 256 possible combinations and thus one of the 168 potentially defective pads); and a third section 240 for storing another location or address of four spare pads used as redundant resources.

[0030] It can be indicated that the multipad redundancy is thus implemented by increasing the defective pad position fields of the second section 230 and by increasing the redundant resource bits of the third section 240; According to an example with reference to the Fig. 2B, the position fields of the defective pads are 8 bits, and the second section 230 is thus 8 bits multiplied by 4, i.e., the number of pads that can be used for redundancy, and similarly, the bits of the redundant resource are up to 4, each bit allowing the interception of the defective pad in the channel according to the following logic: Bit 0: Redundancy Resource Pad 0 Bit 1: Redundancy Resource Pad 1 Bit 2: Redundancy Resource Pad 2 Bit 3: Redundancy Resource Pad 3

[0031] In particular, according to the single-pad redundancy embodiment of the present disclosure, only one spare pad is used, with the third portion 240 being a 1-bit field, essentially another flag. In some embodiments, such a third portion or another flag is not used, and the only redundancy resource pad is directly activated; for example, the pad may be hard-wired. According to the multi-pad redundancy embodiment, more than one spare pad is used, with the third portion 240 comprising more than one bit, for example, a 4-bit field capable of implementing up to four redundant locations or addresses of the spare pads with four 8-bit fields of the second portion 230.

[0032] It can thus be indicated that the first section 220 of the redundant register 200 is a flag indicating that redundancy is ON, the second section 230 of the redundant register 200 is a defective pad area, and the third section 240 of the redundant register 200 is a redundancy resource field.

[0033] According to the embodiment, when a pad is found to be defective, its address is stored in the second section 230, and the redundancy flag of the first section 220 is activated (ON), so that one of the redundant pads enabled by the further enable signal stored in the third part 240 is switched to the defective one. In other words, when the redundancy flag of the first section 220 is ON, the corresponding logic trap defects are always enabled and compare each address used by each flash memory subarray 110 to replace the address of memory cells corresponding to the pads found to be defective.

[0034] In particular, the redundancy flag of the first section 220 is ON, and the content of the third section 240, which is the redundant resource, is used to send the data to the SoC.

[0035] During normal operation, the universe of pads is monitored and compared with the universe of defective pad location sections of the entire redundant enable registers; when the defective location is addressed, the switch is executed with the redundant resources, checking the redundancy flag of the first section 220 for its own status: enable or disable, i.e., ON or OFF.

[0036] In case the enable status is set (ON), the redundant pad whose address is stored in the third section 240 is routed using a multi-channel MUX to replace the defective pad whose address is stored in the second section 230.

[0037] The redundancy register 200 is replicated in each sub-array, and the contents of the corresponding sections 220, 230, and 240 are stored in the flash configuration area because the corresponding stored data is stored only once as other setting data.

[0038] As already indicated, according to the embodiments of the disclosure, after powering up the flash memory architecture 100 and embedding the SoC, the redundancy is always turned on to continuously monitor the communication channel, i.e., 168 pads, in the case exemplified in the present description.

[0039] In the case of a multi-tiered memory architecture 100, a defective pad must be replaced for all layers or pages connected to such defective pad.

[0040] In the case of an embedded flash replacement architecture, as shown schematically in Fig. As shown in Figure 2C, the redundant register 200, also referred to as Red_R, is normally divided into a high page 200H and a low page 200L.

[0041] According to the interconnect redundancy mechanism explained above, if a defective pad is found and the redundancy flag of the first section 220 is enabled (ON), the redundancy register 200 replaces an original cell address 230H with a redundant cell address 240H in the high page 200H, and an original cell address 230L with a redundant cell address 240L in the low page 200L. Pad redundancy applies to all extended pages of the subarray and all data in [the original page] if the defect is in the used pads, as in flexible TDIs.

[0042] In particular, a MUX 250 receives the parallel output data POUT of the redundant cells 240H and 240L instead of the parallel output data POUT of the original cells 230H and 230L when the redundancy flag 220 is enabled or turned on. The functionality of the MUX 250 is described below with reference to the Fig. 3A and Fig. 3B described.

[0043] The memory architecture 100 includes a selection circuit 300 for implementing interconnect redundancy according to an embodiment of the disclosure, as shown in Fig. 3A shown.

[0044] The selection circuit 300 is connected to a pad of the memory architecture 100, referred to as the original pad OP, and to at least one redundant pad RP, and receives addresses and enable signals from the redundant register 200.

[0045] Specifically, the selection circuit 300 includes a first switch SW1 inserted between a plurality of data lines DL and the original pad OP, and a second switch SW2 inserted between the data lines DL and the redundant pad RP. The first switch SW1 is controlled by a first redundancy signal RS1, which is an inverted value of the redundancy flag stored in the first section 220 of the redundancy register 200, obtained by an inverting gate INV, while the second switch SW2 is controlled by a combination between a first redundant signal RS1 and a second redundant signal RS2, which are stored in the third section 240 of the redundant register 200, obtained by a logic gate LG, which is an AND gate.

[0046] In the exemplary embodiment of Fig. 3A, the communication channel provides the redundancy register 200 with an address corresponding to a bit found to be associated with a correctly functioning original pad OP, whose address AddOP is stored in the second section 230 of the redundancy register 200. In particular, bit #4 (000...1000) of a memory page is associated with a "correct," i.e., a non-defective, original pad OP.

[0047] In this case, the enable flag stored in the first section 220 is set to 1, so that the first redundant signal RS1 is set to 0 and the first switch SW1 is closed by the inverted value equal to 1. Furthermore, regardless of the value of the second redundant signal RS2, the logic gate LG opens the second switch SW2 because the first redundant signal RS1 is set to 0.

[0048] In this way, the data from the data lines DL is delivered to the original pad OP, which operates correctly.

[0049] In the embodiment of Fig. 3B, the communication channel provides the redundant register 200 with an address corresponding to a bit found to be associated with a defective original pad OP, whose address AddOP is stored in the second portion 230 of the redundant register 200. In particular, bit #4 (000...1000) of a memory page is associated with a "bad," ie, a defective, original pad OP.

[0050] In this case, the enable flag stored in the first part 220 is set to 0, so that the first redundancy signal RS1 is set to 1 and the first switch SW1 is opened by the inverted value 0. In addition, the value of the second redundancy signal RS2 is set to 1, so that the logic gate LG, which also receives the first redundancy signal RS1, which is set to 1, closes the second switch SW2.

[0051] In this way, the data from the data lines DL is delivered to the redundant pad RP, effectively bypassing the original pad OP, which is not working correctly.

[0052] The redundancy register 200 and the selection circuit 300 thus form a connection redundancy management block included in the memory architecture 100.

[0053] The Fig. 3A and Fig. The exemplary configurations shown in Figure 3B refer to a single defective pad, but it should be immediately verified that the selection circuit 300 can implement the proposed connection redundancy for any number of defective pads up to 168 by increasing the number of registers to hold the defective pad and the new one.

[0054] The memory architecture 100 may be included, in particular embedded, in a system-on-chip (SoC) component, and the interconnect redundancy may be applied to pads connected to the SoC.

[0055] An exemplary method for managing the interconnect redundancy of a memory architecture 100 comprising a plurality of subarrays of memory cells and a plurality of original pads OP is schematically illustrated in Fig. 4, wherein the method 400 comprises the steps: - Step 410: Verify the correct functioning of one of the original pads OP; and - Step 420: if the original pad OP is working correctly, connect the original pad OP to several data lines DL; or - Step 430: If the original pad OP is not working properly, connect a redundant pad RP to the data lines DL.

[0056] With reference to Fig.5, the method 500 comprises in particular the steps: - Step 510: Storing information using the Jtag interface to enable redundancy; - Step 520: Storing a redundancy flag in a first section 220 of the redundancy register 200 to indicate the use of a redundancy pad RP; a first redundancy signal RS1 is associated with the redundancy flag; - Step 530: Storing an address of a defective original pad OP, which is to be switched with the redundant pad RP, in a second section 230 of the redundant register 200; and - Step 540: Storing in a third section 240 of the redundant register 200 for addressing the redundant pad RP if the original pad OP is defective because it is not functioning properly; a second redundant signal RS2 is associated with the address stored in the third section 240.

[0057] It should be noted that the redundancy register 200 includes only one redundancy flag per flash memory subarray 110. In particular, in the case of a multi-position defect, the redundancy flag enabling redundancy does not need to be repeated.

[0058] In summary, the present disclosure provides a memory architecture comprising a plurality of subarrays, each of which is provided with a connection redundancy mechanism implemented by a selection circuit connected to a redundant register.

[0059] In this way, latent defects and / or lifetime defects can be hot-fixed by a SoC that includes the memory architecture, using firmware routines that can correctly control the redundant register and thus the associated selection circuitry.

[0060] It is emphasized that the number of redundant pads used can be adjusted as needed by simply managing the address to be stored and the activation flag.

[0061] The exemplary memory architecture that implements interconnect redundancy also improves the security of the memory and the SoC; in particular, interconnect redundancy allows for reset of errors due to defective or misconnected pads, thereby increasing ECC coverage, with ECC protecting the system from a single defect.

[0062] In addition, interconnect redundancy is appropriately replicated for each subarray of the storage architecture.

[0063] It should also be noted that the redundant register, which is implemented in particular in the Embedded Flash Replacement Device, is located in the SoC, so that the read page was redirected somewhat elsewhere.

[0064] In this way, interconnect redundancy is a transparent strategy.

[0065] In addition, the redundant register is addressed using the low signal count interface 140 or the Jtag interface with or without a flexible TDI, which is a programmable option to improve the overall performance of the memory architecture.

[0066] The size of the redundant registers would depend on the number of possible redundant pads, with complete interconnect redundancy theoretically possible.

[0067] In a real implementation, the number of possible redundant pads and defects that can be corrected is limited by the yield study and / or the pad topology. In some embodiments, each channel (150 or 210) has its own redundant pad resources to repair one or more defective pads (among the 168 pads in the example described above). In other embodiments, the redundant pad resources may be shared between different channels; for example, a spare pad resource may be addressed for redundancy to replace defective pads in one of the system's interconnect channels.For example, the redundant registers 200 of different channels may indicate that redundancy is enabled (in the first section 220), store the address of the faulty pad (in the second section 230), and store (in the third section 240) a position or address of a spare pad used as a redundant resource, where the redundant resource is a shared resource.

[0068] Finally, it should be emphasized that the defective pads are also stored in the SoC in order to be able to read the content of a defective pad in the redundant pad instead of the original.

[0069] In the foregoing detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which specific examples are shown by way of illustration. In the drawings, like reference numerals throughout the several views describe substantially similar components. Other examples may be utilized, and structural, logical, and / or electrical changes may be made without departing from the scope of the present disclosure.

[0070] Similar elements or components in different figures may be identified by the use of like numerals. It is understood that elements shown in the various embodiments herein may be added, substituted, and / or omitted to provide a number of additional embodiments of the present disclosure. Furthermore, the proportions and / or relative scale of the elements provided in the figures are intended to illustrate particular embodiments of the present disclosure and should not be construed in a limiting sense.

[0071] As used herein, "a," or "a number of," can refer to one or more of such things. A "plurality" of something contemplates two or more. As used herein, the term "coupled" can encompass electrically coupled, directly coupled and / or directly connected without intervening elements (e.g., through direct physical contact), or indirectly coupled and / or connected with intervening elements. The term coupled can further encompass two or more elements that cooperate or interact with each other (e.g., as in a cause-and-effect relationship).

Claims

[1] A memory architecture (100) comprising - a plurality of subarrays (110) of memory cells, - a plurality of sense amplifiers (120) connected to the subarrays (110); - a variety of original pads (OP); - at least one redundant pad (RP); - multiple data lines (DL); - a redundant register (200) connected to the plurality of original pads (OP), to the at least one redundant pad (RP) and to the plurality of data lines (DL); and - a selection circuit (300) connected to the redundant register (200), to the plurality of original pads (OP) and to the at least one redundant pad (RP) and configured to implement connection redundancy and connect the at least one redundant pad (RP) to the plurality of data lines (DL) when it is determined that an addressed original pad (OP) is defective by replacing a corresponding address of the defective original pad (OP) with an address of the at least one redundant pad (RP) using the redundant register (200). [2] The memory architecture (100) of claim 1, wherein the redundant register (200) comprises a first portion (220) for indicating the use of the at least one redundant pad (RP) by storing a redundant flag. [3] The memory architecture (100) of claim 2, wherein the redundant register (200) further comprises a second portion (230) for storing the address of the defective original pad (OP) to be switched with the at least one redundant pad (RP). [4] The memory architecture (100) of claim 3, wherein the redundant register (200) further comprises a third portion (240) for storing the address of the at least one redundant pad (RP). [5] The memory architecture (100) of claim 4, wherein the selection circuit (300) comprises: - a first switch (SW1) inserted between the plurality of data lines (DL) and one of the plurality of original pads (OP); - a second switch (SW2) inserted between the plurality of data lines (DL) and the at least one redundant pad (RP); - an inverting gate (INV) receiving a first redundant signal (RS1) associated with the redundancy flag stored in the first section (220) of the redundant register (200) and providing an inverted value to command the first switch (SW1); - a logical AND gate (LG) receiving the first redundant signal (RS1) and a second redundant signal (RS2) associated with the address stored in the third section (240) of the redundant register (200) and providing a combined value to command the second switch (SW2). [6] The memory architecture (100) of claim 5, further comprising a MUX (250) receiving the address stored in the third section (240) of the redundant register (200) to replace the defective original pad (OP) whose address is stored in the second section (230) of the redundant register (200). [7] Link redundancy management block, comprising: - a redundancy register (200) connected to a plurality of original pads (OP), to at least one redundant pad (RP) and to a plurality of data lines (DL) for memory cells; and - a selection circuit (300) connected to the redundant register (200), to the plurality of original pads (OP) and to at least one redundant pad (RP) and configured to implement connection redundancy and connect the at least one redundant pad (RP) to the plurality of data lines (DL) when it is determined that an addressed original pad (OP) is defective by replacing a corresponding address of the defective original pad (OP) with an address of the at least one redundant pad (RP) using the redundant register (200). [8] The connection redundancy management block of claim 7, wherein the redundant register (200) comprises: - a first section (220) for indicating the use of the at least one redundant pad (RP) by storing a redundant flag; - a second section (230) for storing the address of the defective original pad (OP) to be switched with the at least one redundant pad (RP); and - a third section (240) for storing the address of the at least one redundant pad (RP). [9] The connection redundancy management block according to claim 8, wherein the selection circuit (300) comprises: - a first switch (SW1) inserted between the plurality of data lines (DL) and one of the plurality of original pads (OP); - a second switch (SW2) inserted between the plurality of data lines (DL) and the at least one redundant pad (RP); - an inverting gate (INV) receiving a first redundant signal (RS1) associated with the redundancy flag stored in the first section (220) of the redundant register (200) and providing an inverted value to command the first switch (SW1); and - a logical AND gate (LG) receiving the first redundant signal (RS1) and a second redundant signal (RS2) associated with the address stored in the third section (240) of the redundant register (200) and providing a combined value to command the second switch (SW2). [10] The interconnect redundancy management block of claim 9, further comprising a MUX (250) receiving the pad address stored in the third section (240) of the redundant register (200) to replace the defective original pad (OP) whose address is stored in the second section (220) of the redundant register (200). [11] A method (400) for managing the connection redundancy of a storage architecture (100) according to any one of the preceding claims, comprising the steps of: - determining (410) that one of a plurality of original pads (OP) of the memory architecture (100) is functioning correctly; and - in response to determining that the original pad (OP) is functioning correctly, connecting the original pad (OP) to multiple data lines (DL); or - If the original pad is not working correctly, connect at least one redundant pad (RP) to the multiple data lines (DL). [12] The method of claim 11, further comprising the steps of: - storing (520) a redundancy flag in a first section (220) of a redundancy register (200) to indicate the use of the at least one redundant pad (RP); - storing (530) a corresponding address of the defective original pad (OP) to be switched with the at least one redundant pad (RP) in a second section (230) of the redundant register (200); and - storing a corresponding address of the at least one redundant pad (RP) in a third section (240) of the redundant register (200) for addressing the at least one redundant pad (RP) when the original pad (OP) is defective by not functioning properly. [13] A system-on-chip, SoC, component comprising: - a plurality of subarrays (110) of memory cells, - a plurality of sense amplifiers (120) connected to the subarrays (110); - a variety of original pads (OP); - at least one redundant pad (RP); - multiple data lines (DL); and - a redundant register (200) connected to the plurality of original pads (OP), to the at least one redundant pad (RP) and to the plurality of data lines (DL); and - a selection circuit (300) connected to the redundant register (200), to the plurality of original pads (OP) and to the at least one redundant pad (RP) and implementing connection redundancy and connecting the at least one redundant pad (RP) to the plurality of data lines (DL) when an addressed original pad (OP) is found to be defective by replacing a corresponding address of the defective original pad (OP) with an address of the at least one redundant pad (RP) using the redundant register (200). [14] The SoC component of claim 13, wherein the redundant register (200) comprises: - a first section (220) for indicating the use of the at least one redundant pad (RP) by storing a redundancy flag; - a second section (230) for storing the address of the defective original pad (OP) to be exchanged with the at least one redundant pad (RP); and - a third section (240) for storing the address of the at least one redundant pad (RP) for addressing the at least one redundant pad (RP). [15] The SoC component of claim 14, wherein the selection circuit (300) comprises: - a first switch (SW1) inserted between the plurality of data lines (DL) and the plurality of original pads (OP); - a second switch (SW2) inserted between the plurality of data lines (DL) and the at least one redundant pad (RP); - a logical AND gate (LG) receiving a first redundant signal (RS1) and a second redundant signal (RS2) associated with the address stored in the third section (240) of the redundant register (200) and providing a combined value to command the second switch (SW2). [16] The SoC component of claim 15, further comprising a MUX (250) that receives the address of the redundant pad (RP) stored in the third section (240) of the redundancy register (200) to replace the defective original pad (OP) whose address is stored in the second section (230) of the redundancy register (200).

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