IMPROVED SECURITY AND CORRECTNESS WHEN READING AND PROGRAMMING DATA IN A NON-VOID STORAGE DEVICE

Abstract

comprising a non-volatile storage device (100): - an array (90) of memory cells with a plurality of memory blocks; - a dummy line (200) corresponding to a memory block (160) of the plurality of memory blocks, for storing a known pattern and a trim parameter, wherein the trim parameter enables the known pattern to be read from outside an address space of the corresponding memory block (160) of the plurality of memory blocks; - a controller (101) of the storage device (100) which is configured to trigger the detection of a thermal drift in a storage block (160) of the multiple storage blocks using the known pattern stored in the dummy line (200) corresponding to the storage block (160) in response to the detection of a temperature change of the storage device (100); - Read circuits controlled by the controller (101) for reading the known pattern stored in the dummy line (200) by executing read cycles and changing the read trim parameter, which is stored in the dummy line (200) for reading the known pattern, until a moment when a value of the known pattern is correctly read, wherein the value of the known pattern is stored in the dummy line (200), wherein the controller (101) is configured such that it: ◯ in a subsequent reading phase, based on a missing trim parameter in the dummy row (200), it is determined that a power loss has occurred; and ◯ In response to the detection of a performance loss, it erases the entire memory block.

Description

TECHNICAL AREA

[0001] The present disclosure relates generally to storage devices and in particular to embodiments relating to security and improved performance in reading and programming data in non-volatile storage devices.

[0002] Embodiments of the present disclosure relate in particular to a method for re-trimming the setting of a memory component in order to improve the cross-temp robustness of the memory device. STATE OF THE ART

[0003] Storage devices are well-known in the field of electronics for storing and accessing digital information. Generally, various types of semiconductor storage devices can be incorporated into more complex systems that include either non-volatile or volatile memory components, such as in so-called system-on-chips (SoCs), where the aforementioned memory components are embedded.

[0004] However, nowadays the need for real-time operating systems, especially for automotive applications, requires SoCs with ever greater performance and efficiency, and the known solutions partially meet these requirements, but not in a cost-effective and profitable way.

[0005] Non-volatile memory can provide persistent data by retaining stored data when it is not powered on, and can include, among others, NAND flash memory, NOR flash memory, 3DXP memory, MRAMs, STTRAMs, and CBRAMs. NAND flash has faster erase and write times and requires less chip area per cell, enabling higher storage density and lower cost per bit than NOR flash. However, the I / O interface of NAND flash does not offer an external address bus with random access. Instead, data must be read in blocks, with typical block sizes ranging from hundreds to thousands of bits.

[0006] Flash memory devices are susceptible to temperature fluctuations, particularly temperature increases during operation. This is primarily due to the fact that when the floating gates forming the memory are biased in the presence of higher temperatures, they can reach an energy level sufficient to cause a jump in the channel, resulting in charge loss. In other technologies, such as those using charge traps, high temperatures accelerate recombination, leading to the loss of stored information. These problems compromise the security and accuracy of data read from the memory device.

[0007] US Patent 2016 / 0342494A1 discloses a storage system with non-volatile memory in which each memory block can be monitored with regard to its state and behavior. For this purpose, one or more dummy word lines are used within each block, which are not accessible for normal data storage. These dummy word lines are programmed with a known data pattern that can be read and analyzed to detect potential errors and represent the health of the memory block. Based on this analysis, the operating parameters, such as read voltages, can be adjusted to optimize the performance of each memory block.

[0008] US patent 2018 / 0293029A1 discloses a storage system comprising non-volatile memory and a controller that responds to temperature differences between data writing and reading. The controller can measure the threshold values ​​(Vt) of memory cells under varying parameters and determine correction values ​​to adjust the read threshold accordingly. Additionally, data written at unusual write temperatures is marked as requiring a refresh or stored with increased reliability. In this way, read parameters are adjusted based on temperature to enhance data integrity and storage reliability.

[0009] US 2016 / 0322108A1 discloses a non-volatile storage system with NAND architecture in which one or more word lines at the ends of a memory block are designated as dummy word lines that are not used for storing user data. These dummy word lines serve to store metadata about the block's state, trim parameters, error statistics, and other status information. Based on this metadata, the memory controller can adjust read parameters or perform block reshuffles.

[0010] One objective of the present disclosure is to provide a flash storage device and a method for reading flash storage devices that reduce the influence of age and temperature on the performance of the storage device, thereby reducing the risk of information loss. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 shows a schematic view of a system with a storage component associated with a controller that exchanges data, address and control signals with the storage device; Fig. Figure 2 is a schematic view of the storage component according to the present disclosure; Fig. Figure 3 is a schematic view of the storage component according to the present disclosure; Fig. Figure 4 is a schematic view of a memory block formed by a plurality of rows of a memory array according to an embodiment of the present disclosure; Fig. Figure 5 is a schematic view of a group of address registers for a memory page in the memory section of the present disclosure; Fig. Figure 6 shows in a schematic diagram the distribution of a well-erased / programmed cell (1 bit / cell); Fig. 7. A diagram accordingly Fig. 6, which shows an enlarged distribution shifted towards the depletion state (negative Vth) due to aging, temperature and stress; Fig. Figure 8 shows in a block diagram the phases of a process according to the present disclosure. DETAILED DESCRIPTION

[0011] The following detailed description refers to the accompanying drawings, which form part of this document and depict specific embodiments for illustrative purposes. In the drawings, the same reference numerals in the different views describe essentially similar components. Other embodiments may also be disclosed, and structural, logical, and electrical modifications may be made without departing from the scope of this disclosure. Therefore, the following detailed description should not be interpreted as limiting.

[0012] Several embodiments of the present disclosure relate to memory devices, systems with memory devices and methods for operating memory devices that avoid potential problems of aging, temperature and process drift during memory operation.

[0013] In one embodiment of the present disclosure, a new storage architecture is provided for improved security and performance of the data read phase in the non-volatile storage device.

[0014] In particular, the present disclosure relates to a non-volatile storage device comprising at least one array of memory cells with a plurality of memory blocks; - at least one dummy row for each block to store at least one known pattern; - a controller of the storage device; - Controlled reading circuits for reading the known pattern stored in the dummy series by performing several read cycles and changing the read trim parameters until the moment the value of the known pattern is read correctly.

[0015] The known pattern is recognized by the memory controller.

[0016] Furthermore, the modified trim parameters of the correct measured value correspond to a set temperature value that was recorded in a programmable register at factory level.

[0017] This dummy line also stores internal block variables from the read and / or erase phase. These internal block variables are parameters such as the read pulses and / or the target voltages applied to the memory block during the read phase.

[0018] For a better understanding of the present disclosure, it should be noted that flash memory typically uses a basic memory element. For example, a transistor is used as the memory element in all technologies that employ a floating gate, a charge trap, a split gate, and the like. Other technologies, such as 3D XPoint memory or phase change memory, use a different type of basic memory element. In all cases, however, there is a need to manage the stored data in a timely manner and to read this data more quickly.

[0019] When addressing a memory array, there can be one or more layers of address translation, for example, a translation between a logical address used by a host device and a physical address corresponding to a location in the memory array. Such a mechanism is very useful for implementing advanced features like block wear leveling and / or factory / on-field block redundancy.

[0020] Although unusual, a power outage can occur during a deletion process. In such a scenario, it is crucial to have a mechanism that allows for the detection of blocks that were not properly or completely deleted. An interruption in deletion causes several problems: 1) Data cannot be programmed, because the memory block can display programmed bits; 2) The block may appear deleted, but has reliability issues, i.e., problems with data storage; 3) The block may appear defective in certain places due to exhausted cells.

[0021] Since a poorly erased block cannot be programmed, it would be extremely important to avoid any unexplained errors during a programming phase of a block in which a power outage has occurred.

[0022] In some embodiments, during each power-on and / or reset phase and / or at user request, all blocks in the array are checked to determine if any of them are in a power-off state. This can be done by verifying the presence of the known pattern in the aforementioned dummy array.

[0023] In case of a power outage: - A warning message may reach the host device when a status register read operation is performed; and / or Deleting such a block is performed to restore the entire block. This can happen automatically during power-up and / or when the problem is detected by a host command. However, these measures do not prevent the problem.

[0024] Furthermore, temperature fluctuations within a device can lead to measurement drifts, which are referred to as the ghost temperature problem.

[0025] The disadvantage associated with such temperature fluctuations affects the real bit distribution, which is detected by the read amplifiers as shifted with respect to the ideal central value for which they were programmed.

[0026] To give just one practical example: If the programming phase was performed at -40°C, the read results at 120°C may contain many errors. This is a real problem for all chips installed in automotive devices, where temperature increases during vehicle operation must be taken into account; furthermore, a temperature increase shifts or increases the distribution of correctly erased / programmed cells to the left and / or right.

[0027] Therefore, the read phase of the storage device is usually performed under environmental conditions similar to the original programming phase; this also applies to the erase phase.

[0028] A storage device can be defined as a kind of "real-time" device in the sense that it must release reliable data in all environmental operating conditions, regardless of whether it has been tested in the factory that reports approval based on positive test results.

[0029] Furthermore, temperature-related drift is further increased by the age of the device, and this problem could be particularly critical for storage devices integrated into system-on-chip autonomous vehicles.

[0030] Fig. Figure 1 illustrates a schematic example of a system 10 that includes a flash memory device 100. The system also includes a memory controller 101 that is coupled to the memory device 100.

[0031] The controller 101 is shown coupled to the storage device 100 via a data bus 105, a control bus 106, and an address bus 107. In one embodiment, the data bus could be a 64-bit and / or 128-bit double data rate (DDR) bus.

[0032] The in Fig. The system device 10 shown in Figure 1 can be a host device or a system-on-a-chip coupled with the memory component 100, as will be apparent from the description of other embodiments of this disclosure, which is made with reference to other figures. In each case, a part of the system-on-a-chip 10 and the memory component 100 are implemented on a corresponding chip, which is manufactured using a different lithography process. In the following description by SoC, this can refer to a part of the entire system (e.g., the section to which the memory device is coupled) or to the system as a whole, e.g., the combination of the host device section and the memory device.

[0033] The memory component 100 is an independent structure, but it is strictly associated with the host device or SoC structure. Specifically, the memory device 100 is connected and linked to the SoC structure, partially overlapping it, while the corresponding semiconductor area of ​​the SoC structure is used for other logic circuits and to support the partially overlapping, structurally independent memory device 100, for example, by means of a variety of pillars or other similar alternative connections such as bumping balls or with a flip-chip-like technology.

[0034] More precisely, the non-volatile memory component 100, with reference to 2, comprises an array 90 of flash memory cells and a circuit arranged around the memory array, as described in more detail below. The coupling between the SoC structure 10 and the memory component 100 is achieved by connecting a multitude of corresponding pads or pin connectors that are opposite each other in a circuit layout that maintains the orientation of the pads even if the size of the memory component is changed.

[0035] In one embodiment of the present disclosure, the pads of the memory component are arranged on a surface of the memory component 100, in practice on the top side of the array. More precisely, the pads are arranged above the array such that when the memory component 100 is turned over, its pads face the corresponding pads of the host or SoC structure 10.

[0036] Ultimately, the memory component 100 is manufactured according to the user's needs within a range of values ​​that can vary depending on the available technology, e.g., from a minimum of 128 Mbit to 512 Mbit or even more, without restricting the applicant's rights. More precisely, the proposed external architecture allows for exceeding the limitations of current eFlash technology (i.e., embedded flash technology), enabling the integration of larger memory, which, depending on the memory technology and technology node, can reach 512 Mbit and / or 1 Gbit and / or more.

[0037] The final configuration will be a face-to-face SoC / Flash array connection, with the read amplifiers connected to the SoC in a direct memory access configuration for user modes with high-frequency access.

[0038] Direct memory access allows for a reduction in the final latency that the SoC may experience when reading data. Furthermore, the final latency is also reduced by the block form factor, the distribution of read amplifiers across blocks, the selection of the comparison threshold in the read amplifiers, and the optimized path.

[0039] For a better understanding of the principle of the present disclosure, it should be noted that direct memory access is a feature of computer systems that allows certain hardware subsystems to access the main system memory (generally volatile, such as the CPU (central processing unit)).

[0040] More precisely, DMA is used when the CPU uses memory, and it is typically occupied for a certain clock cycle of the read or write operation. Therefore, whenever I / O devices access memory, it takes a significant amount of time to get the data into and / or out of memory.

[0041] The I / O devices first initiate the transfer with the DMA controller, relinquish control of the buses from the CPU, and then the CPU performs other operations while the transfer is in progress. Finally, it receives an interrupt from the DMA controller when the operation is complete, freeing up address or data buses for its internal operations. This feature is useful whenever the CPU cannot keep pace with the data transfer rate or when the CPU needs to perform work while waiting for a relatively slow I / O data transfer (input or output). Many hardware systems use DMA, including hard disk controllers, graphics cards, network cards, and sound cards.

[0042] According to the present disclosure, DMA is used for intra-chip data transfer in multi-core processors. Cores with DMA channels can transfer data to and from memory components with significantly less CPU overhead than cores without DMA channels. Similarly, a processing element within a multi-core processor can transfer data to and from its local memory without consuming its processor time, thus enabling computation and data transfer to occur in parallel.

[0043] The direct memory access described in this disclosure uses boundary-scan cells and read amplifiers as a system and method for addressing the direct memory access operation and for locating the memory address to a specific DMA flash array. A modified JTAG cell structure is implemented to allow for an increase in the number of memory pages to be read during a direct access.

[0044] With more specific reference to the example of Fig. 2 The main structure of the memory component 100 according to an embodiment of the present disclosure is disclosed.

[0045] The memory component 100 contains at least: an I / O circuit 5, a microsequencer 3, an array of memory cells 90, voltage and current reference generators 7, charge pumps 2 and decoding circuits 8 located at the periphery of the array or below the array, read amplifiers 9 and corresponding latches, a command user interface, for example a CUI block 4.

[0046] The array of memory cells 90 contains non-volatile flash memory cells. The cells can be erased in blocks, rather than one byte at a time. Each erasable memory block comprises a multitude of non-volatile memory cells arranged in a matrix of rows and columns. Each cell is coupled to an access line and / or a data line. The cells are programmed and erased by manipulating the voltages and timing on the access and data lines.

[0047] A special logic circuit section is provided for writing and erasing the memory cells of the array 90, which contains a simplified RISC controller (Reduced Instruction Set Computer) or a Modify Finite State Machine, i.e. the logic circuit for handling the programming and erasing algorithms.

[0048] A dedicated circuit section is provided for reading the memory cells of array 90. This section includes an optimized Read Finite State Machine (RISC) that ensures high read performance, including features such as branch prediction, fetch / pre-fetch, interrupt management, and so on. Error correction is handled by the SoC 10; the additional bits are allocated to the controller 101 to store any possible ECC syndrome associated with the page. The ECC cells allow the host controller to understand whether data corruption, including address content, has occurred. The ECC also enables the host to correct the received data. The host is responsible for committing the data to memory based on the correction made to the received data.

[0049] The write and erase phases described above are handled by the memory controller within the storage device, as the internal flash controller does not operate during read operations, which are controlled by the host.

[0050] With more specific reference to the example of Fig. In one embodiment of the present disclosure, the memory array 90 is structured as a collection of subarrays 120. In this way, with smaller sectors compared to known solutions, the access time is significantly reduced and the overall throughput of the memory element is improved.

[0051] The advantage of this architecture is that it is highly scalable and that increasing or decreasing the density of the terminal device is achieved simply by mirroring a subarray and establishing the connection.

[0052] The host device or system-on-chip 10 typically comprises more than one core, and each core is connected to a corresponding bus or channel for receiving and transmitting data to the memory component 1. Each subarray 120 has access to a corresponding channel to communicate with a corresponding core of the system-on-chip.

[0053] The host device's core can access a JTAG interface via some internal pads. These pads are fast and capable of supporting the maximum frequency. However, they cannot manage analog voltage outside the flash array.

[0054] In embodiments of the present disclosure, direct memory access (DMA) enables a reduction in the final latency that the SoC may experience when reading the data.

[0055] To overcome the problems of flash memory components embedded in system-on-chips and to achieve very low initial latency and high throughput, a scalable, cost-effective, efficient and reliable storage device and method were developed that completes the read operation with data, address and ECC through DMA flash array, ensuring that the data must be read from exactly the same memory location required by the controller.

[0056] Upon closer examination of the internal structure of the storage component 100, it can be seen that the architecture of the array 90 is structured as a collection of subarrays 120, as shown in Fig. 3 shown schematically.

[0057] Each subarray 120 is independently addressable within the storage device 100. Each subarray 120 contains multiple memory blocks 160, as shown in the Fig. 3 and Fig. 4 shown.

[0058] In this way, smaller sectors significantly reduce access time compared to known solutions, improving the overall throughput of the memory device. The reduction in initial latency occurs at the block level, as the row and column lines, the latency associated with the read path, and external communication have been optimized.

[0059] In the embodiments disclosed herein, the memory array 90 is structured with a number of subarrays 120 that corresponds at least to the number of cores of the associated SoC 10 and thus to the number of corresponding communication channels. For example, at least four memory subarrays 120 are provided, one for each communication channel with a corresponding core of the SoC 10.

[0060] The host device or system-on-chip 10 typically contains more than one core, and each core is connected to a corresponding bus or channel for receiving and transmitting data to the memory component 100.

[0061] Therefore, in the present implementation, each subarray 120 has access to a corresponding channel to communicate with a corresponding core of the system-on-chip 10. The result of the memory block operations is transferred directly to the SoC without using high-performance buffers or optimizing the path.

[0062] The advantage of this architecture is that it is highly scalable, with increasing and / or decreasing the density of the end device only resulting from mirroring a subarray and creating the connection or increasing the number of blocks in each subarray, i.e., the available density per core.

[0063] Furthermore, in one embodiment of the present disclosure, each memory subarray 120 is structured into memory blocks 160, which are in Fig. 4 are shown schematically.

[0064] Each independently addressable memory location of the blocks of each memory subarray 90 addresses an extended page 150, which is also defined below, where the term superpage means a double extended page.

[0065] In other words, the atomic side of 128 bits used in each subarray 120 to fill the communication channel with the SoC device has been enlarged in the present implementation to include the stored address and the ECC.

[0066] As a non-restrictive example, this extended page 150 includes a string comprising a first group of at least N bits, for example, one hundred and twenty-eight (128) bits for I / O data exchange with the SoC device 10, plus at least a second group of M bits, for example, twenty-four (24) address bits, and a final or third group of at least R bits, for example, sixteen (16) ECC bits. The M address bits (in the example, the 24 address bits) are sufficient to address up to 2 gigabits of available memory.

[0067] According to the present disclosure, the outputs of the read amplifiers SA each prepare a doubly extended page, i.e., a super page 150 with a number of bits given by the double combination of the above-mentioned three groups of data bits, address bits and ECC bits, corresponding to the size of the memory array.

[0068] In the specific but non-limiting example hereby disclosed, each extended page contains at least 168 bits, obtained by combining the above three groups of N+M+R = 128 + 24 + 16 data, address and ECC bit, and each superpage is formed by a pair of extended pages, i.e. a group of 168 x 2 bits.

[0069] To give just one non-restrictive numerical example, each line of a memory block contains 160 sixteen extended pages. Therefore, the resulting line contains 2688 bits, derived from the combination of sixteen independently addressable extended pages, each containing 168 bits, or, in other words, the combination of eight superpages.

[0070] Each memory block contains at least 256 rows, and each row contains sixteen superpages of the size mentioned above. Each superpage contains at least 168 bits as a combination of data, addressing, and ECC bits. Therefore, each row of the memory array can contain up to sixteen double words of 32 bits each, plus the address and ECC syndrome replacement bits per page.

[0071] To specify only a numerical value, a superpage is formed from 128 + 16 + 24 = 168 bits, and sixteen superpages per line comprise 168 * 16 = 2688 bits.

[0072] Therefore, each line 135 of a memory block 160 contains at least sixteen pages comprising a memory word plus the corresponding address bits and the corresponding ECC bits.

[0073] Obviously, a different size can be selected, and the reported value serves only to illustrate a non-restrictive example. The block output is controlled directly by the host device or SoC 10, without using the high-performance output buffers of known solutions, and the path is optimized thanks to a modified and optimized JTAG interface.

[0074] The outputs of the SA reading amplifiers per subarray 120 are buffered by an internal reading interface circuit. The memory structure can be expanded to allow reading multiple pages, with the already read page being moved to a separate storage location.

[0075] The SA read amplifiers are directly connected to a modified JTAG cell, which will be disclosed later, to integrate a JTAG structure and the read amplifiers into a single circuit component. This allows the delay in passing the memory array's output to the SoC to be reduced as much as possible.

[0076] As mentioned previously, the internal read amplifiers 9 prepare two pages with at least 128 bits plus address and ECC bits for a total of 168 bits, and while the first page is ready to be moved, another read operation is performed internally on a second page associated with the same address.

[0077] This allows the preparation of five to eight double words, typical for RTOS applications, which enables the read amplifiers to perform another internal read operation to prepare the second nibble, or group of 168 bits, if the system is structured with two pages of 168 bits. For this reason, a double page of 2 x 128 bits plus corresponding addresses and ECC bits was chosen.

[0078] This second part of four double words is transferred to the output of the flash array 90, using an additional enable signal (i.e., an internal clock signal or an ADV signal) that transfers the content read at the read amplifier level to the host device or SoC device 10. The signal names are load_data [0, 1].... When using the superside, an address increment is not required.

[0079] The combined chain of data cells + address cells + ECC cells enables the implementation of the entire security coverage of the communication channel according to the standard requirements of the ISO26262 rule, since the host first corrects the data stream, if any, and then compares the sent address with the received one.

[0080] Furthermore, the ECC covers all bus communication (data cells + address cells), while the presence of the address cells ensures that the data comes exactly from the addressed location of the controller, i.e., when ADD == ADD0.

[0081] A JTAG interface is used to test the memory component, enabling the reuse of the test tool. The memory component of this disclosure also includes JTAG logic with a JTAG interface.

[0082] More precisely, each memory field contains at least one JTAG interface that receives standard JTAG signals as inputs: TMS, TCK, TDI, as well as data from a memory page, e.g., the one in Fig. 5 schematically depicted page. According to the embodiments of the present disclosure, a flexible TDI signal is used. The flexibility is based on the fact that the number of parallel bits operating as TDI depends on a selected register, i.e., the instruction register, the address register, or the data register, etc.

[0083] This JTAG interface generates data, addresses and control signals as output, which are transmitted to a memory address decoder and also to the internal flash controller to perform modification, testing and verification operations.

[0084] The decoder's activity is enabled by the aforementioned charge pumps, which are designed to keep the voltages and timings for managing the array secret. The decoding phase drives the data lines, while the charge pumps provide the high voltage fed from the address decoder into the selected data lines.

[0085] This decoder addresses the selected memory block. The address decoder is connected to the array to select the correct data lines, i.e., row and column for each superpage. Reading, modifying, and all other operations use the address decoder to correctly address bytes in the memory array.

[0086] The memory blocks are connected to the read amplifiers, and the read interface's read amplifiers are connected to modified JTAG cells (not shown in the diagrams) to integrate a JTAG structure and the read amplifiers into a single circuit section. This allows the delay in passing the memory array's output to the SoC to be reduced as much as possible.

[0087] Each subarray 120 contains multiple memory blocks. The subarrays 120 serve each core of the host device and use a circuit with an optimized block form factor to address low latency.

[0088] In this way, with smaller sectors compared to known solutions, the access time is significantly reduced and the overall throughput of the memory component is improved.

[0089] Each subarray 1120 within the storage device 100 is independently addressable. Furthermore, the storage array 90 is structured with at least four storage subarrays 120, one for each communication channel with a corresponding core of the host device or SoC 10. The host device or system-on-chip 10 typically contains more than one core, and each core is connected to a corresponding bus or channel for receiving and transmitting data to the storage component 100.

[0090] Therefore, in the present implementation, each subarray 120 has access to a corresponding channel to communicate with a corresponding core of the system-on-chip 10.

[0091] Furthermore, it should be noted that each subarray contains 120 address registers connected to data buffer registers, similar to an architecture used in a DRAM memory device.

[0092] Furthermore, according to one embodiment of the present disclosure, as in Fig. As shown in Figure 4, each block 160 of the memory subarray 120 is assigned at least one dummy row 200.

[0093] This dummy line 200 is located outside the address space of memory array 90 and is used to optimize read, write, and erase parameters. Furthermore, this dummy line is used to monitor erase robustness, ensuring modification operations and other purposes are completed successfully.

[0094] According to another embodiment, the dummy row of a block 160 is provided in another block of the memory subarray 120.

[0095] The presence of this dummy line allows the read parameters to be stored at a suitable time and in a suitable manner in order to use the monitoring operation to optimize further steps.

[0096] Therefore, a primary purpose of this dummy line 200 is to track parameters that can be used during the read and erase phases of the memory component 100, and / or to store some parameters in order to detect any possible performance loss that may have occurred.

[0097] The dummy line 200 contains a pattern known to the controller 101 of the storage device 100.

[0098] Let's assume we record a known value like 0x55 or 0xAA in hexadecimal form in dummy line 200. This value is particularly suitable because it contains the same number of logical values ​​of "0" and logical values ​​of "1" stored within the array in different flash memory cells with two different thresholds. However, this does not preclude the possibility of using multi-level technology, which would allow more than two bits to be stored for each memory transistor or memory element.

[0099] Since this value is also known a priori to the memory controller, the system performs several read cycles that modify the read trim parameters until the value is read correctly. The modified trim parameter of the correct measured value corresponds to a set temperature value recorded in the programmable register. With different memory technologies, such as multilevel cell memory (N levels), the values ​​to be stored must be chosen to cover all N levels present in the memory array.

[0100] Only if the trim parameters set for the read phase perfectly allow the correct known value to be retrieved can the read phase of the other memory blocks of subarray 120 be performed. In this case, the search for the optimized read parameter corresponds to determining the best sampling point in this operating state, as is the case when using an eye diagram.

[0101] According to one embodiment of the present disclosure, the temperature and aging drift affecting the storage array 90 can be detected by the storage component 100 itself using a stored reference.

[0102] By using the drift information of the stored known pattern, it is possible to set the best parameters for the next or any subsequent operation, including the programming phase. In particular, such information can be used to correctly trim all voltage values ​​and timing (i.e., the waveform) to be used in every phase of the read and / or erase algorithm.

[0103] Generally, the correct voltage level and timing in each erase or programming phase must conform to technological guidelines. Such guidelines are usually known for a given technology, as they can be provided by flash cell technologists as a chart showing the relationship between the degree of aging and the corresponding voltage / time values ​​to be used.

[0104] Let us now look at the read, program and / or delete operations according to this methodology:

[0105] The known parameters are read from dummy line 200 and processed by the internal control system to determine the best parameters to use in the next steps. Then the reading and programming algorithm can start.

[0106] If the parameters in dummy line 200 are missing, this indicates a performance loss. This issue must be rectified by deleting the entire block. Otherwise, the block cannot be programmed or read correctly, and the host will have to handle the situation if the operation is not already in a delete phase.

[0107] During an erasure pulse phase, voltage and pulse duration can be adjusted so that the cells in the block are erased quickly and safely (according to the previous step).

[0108] When the block is cyclically processed (many program-erase cycles, estimated using drift information), several suitable high voltages and pulse durations are used. Typically, a block is erased by applying multiple erase pulses at different values ​​(negative for the gate voltage and / or positive for the body-source). This sequence is called a staircase and is used to apply a suitable pulse to modify the array's contents. Sometimes, as the block ages, the staircase becomes larger or lasts longer.

[0109] Once a clear pulse is issued (as above), the clear cell status is verified by applying a suitable cell-gate voltage value, which is used to perform a clearing verification with sufficient margin to guarantee a properly cleared cell distribution. Additionally, drift information can be used here to select the correct clearing verification values.

[0110] Fig. Figure 6, for example, shows in a schematic diagram the distribution of a good erased / programmed (1 bit / cell) cell. The entire cell threshold population is correctly restricted to the assigned limit (i.e., programmed '0' or erased '1'). Steps #1 and #2 are repeated until all cells meet the erasure check criteria.

[0111] Once all cells have been correctly verified (deleted), the system also checks for cells with a threshold that is too low. Fig. 6 shows this through the Label Depletion Verification (DV).

[0112] In the event of cell exhaustion, a soft program operation is executed for the cells that require it. The parameters used to perform a soft drift of the cells, in order to correctly position the thresholds within the deletion cell distribution, can be chosen according to the age of the cells.

[0113] An incorrect selection of such a parameter can lead to the threshold of cells outside the deleted distribution (above the deletion check value) being incorrectly placed, and this would mean that the block would have to be deleted again from step 1 above (this would be time-consuming).

[0114] Once the erasure process is complete (the above phases are finished), the known pattern is written to row 200 for use in the next erasure cycle. Specifically, the pattern selected by storing the set values ​​(0x55, 0xAA, etc.) is programmed and verified accordingly (see the PV phase of...). Fig. 6) using a suitable programming pulse, the voltage and timing of which depend on the current aging level of the block. The contents of dummy line 200 are also erased accordingly; the flash controller must then restore it after erasure.

[0115] By using the drift information and the number of erase pulses provided during the erase phase (point 1 above), it is possible to infer that a block is nearing the end of its lifespan. This information could be used as a warning to the customer or as a flag for an internal algorithm to trigger potential block wear leveling or on-field block redundancy (OFBR) operation, if implemented.

[0116] Fig. Figure 7 shows a diagram accordingly Fig. Figure 6, however, shows an increased distribution due to aging, temperature, and stress. With aging, temperature, and stress, the distributions tend to increase and shift. According to the methodology of the present disclosure, it is possible to use the increased distribution to track cell degradation and to use this information to correct subsequent quenching pulses. This makes it possible to improve the reliability and performance of the quenching phase.

[0117] The trim sequence for performing a read phase of the memory array at different temperatures or different aging of the memory devices can be recorded in a laboratory and stored in a programmable register of the memory controller 101.

[0118] Similarly, the parameters used during the deletion and programming phase can be regulated in the same way during actual operation.

[0119] The content of a correct reading phase does not depend on the actual temperature at which the reading phase is performed. Such a temperature could be higher (even much higher) or lower compared to the temperature at which the programming phase of the known value was performed.

[0120] The system is automatically protected against any thermal drift because the read trim parameters are selected after the known sequence stored in the dummy row 200 has been correctly read and the trim parameter has been adjusted accordingly for the correct reading of this known value. This feature can be a capability that is left to the host device and controlled by it, since there is no time for parallel reading of the dummy row during the read phase. The same applies before the start of the read phase due to the low initial latency supported by the present embodiments.

[0121] The procedure for identifying more suitable read trim parameters for a correct read phase at a given temperature is not necessarily repeated in every read phase. On the contrary, such a procedure can be performed periodically or in a more suitable manner when potential problems are detected by the ECC bits.

[0122] For example, an increased number of ECC bits may indicate an excessive number of incorrect reads from the storage device (e.g., when the number of bits corrected by the error correction engine exceeds a threshold). In such a case, the system can automatically initiate a procedure to detect potential thermal drift or aging and the resulting need to adjust the trim parameters.

[0123] In one embodiment, the above method could be triggered by a host command. In some embodiments, the method can be triggered by a specific event, such as a temperature fluctuation detection.

[0124] The dummy line 200 can be configured to store information indicating a failure of the deletion operation.

[0125] The method of the present disclosure makes it possible to correctly perform the read phase of the memory component 100 or better of a memory block 160.

[0126] The process phases are shown in the block diagram of the Fig. 8 shown schematically.

[0127] Method 800 for improving the security of the read phase of a non-volatile storage device comprising at least an array of memory cells with associated decoding and reading circuitry and a memory controller, wherein the method comprises: - Storing at least one known pattern in a dummy row of the memory block; - Perform several read cycles, changing the read trim parameters, until the moment the known value is read correctly; - Transfer of the trim parameters for the correct reading to the subsequent reading phases.

[0128] The above steps are shown in the respective squared blocks 810, 820 and 830.

[0129] In one embodiment, the known pattern has a large number of programmed ('0') and erased ('1') bits in equal numbers, for example assuming a hexadecimal configuration of (0xAA, 0x55 etc.).

[0130] Furthermore, the control based on the dummy row content can include the selection of the bias values ​​of the cells to be read and / or the selection of a suitable value to be used as the read reference cell.

[0131] Only when the trim parameters set for the read phase allow the determination of the correct known value can the read phase of the other memory blocks of subarray 120 be carried out.

[0132] Each subarray 120 can have its own blocks, and the optimal parameters can even differ from one subarray to another and from block to block.

[0133] The modified trim parameters for correct reading correspond to a temperature setpoint stored in the programmable register.

[0134] In fact, storing the critical parameters can provide feedback on the state of the block, which also determines how wear compensation must be applied to block 160 of subarray 120.

[0135] The presence of the known pattern at the end of the dummy series ensures the correctness of the operation.

[0136] The method of the present invention enables the obtaining of a dynamic extinguishing verification of the extinguishing phase, since it is possible to obtain reliable feedback on the correctness of the extinguishing process even under different operating environment conditions.

Claims

[1] comprising a non-volatile storage device (100): - an array (90) of memory cells with a plurality of memory blocks; - a dummy line (200) corresponding to a memory block (160) of the plurality of memory blocks, for storing a known pattern and a trim parameter, wherein the trim parameter enables the known pattern to be read from outside an address space of the corresponding memory block (160) of the plurality of memory blocks; - a controller (101) of the storage device (100) which is configured to trigger the detection of a thermal drift in a storage block (160) of the multiple storage blocks using the known pattern stored in the dummy line (200) corresponding to the storage block (160) in response to the detection of a temperature change of the storage device (100); - Read circuits controlled by the controller (101) for reading the known pattern stored in the dummy line (200) by executing read cycles and changing the read trim parameter, which is stored in the dummy line (200) for reading the known pattern, until a moment when a value of the known pattern is correctly read, wherein the value of the known pattern is stored in the dummy line (200), wherein the controller (101) is configured such that it: ◯ in a subsequent reading phase, based on a missing trim parameter in the dummy row (200), it is determined that a power loss has occurred; and ◯ In response to the detection of a performance loss, it erases the entire memory block. [2] Non-volatile storage device (100) according to claim 1, wherein the known pattern of the control (101) of the storage device (100) is known and wherein the known pattern contains an equal number of programmed ('0') and erased ('1') bits. [3] Non-volatile storage device (100) according to claim 1, wherein the modified trim parameter corresponds to a set temperature value recorded in a programmable register. [4] Non-volatile storage device (100) according to claim 1, wherein the dummy row (200) is configured to store internal block variables of a read, a programming and / or a delete phase. [5] Non-volatile storage device (100) according to claim 4, wherein the internal block variables comprise read pulses and the target voltages applied to the storage block (160) during the read phase. [6] Non-volatile storage device (100) according to claim 1, wherein the dummy line (200) is located outside an address space of the memory block (160). [7] Non-volatile storage device according to claim 1, wherein the dummy row (200) is provided in another storage block (160) of the array (90) of memory cells. [8] Having a device: - a host device comprising a system-on-chip (SoC) wherein the SoC is configured to perform error correction operations on data retrieved from an addressable space of a non-volatile memory component; - the non-volatile memory component wherein the non-volatile memory component comprises a structure independent of the SoC but coupled to the host device, comprising an array (90) of memory cells with a plurality of memory blocks and wherein one memory block of the plurality of memory blocks is configured to store the data in the addressable space; - the dummy line (200) corresponding to the memory block (160) of the plurality of memory blocks, for storing a known pattern and the trim parameter, wherein the trim parameter enables the known pattern to be read from outside an address space of the corresponding memory block (160) of the plurality of memory blocks; - a controller (101) of the memory component configured to trigger detection of thermal drift or aging using the known pattern stored in the dummy line (200) in response to a number of ECC bits from the correction of data retrieved from the addressable space of the non-volatile memory component by the SoC that exceeds a threshold; and - Read circuits controlled by the controller (101) for reading the known pattern stored in the dummy line (200) by performing a read cycle and changing the read trim parameter until the moment when the value of the known pattern is correctly read by means of the trim parameter, wherein the controller (101) is configured such that it: ◯ in a subsequent reading phase, based on the absence of the trim parameter from the dummy row (200), it is determined that a power loss has occurred; and ◯ In response to the detection of a performance loss, it erases the entire memory block. [9] Device according to claim 8, wherein the dummy row (200) is configured to store internal block variables of a read phase and a delete phase. [10] Device according to claim 9, wherein the internal block variables comprise read pulses or the target voltages applied to the memory block (160) during the read phase. [11] Device according to claim 8, wherein the array (90) of memory cells contains a plurality of independently addressable memory blocks; wherein each of the plurality of independently addressable memory blocks contains at least 256 rows of memory cells and each row contains at least sixteen superpages, each formed by a combination of data bits, address bits and ECC bits of a memory location. [12] Device according to claim 11, wherein the read cycles are automatically performed by the controller (101) when an increased number of ECC bits represents an excessive number of misreads from the memory component. [13] Procedure that includes: - Storing a known pattern in a dummy row (200), wherein the dummy row (200) corresponds to a memory block (160) of a plurality of memory blocks of an array (90) of memory cells, wherein the known pattern is associated with the detection of a thermal drift in the memory block (160), wherein the array (90) of memory cells stores data in an address space of the array 90 of memory cells, and wherein the dummy row (200) stores the known pattern outside the address space of the array 90 of memory cells; - Performing read cycles and changing a trim parameter stored in the dummy line (200) until the known pattern is correctly read using the trim parameter; and - the adoption of the trim parameter for the correct reading of the known pattern for the subsequent reading phases of the address space - Determine in a subsequent reading phase, based on the absence of the trim parameter from the dummy row (200), that a power loss has occurred; and - Erasing memory block (160) in response to the determination that a performance loss has occurred. [14] Method according to claim 13, wherein the modified trim parameters correspond to a temperature setpoint recorded in a programmable register for correct reading. [15] Method according to claim 13, wherein the adoption of the trim parameter is carried out in response to the correct reading of the known value. [16] Method according to claim 13, wherein the known pattern contains values ​​in hexadecimal form comprising the same number of logical values ​​of “0” and logical values ​​of “1”. [17] Method according to claim 13, wherein the read cycles are performed automatically when an increased number of ECC bits is representative of an excessive number of misreads from a non-volatile storage device comprising the array (90) of memory cells. [18] Method according to claim 13, wherein the dummy line (200) is configured to store information indicating a failure of a deletion operation. [19] Method according to claim 13, further comprising starting a delete phase on the memory block (160) based on retrieving internal block variables of a previous delete phase from the dummy line (200).

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