TEMPERATURE-BASED STORAGE MANAGEMENT

Abstract

Procedure, comprehensive: Identifying data for writing to a storage device (305) comprising memory cells of a first kind (325) and memory cells of a second kind (330); Identifying a temperature of the storage device (305); Determine whether the temperature of the storage device (305) is outside a nominal operating range of the storage device (305); Selecting the storage cells of the first type (325) based at least partially on the fact that the temperature of the storage device (305) is outside the nominal operating range of the storage device (305); Determine whether a data set stored in the memory cells of the first type (325) satisfies a threshold data set; and Writing the data to one or more memory cells of the first kind based at least partially on selecting the memory cells of the first kind (325) and on the fact that the amount of data stored in the memory cells of the first kind (325) does not meet the threshold data amount.

Description

BACKGROUND

[0001] The following generally relates to a system including at least one memory device, and more particularly to temperature-based memory management.

[0002] A system may include various types of memory devices and controllers coupled via one or more buses to manage information in numerous electronic devices such as computers, wireless communication devices, the Internet of Things, cameras, digital displays, and the like. Memory devices are widely used to store information in such electronic devices. Information is stored by programming various states of a memory cell. For example, binary memory cells can store one of two states, often corresponding to a logical "1" or a logical "0." Some memory cells are capable of storing one of more than two states. To access the stored information, the memory device can read or sense the stored state in the memory cell.To store information, the memory device can write or program the state into the memory cell.

[0003] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic random-access memory (DRAM), synchronous dynamic random-access memory (SDRAM), ferroelectric RAM (FeRAM), magnetoresistive random-access memory (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), three-dimensional XPoint memory (3D XPoint), flash memory (such as floating-gate flash and charge-trapping flash, which can be used in not-or (NOR) or not-and (NAND) memory devices), and others. Memory devices can be volatile or non-volatile. Non-volatile memory cells, e.g.Flash memory cells can retain their stored logic state for extended periods of time, even when no external power source is present. Volatile memory cells, e.g., DRAM cells, can lose their stored state over time unless they are regularly refreshed by an external power source. Flash-based memory devices can exhibit improved performance compared to some non-volatile and volatile memory devices. US 10,339,983 B1 relates to a memory device comprising memory cells of a first type, memory cells of a second type, and a controller. The controller is configured to write data to the memory cells of the second type only when the operating temperature is moderate and when the data to be written is of sufficient size; otherwise, the data is written to the memory cells of the first type. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates an example of a memory device that supports temperature-based memory management according to the examples disclosed herein. Fig. 2 illustrates an example NAND memory circuit that supports temperature-based memory management according to the examples disclosed herein. Fig. 3 illustrates an example of a system that supports temperature-based memory management according to the examples disclosed herein. Fig. 4 illustrates an example flowchart for a process that supports temperature-based memory management according to the examples disclosed herein. Fig. 5 illustrates an example of a system that supports temperature-based memory management in accordance with the examples disclosed herein. Fig. 6 illustrates an example block diagram supporting temperature-based memory management according to the examples disclosed herein. Fig. 7 and Fig. 8 show flowcharts illustrating one or more methods supporting temperature-based memory management according to the examples disclosed herein. DETAILED DESCRIPTION

[0004] In some cases, a memory device may be exposed to a wide range of operating temperatures, possibly including relatively extreme (high or low) temperatures. Operating the memory device under such conditions can increase the likelihood of errors in the memory device, which can be particularly problematic for systems (such as automotive applications or other systems) where accuracy and reliability are critical (e.g., related to safety).

[0005] Some types of memory cells are capable of storing a single bit of information in each memory cell. Such memory cells may be referred to as single-level cells (SLCs). Some types of memory cells are capable of storing two or more bits of information in each memory cell. Such memory cells are referred to herein as multi-level cells and may include, for example, memory cells capable of storing two bits, three bits, four bits, etc. Memory cells that store two bits are sometimes referred to as multi-level cells (MLCs), although this term is sometimes used to refer to any memory cell that stores more than one bit. Memory cells that store three bits may be referred to as triple-level cells (TLCs), and memory cells that store four bits may be referred to as quad-level cells (QLCs).Multi-level cells, such as MLCs, TLCs, and QLCs, may offer cost and / or density advantages over SLCs, while SLCs may be faster and more reliable than multi-level cells. In some cases, NAND (NAND) memory cells may be SLCs or multi-level cells (e.g., configured or operated as such). In general, the more bits stored in a memory cell, the more sensitive the memory cell may be to noise or other disturbances, such as those that might occur under relatively extreme operating conditions. For example, an SLC may be more robust to extreme temperatures than a multi-level cell, but may cost more and provide less density. Similarly, an MLC cell may be more robust than a TLC cell, and a TLC cell may be more robust than a QLC cell.

[0006] Some safety-critical systems, such as those in automotive applications, rely on SLC-based memory to improve system reliability. However, this approach can increase system cost and may not leverage the density advantages of multi-level memory cells. Thus, as described herein, a memory device (e.g., a NAND memory device) may include both SLC memory (or another type of high-reliability memory) and multi-level cell memory (or another type of high-density or low-cost memory) and may determine which type of memory to use based, for example, on the temperature of the memory device.For example, the memory device may be configured to write data to SLC memory blocks when the memory device operates under relatively extreme temperatures and to write data to multi-level cell memory when the memory device operates in a less extreme temperature range. In this way, a memory device can offer excellent reliability under a range of operating conditions while providing lower cost and higher density compared to pure SLC designs.

[0007] Features of the disclosure are first described in the context of a memory device and a memory circuit, as described with reference to Fig. 1 and Fig. 2. These and other features of the disclosure are further illustrated and described with reference to system diagrams and flowcharts relating to temperature-based memory management, as described with reference to the Fig. 3 - 8 described.

[0008] Fig. 1 illustrates an example of a memory device 100 according to examples disclosed herein. In some cases, the memory device 100 may be referred to as a memory chip, a memory die, or an electronic memory device. The memory device 100 may include one or more memory cells, such as memory cell 105-a and memory cell 105-b (other memory cells are not labeled). A memory cell 105 may, for example, be a flash memory cell (such as in the enlarged view of memory cell 105-a in Fig. 1), a DRAM memory cell, a FeRAM memory cell, a PCM memory cell, or another type of memory cell.

[0009] Each memory cell 105 can be programmed to store a logical state representing one or more bits of information. In some cases, a memory cell 105 can store one bit of information at a time (e.g., a logical state 0 or a logical state 1), such as in the memory cells of SLC memory blocks, which may be referred to as SLC memory cells. In some cases, a single memory cell 105 can store more than one bit of information at a time, such as in the memory cells of MLC, TLC, or QLC memory blocks. For example, a single memory cell 105 in an MLC memory block (e.g., an MLC memory cell) can store two bits of information at a time by storing one of four logical states: logical state 00, logical state 01, logical state 10, or logical state 11. For example, a single memory cell 105 in a TLC memory block (e.g.,a TLC memory cell) can store three bits of information simultaneously by storing one of eight logical states: 000, 001, 010, 011, 100, 101, 110, 111.

[0010] In some cases, a multi-level memory cell 105 (e.g., an MLC memory cell, a TLC memory cell, or a QLC memory cell) may be physically different from an SLC cell. For example, a multi-level memory cell 105 may use a different cell geometry or be fabricated using different materials. In some cases, a multi-level memory cell 105 may be physically the same or similar to an SLC cell, and other circuitry in a memory block (such as control circuitry, sense amplifiers, drivers, etc.) may be configured to operate (e.g., read and write) the memory cell as an SLC cell, an MLC cell, a TLC cell, etc.

[0011] Different memory cell architectures can store a logical state in different ways. For example, in FeRAM architectures, each memory cell 105 can include a capacitor containing a ferroelectric material to store a charge and / or a polarization representative of the programmable state. In DRAM architectures, each memory cell 105 can include a capacitor containing a dielectric material (e.g., an insulator) to store a charge representative of the programmable state.

[0012] In flash memory architectures, each memory cell 105 may include a transistor having a floating gate and / or a dielectric material to store a charge representing the logic state. The enlarged diagram of memory cell 105-a in Fig. 1 is a flash memory cell including a transistor 110 (e.g., a metal-oxide-semiconductor (MOS) transistor) that can be used to store a logic state. Transistor 110 has a control gate 115 and may include a floating gate 120 sandwiched between dielectric material 125. Transistor 110 includes a first node 130 (e.g., source or drain) and a second node 135 (e.g., drain or source). A logic state can be stored in transistor 110 by placing (e.g., writing, storing) an amount of electrons (e.g., a charge) on floating gate 120. The amount of charge to be stored on floating gate 120 may depend on the logic state to be stored.The charge stored on floating gate 120 can affect the threshold voltage of transistor 110, thereby affecting the amount of current that can flow through transistor 110 when transistor 110 is enabled. The logic state stored in transistor 110 can be read by applying a voltage to control gate 115 (e.g., at control node 140) to enable transistor 110 and measuring (e.g., detecting, sensing) the resulting amount of current flowing between first node 130 and second node 135.

[0013] For example, a sensing component 170 may determine whether an SLC memory cell stores a logic 0 or a logic 1 in a binary manner; e.g., based on the presence or absence of current from the memory cell or based on whether the current is above or below a threshold current. However, for multi-level cells, a sensing component 170 may determine the logic state stored in the memory cell based on various intermediate current levels. For example, a sensing component 170 may determine the logic state of a TLC cell based on eight different current levels (or current ranges) that define the eight potential logic states that could be stored by the TLC cell. Such current levels may be quite closely spaced (in terms of magnitude), providing a smaller margin of error than in the case of an SLC.

[0014] Similarly, a flash SLC memory cell can be written to by applying one of two voltages (e.g., a voltage above a threshold or a voltage below a threshold) to the memory cell to store (or not store) an electrical charge on the floating gate, representing one of two possible logic states. In contrast, writing to a flash multi-level cell may require applying voltages with a finer level of granularity to more finely control the amount of charge stored on the floating gate, allowing a larger set of logic states to be represented. Thus, multi-level cells can be more sensitive to voltage or current fluctuations that can occur in a memory device due to temperature variations or other operating conditions.

[0015] A charge-trapping flash memory cell may operate similarly to a floating-gate flash memory cell, but instead of (or in addition to) storing a charge on a floating gate 120, a charge-trapping flash memory cell may store a charge representing the state in a dielectric material beneath the control gate 115. Thus, a charge-trapping flash memory cell may or may not include a floating gate 120.

[0016] In some examples, each row of memory cells 105 is connected to a word line 160, and each column of memory cells 105 is connected to a digit line 165. Thus, a memory cell 105 may be located at the intersection of a word line 160 and a digit line 165. This intersection may be referred to as the address of a memory cell. Digit lines are sometimes referred to as bit lines. In some cases, the word lines 160 and the digit lines 165 may be substantially perpendicular to each other, forming an array of memory cells 105. In some cases, the word lines 160 and the digit lines 165 are generally referred to as access lines or select lines.

[0017] In some cases, the memory device 100 may include a three-dimensional (3D) memory array with multiple two-dimensional (2D) memory arrays formed on top of one another. This may increase the number of memory cells that can be placed or created on a single chip or substrate compared to 2D arrays, which in turn may reduce production costs or increase the performance of the memory array, or both. In the example of Fig. 1, the memory device 100 includes multiple levels of memory arrays. The levels may, in some examples, be separated by an electrically insulating material. Each level may be aligned or positioned such that the memory cells 105 across each level may be aligned (exactly, overlapping, or approximately) with each other, thereby forming the memory cell stack 175. In some cases, the memory cell stack 175 may be referred to as a series of memory cells, which will be described in more detail with reference to Fig. 2 is discussed.

[0018] Access to memory cells 105 may be controlled by row decoder 145 and column decoder 150. For example, row decoder 145 may receive a row address from memory controller 155 and activate an appropriate word line 160 based on the received row address. Similarly, column decoder 150 may receive a column address from memory controller 155 and activate an appropriate digit line 165. Thus, a memory cell 105 may be accessed by activating a word line 160 and a digit line 165.

[0019] When accessed, the memory cell 105 may be read or sensed by the sense component 170. For example, the sense component 170 may be configured to determine the stored logic state of the memory cell 105 based on a signal generated by accessing the memory cell 105. The signal may include a voltage or an electrical current, or both, and the sense component 170 may include voltage sense amplifiers, current sense amplifiers, or both. For example, a current or voltage may be applied to a memory cell 105 (using the corresponding word line 160 and / or digit line 165), and the magnitude of the resulting current or voltage on the digit line 165 may depend on the logic state stored by the memory cell 105.For example, for a flash memory cell, the amount of charge stored on a floating gate or in an insulating layer of a transistor in memory cell 105 can affect the transistor's threshold voltage, thereby affecting the amount of current flowing through the transistor in memory cell 105 when memory cell 105 is accessed. Such current differences can be used to determine the logic state stored in memory cell 105.

[0020] The sensing component 170 may include various transistors or amplifiers to detect and amplify a signal (e.g., a current or voltage) on a digit line 165. The detected logic state of the memory cell 105 may then be output via the input / output block 180. In some cases, the sensing component 170 may be part of the column decoder 150 or the row decoder 145, or the sensing component 170 may otherwise be connected to or in electronic communication with the column decoder 150 or the row decoder 145.

[0021] A memory cell 105 may be set or written by similarly activating the relevant word line 160 and digit line 165 to enable a logic state (e.g., representing one or more bits of information) to be stored in the memory cell 105. The column decoder 150 or the row decoder 145 may accept data, for example, from the input / output block 180, to be written to the memory cells 105. As previously discussed, in the case of flash memory (such as flash memory used in NAND and 3D NAND memory devices), a memory cell 105 is written by storing electrons in a floating gate or insulating layer.

[0022] The memory controller 155 may control the operation (e.g., reading, writing, rewriting, refreshing) of the memory cells 105 through the various components, for example, the row decoder 145, the column decoder 150, and the sense component 170. In some cases, one or more of the row decoder 145, the column decoder 150, and the sense component 170 may be co-located with the memory controller 155. The memory controller 155 may generate row and column address signals to activate the desired word line 160 and digit line 165. The memory controller 155 may also generate and control various voltages or currents used during operation of the memory device 100.

[0023] In some cases, memory controller 155 may identify data to be written to a memory device 100 that includes memory cells of the first type and memory cells of the second type. For example, memory cells of the first type may be SLC memory cells, and memory cells of the second type may be multi-level memory cells. For example, memory cells of the first type and memory cells of the second type may be two different types of NAND memory cells.

[0024] The memory controller 155 may identify a temperature of the memory device based, for example, on a signal received from a temperature sensor. The memory controller 155 may select a memory cell type from a set of memory cell types based at least in part on the temperature of the memory device, wherein the set of memory cell types includes the first type and the second type. For example, the set of memory cell types may include SLC memory cells, MLC memory cells, TLC memory cells, QLC memory cells, etc. The memory controller 155 may write the data to one or more memory cells of the selected type based at least in part on selecting the memory cell type from the set of memory cell types.In this way, the memory controller 155 can write the data to high-density, low-cost memory cells under normal operating conditions, while the memory controller 155 can write the data to high-reliability memory cells under extreme operating conditions.

[0025] Fig. Figure 2 illustrates an example of a NAND memory circuit 200 that supports temperature-based memory management according to the examples of the present disclosure. The NAND memory circuit 200 may be an example of a portion of a memory device, such as the memory device 100. Although some Fig. 2 are identified by reference numerals, other corresponding elements are not identified even though they are the same or would be understood as similar in order to increase the visibility and clarity of the features shown.

[0026] The NAND memory circuit 200 includes a plurality of flash memory cells 205 (which may be, for example, flash memory cells as described with reference to Fig. 1) connected in a NAND configuration. In a NAND memory configuration (referred to as NAND memory), a plurality of flash memory cells 205 are connected in series to form strings 210 of memory cells 205, in which the drain of each flash memory cell 205 in the string 210 is coupled to the source of another flash memory cell 205 in the string. In some cases, flash memory cells connected in a NAND configuration to form NAND memory may be referred to as NAND memory cells.

[0027] Each string 210 of memory cells 205 may be associated with a corresponding digit line 215 shared by the memory cells 205 in the string 210. Each memory cell 205 in a string 210 may be associated with a separate word line 230 (e.g., word line 230-a, 230-i, 230-n), so that the number of word lines 230 may equal the number of memory cells 205 in a string 210.

[0028] In general, NAND memory may be hierarchically organized as strings 210 containing multiple memory cells 205, pages containing multiple strings 210, and blocks containing multiple pages. In some cases, NAND memory may be written to and read from at the page level of granularity, but may not be erasable at the page level of granularity. For example, NAND memory may instead be erasable at a higher granularity level, such as the block granularity level. In some cases, a NAND memory cell may need to be erased before it can be rewritten. Different memory devices may have different read / write / erase characteristics.

[0029] Each string 210 of memory cells 205 in NAND memory circuit 200 is coupled to a select gate device for drain (SGD) transistor 220 at one end of string 210 and a select gate device for source (SGS) transistor 225 at the other end of string 210. SGD transistor 220 and SGS transistor 225 can be used to couple a string 210 of memory cells 205 to a bit line 215 and / or to a source node 250 by applying a voltage to gate 245 of SGD transistor 225 and / or to gate 240 of SGS transistor 225.

[0030] During NAND memory operations, various voltage levels associated with source node 250, gate 240 of an SGS transistor 225 associated with source node 250, word lines 230, drain node 235, gate 245 of an SGD transistor 220 associated with drain node 235, and bit line 215 may be applied to perform one or more operations (e.g., program, erase, or read) on at least some NAND memory cells in a string 210.

[0031] In some cases, during a first operation (e.g., a read operation), a positive voltage may be applied to bit line 215 associated with drain node 235, while source node 250 may be associated with ground or a virtual ground (e.g., approximately 0 V). For example, the voltage applied to drain node 235 may be 1 V. At the same time, the voltages applied to gates 245 and 240 may be increased above the threshold voltages of the one or more SGSs 225 associated with source node 250 and the one or more SGDs 220 associated with drain node 235, such that a channel associated with memory string 210 may be electrically connected to drain node 235 and source node 250. A channel may be an electrical path through the memory cells 205 in a string 210 (e.g.by the transistors in the memory cells 205), which can conduct current under certain operating conditions.

[0032] At the same time, multiple wordlines 160 (e.g., in some cases, all wordlines 160) except for a selected wordline (i.e., wordlines associated with unselected cells in string 210) may be connected to a voltage (e.g., VREAD) that is higher than the highest threshold voltage (VT) of memory cells in string 210. VREAD may cause all unselected memory cells in string 210 to turn "ON" so that each unselected memory cell can maintain high conductivity in a channel associated with it. In some examples, a wordline 160 associated with a selected cell may be connected to a voltage VTarget. VTarget may be selected with a value between VT of an erased memory cell and VT of a programmed memory cell in memory string 345. If the selected memory cell has an erased VT (e.g.,If the selected memory cell has a programmed VT (e.g., VTarget > VT of the selected memory cell), the selected memory cell 205 may turn "ON" in response to the application of VTarget, thus allowing a current to flow in the channel of the memory string 210 from the bit line 215 to the source 250. If the selected memory cell has a programmed VT (e.g., VTarget < VT of the selected memory cell), the selected memory cell may turn "OFF" in response to VTarget, thus preventing a current from flowing in the channel of the memory string 210 from the bit line 215 to the source 250. The amount of current flow (or lack thereof) may be sensed by the sense component 170, as described with reference to FIG. Fig. 1 to read stored information in the selected memory cell 205 within string 210.

[0033] Fig. Figure 3 illustrates an example of a system 300 that supports temperature-based memory management according to the examples disclosed herein. System 300 includes a memory device 305 that includes a temperature sensor 310, a controller 320, a first type of memory block 325, and a second type of memory block 330.

[0034] Sensor 310 may be a temperature sensor, voltage sensor, power sensor, or other type of sensor configured to sense a temperature, voltage, power, or other operating condition associated with storage device 305. For example, sensor 310 may be a temperature sensor configured to measure (e.g., detect, determine, identify, sense) a temperature of storage device 305. Sensor 310 may be configured to output a signal representing a value of the temperature (or a value of another operating condition) to a controller 320 via communication path 315.

[0035] The memory device 305 includes a first type of memory blocks 325 and a second type of memory blocks 330. The first type of memory blocks 325 may include a plurality of memory cells, such as the memory cells 105, 205, with reference to the Fig. 1 to 2. The first type of memory blocks 325 may, for example, be a type of memory block that is relatively robust to temperature changes and noise and offers a high degree of reliability. In some cases, memory cells of the first type of memory blocks 325 may each be used to store a single bit, such as in SLC memory cells. In some cases, memory cells of the first type of memory blocks 325 may each be used to store multiple bits, such as in multi-level memory cells (e.g., MLC, TLC, QLC). In some cases, memory cells of the first type of memory blocks 325 may be connected in a NAND configuration, as described with reference to FIG. 2, and may be referred to as NAND memory cells.

[0036] The second type of memory blocks 330 may, for example, be a type of memory block that provides cost and / or density advantages relative to the first type of memory blocks 325, but may be less robust to temperature variations and noise. In some cases, memory cells of the second type of memory blocks 330 may each store multiple bits, such as in MLC, TLC, or QLC memory cells. In some cases, each memory cell in the second type of memory blocks 330 may store more bits than each memory cell in the first type of memory blocks 325. For example, if the first type of memory blocks 325 includes SLC memory cells that store one bit, the second type of memory blocks 330 may include MLC memory cells that store two bits, TLC memory cells that store three bits, or QLC memory cells that store four bits.For example, if the first type of memory blocks 325 includes MLC memory cells that store two bits, the second type of memory blocks 330 may include TLC memory cells that each store three bits, or QLC memory cells that each store four bits. In some cases, memory cells of the second type of memory blocks 330 may be connected in a NAND configuration and may be referred to as NAND memory cells. In some cases, the first type of memory blocks 325 may provide less storage capacity than the second type of memory blocks 330. In some cases, there may be fewer memory blocks 325 of the first type than memory blocks 330 of the second type, or the footprint of the first type of memory blocks 325 may be smaller than the footprint of the second type of memory blocks 330.

[0037] In some cases, the memory cells in the first type of memory blocks 325 may be physically different from the memory cells in the second type of memory blocks 330. For example, the memory cells in the first type of memory blocks 325 may have a different geometry or be made of different materials than the memory cells in the second type of memory blocks 330. In some cases, the memory cells in the second type of memory blocks 330 may be physically the same or similar to memory cells in the first type of memory blocks 325, but may be physically different due to differences in other circuitry, such as differences in control circuitry, sense amplifiers, etc., that are or can be coupled to the memory cells in the second type of memory blocks 330.

[0038] In some cases, the memory device 305 may be configured to use the sensor 310 to sense a temperature (or other operating condition) associated with the memory device 305 and provide an indication of the value of the sensed temperature to the controller 320 via the communication path 315. The controller 320 may include control circuitry associated with accessing memory cells in the memory device 305 and may be located on or within the same die, package, or chip as the first type of memory blocks 325 and the second type of memory blocks 330. The controller 320 may use the indication of the sensed temperature to select the first type of memory blocks 325 or the second type of memory blocks 330 for a write operation and cause the memory device 305 to write the data to the selected type of memory block.For example, if the sensed temperature is within a nominal temperature range, the controller 320 may select the second type of memory blocks 330 and write the data to the second type of memory blocks 330 to take advantage of the increased density and reduced cost associated with the second type of memory blocks 330. If the sensed temperature is outside the nominal temperature range, indicating a higher probability of failure, the controller 320 may select the first type of memory blocks 325 and write the data to the first type of memory blocks 325 to take advantage of the high reliability associated with the first type of memory blocks 325.

[0039] In some cases, after writing data to the first type of memory blocks 325, the controller 320 may subsequently move the data to the second type of memory blocks 330 when the sensor 310 detects that the temperature of the memory device 305 has returned to the nominal temperature range. In this way, the first type of memory blocks 325 may serve as a data cache or buffer during times of extreme operating temperatures to ensure data integrity and may be scrubbed (e.g., erased) after the data has been moved to the higher density memory blocks. Additional details regarding the operation of the system 300 will be described with reference to Fig. 4. Although the discussion here is mainly directed to the case of a memory device including two types of memory blocks, in some cases, a memory device may include a set of three or more types of memory blocks (e.g., SLC, MLC, TLC, QLC) and may select the memory block type from the set of memory block types based on the temperature.

[0040] Fig. 4 illustrates a conceptual flowchart 400 supporting temperature-based memory management according to the examples disclosed herein. The operations of flowchart 400 may be performed by a memory device, such as memory device 100, or by a system including a memory device, such as system 300. In some cases, some operations shown in flowchart 400 may be omitted or rearranged. Although flowchart 400 primarily discusses managing memory based on temperature, a similar approach may be used to manage memory based on another operating state.

[0041] At 405, a memory device may identify or determine that there is data to be written to memory cells within the memory device. For example, a memory device may receive a write command (e.g., from a host device coupled to the memory device) to write data to memory cells.

[0042] At 410, the memory device may identify a temperature of the memory device based on a signal received from a temperature sensor and may determine whether the temperature of the memory device is between a lower threshold (T niedrig ) and a higher threshold (T hoch ), expressed by the temperature range T niedrig < Temperature < T hoch In some cases, the temperature range between T niedrig and T hochbe considered a relatively low-risk operating range, or nominal operating range, in which the probability of temperature-induced errors is relatively low. Temperatures outside this range may be associated with a higher risk of temperature-induced errors, particularly for memory cells that may be more sensitive to severe operating conditions, such as some multi-level cells (MLC, TLC, QLC, etc.). In some cases, the memory device may identify (e.g., sense, detect, monitor) the temperature of the memory device in response to receiving a write command to enable the memory device to select a memory block type to which the data is written.In some cases, the storage device may additionally or alternatively identify the temperature of the storage device in response to other stimuli or criteria, such as at periodic intervals, or may monitor the temperature substantially continuously.

[0043] In some cases, if the memory device determines at 410 that the temperature is within the nominal operating range, the memory device may then select a second type of memory blocks at 415, such as those described with reference to Fig. 3, and write the data to the second type of memory blocks. The second type of memory blocks may, for example, be multi-level memory blocks, such as MLC, TLC, or QLC memory blocks. In some cases, the second type of memory includes multi-level memory cells organized in a NAND configuration, such as NAND memory.

[0044] If the memory device determines at 410 that the temperature is outside the nominal operating range (e.g., very hot or very cold), the memory device may then select at 420 the first type of memory blocks, such as the first type of memory blocks 325 described with reference to Fig. 3, and determine whether the first type of memory blocks meets a threshold amount of data. For example, the memory device may determine whether a certain percentage or amount of memory blocks of the first type of memory blocks is already in use (e.g., contains data) and may therefore not be available to store data. The first type of memory blocks may be a type of memory that is less error-prone under harsh operating conditions than the second type of memory blocks, such as SLC memory blocks. In some cases, the first type of memory includes memory cells organized in a NAND configuration, such as NAND memory.

[0045] If the storage device determines at 420 that the first type of storage blocks meets (e.g., meets or exceeds) the threshold data amount, the storage device may then transmit a message (e.g., to a host device) at 425 indicating that the first type of storage blocks meets the threshold data amount. For example, the message may indicate that the first type of storage blocks is full or almost full (e.g., that the available capacity of the first type of storage blocks is below a threshold capacity, or that storage cells in the first type of storage blocks are unavailable to store additional data, or that the number of storage cells of the first type available to store additional data is below the threshold).In some cases, the host device may respond to the message by, for example, reducing the amount of data being written to memory, instructing the memory device to store the data elsewhere, reducing the clock speed of the memory device, or entering a read-only mode until the temperature returns to the rated temperature range. In some cases, the host device may configure the memory device with one or more threshold data sets, allowing the memory device to send an error message indicating when the use of the first type of memory blocks has reached each configured threshold data set, thereby providing progressive indications of the remaining capacity in the first type of memory blocks.

[0046] In some cases, at 425, the storage device may send one of at least two types of messages—a first type of message indicating that the first type of memory blocks is almost full (as described above) and a second type of message indicating that the first type of memory blocks is full (as also described above)—depending on whether the amount of data stored in the first type of memory blocks meets (or an amount of the remaining capacity of the first type of memory blocks is below) a first threshold corresponding to the first type of message or a second threshold corresponding to the second type of message.

[0047] If the storage device determines at 420 that the first type of memory blocks does not meet the threshold amount of data, then at 430 the storage device may write the data to memory cells in the first type of memory blocks. In some cases, if the storage device determines at 420 that the first type of memory blocks meets the threshold amount of data, but there are still blocks available for storage (e.g., if the first type of memory blocks is not completely full), the storage device may, in addition to sending an error message to the host device, write the data to memory cells in the first type of memory blocks.

[0048] After writing the data to the first type of memory blocks at 430, the memory device may then identify or monitor the temperature of the memory device at 435. When the memory device determines that the temperature of the memory device has returned to the nominal operating range, the memory device may then move some or all of the data stored in the first type of memory blocks to the second type of memory blocks at 440. In some cases, the memory device may then erase some or all of the contents of the first type of memory blocks to free the first type of memory blocks for subsequent data storage.

[0049] Fig. 5 shows an example of a system 500 that supports temperature-based memory management according to the examples disclosed herein. The system 500 may include a device 505, which may include a processor 510, a system memory controller 515, and a memory device 520. The memory device 520 may, for example, be an example of the memory device 100. The processor 510 may be configured to operate in coordination with the system memory controller 515 via the bus 525. The system memory controller 515 may be configured to operate with the processor 510 and the memory device 520 via the buses 525, 530.

[0050] In some examples, the memory device 520 may include one or more memory arrays 540, each of which may be coupled to a corresponding local memory controller 545. In some cases, the memory arrays 540 may be arrays of NAND memory cells, for example. In some cases, one or more of the memory arrays 540 may include a first type of memory blocks, and one or more of the memory arrays may include a second type of memory blocks. For example, the memory array 540-a may include SLC memory cells, and the memory array 540-n may include MLC, TLC, or QLC memory cells. In some cases, the memory arrays described with reference to Fig. 4 may be performed by local memory controller 545 and / or system memory controller 515. In some cases, device 505 may be coupled to an external host device 550, such as an external memory controller.

[0051] The local storage controller 545 may be configured to control operations of the storage array 540. Likewise, the local storage controller 545 may be configured to communicate with the system storage controller 515 (e.g., to receive and send data and / or commands). The local storage controller 545 may assist the system storage controller 515 in controlling the operation of the storage device 520 as described herein. In some cases, the storage device 520 does not include the system storage controller 515, and the local storage controller 545 of a host device 550 may perform the various functions described herein. As such, the local storage controller 545 may be configured to communicate with the system storage controller 515, with other local storage controllers 545, or directly with the host device 550.

[0052] Fig. 6 shows a block diagram 600 of a memory device 605 that supports temperature-based memory management according to examples disclosed herein. The memory device 605 may be an example of aspects of a memory device as described with reference to Fig. 1. The memory device 605 may include an identification component 610, a command component 615, a type selection component 620, a memory access component 625, and a sensor component 630. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses or other conductive connections).

[0053] The identification component 610 may identify data to be written to a memory device that includes memory cells of the first type and memory cells of the second type. In some examples, the identification component 610 may identify second data to be written to the memory device after the data is written to the one or more memory cells of the first type.

[0054] The sensor component 630 may identify a temperature of the storage device. In some examples, the sensor component 630 may determine that the temperature of the storage device is outside a temperature range. In some examples, the sensor component 630 may identify a temperature of the storage device. In some examples, the sensor component 630 may determine that the second temperature of the storage device is within the temperature range.

[0055] In some examples, after writing the data to the one or more memory cells of the first type, the sensor component 630 may identify a second temperature of the memory device. In some examples, the sensor component 630 may determine that the second temperature of the memory device is within the temperature range. In some examples, the sensor component 630 may determine that the temperature of the memory device is below a first threshold. In some examples, the sensor component 630 may determine that the temperature is above a second threshold.

[0056] In some examples, based on receiving a write command, sensor component 630 may determine that a first value of an operating state of the memory device is outside a range associated with the operating state. In some examples, after writing the data to the one or more memory cells of the first type, sensor component 630 may determine that a second value of the operating state of the memory device is within the range.

[0057] In some examples, the sensor component 630 may determine, based on receiving a write command, that a first value of an operating state of the memory device is outside a range associated with the operating state.

[0058] The type selection component 620 may select a memory cell type from a set of memory cell types based on the temperature of the memory device, wherein the set of memory cell types includes the first type and the second type. In some cases, the memory cells of the first type include non-and (NAND) memory cells, each configured to store a single bit. In some cases, the memory cells of the second type include NAND memory cells, each configured to store a set of respective bits.

[0059] In some examples, the type selection component 620 may select the memory cells of the first type based on the temperature being outside the temperature range. In some examples, the type selection component 620 may select the memory cells of the second type based on the second temperature being within the temperature range.

[0060] In some examples, the type selection component 620 may select the memory cells of the first type based on the temperature being below the first threshold. In some examples, the type selection component 620 may select the memory cells of the second type based on the temperature being above the temperature range.

[0061] Command component 615 may receive a write command for data at a memory device including memory cells of a first type and memory cells of a second type. In some examples, command component 615 may receive a second write command for second data at the memory device.

[0062] The memory access component 625 may write the data to one or more memory cells of the selected types based on selecting the type of memory cell from the set of memory cell types. In some examples, the memory access component 625 may write the data to one or more memory cells of the first type based on determining that the first value of the operating state is outside the range. In some examples, the memory access component 625 may write the data to one or more memory cells of the second type based on determining that the second value of the operating state is within the range.

[0063] In some examples, the memory access component 625 may write the second data to one or more of the memory cells of the second type. In some examples, the memory access component 625 may write the data to one or more memory cells of the second type based on the second temperature being within the temperature range. In some examples, the memory access component 625 may write the data to one or more memory cells of the second type based on determining that the third value of the operating state is within the range.

[0064] In some examples, the memory access component 625 may delete at least a portion of the data from the one or more memory cells of the first type after the data has been written to the one or more memory cells of the second type.

[0065] In some examples, the memory access component 625 may determine that an amount of data stored in memory cells of the first type meets a threshold data amount. In some examples, the memory access component 625 may indicate to a host device that the amount of data stored in the memory cells of the first type meets the data amount threshold.

[0066] In some examples, the memory access component 625 may determine that a second amount of data stored in memory cells of the first type meets a second threshold amount of data, where the threshold amount of data is less than the second threshold amount of data. In some examples, the memory access component 625 may indicate to the host device that the second amount of data stored in memory cells of the first type meets the second threshold amount of data.

[0067] In some examples, the memory access component 625 of the host device may indicate a characteristic of the temperature based on determining that the amount of data stored in memory cells of the first type meets the threshold amount of data.

[0068] In some examples, the memory access component 625 may determine that an available capacity of the memory cells of the first type is below a threshold capacity. In some examples, the memory access component 625 may indicate to a host device that the available capacity of the memory cells of the first type is below the threshold capacity.

[0069] Fig. 7 shows a flowchart illustrating one or more methods 700 that support temperature-based memory management according to the examples disclosed herein. The operations of method 700 may be implemented by a memory device or its components as described herein. For example, the operations of method 700 may be performed by a memory device as described with reference to Fig. 1 and Fig. 6. In some examples, a memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, a memory device may perform aspects of the described functions using specialized hardware.

[0070] At 705, the memory device may identify data for writing to the memory device, wherein the memory device includes memory cells of a first type and memory cells of a second type. The operations of 705 may be performed according to the methods disclosed herein. In some examples, aspects of the operations of 705 may be performed by an identification component, as described with reference to Fig. 6 described.

[0071] At 710, the memory device may identify a temperature of the memory device. The operations of 710 may be performed according to the methods disclosed herein. In some examples, aspects of the operations of 710 may be performed by a sensor component, as described with reference to Fig. 6 described.

[0072] At 715, the memory device may select a memory cell type from a set of memory cell types based on the temperature of the memory device, wherein the set of memory cell types includes the first type and the second type. The operations of 715 may be performed according to the methods disclosed herein. In some examples, aspects of the operations of 715 may be performed by a type selection component, as described with reference to Fig. 6 described.

[0073] At 720, the memory device may write the data to one or more memory cells of the selected types based on selecting the type of memory cell from the set of memory cell types. The operations of 720 may be performed according to the methods disclosed herein. In some examples, aspects of the operations of 720 may be performed by a memory access component, as described with reference to Fig. 6 described.

[0074] In some examples, a device described herein may perform one or more methods, such as method 700. The device may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for identifying data to write to a memory device including memory cells of a first type and memory cells of a second type, identifying a temperature of the memory device, selecting a memory cell type from a set of memory cell types based on the temperature of the memory device, the set of memory cell types including the first type and the second type, and writing the data to one or more memory cells of the selected type based on selecting the memory cell type from the set of memory cell types.

[0075] Some examples of the method 700 and the apparatus described herein may further include acts, features, means, or instructions for receiving a write command for the data, where determining the temperature may be based on receiving the write command.

[0076] In some examples of the method 700 and the apparatus described herein, selecting the memory cell type may include acts, features, means, or instructions for determining that the temperature of the memory device may be outside a temperature range and for selecting the memory cells of the first type based on the temperature being outside the temperature range.

[0077] Some examples of the method 700 and the apparatus described herein may further include acts, features, means, or instructions for identifying second data to write to the memory device after writing the data to the one or more memory cells of the first type, identifying a second temperature of the memory device, determining that the second temperature of the memory device may be within the temperature range, selecting the memory cells of the second type based on the second temperature being within the temperature range, and writing the second data to one or more of the memory cells of the second type.

[0078] Some examples of the method 700 and the apparatus described herein may further include acts, features, means, or instructions for identifying a second temperature of the memory device after writing the data to one or more memory cells of the first type, determining whether the second temperature of the memory device may be within the temperature range, and writing the data to one or more memory cells of the second type based on whether the second temperature is within the temperature range.

[0079] Some examples of the method 700 and the apparatus described herein may further include acts, features, means, or instructions for erasing at least a portion of the data from the one or more memory cells of the first type after writing the data to the one or more memory cells of the second type.

[0080] In some examples of the method 700 and the apparatus described herein, selecting the memory cell type may include acts, features, means, or instructions for determining that the temperature may be below a first threshold and selecting the memory cells of the first type based on the temperature being below the first threshold.

[0081] In some examples of the method 700 and the apparatus described herein, selecting the memory cell type may include acts, features, means, or instructions for determining that the temperature may be above a second threshold and selecting the memory cells of the second type based on the temperature being above the second threshold.

[0082] Some examples of the method 700 and the apparatus described herein may further include acts, features, means, or instructions for determining that an amount of data stored in memory cells of the first type meets a threshold amount of data, and for indicating to a host device that the amount of data stored in memory cells of the first type meets the threshold amount of data.

[0083] Some examples of the method 700 and the apparatus described herein may further include acts, features, means, or instructions for determining that a second amount of data stored in memory cells of the first type meets a second threshold amount of data, wherein the threshold amount of data is less than the second threshold amount of data, and for indicating to the host device that the second amount of data stored in memory cells of the first type meets the second threshold amount of data.

[0084] Some examples of the method 700 and the apparatus described herein may further include acts, features, means, or instructions for indicating a characteristic of the temperature of the host device based on determining that the amount of data stored in memory cells of the first type meets the threshold amount of data.

[0085] In some examples of the method 700 and the apparatus described herein, the memory cells of the first type include NAND memory cells each configured to store a single respective bit, and the memory cells of the second type include NAND memory cells each configured to store a set of respective bits.

[0086] Fig. 8 shows a flowchart illustrating one or more methods 800 that support temperature-based memory management according to the examples disclosed herein. The operations of method 800 may be implemented by a memory device or its components as described herein. For example, the operations of method 800 may be performed by a memory device as described with reference to Fig. 1 and Fig. 6. In some examples, a memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, a memory device may perform aspects of the described functions using specialized hardware.

[0087] At 805, the memory device may receive a write command for data at a memory device including memory cells of a first type and memory cells of a second type. The operations of 805 may be performed according to the methods disclosed herein. In some examples, aspects of the operations of 805 may be performed by a command component, as described with reference to Fig. 6 described.

[0088] At 810, the memory device may determine, based on receiving the write command, that a first value of an operating state of the memory device is outside a range associated with the operating state. The operations of 810 may be performed according to the methods disclosed herein. In some examples, aspects of the operations of 810 may be performed by a sensor component, as described with reference to Fig. 6 described.

[0089] In 815 examples, the memory device may write the data to one or more memory cells of the first type based on determining that the first value of the operating state is out of range. The operations of 815 may be performed according to the methods disclosed herein. In some examples, aspects of the operations of 815 may be performed by a memory access component, as described with reference to Fig. 6 described.

[0090] In 820 examples, after writing the data to the one or more memory cells of the first type, the memory device may determine that a second value of the operating state of the memory device is within the range. The operations of 820 may be performed according to the methods disclosed herein. In some examples, aspects of the operations of 820 may be performed by a sensor component, as described with reference to Fig. 6 described.

[0091] In 825 examples, the memory device may write the data to one or more memory cells of the second type based on determining that the second value of the operating state is out of range. The operations of 825 may be performed according to the methods disclosed herein. In some examples, aspects of the operations of 825 may be performed by a memory access component, as described with reference to Fig. 6 described.

[0092] In some examples, a device described herein may perform one or more methods, such as method 800. The device may include features, means, or instructions (e.g.,a non-transitory computer-readable medium storing processor-executable instructions) to receive a write command for data at a memory device including memory cells of a first type and memory cells of a second type, determine based on receipt of the write command that a first value of an operating state of the memory device is outside a range associated with the operating state, write the data to one or more memory cells of the first type based on determining that the first value of the operating state is outside the range, determine, after writing the data to the one or more memory cells of the first type, that a second value of the operating state of the memory device is within the range, and write the data to one or more memory cells of the second type based on determining that the second value of the operating state is within the range.

[0093] Some examples of the method 800 and the apparatus described herein may further include acts, features, means, or instructions for receiving a second write command for second data at the memory device, determining, based on receiving the second write command, that a third value of the operating state of the memory device may be within the range, and writing the second data to one or more memory cells of the second type based on determining that the third value of the operating state may be within the range.

[0094] Some examples of the method 800 and the apparatus described herein may further include acts, features, means, or instructions for determining that an available capacity of the memory cells of the first type may be below a threshold capacity, and for indicating to a host device that the available capacity of the memory cells of the first type may be below the threshold capacity.

[0095] It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions of two or more of the methods may be combined.

[0096] A device is described. The device may include memory cells of a first type, memory cells of a second type, a temperature sensor, a controller coupled to the memory cells of the first type, the memory cells of the second type, and the temperature sensor, the controller operable to cause the device to identify data for writing to a memory device, determine that a temperature indicated by the temperature sensor is outside a temperature range, and write the data to one or more memory cells of the first type based on the temperature being outside the temperature range.

[0097] Some examples may further include receiving a write command for the data, where identifying the data and determining that the temperature may be outside the temperature range may be based on receiving the write command.

[0098] Some examples may further include, after writing the data to one or more memory cells of the first type, identifying second data to write to the memory device, determining that a second temperature indicated by the temperature sensor may be within the temperature range, and writing the second data to one or more memory cells of the second type based on the determination that the second temperature may be within the temperature range.

[0099] Some examples may further include, after writing the data to one or more memory cells of the first type, determining that a second temperature indicated by the temperature sensor may be within the temperature range, and writing the data to one or more memory cells of the second type after determining that the second temperature may be within the temperature range.

[0100] Some examples may further include determining whether an amount of the memory cells of the first type that may be available to store additional data may be below a threshold, and transmitting an indication that the amount of the memory cells of the first type that may be available to store additional data may be below the threshold.

[0101] Some examples may further include determining that memory cells of the first type may not be available to store additional data and communicating an indication that memory cells of the first type may not be available to store additional data to a host device.

[0102] In some examples, the memory cells of the first type may be configured to store a first amount of information per memory cell, and the memory cells of the second type may be configured to store a second amount of information per memory cell, wherein the second amount is greater than the first amount.

[0103] In some examples, the memory cells of the first type include non-and (NAND) memory cells, each configured to store a single respective bit, and the memory cells of the second type include NAND memory cells, each configured to store a set of respective bits.

[0104] In some examples, the temperature sensor, the memory cells of the first type, and the memory cells of the second type may be included in the memory device.

[0105] In some examples, the controller may be included in the storage device.

[0106] The information and signals described herein may be represented using a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referred to in the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. In some drawings, signals may be represented as a single signal; however, one skilled in the art will understand that the signal may represent a bus of signals, where the bus may have a variety of bit widths.

[0107] The term "virtual ground," as used here, refers to a node in an electrical circuit that is maintained at a voltage of approximately zero volts (0 V) but is not directly coupled to ground. Accordingly, the voltage of a virtual ground can fluctuate temporarily and return to approximately 0 V in steady-state. A virtual ground can be implemented using various electronic circuit elements, such as a voltage divider consisting of operational amplifiers and resistors. Other implementations are also possible. "Virtual ground" or "virtual grounded" means connected to approximately 0 V.

[0108] The terms "electronic communication," "conductive contact," "connected," and "coupled" can refer to a relationship between components that supports the flow of signals between the components. Components are considered to be electronically communicating with each other (or in conductive contact with each other, or connected or coupled) if there is a conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with each other, or connected or coupled to each other) can be an open circuit or a closed circuit, depending on the operation of the device that includes the connected components.The conductive path between the connected components can be a direct conductive path between the components, or the conductive path between the connected components can be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some cases, the signal flow between the connected components may be temporarily interrupted, e.g., by one or more intermediate components such as switches or transistors.

[0109] The term "coupling" refers to a transition from an open circuit between components, where signals cannot currently be transmitted through a conductive path between the components, to a closed circuit between components, where signals can be transmitted through the conductive path between components. When one component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components through a conductive path that previously did not allow signal flow.

[0110] The term "isolated" refers to a relationship between components in which no signals can currently flow between the components. Components are isolated from each other when an open circuit exists between them. For example, two components separated by a switch positioned between the components are isolated from each other when the switch is open. When a controller isolates two components from each other, the controller causes a change that prevents signals from flowing between the components along a conductive path that previously allowed signals to flow.

[0111] As used here, the term "essentially" means that the modified feature (e.g., a verb or adjective modified by the term "essentially") need not be absolute, but is close enough to achieve the benefits of the feature.

[0112] The devices discussed herein, including a memory device, can be formed on a semiconductor substrate, such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate, or portions of the substrate, can be controlled by doping with various chemicals such as phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by some other dopant.

[0113] A switching component or transistor discussed here may be a field-effect transistor (FET), a three-terminal device containing a source, a drain, and a gate. The terminals may be connected to other electronic elements through conductive materials, such as metals. The source and drain may be conductive and may contain a heavily doped, such as a degenerate, semiconductor region. The source and drain may be separated by a lightly doped semiconductor region, or channel. If the channel is n-type (i.e., most of the charge carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most of the charge carriers are holes), the FET may be referred to as a p-type FET. The channel may be covered by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate.For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to conduct. A transistor can be "turned on" or "activated" when a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate. The transistor can be "turned off" or "deactivated" when a voltage less than the transistor's threshold voltage is applied to the transistor's gate.

[0114] The description contained herein, in conjunction with the accompanying drawings, describes example configurations and does not represent all examples that may be implemented or fall within the scope of the claims. As used herein, the term "exemplary" means "serving as an example, variation, or illustration" and not "preferred" or "advantageous over other examples." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form so as not to obscure the concepts of the described examples.

[0115] In the accompanying figures, similar components or features may have the same reference numeral. Furthermore, different components of the same type may be distinguished by following the reference numeral with a hyphen and a second designation that distinguishes the similar components. If only the first reference numeral is used in the description, the description applies to each of the similar components with the same first reference numeral, regardless of the second reference numeral.

[0116] For example, the various illustrative blocks and components described in connection with the present disclosure may be implemented or executed using a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof to perform the functions described herein. A general-purpose processor may be a microprocessor; alternatively, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0117] The functions described herein may be implemented in hardware, in software executed by a processor, in firmware, or in a combination thereof. When implemented in software executed by a processor, the functions may be stored or transmitted on a computer-readable medium as one or more instructions or as code. Other examples and implementations are within the scope of the disclosure and the appended claims. For example, due to the nature of software, the described functions may be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations thereof. Features that implement functions may also be physically arranged in different locations, including being distributed such that portions of functions are implemented in different physical locations.

Claims

[1] Method comprising: Identifying data for writing to a memory device (305) comprising memory cells of a first type (325) and memory cells of a second type (330); Identifying a temperature of the storage device (305); Determining whether the temperature of the memory device (305) is outside a nominal operating range of the memory device (305); Selecting the memory cells of the first type (325) based at least in part on the temperature of the memory device (305) being outside the nominal operating range of the memory device (305); Determining whether an amount of data stored in the memory cells of the first type (325) satisfies a threshold amount of data; and Writing the data to one or more memory cells of the first type based at least in part on selecting the memory cells of the first type (325) and the amount of data stored in the memory cells of the first type (325) not meeting the threshold amount of data. [2] The method of claim 1, further comprising: Receiving a write command for the data, wherein the temperature determination is based at least in part on receiving the write command. [3] The method of claim 1, further comprising: identifying second data for writing to the memory device (305) after writing the data to the one or more memory cells of the first type (325); identifying a second temperature of the storage device; Determining that the second temperature of the storage device is within the nominal operating range of the storage device (305); Selecting the memory cells of the second type based at least in part on the second temperature being within the nominal operating range of the memory device (305); and Writing the second data into one or more of the memory cells of the second type (330). [4] The method of claim 1, further comprising: identifying a second temperature of the memory device (305) after writing the data to the one or more memory cells of the first type (325); Determining that the second temperature of the storage device is within the nominal operating range of the storage device (305); and Writing the data to one or more memory cells of the second type based at least in part on the second temperature being within the nominal operating range of the memory device (305). [5] The method of claim 4, further comprising: Deleting at least a portion of the data from the one or more memory cells of the first type (325) after writing the data to the one or more memory cells of the second type (330). [6] The method of claim 1, wherein selecting the memory cells of the first type (325) comprises: Determining that the temperature is below a first threshold; and Selecting the memory cells of the first type (325) based at least in part on the temperature being below the first threshold. [7] The method of claim 1, wherein selecting the memory cells of the first type (325) comprises: Determining that the temperature is above a second threshold; and Selecting the memory cells of the second type based at least in part on the temperature being above the second threshold. [8] The method of claim 1, further comprising: Determining that the amount of data stored in the memory cells of the first type (325) satisfies the threshold data amount; and indicate to a host device that the amount of data stored in memory cells of the first type (325) meets the threshold data amount. [9] The method of claim 8, further comprising: determining that a second data set stored in memory cells of the first type (325) satisfies a second threshold data set, wherein the threshold data set is less than the second threshold data set; and indicate to the host device that the second amount of data stored in memory cells of the first type (325) meets the second threshold amount of data. [10] The method of claim 8, further comprising: indicate to the host device a characteristic of the temperature based at least in part on determining that the amount of data stored in memory cells of the first type (325) meets the threshold amount of data. [11] The method of claim 1, wherein: the memory cells of the first type (325) comprise NAND memory cells each configured to store a single respective bit; and the memory cells of the second type (330) comprise NAND memory cells each configured to store a plurality of respective bits. [12] Device comprising: Memory cells of a first type (325); memory cells of a second type (330); a temperature sensor (310); and a controller (320) coupled to the first type of memory cells (325), the second type of memory cells (330), and the temperature sensor (310), the controller (320) operable to cause the device to: identifying data to be written to a storage device (305); Determining that a temperature indicated by the temperature sensor is outside a nominal operating range of the memory device (305); Determining whether an amount of data stored in the memory cells of the first type (325) satisfies a threshold amount of data; and Writing the data to one or more memory cells of the first type (325) based at least in part on the temperature being outside the nominal operating range of the memory device (305) and determining that the amount of data stored in the memory cells of the first type (325) does not meet the threshold data amount. [13] The device of claim 12, wherein the controller (320) is further operable to cause the device to: Receiving a write command for the data, wherein identifying the data and determining that the temperature is outside the nominal operating range of the memory device (305) are based at least in part on receiving the write command. [14] The device of claim 12, wherein the controller (320) is further operable to cause the device to: identifying second data for writing to the memory device (305) after writing the data to one or more memory cells of the first type (325); Determining that a second temperature indicated by the temperature sensor is within the nominal operating range of the storage device (305); and Writing the second data to one or more memory cells of the second type (330) based on determining that the second temperature is within the nominal operating range of the memory device (305). [15] The device of claim 12, wherein the controller (320) is further operable to cause the device to: Determining, after writing the data to one or more memory cells of the first type (325), that a second temperature indicated by the temperature sensor is within the nominal operating range of the memory device (305); and Writing the data to one or more memory cells of the second type (330) after determining that the second temperature is within the nominal operating range of the memory device (305). [16] The device of claim 12, wherein the controller (320) is further operable to cause the device to: Determining whether a quantity of the memory cells of the first type (325) available for storing additional data is below a threshold; and Transmitting to a host device an indication that the amount of memory cells of the first type (325) available for storing additional data is below the threshold. [17] The device of claim 12, wherein the controller (320) is further operable to cause the device to: Determining that memory cells of the first type (325) are not available to store additional data; and Transmitting an indication that memory cells of the first type (325) are not available to store additional data to a host device. [18] Apparatus according to claim 12, wherein: the memory cells of the first type (325) are configured to store a first amount of information per memory cell; and the memory cells of the second type (330) are configured to store a second amount of information per memory cell, the second amount being greater than the first amount. [19] Apparatus according to claim 12, wherein: the memory cells of the first type (325) comprise NAND memory cells each configured to store a single respective bit; and the memory cells of the second type (330) comprise NAND memory cells each configured to store a plurality of respective bits. [20] The device of claim 12, wherein the temperature sensor (310), the memory cells of the first type (325) and the memory cells of the second type (330) are included in the memory device (305). [21] The device of claim 12, wherein the controller (320, 510) is included in the storage device (305). [22] Method comprising: Receiving a write command for data to a memory device (305) comprising memory cells of a first type (325) and memory cells of a second type (330); Determining, based at least in part on receiving the write command, that a first value of an operating state of the memory device (305) is outside a range associated with the operating state; determining that an available capacity of the memory cells of the first type (325) is below a threshold capacity; Writing the data to one or more memory cells of the first type (325) based at least in part on determining that the first value of the operating state is out of range and determining that the available capacity of the memory cells of the first type (325) is below the threshold capacity; Determining, after writing the data to the one or more memory cells of the first type (325), that a second value of the operating state of the memory device (305) is within the range; and Writing the data to one or more memory cells of the second type (330) based at least in part on determining that the second value of the operating state is within the range. [23] The method of claim 22, further comprising: Receiving a second write command for second data on the storage device (305); Determining, based at least in part on receiving the second write command, that a third value of the operating state of the memory device (305) is within the range; and Writing the second data to one or more memory cells of the second type (330) based at least in part on determining that the third value of the operating state is within the range. [24] The method of claim 22, further comprising: indicate to a host device that the available capacity of the memory cells of the first type (325) is below the threshold capacity.

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