Multilayer ceramic capacitor with ultra-wideband performance and method of manufacturing

Abstract

A multilayer broadband ceramic capacitor (100) having a first end (119) and a second end (121) spaced from the first end (119) in a longitudinal direction (132) perpendicular to a lateral direction (134), wherein the lateral direction (134) and the longitudinal direction (132) are each perpendicular to a Z-direction (136), the multilayer broadband ceramic capacitor (100) comprising: a monolithic body comprising a plurality of dielectric layers; a first outer terminal (118) located along the first end (119); a second outer terminal (120) located along the second end (121); comprising a plurality of active electrodes (106, 108) arranged within the monolithic body and parallel to the longitudinal direction (132); a first shielding electrode (22) arranged within the monolithic body and parallel to the longitudinal direction (132), wherein the first shielding electrode (22) is connected to the first external terminal (118), wherein the first shielding electrode (22) has a first longitudinal edge (28) oriented in the lateral direction (134) and facing away from the first external terminal (118), wherein the first shielding electrode (22) has a second longitudinal edge (30) oriented in the lateral direction (134) and facing away from the first external terminal (118), and wherein the second longitudinal edge (30) is offset in the longitudinal direction (132) by a shielding electrode offset distance (32) from the first longitudinal edge (28); and a second shield electrode (24) connected to the second external terminal (120), the second shield electrode (24) being approximately aligned with the first shield electrode (22) in the Z direction (136).

Description

Background of the invention

[0001] The diversity of modern technical applications creates a need for efficient electronic components and the integrated circuits in which they are used. Capacitors are a fundamental component used for filtering, coupling, bypassing, and other aspects of such modern applications, including wireless communications, alarm systems, radar systems, circuit switching, matching networks, and many other applications. A drastic increase in the speed and packaging density of integrated circuits, in particular, requires advances in coupling capacitor technology. When high-capacity coupling capacitors are subjected to the high clock frequencies of many current applications, performance characteristics become increasingly important. Because capacitors are fundamental to such a wide variety of applications, their precision and efficiency are essential.Many specific aspects of capacitor construction are therefore in focus to improve their performance characteristics.

[0002] US 2012 / 0 297 596 A1 describes a method for producing a multilayer ceramic component, comprising: forming a ceramic capacitor body from a plurality of electrode layers and dielectric layers;

[0003] Attaching first and second external terminals to opposite ends of the ceramic capacitor body; and

[0004] Coating the ceramic capacitor body to increase the breakdown voltage; wherein the plurality of electrode layers comprises layers of active electrodes and layers of shielding electrodes, and wherein the layers of active electrodes are alternately arranged such that a first of the plurality of active electrodes extends inwardly from one end of the ceramic capacitor body and a next inner active electrode extends inwardly from an opposite end of the ceramic capacitor body; wherein the layers of shielding electrodes comprise an upper inner electrode shield and an opposite lower inner electrode shield, the upper inner electrode shield and the opposite lower inner electrode shield being located on opposite sides of the plurality of active electrodes, each electrode shield extending inwardly to or beyond a corresponding external terminal to provide shielding; wherein the layers of active electrodes further comprise layers of side shields on opposite sides of the active electrodes to provide additional shielding.

[0005] US 2010 / 0 039 749 A1 describes a multilayer capacitor comprising: a plurality of first electrode sheets, each first electrode sheet comprising a first main electrode and a separate first counter electrode arranged substantially in the same plane, the first main electrode comprising a central portion and at least one extension arm positioned adjacent to the central portion, and the first counter electrode comprising at least one extension arm substantially longitudinally aligned with the at least one extension arm of the first main electrode; a plurality of second electrode sheets, each second electrode sheet comprising a second main electrode and a separate second counter electrode arranged substantially in the same plane, the second main electrode comprising a central portion and at least one extension arm positioned adjacent the central portion, and the second counter electrode comprising at least one extension arm longitudinally aligned with the at least one extension arm of the second main electrode;

[0006] dielectric material interposed between adjacently stacked first and second electrode sheets to form a stacked array of unit cells, wherein in each unit cell at least a portion of the central portion of each first main electrode overlaps with at least a portion of the central portion of a second main electrode; a first external terminal electrically connected to each first main electrode and each second counter electrode; and a second external terminal electrically connected to each second main electrode and each first counter electrode. Brief description of the invention

[0007] According to one embodiment of the present invention, a multilayer broadband ceramic capacitor may have a first end and a second end spaced from the first end in a longitudinal direction perpendicular to a lateral direction. The lateral direction and the longitudinal direction may each be perpendicular to a Z direction. The multilayer broadband ceramic capacitor may include a monolithic body comprising a plurality of dielectric layers, a first external terminal located along the first end, and a second external terminal located along the second end. The multilayer broadband ceramic capacitor may include a plurality of active electrodes disposed within the monolithic body and parallel to the longitudinal direction.The multilayer broadband ceramic capacitor may include a first shield electrode disposed within the monolithic body and parallel to the longitudinal direction. The first shield electrode may be connected to the first external terminal. The first shield electrode may have a first longitudinal edge oriented in the lateral direction and facing away from the first external terminal. The first shield electrode may have a second longitudinal edge oriented in the lateral direction and facing away from the first external terminal. The second longitudinal edge may be offset longitudinally from the first longitudinal edge by a shield electrode offset distance. A second shield electrode may be connected to the second external terminal and approximately aligned with the first shield electrode in the Z direction.

[0008] According to another embodiment of the present invention, a method for forming a multilayer broadband ceramic capacitor is disclosed. The method may comprise forming a plurality of active electrodes on a plurality of active electrode layers. The method may comprise forming a first shield electrode on a shield electrode layer. The first shield electrode may extend to a first end of a monolithic body of the capacitor. The first shield electrode may have a first longitudinal edge oriented in the lateral direction and facing away from the first external terminal. The first shield electrode may have a second longitudinal edge oriented in the lateral direction and facing away from the first external terminal. The second longitudinal edge may be longitudinally offset from the first longitudinal edge by a shield electrode offset distance.The method may include forming a second shield electrode on the shield electrode layer, extending to the second end of the monolithic body and approximately aligned with the first shield electrode in the Z direction. The method may include stacking the plurality of active electrode layers and the shield electrode layer to form the monolithic body such that the plurality of active electrode layers and the plurality of shield electrodes are parallel to a longitudinal direction of the capacitor. Brief description of the drawings

[0009] A full and thorough disclosure of the present invention, including the best mode of carrying it out, to those skilled in the art is particularly pointed out in the remainder of the specification, including reference to the accompanying drawings, in which: Fig.1A shows a top view of an embodiment of an active electrode layer according to aspects of the present disclosure; Fig. Figure 1B shows a perspective view of alternating electrode layers arranged as shown in Fig. 1A, configured in accordance with aspects of the present disclosure; Fig. Figure 1C shows a plan view of the embodiment of the active electrode layer of Fig. 1A, in which a plurality of capacitive regions are formed according to aspects of the present disclosure; Fig. 1D shows a top view of the embodiment of a shield electrode layer in which a plurality of capacitive regions are formed according to aspects of the present disclosure; Fig. Figure 1E shows a side cross-sectional view of an embodiment of a capacitor comprising a plurality of regions in which active electrode layers are configured as shown in Figures Fig.1A to 1C, and a shielding electrode layer is configured as shown in Fig. 1C, according to aspects of the present disclosure; Fig. 2A shows a top view of another embodiment of an active electrode layer according to aspects of the present disclosure; Fig. Figure 2B shows a top view of the embodiment of the active electrode layer of Fig. 2A, in which a plurality of capacitive regions are formed according to aspects of the present disclosure; Fig. Figure 2C shows a perspective view of alternating electrode layers arranged as shown in Fig. 2A, configured in accordance with aspects of the present disclosure; Fig. 3A is a side cross-sectional view of another embodiment of a capacitor including multiple regions in which active electrode layers are configured as shown in FIGS. Fig.2A to 2C, and a shielding electrode layer is configured as shown in Fig. 1D, according to aspects of the present disclosure; Fig. 3B shows another embodiment of a capacitor according to aspects of the present disclosure; Fig. Figure 4 shows a schematic diagram of a circuit of the embodiment of a capacitor used in the Fig. 1A to 1E, with multiple capacitive regions; Fig. Figure 5 shows a schematic diagram of a circuit of the embodiment of a capacitor used in the Fig. 2A to 2C, with multiple capacitive regions; Fig. Figure 6 shows simulated insertion loss data of the capacitor of the Fig. 1A to 1E in a first orientation as shown in Fig. 1E, and a second orientation; Fig.7A to 7D show top views of armature electrodes, shield electrodes and active electrodes of the capacitor of Fig. 6 according to an embodiment of the present invention; The Fig. 8A to 8D show top views of additional embodiments of active electrode layers according to certain embodiments of the present invention; Fig. 9 shows the capacitor of Fig. 1E in the second orientation; and Fig. Figure 10 shows a representative insertion loss characteristic measured for one multilayer ceramic out of eight multilayer ceramic capacitors that were manufactured. Detailed description of the preferred embodiments

[0010] Those skilled in the art should understand that the present discussion is only a description of exemplary embodiments and is not intended to limit the broader aspects of the present invention.

[0011] Generally speaking, the present invention relates to a multilayer ceramic capacitor. More specifically, the present invention relates to a multilayer ceramic capacitor comprising alternating dielectric and electrode layers within a single monolithic body.

[0012] A plurality of active electrodes, a first shield electrode, and a second shield electrode may be arranged within the monolithic body. The shield electrodes may be configured to improve the response (e.g., insertion loss, return loss, etc.) of the capacitor. The shield electrodes may have offset longitudinal edges defining one or more steps, as described, for example, below with reference to Fig.1D. For example, the first shield electrode may be connected to the first external terminal. The first shield electrode may have a first longitudinal edge oriented in the lateral direction and facing away from the first external terminal. The first shield electrode may have a second longitudinal edge oriented in the lateral direction and facing away from the first external terminal. The second longitudinal edge may be offset in the longitudinal direction from the first longitudinal edge by a shield electrode offset distance. A second shield electrode may be connected to the second external terminal and approximately aligned with the first shield electrode in the Z direction. The multilayer broadband ceramic capacitor may be configured for mounting on the mounting surface such that the first and second shield electrodes are present between the plurality of active electrode layers and the mounting surface.

[0013] The active electrode region may comprise active electrodes configured to have a plurality of capacitive elements within a single set of stacked electrodes. For example, a primary capacitive element may be effective at relatively low frequencies, while a secondary capacitive element may be effective at relatively moderate and / or high frequencies. For example, the primary capacitance may be between 1 and 500 nF, such as between about 10 and 100 nF, while the secondary capacitance may be between 1 and 500 pF, such as between 10 and 100 pF.

[0014] The inventors have discovered that such a configuration can provide a multilayer ceramic capacitor with low insertion loss over a wide frequency range. In general, insertion loss is the power loss through the capacitor and can be measured using any method well known in the art.

[0015] The shielding electrodes may be arranged within the monolithic body in a variety of configurations, which may have different insertion loss characteristics. For example, in one embodiment, shielding electrodes may be located between an active electrode region and a bottom surface of the capacitor. A dielectric region free of shielding electrodes may be located between the active electrode region and a top surface of the capacitor, as described below, for example, with respect to Fig.1E. In such embodiments, the capacitor may have an insertion loss that is greater than about -0.5 dB from about 1 GHz to about 40 GHz, in some embodiments greater than about -0.4 dB, in some embodiments greater than about -0.35 dB, and in some embodiments greater than about -0.3 dB. In some embodiments, the capacitor may have an insertion loss that is greater than about -0.4 dB at about 10 GHz, in some embodiments greater than about -0.35 dB at about 10 GHz, in some embodiments greater than about -0.3 dB, and in some embodiments greater than about -0.25 dB at about 10 GHz. The capacitor may have an insertion loss that is greater than about -0.4 dB at about 20 GHz, in some embodiments greater than about -0.35 dB at about 20 GHz, and in some embodiments greater than about -0.3 dB at about 20 GHz.The capacitor may have an insertion loss greater than about -0.4 dB at about 30 GHz, in some embodiments greater than about -0.35 dB at about 30 GHz, in some embodiments greater than about -0.3 dB at about 30 GHz, and in some embodiments greater than about -0.25 dB at about 30 GHz. The capacitor may have an insertion loss greater than about -0.4 dB at about 40 GHz, in some embodiments greater than about -0.35 dB at about 40 GHz, in some embodiments greater than about -0.3 dB at about 40 GHz, and in some embodiments greater than about -0.25 dB at about 40 GHz.

[0016] In some embodiments, the broadband multilayer ceramic capacitor may have an insertion loss that is in the range of about -0.05 dB to about -0.4 dB from about 5 GHz to about 20 GHz, in some embodiments in the range of about -0.05 dB to about -0.3 dB from about 10 GHz to about 20 GHz, in some embodiments from about -0.05 dB to about -0.3 dB from about 20 GHz to about 30 GHz, and in some embodiments from about 30 GHz to about 40 GHz from about -0.05 dB to about -0.3 dB.

[0017] In another embodiment, one or more lower shielding electrodes may be arranged between the active electrode region and the bottom surface of the capacitor. One or more upper shielding electrodes may be arranged between the active electrode region and the top surface of the capacitor, as described below, for example, with respect to Fig.3B. In such embodiments, the insertion loss may be approximately -0.3 dB or more, such as approximately -0.28 dB or more, such as approximately -0.25 dB or more, such as approximately -0.23 dB or more, when measured over a frequency range of 4 GHz to 10 GHz.

[0018] In such embodiments, the insertion loss may be about -0.4 dB or more, such as about -0.38 dB or more, such as about -0.35 dB or more, such as about -0.34 dB or more, when measured over a frequency range of 13 GHz to 20 GHz.

[0019] In such embodiments, the insertion loss may be about -0.45 dB or more, such as about -0.4 dB or more, such as about -0.38 dB or more, such as about -0.35 dB or more, such as about -0.32 dB or more, when measured over a frequency range of 23 GHz to 30 GHz.

[0020] In such embodiments, the insertion loss may be about -0.55 dB or more, such as about -0.5 dB or more, such as about -0.48 dB or more, such as about -0.45 dB or more, such as about -0.43 dB or more when measured over a frequency range of 33 GHz to 40 GHz.

[0021] The ratio of the capacitor length to the shield electrode offset distance may be greater than about 2, in some embodiments greater than about 5, in some embodiments, in some embodiments greater than about 10, in some embodiments greater than about 15, in some embodiments greater than about 20, and in some embodiments greater than about 40.

[0022] The first shielding gap distance and / or second shielding gap distance may be in a range from about 10 µm to about 200 µm, in some embodiments from about 20 µm to about 150 µm, and in some embodiments from about 30 µm to about 80 µm.

[0023] The shield electrode offset distance may range from about 75 µm to about 300 µm, in some embodiments from about 100 µm to about 250 µm, and in some embodiments from about 125 µm to about 175 µm.

[0024] In some embodiments, the second shield electrode may have a first longitudinal edge oriented in the lateral direction and facing away from the second outer terminal. The second shield electrode may have a second longitudinal edge oriented in the lateral direction and facing away from the second outer terminal. The second longitudinal edge may be offset in the longitudinal direction from the first longitudinal edge by approximately the shield electrode offset distance.

[0025] A first shield gap distance may be formed in the longitudinal direction between the first longitudinal edge of the first shield electrode and the first longitudinal edge of the second shield electrode. The capacitor may have a capacitor length in the longitudinal direction between the first end and the second end of the capacitor. The ratio of the capacitor length to the first shield gap distance may be greater than about 2, in some embodiments greater than about 5, in some embodiments, greater than about 10, in some embodiments, greater than about 15, in some embodiments, greater than about 20, and in some embodiments, greater than about 40. For example, the first shield gap distance may be in a range from about 25 µm to about 400 µm, in some embodiments from about 40 µm to about 300 µm, in some embodiments from about 50 µm to about 200 µm, and in some embodiments from about 75 µm to about 150 µm.

[0026] In some embodiments, a second shield gap distance may be created in the longitudinal direction between the second longitudinal edge of the first shield electrode and the second longitudinal edge of the second shield electrode. The ratio of the second shield gap distance to the first shield gap distance may range from about 0.5 to about 40, in some embodiments from about 0.7 to about 20, in some embodiments from about 1.1 to about 10, in some embodiments from about 1.5 to about 8, and in some embodiments from about 2 to about 6. The ratio of the second shield gap distance to the capacitor length may range from about 1.1 to about 40, in some embodiments from about 1.2 to about 20, in some embodiments from about 1.3 to about 10, in some embodiments from about 1.5 to about 5, and in some embodiments from about 2 to about 4.For example, the second shield gap distance may be in a range from about 25 µm to about 1200 µm, in some embodiments from about 50 µm to about 1000 µm, in some embodiments from about 100 µm to about 800 µm, and in some embodiments from about 200 µm to about 600 µm.

[0027] However, it should be understood that in some embodiments, the second shield gap spacing may be approximately equal to the first shield gap spacing. In other words, the shield electrodes may be free of stepped portions, so that the shield gap spacing between the shield electrodes may be approximately uniform across the width of the shield electrodes.

[0028] The first shield electrode may have a third longitudinal edge oriented in the lateral direction and facing away from the first outer terminal. The second shield electrode may have a third longitudinal edge oriented in the lateral direction and facing away from the second outer terminal. A third shield gap spacing may be created in the longitudinal direction between the third longitudinal edge of the first shield electrode and the third longitudinal edge of the second shield electrode. The first shield electrode may be symmetrical in the lateral direction about a longitudinal centerline extending in the longitudinal direction.

[0029] In some embodiments, a shield-to-ground distance may be defined as the distance between the shield electrodes and the bottom surface of the capacitor. When multiple shield electrode layers are used, the shield-to-ground distance may be defined as the distance between the bottommost shield electrode layer and the bottom surface. The ratio of the capacitor thickness to the shield-to-ground distance may be greater than about 2, in some embodiments, greater than about 5, in some embodiments, greater than about 10, in some embodiments, greater than about 15, in some embodiments, greater than about 20, and in some embodiments, greater than about 40.

[0030] At least one of the active electrode layers may comprise a third electrode having a base portion electrically connected to the first external terminal. A third electrode arm may extend from the base portion in the longitudinal direction. A central portion of the first electrode may extend from the base portion in the longitudinal direction. The central portion of the first electrode may have a first width at a first location and a second width greater than the first width at a second location. The second location may be offset from the first location in the longitudinal direction.

[0031] At least one of the active electrode layers may comprise a second electrode having a base portion electrically connected to the second external terminal. A central end gap distance may be formed in the longitudinal direction between the central portion of the first electrode and the base portion of the second electrode.

[0032] In some embodiments, at least one of the active electrode layers may comprise a second electrode comprising a base portion electrically connected to the second external terminal, wherein a central edge gap distance is formed in the lateral direction between the central portion of the first electrode and the second electrode arm. I. Exemplary embodiments

[0033] If we look at the Fig. 1A-1E, an embodiment of a multilayer ceramic capacitor 100 is disclosed. Fig.1E is a simplified side view of the multilayer capacitor 100 mounted on a mounting surface 101, such as a circuit board or substrate. The multilayer capacitor 100 may include a plurality of electrode regions 10 stacked in the Z direction 136. The plurality of electrode regions 10 may include a dielectric region 12, an active electrode region 14, and a shield electrode region 16. The active electrode region 14 may be located between the dielectric region 12 and the shield electrode region 16 in the Z direction 136. The dielectric region 12 may extend from the active electrode region 14 to a top surface 18 of the broadband multilayer ceramic capacitor 100. The capacitor 100 may include a bottom surface 20 opposite the top surface 18 in the Z direction 136.

[0034] The electrode regions 10 may include a plurality of dielectric layers. Some dielectric layers may include electrode layers formed thereon. In general, the thickness of the dielectric layers and the electrode layers is not limited and may be any desired thickness depending on the performance characteristics of the capacitor. For example, the thickness of the electrode layers may be, but is not limited to, about 500 nm or more, such as about 1 μm or more, such as about 2 μm or more, such as about 3 μm or more, such as about 4 μm or more, to about 10 μm or less, such as about 5 μm or less, such as about 4 μm or less, such as about 3 μm or less, such as about 2 μm or less. For example, the electrode layers may have a thickness of about 1 μm to about 2 μm. Furthermore, in one embodiment, the thickness of the dielectric layer may be defined according to the above-mentioned thickness of the electrode layers.Furthermore, it should be understood that these thicknesses of the dielectric layers may also apply to the layers between the active electrode layers and / or the shielding electrode layers, if present and as defined herein.

[0035] In general, the present invention provides a multilayer capacitor with an electrode having a unique configuration that provides various benefits and advantages. In this regard, it should be understood that the materials used in constructing the capacitor are not limited and may be any materials generally used in the art and may be formed using any method generally used in the art.

[0036] In general, the dielectric layers are typically formed from a material having a relatively high dielectric constant (K), such as about 10 to about 40,000, in some embodiments about 50 to about 30,000, and in some embodiments about 100 to about 20,000.

[0037] In this regard, the dielectric material may be a ceramic. The ceramic may be provided in a variety of forms, such as a wafer (e.g., pre-fired) or a dielectric material that is co-fired within the device itself.

[0038] Specific examples of the type of high dielectric constant material include NPO (COG) (up to about 100), X7R (about 3000 to about 7000), X7S, Z5U, and / or Y5V. It should be understood that the above materials are described using their industry-accepted definitions, some of which are standard classifications established by the Electronic Industries Alliance (EIA), and as such, they should be recognized by those skilled in the art. For example, such a material may include a ceramic. Such materials may include a perovskite, such as barium titanate and related solid solutions (e.g., barium strontium titanate, barium calcium titanate, barium zirconate titanate, barium strontium zirconate titanate, barium calcium zirconate titanate, etc.), lead titanate and related solid solutions (e.g., lead zirconate titanate, lead lanthanum zirconate titanate), sodium bismuth titanate, etc.In a particular embodiment, for example, barium strontium titanate (“BSTO”) of the formula Ba. x Sr 1-x TiO3, where x = 0 to 1, in some embodiments about 0.15 to about 0.65, and in some embodiments about 0.25 to about 0.6. Other suitable perovskites may include, for example, Ba x Ca 1-x TiO3, where x is about 0.2 to about 0.8 and in some embodiments about 0.4 to about 0.6, Pb x Zr 1-x TiO3 (“PZT”), where x ranges from about 0.05 to about 0.4, lead lanthanum zirconium titanate (“PLZT”), lead titanate (PbTiO3), barium calcium zirconium titanate (BaCaZrTiO3), sodium nitrate (NaNO3), KNbO3, LiNbO3, LiTaO3, PbNb2O6, PbTa2O6, KSr(NbO3), and NaBa2(NbO3)5KHb2PO4. Still other complex perovskites may include A[B1 1 / 3 B2 2 / 3 ]O3 materials, where A = Ba x Sr 1-x is (x can be a value from 0 to 1); B1 = Mg y Zn 1-yis (y can be a value from 0 to 1); B2 = Ta z Nb 1-z (z may be a value from 0 to 1). In a particular embodiment, the dielectric layers may comprise a titanate.

[0039] The electrode layers may be formed from a variety of materials, as is known in the art. The electrode layers may be composed of a metal, such as a conductive metal. The materials may include noble metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and various combinations thereof. Sputtered titanium / tungsten (Ti / W) alloys, as well as respective sputtered layers of chromium, nickel, and gold, may also be suitable. The electrodes may also be formed from a low-resistivity material, such as silver, copper, gold, aluminum, palladium, etc. In a particular embodiment, the electrode layers may comprise nickel or an alloy thereof.

[0040] If we turn to Fig.1E, in some embodiments, the dielectric region 12 may be free of electrode layers extending from a first end 119 or a second end 120 of the capacitor 100 for more than about 25% of the length 21 of the capacitor 100 (shown schematically by box 21), in some embodiments, free of electrode layers extending for more than about 20% of the length of the capacitor, in some embodiments, greater than about 15% of the length of the capacitor, in some embodiments, greater than about 10% of the length of the capacitor, in some embodiments, greater than about 5% of the length of the capacitor, and in some embodiments, greater than about 2% of the length of the capacitor. For example, in such embodiments, the dielectric region 12 may include one or more floating electrodes and / or dummy electrode tabs.In other embodiments, however, the dielectric region 12 may be free of all electrode layers. In some embodiments, the multilayer broadband ceramic capacitor 100 may be free of shield electrodes 22, 24 above a plurality of active electrode layers 102, 104 in the Z direction 136. In some embodiments, the multilayer broadband ceramic capacitor 100 may be free of shield electrodes 22, 24 above a bottommost electrode layer 19 of the plurality of active electrode layers 102, 104 in the Z direction 136.

[0041] The plurality of active electrode layers 102, 104 may be arranged within the active electrode region 14. Each active electrode layer 102, 104 may comprise one or more active electrodes, as described below, for example, with respect to the Fig.1A to 1C. For example, in some embodiments, each active electrode layer 102, 104 may include a third electrode 106 and a second electrode 108.

[0042] The multilayer capacitor 100 may include a first external terminal 118 connected to the first electrode 106 of a third electrode layer 102 and a second (counter) electrode 108 of the second electrode layer 104. The multilayer capacitor 100 may include a second external terminal 120 connected to the first electrode 106 of the second electrode layer 104 and the second (counter) electrode 108 of the first electrode layer 102.

[0043] The shielding electrode region 16 may comprise one or more shielding electrodes, as described below, for example, with respect to Fig.1D. For example, the shield electrode region 16 may include a first shield electrode 22 disposed within a monolithic body of the capacitor 100. The first shield electrode 22 may be parallel to the longitudinal direction 132. The first shield electrode 22 may be connected to the first external terminal 118. The shield electrode region 16 may include a second shield electrode 24, which may be connected to the second external terminal 120. The second shield electrode 24 may be approximately aligned with the first shield electrode 22 in the Z direction 136.

[0044] In general, with respect to the embodiments discussed herein, the external terminals may be made of a variety of different metals, as is known in the art. The external terminals may be made of a metal, such as a conductive metal. The materials may include precious metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and so on, as well as various combinations thereof. In a particular embodiment, the external terminals may comprise copper or an alloy thereof.

[0045] The external leads can be formed using any method commonly known in the art. The external leads can be formed using techniques such as sputtering, painting, printing, electroless plating or copper refining (FCT), electroplating, plasma deposition, propellant spray / airbrushing, and so on.

[0046] In one embodiment, the external terminals may be formed so that the external terminals are relatively thick. For example, such terminals may be formed by applying a thick film strip of a metal to exposed portions of electrode layers (e.g., by immersing the capacitor in a liquid external terminal material). Such a metal may be present in a glass matrix and may comprise silver or copper. As an example, such a strip may be printed and fired onto the capacitor. Thereafter, additional deposition layers of metal (e.g., nickel, tin, solder, etc.) may be created over the terminal strip so that the capacitor can be soldered to a substrate. Such application of thick film strips may be achieved by any method well known in the art (e.g.,by a connecting machine and a pressure wheel to transfer a metal-loaded paste over the exposed electrode layers).

[0047] The thickly deposited outer terminals may have an average thickness of about 150 µm or less, such as about 125 µm or less, such as about 100 µm or less, such as about 80 µm or less. The thickly deposited outer terminals may have an average thickness of about 25 µm or more, such as about 35 µm or more, such as about 50 µm or more, such as about 75 µm or more. For example, the thickly deposited outer terminals may have an average thickness of from about 25 µm to about 150 µm, such as from about 35 µm to about 125 µm, such as from about 50 µm to about 100 µm.

[0048] In another embodiment, the external terminals may be formed such that the external terminal is a thin-film deposition of a metal. Such a thin-film deposition may be formed by depositing a conductive material, such as a conductive metal, on an exposed portion of an electrode layer. For example, a leading edge of an electrode layer may be exposed to allow the formation of a coated terminal.

[0049] The thinly deposited outer terminals may have an average thickness of about 50 µm or less, such as about 40 µm or less, such as about 30 µm or less, such as about 25 µm or less. The thinly deposited outer terminals may have an average thickness of about 5 µm or more, such as about 10 µm or more, such as about 15 µm or more. For example, the outer terminals may have an average thickness of from about 5 µm to about 50 µm, such as from about 10 µm to about 40 µm, such as from about 15 µm to about 30 µm, such as from about 15 µm to about 25 µm.

[0050] In general, the outer terminal may comprise a deposited terminal. For example, the outer terminal may comprise an electrodeposited terminal, an electroless deposited terminal, or a combination thereof. For example, an electrodeposited terminal may be formed by electrolytic deposition. An electroless deposited terminal may be formed by electroless deposition.

[0051] If multiple layers form the outer terminal, the outer terminal can comprise an electrodeposited terminal and an electroless deposited terminal. For example, electroless deposition can be used first to deposit an initial layer of material. Then, the deposition technique can be switched to an electrochemical deposition system, which allows for faster material growth.

[0052] When the deposited terminals are formed using either deposition method, a leading edge of the terminal tabs of the electrode layers, which is exposed from the main body of the capacitor, is exposed to a deposition solution. During this exposure, the capacitor may, in one embodiment, be immersed in the deposition solution.

[0053] The plating solution contains a conductive material, such as a conductive metal, and is used to form the deposited terminal. Such a conductive material may be one of the aforementioned materials or one generally known in the art. For example, the plating solution may be a nickel sulfamate bath solution or other nickel solution, such that the deposited layer and the outer terminal comprise nickel. Alternatively, the plating solution may be a copper acid bath or other suitable copper solution, such that the deposited layer and the outer terminal comprise copper.

[0054] Furthermore, it should be noted that the deposition solution may also include other additives, as is well known in the art. For example, the additives may also include other organic additives and media that may assist the deposition process. Furthermore, additives may be used to maintain the deposition solution at a desired pH. In one embodiment, resistance-reducing additives may be used in the solutions to promote complete coverage of the deposition and adhesion of the deposition materials to the capacitor and the exposed leading edges of the terminal tabs.

[0055] The capacitor may be treated with, submerged in, or immersed in the plating solution for a predetermined period of time. This exposure time is not necessarily limited, but may be sufficiently long to allow sufficient plating material to deposit to form the coated terminal. In this regard, the time should be sufficient to allow the formation of a permanent connection between the desired exposed, adjacent leading edges of terminal tabs of a given polarity of the respective electrode layers within a set of alternating dielectric layers and electrode layers.

[0056] In general, the difference between electrodeposition and electroless plating is that electrodeposition involves an electrical bias, such as using an external power source. The electrodeposition solution can typically be exposed to a high current density range, for example, 10 to 15 amperes / foot. 2 (rated at 9.4 volts). A connection can be created with a negative connection to the capacitor, which requires the formation of the deposited terminals, and a positive connection to a solid material (e.g., Cu in Cu plating solution) in the same plating solution. This means that the capacitor is biased to a polarity opposite that of the plating solution. Using this process, the conductive material of the plating solution is attracted to the metal of the exposed leading edge of the terminal tabs of the electrode layers.

[0057] Before immersing or treating the capacitor in a plating solution, various pretreatment steps can be used. Such steps can be performed for various purposes, including catalyzing, accelerating, and / or improving the adhesion of the deposition materials to the leading edges of the terminal tabs.

[0058] Additionally, an initial cleaning step may be employed prior to deposition or any other pretreatment steps. Such a step may be employed to remove any oxide buildup that develops on the exposed terminal tabs of the electrode layers. This cleaning step may be particularly useful in assisting in the removal of nickel oxide buildup when the internal electrodes or other conductive elements are made of nickel. Component cleaning may be accomplished by full immersion in a pre-cleaning bath, such as one containing an acid cleaner. In one embodiment, exposure may occur for a predetermined time, such as on the order of about 10 minutes. Alternatively, cleaning may be accomplished by chemical polishing or harperization steps.

[0059] Additionally, a step may be performed to activate the exposed metallic leading edges of the terminal tabs of the electrode layers to facilitate the deposition of the conductive materials. Activation may be achieved by immersion in palladium salts, photopatterned organometallic palladium precursors (via mask or laser), screen-printed or inkjet-deposited palladium compounds, or electrophoretic palladium deposition. It should be noted that palladium-based activation is currently disclosed only as one example of activation solutions, which often work well with activation for exposed tab parts made of nickel or an alloy thereof. However, it should be understood that other activation solutions may also be used.

[0060] Furthermore, instead of or in addition to the above-mentioned activation step, the activating dopant can be introduced into the conductive material when forming the electrode layers of the capacitor. For example, if the electrode layer comprises nickel and the activating dopant comprises palladium, the palladium dopant can be introduced into the nickel ink or composition forming the electrode layers. This can eliminate the palladium activation step. It should also be noted that some of the above activation methods, such as organometallic precursors, are also suitable for co-depositing glass formers for enhanced adhesion to the generally ceramic body of the capacitor.When activation steps are undertaken as described above, traces of the activator material often remain on the exposed conductive parts before and after terminal deposition.

[0061] Additionally, post-deposition treatment steps can also be used. Such steps can be performed for a variety of purposes, including strengthening and / or improving the adhesion of the materials. For example, a heating (or annealing) step can be used after the deposition step. This heating can be achieved by firing, laser exposure, UV irradiation, microwave irradiation, arc welding, etc.

[0062] As previously stated, the outer terminal may comprise at least one deposition layer. In one embodiment, the outer terminal may comprise only one deposition layer. However, it should be understood that the outer terminals may comprise a plurality of deposition layers. For example, the outer terminals may comprise a first deposition layer and a second deposition layer. Furthermore, the outer terminals may also comprise a third deposition layer. The materials of these deposition layers may be any of those mentioned above and those generally known in the art.

[0063] For example, one deposition layer, such as a first deposition layer, may comprise copper or an alloy thereof. Another deposition layer, such as a second deposition layer, may comprise nickel or an alloy thereof. Another deposition layer, such as a third deposition layer, may comprise tin, lead, gold, or a combination, such as an alloy. Alternatively, an initial deposition layer may comprise nickel, followed by deposition layers of tin or gold. In another embodiment, an initial deposition layer of copper may be formed, followed by a nickel layer.

[0064] In one embodiment, the initial or first deposition layer may consist of a conductive metal (e.g., copper). This area may then be covered with a second layer containing a polymeric resistive material for sealing. The area may then be polished to selectively remove the polymeric resistive material and then re-metallized with a third layer containing a conductive metallic material (e.g., copper).

[0065] The above-mentioned second layer above the initial deposition layer may correspond to a solder barrier layer, for example, a nickel solder barrier layer. In some embodiments, the above-mentioned layer may be formed by electroplating an additional layer of metal (e.g., nickel) over an initial electrolessly deposited or electroplated layer (e.g., deposited copper). Other exemplary materials for the above-mentioned solder barrier layer are nickel-phosphorus, gold, and silver. A third layer on the above-mentioned solder barrier layer may, in some embodiments, correspond to a conductive layer, such as deposited Ni, Ni / Cr, Ag, Pd, Sn, Pb / Sn, or other suitable deposited solder metal.

[0066] Additionally, a deposition layer may be formed, followed by an electroplating step to obtain a resistive or higher-resistivity metal alloy, such as an electroless Ni-P alloy over such a deposit. However, it should be understood that any metal coating may be used, as will be understood by those skilled in the art from the present full disclosure.

[0067] It should be noted that each of the above steps can be performed as a bulk process, such as drum deposition, fluidized bed deposition, and / or flow-through deposition finishing processes, all of which are well known in the art. Such bulk processes allow multiple components to be processed at once, resulting in an efficient and rapid finishing process. This is a particular advantage over conventional finishing processes, such as thick-film terminal printing, which requires individual processing of components.

[0068] As described herein, the formation of the outer terminals is generally determined by the position of the exposed leading edges of the terminal tabs of the electrode layers. Such phenomena may be referred to as "self-determining" because the formation of the outer metallized terminals is determined by the configuration of the exposed conductive metal of the electrode layers at the selected peripheral locations on the capacitor. In some embodiments, the capacitor may include dummy tabs to provide exposed conductive metal along portions of the monolithic body of the capacitor that do not include other electrodes (e.g., active or shield electrodes).

[0069] It should be understood that additional techniques for forming capacitor terminals may also fall within the scope of the present technique. Exemplary alternatives include, but are not limited to, forming terminals by deposition, magnetism, masking, electrophoresis / electrostatics, sputtering, vacuum deposition, printing, or other techniques for forming conductive thick or thin films.

[0070] Fig. 1A shows a top view of an embodiment of an active electrode configuration for one or more electrodes in the active electrode region 14 according to aspects of the present disclosure. In particular, the active electrode region 14 may comprise first electrode layers 102 and second electrode layers 104 in an alternating arrangement, as described, for example, below with respect to Fig. 1B. If we focus on Fig.1A, each electrode layer 102, 104 may include a third electrode 106 and a second electrode 108. The first electrode 106 may have a base portion 114 extending along a longitudinal edge of the first electrode 106 in the lateral direction 134. The first electrode 106 may have a pair of electrode arms 110 extending from a base portion 114 in the longitudinal direction 132. The second electrode 108 may have a base portion 114 extending along a longitudinal edge of the second electrode layer 108 in the lateral direction 134. The second electrode 108 may have a pair of electrode arms 110 extending from the base portion 114 in the longitudinal direction 132.

[0071] The electrode arm(s) 110 of the first electrode 106 may be substantially longitudinally aligned with respect to the electrode arm(s) 110 of the second electrode 108. An arm gap(s) 226 may be defined in the longitudinal direction 132 between aligned electrode arms 110 of the first and second electrodes 106, 108.

[0072] A central edge gap distance 23 may be defined in the lateral direction 134 between the central portion 122 of the first electrode and the second electrode arm 110. A central end gap distance may be defined in the longitudinal direction 132 between the central portion 122 of the first electrode 106 and the base portion 114 of the second electrode 108. In some embodiments, the central edge gap distance 23 may be approximately equal to the central end gap distance.

[0073] The central portion 112 of the first electrode 106 may have a first width 27 at a first location and a second width 29 at a second location that is greater than the first width 27. The first location of the first width 27 may be offset in the longitudinal direction 132 from the second location of the second width. Such a configuration may allow for adjusting an overlap area between central portions 112 of adjacent electrodes in the Z direction 136 without changing the central edge gap distance 23.

[0074] In Fig. 1B, a plurality of first electrode layers 102 and a plurality of second electrode layers 104 may be present in an alternating mirrored configuration. As shown, the center portions 112 of the respective electrode layers at least partially overlap. Fig.Figure 1B shows a total of four electrode layers; however, it should be understood that any number of electrode layers can be used to achieve the desired capacitance for the desired application.

[0075] According to Fig. 1C, multiple capacitive regions may be formed between the first electrode 106 and the second electrode 108. For example, in some embodiments, a central capacitive region 122 may be formed between the central portion 112 of the first electrode 106 and the base portion 114 and / or the arms 128 of the second electrode 108. In some embodiments, an arm gap capacitive region 124 may be formed within the arm gap between the electrode arms 110 of the first electrode 106 and the second electrode 108.

[0076] Fig. 1D shows a shielding electrode layer 26 disposed within the shielding electrode region 16 (in Fig.1E) may be included within the monolithic body of the capacitor 100. According to the above indication, the first shielding electrode 22 may be parallel to the longitudinal direction 132 (e.g., parallel to the direction shown in Fig. 1E). The first shielding electrode 22 may have a first longitudinal edge 28 aligned in the lateral direction 134 and extending from the first outer terminal 118 (in Fig. 1E) and first end 119. The first shielding electrode 22 may have a second longitudinal edge 30 aligned in the lateral direction 134 and extending from the first outer terminal (in Fig. 1E) and facing away from the first end 119. The second longitudinal edge 30 can be offset in the longitudinal direction 132 by a shield electrode offset distance 32 from the first longitudinal edge 28.

[0077] The second shielding electrode 24 can be connected to the second external terminal 120 (in Fig. 1E) and the second end 121. The second shielding electrode 24 can be arranged in the Z-direction 136 (in Fig. 1E) may be approximately aligned with the first shielding electrode 22. The second shielding electrode 24 may have a similar configuration to the first shielding electrode 22. For example, the second shielding electrode 24 may have a first longitudinal edge 28 aligned in the lateral direction 134 and separated from the second outer terminal 120 (in Fig. 1E) and the second end 121. The second shielding electrode 24 may have a second longitudinal edge 30 oriented in the lateral direction 134 and extending from the second outer terminal 120 (in Fig.1E) and second end 121. The second longitudinal edge 30 of the second shielding electrode 24 can be offset in the longitudinal direction 132 by the shielding electrode offset distance 32 relative to the first longitudinal edge 28 of the second shielding electrode 24.

[0078] A first capacitive shielding region 34 may be formed between the first longitudinal edges 28 of the first and second shielding electrodes 119, 121. A second capacitive shielding region 36 may be formed between the second longitudinal edges 30 of the first and second shielding electrodes 119, 121. In some embodiments, the width 38 of the first longitudinal edge 28 in the lateral direction 134 may be smaller than the width 40 of the first shielding electrode 22 in the lateral direction 134.

[0079] A first shielding gap distance 42 can be created in the longitudinal direction 132 between the first longitudinal edge 28 of the first shielding electrode 22 and the first longitudinal edge 28 of the second shielding electrode 24. A second shielding gap distance 44 can be created in the longitudinal direction 132 between the second lateral edge 30 of the first shielding electrode 22 and the second lateral edge 30 of the second shielding electrode 22.

[0080] In some embodiments, a third shield gap distance 46 may be created between a third longitudinal edge 48 of the first shield electrode 22 and a third longitudinal edge 48 of the second shield electrode 24. A third capacitive shielding region 51 may be created between the third longitudinal edges 48 of the first and second shield electrodes 119, 121. In some embodiments, the third shield gap distance 46 may be approximately equal to the second shield gap distance 44, such that the third capacitive shielding region 51 may have substantially the same size and shape as the second capacitive shielding region 36. For example, in some embodiments, the first shield electrode 22 and / or second shield electrode 24 may be symmetrical in the lateral direction 134 about a longitudinal centerline 50 extending in the longitudinal direction 132.

[0081] However, in other embodiments, the third shield gap distance 46 may be larger or smaller than the second shield gap distance 44 such that the third capacitive region 51 has a different size and / or shape than the second capacitive region 36 and generates a different capacitance than the second capacitive region.

[0082] It should be appreciated that in some embodiments, one or more of the shield electrodes 22, 24 may be rectangular. In other words, the shield electrode offset distance 32 may be zero or approximately zero, such that the first longitudinal edge 28 and the second longitudinal edge 30 are aligned or approximately aligned.

[0083] The Fig. 2A and Fig.2B show another embodiment of the first and second electrode layers 102, 104. In particular, each electrode layer 102, 104 may include a third electrode 106 and a second electrode 108. The first electrode 106 may have a base portion 114. A pair of electrode arms 110 and at least a central portion 112 may extend from the base portion 114. The second electrode 108 may have a base portion 114 extending along a longitudinal edge of the second electrode layer 108. The second electrode 106 may have a pair of electrode arms 110 extending from the base portion 114. The electrode regions 12, 14, 16 may be substantially non-overlapping.

[0084] If we focus on Fig. 1E, in some embodiments, the multilayer broadband ceramic capacitor 100 may have a capacitor thickness 56 in the Z direction 136 between the top surface 18 and the bottom surface 20.

[0085] The dielectric region 12 may have a thickness of the dielectric region 58 in the Z direction 136. In some embodiments, the ratio of the capacitor thickness 56 to the thickness of the dielectric region 58 may be in a range from about 1.1 to about 20, in some embodiments from about 1.5 to about 10, in some embodiments from about 1.7 to about 5.

[0086] The active electrode region 14 may have a thickness of the active electrode region 59 in the Z-direction 136. The active electrode region 14 may be free of shielding electrodes 22, 24 and / or may include only overlapping electrodes. The thickness of the active electrode region 59 may be defined between the lowest active electrode layer 19 and a highest electrode layer 65. The ratio of the capacitor thickness 56 to the thickness of the active electrode region 59 may be in a range from about 1.1 to about 20.

[0087] The shield electrode region 16 may have a thickness of the shield electrode region 61 in the Z direction 136. The thickness of the shield electrode region 61 may be defined between the bottom surface 20 of the capacitor 100 and a lowest electrode layer 19 of the plurality of active electrodes. The ratio of the capacitor thickness 56 to the thickness of the shield electrode region 61 may be in a range from about 1.1 to about 20, in some embodiments from about 1.5 to about 10, in some embodiments from about 1.7 to about 5.

[0088] In some embodiments, the shield-to-bottom distance 63 may be defined as the distance between the shield electrodes 22, 24 and the bottom surface 20 of the capacitor 100. If multiple shield electrode layers are present, the shield-to-bottom distance 63 may be defined as the distance between the lowest of the shield electrode layers and the bottom surface 20. The ratio of the capacitor thickness 56 to the shield-to-bottom distance 63 may range from about 1.1 to about 20, in some embodiments from about 1.5 to about 10, in some embodiments from about 1.7 to about 5.

[0089] In some embodiments, the shield electrodes 22, 24 may be spaced from the active electrodes 106, 108 by a first shield-to-active distance 67. The ratio of the first shield-to-active distance 67 to the distance between the shield and the ground surface 63 may range from about 1 to about 20, in some embodiments from about 2 to about 10, and in some embodiments from about 3 to about 5.

[0090] In addition, Fig.2A Electrode arms 110 comprising a main portion 128 and a step portion 130. In particular, an electrode arm 110 of the first electrode 106 may comprise a first longitudinal edge 60 extending in the lateral direction 134 and may define an edge of the step portion 130. A second longitudinal edge 62 may extend in the lateral direction 134 and may define an edge of the main portion 128 of the arm 110. The first longitudinal edge 60 may be offset from the second longitudinal edge 62 in the longitudinal direction 132 by an arm offset distance 64. One or both electrode arms 110 of the first electrode 106 and / or the second electrode 108 may each comprise a main portion 128 and a step portion 130. For example, both arms 110 of the two electrodes 106, 108 may each comprise main parts 128 and step parts 130, as shown, for example, in Fig.2A. Main arm gaps 240 may be formed between the step portions 130 of the aligned arms 110. Step arm gaps 242 may be formed between the main portions 128 of the aligned arms 110.

[0091] If we focus on the Fig. 2B, between the first electrode 106 and the second electrode 108 of the electrode configuration of Fig. 2A, multiple capacitive regions may be formed. For example, in some embodiments, a central capacitive region 122 may be formed between the central portion 112 of the first electrode 106 and the base portion 114 and / or the arms 110 of the second electrode 108. In some embodiments, a main arm gap 125 capacitive region may be formed within the main arm gap 240, and a step gap 126 capacitive region may be formed within the step arm gap 242.

[0092] If we focus on Fig.3A, in some embodiments, the dielectric region 12 may include first dummy tab electrodes 52 connected to the first terminal 118 and / or second dummy tab electrodes 54 connected to the second terminal 120. In some embodiments, the shield electrode region 16 may include first dummy tab electrodes 55 connected to the first terminal 118 and / or second dummy tab electrodes 54 connected to the second terminal 120.

[0093] In particular, the dummy tab electrodes 52, 54, 55, 57 can be used to form (e.g., deposit) the terminals 118, 120, for example, using a copper refining process. The dummy tab electrodes 52, 54, 55, 57 can extend over less than 25% of the capacitor length 21 relative to the first end 119 or the second end 121.

[0094] Furthermore, in some embodiments, the shield electrode region 16 may include multiple shield electrode layers. For example, a first and a second shield electrode 22 may be disposed within a monolithic body of the capacitor 100 and connected to the first external terminal 118 and the second external terminal 120, respectively, as described above with reference to the figure. The second shield electrode 24 may be approximately aligned with the first shield electrode 22 in the Z-direction 136. An additional pair of shield electrodes 150 may be located within the shield electrode layer 166 between the first and second electrodes 22, 24 (which may be defined as the lowest shield electrodes) and the lowest active electrode layer 19.In such embodiments, the first shield-to-active distance 67 may be defined between the lowest active electrode 19 and the shield electrode(s) closest to the lowest active electrode 19 in the Z direction 136. In this example, the first shield-to-active distance 67 is defined between the lowest active electrode 19 and the additional pair of shield electrodes 150.

[0095] The electrode configurations described herein may allow for a primary capacitive element between the central portions 112 of the adjacent electrode layers 102, 104 (i.e., parallel plate capacitance) as well as additional secondary capacitive elements, such as described above with respect to the Fig. 1C, Fig. 1D and Fig. 2B. These configurations are described in the Fig. 4A and Fig. 4B is shown schematically.

[0096] In some embodiments, the capacitor 100 may include one or more floating electrodes 111. The floating electrode 111 may be located in the dielectric region 12. However, in other embodiments, the floating electrode 111 may be located in the active electrode region 14 and / or the shield electrode region 16. Generally, such floating electrodes 111 are not directly connected to an external terminal 118, 120.

[0097] However, in some embodiments, the floating electrode may be part of a floating electrode layer that includes at least one electrode electrically connected to an external terminal; however, such a floating electrode layer includes at least one floating electrode that does not have direct contact with such an electrode or an external terminal.

[0098] The floating electrode may be positioned and configured using any method known in the art. For example, the floating electrode may be provided to overlap at least a portion, such as a central portion, of a first active electrode and / or a second active electrode of an active electrode layer. In this regard, the floating electrode layer may be layered and arranged alternately with the first electrode layers and the second internal electrode layers; in this regard, such layers may be separated from each other by the dielectric layers.

[0099] Furthermore, such floating electrodes may have any shape, as is well known in the art. For example, in one embodiment, the floating electrode layers may include at least one floating electrode with a dagger-like configuration. For example, such a configuration may be similar to the configuration and shape of the first electrode described herein. However, it should be understood that such a first electrode may or may not include an electrode arm with a step portion.

[0100] Furthermore, in one embodiment, the floating electrode layer may include at least one floating electrode, wherein the end of the floating electrode is adjacent to, but does not contact, at least one external terminal. In this regard, such a gap may be referred to as a floating electrode gap in a longitudinal direction. Such a floating electrode gap may be greater than 0%, such as about 3% or more, such as about 5% or more, to about 50% or less, such as about 40% or less, such as about 30% or less, such as about 20% or less, such as about 10% or less, of the length of the capacitor in the longitudinal direction.

[0101] Fig.3B shows another embodiment of a capacitor 160 according to aspects of the present disclosure. The capacitor 160 may include a plurality of electrode regions 162. The plurality of electrode regions 162 may include an active electrode region 14, a first shield electrode region 164, and a second shield electrode region 166. The active electrode region 14 may be located between the first shield electrode region 164 and the second electrode region 166.

[0102] In some embodiments, the capacitor 160, or a portion thereof, may be symmetrical about a longitudinal centerline 167 extending in the longitudinal direction. For example, the shield electrodes 22, 24 of the lower shield electrode region 164 may be symmetrical about the longitudinal centerline 167 with respect to the shield electrodes 22, 24 of the upper electrode region 166. In other words, the distance between the shield and bottom surface 63 may be approximately equal to the distance from the shield to the upper surface 168, which may be defined between the shield electrodes 22, 24 of the upper shield electrode region 166 and the upper surface 18 of the capacitor 160.For example, in some embodiments, the ratio of the distance between shield and bottom surface 63 and the distance from shield to top surface 168 may be in a range from about 0.8 to about 1.2, in some embodiments from about 0.9 to about 1.1, in some embodiments from about 0.95 to about 1.05, and in some embodiments from about 0.98 to about 1.02.

[0103] The shield electrodes 22, 24 of the upper shield electrode region 166 may be spaced from the active electrodes 106, 108 by a second shield-to-active distance 169. The ratio of the second shield-to-active distance 169 to the shield-to-upper surface distance 168 may range from about 1 to about 20, in some embodiments from about 2 to about 10, and in some embodiments from about 3 to about 5. Additionally, the ratio of the first shield-to-active distance 67 to the second shield-to-active distance 169 may range from about 0.8 to about 1.2, in some embodiments from about 0.9 to about 1.1, in some embodiments from about 0.95 to about 1.05, and in some embodiments from about 0.98 to about 1.02.

[0104] The capacitor 160 may have comparable insertion loss characteristics in the first orientation (as shown) through the third orientation, in which the capacitor 160 is rotated 180 degrees around the longitudinal direction 132 (which appears substantially similar, as shown). The second orientation of the capacitor 160 may be defined relative to the first orientation by a 90-degree rotation around the longitudinal direction 132, such that the shielding electrodes 22, 24 are perpendicular to the mounting surface 101.

[0105] In the first orientation, the capacitor 160 may have a first insertion loss value at a test frequency greater than about 2 GHz. In the second orientation relative to the mounting surface, the capacitor 160 may have a second insertion loss value at approximately the test frequency that differs from the first insertion loss value by at least about 0.3 dB.

[0106] Fig.Figure 4 shows schematically three capacitive elements of the electrode configuration of Fig. 1C: a primary capacitive element 112' between adjacent electrode layers, a central capacitive element 122', and an arm gap capacitive element 124'. The capacitive elements 112', 122', and 124' correspond to the central region 112, the central capacitive region 122, and the arm gap capacitive region 124, respectively, of Fig. 1C. In addition, external connections are Fig. 4 shown as 118 and 128.

[0107] Fig. Figure 5 shows schematically four capacitive elements of the electrode configuration of Fig. 2B, in which the capacitive elements 112', 122' and 125' and 126' correspond to the central region 112, the capacitive region 122, the capacitive region of the main arm gap 125 and the capacitive region of the step gap 126, respectively, of Fig.2B. It should be noted that the dimensions of the various columns can be specifically designed to achieve the desired respective capacity values ​​for the Fig. 4 and Fig. 5. In particular, the configuration of the capacitor and various parameters, such as the number of electrode layers, the area of ​​the overlapping central portions of electrode pairs, the distance separating electrodes, the dielectric constant of the dielectric material, etc., can be selected to achieve the desired capacitance values. Nevertheless, the capacitor as disclosed herein may comprise an array of combined series and parallel capacitors to provide effective broadband performance.

[0108] In an exemplary embodiment of an ultra-wideband capacitor, primary capacitor 112' generally corresponds to a relatively large capacitance suitable for operation in a generally lower frequency range, such as on the order of between about several kilohertz (kHz) to about 200 megahertz (MHz), while secondary capacitors 122', 124', and 126' generally correspond to smaller value capacitors configured to operate in a higher frequency range, such as on the order of between about 200 megahertz (MHz) to many gigahertz (GHz).

[0109] Thus, the active electrodes may be configured to include a plurality of capacitive elements within a single set of stacked electrodes. For example, a primary capacitive element may be effective at relatively low frequencies, while the secondary capacitive elements (e.g., the central capacitive region 122 and / or capacitive region of the arm gap 124) may be effective at relatively medium and / or high frequencies. For example, the primary capacitance may be between 1 and 500 nF, such as between about 10 and 100 nF, while the secondary capacitance may be between 1 and 500 pF, such as between 10 and 100 pF.

[0110] Let us consider Fig.6, in some embodiments, a multilayer capacitor 300 may include a first external terminal 118 located along a first end 119 and a second external terminal 120 located along a second end 121 opposite the first end 119 in the longitudinal direction 132. The multilayer capacitor 300 may include a plurality of dielectric layers and a plurality of electrode layers, wherein the electrode layers are alternately layered in an opposing and spaced-apart relationship with a dielectric layer located between each adjacent electrode layer.

[0111] In addition, as already mentioned, the multilayer capacitor may include a shielding electrode. For example, as in Fig.As shown in Figure 6, the multilayer capacitor 300 may include a first shield region 210 and a second shield region 212, and each of the shield regions 210, 212 may include one or more shield electrode layers 214. The shield regions 210, 212 may be spaced from the active electrode region 216 by a dielectric region (e.g., one that does not include any electrode layers).

[0112] The shield electrode layers 214 may have a first shield electrode configuration in which each shield electrode 220 is substantially rectangular. In other embodiments, the shield electrode layers 214 may have a second shield electrode configuration in which the shield electrodes 222 include a step 224, for example, as described above with respect to the electrodes of Fig. 1D is explained.

[0113] In some embodiments, an active electrode region 218 may be located between the first and second shielding regions 210, 212. The active electrode region 216 may include a plurality of alternating active electrode layers 218, as described, for example, with reference to FIG. Fig. 2A-2D. Additionally, a pair of ceramic covers 227 may be located along the top and / or bottom surface of the capacitor 300.

[0114] Let us consider Fig.6, in some embodiments, the multilayer capacitor 300 may also include armature electrode regions 302, 304, 316, and / or 318. For example, the multilayer capacitor 300 may include a first armature electrode region 304 on the active electrode region 216. Further, a shield electrode region 210 including a shield electrode layer 214 may be located above, such as on, the first armature electrode region 304. Additionally, a second armature electrode region 302 may be located above, such as on top of, the shield electrode region 210. Similarly, the multilayer capacitor 300 may include a third armature electrode region 316 below, such as immediately below, the active electrode region 216. Further, a shield electrode region 210 including a shield electrode layer 214 may be located below, such as immediately below, the third armature electrode region 316.Additionally, a fourth armature electrode region 318 may be located below, such as immediately below, the shield electrode region 210. In this regard, the active electrode region 216 may be located, for example, between the first armature electrode region 304 and the third armature electrode region 316. The active electrode region 216 may be configured as described above with respect to FIG. Fig. 1A to 1C, the Fig. 2A to 2C, or as described below in 8A to 8D.

[0115] Let us consider the Fig.7A, the armature electrode regions 302, 304, 316 and / or 318 may comprise a plurality of armature electrode layers 310, each having a pair of armature electrodes 312. The armature electrodes 312 may comprise a pair of electrode arms 314. Each electrode arm 314 of the armature electrodes 312 may comprise a main portion 328 and a step portion 330, for example, in a similar manner as described above with respect to the electrodes of Fig. 1A and Fig. 2 is described.

[0116] Let us consider the Fig. 7B to 7D, the armature electrodes 312 can have different configurations. For example, consider the Fig. 7B, in some embodiments, the electrode arms 314 of the anchor electrodes 312 do not include a step. For example, such electrodes may be in a C-shaped configuration without a step. Consider the Fig.7C, in some embodiments, the electrode arms 314 of the armature electrodes 312 may include a step portion 320 that is offset inwardly relative to an outer lateral edge 322 of the armature electrode 312. Consider the Fig. 7D, in other embodiments, the stepped portion 320 may be offset from an inner lateral edge 324 of the arms 314 of the armature electrodes 312. Other configurations are also possible. For example, in some embodiments, the stepped portion 320 may be offset from both the outer lateral edge 322 and the inner lateral edge 324.

[0117] Let us consider the Fig. 8A-8C, in some embodiments, the active electrodes 106, 108 may have various other configurations. For example, consider the Fig.8A, in some embodiments, the first electrodes 106 and the second electrodes 108 may each comprise a single arm 110 instead of a pair of arms 110, 202 as described above with respect to Fig. 1A. In this regard, such electrodes may comprise an electrode including a central portion extending from a base portion and an electrode arm also extending from the base portion; whereas, the counter electrode may comprise a base portion and only a single electrode arm extending from the base portion of this second electrode.

[0118] Let us consider the Fig.8B, in some embodiments, the first electrodes 106 and the second electrodes 108 may each include central portions 112. For example, each electrode 106, 108 may include a central portion 112 extending away from a respective base portion in addition to at least one electrode arm 110, 202, such as two electrode arms 110, 202, extending away from the respective base portion.

[0119] Let us consider the Fig. 8C, in some embodiments, the electrode arms 110, 202 of the electrodes 106, 108 may include a stepped portion 130 that is offset outwardly from an inner lateral edge 324 of the main portion of an electrode arm from a lateral centerline 236 of at least one of the electrodes 106, 108 of the electrode layers. Finally, consider the Fig.8D, in some embodiments, the electrode arms 110 of the electrodes 106, 108 may include step portions 130 that are offset from both the outer lateral edge 322 and the inner lateral edge 324 of the electrode arms 110, 202. II. Insertion loss

[0120] Aspects of the present disclosure relate to a multilayer broadband capacitor having orientation-sensitive insertion loss characteristics. The multilayer broadband capacitor may have an insertion loss at a test frequency in a first orientation that varies by more than about 0.3 dB compared to an insertion loss at the test frequency in a second orientation. In the first orientation, the longitudinal direction 132 of the multilayer ceramic capacitor 100 may be parallel to the mounting surface 101 (as shown, for example, in Fig.1E). In the first orientation, the electrodes (e.g., active electrodes 106, 108 and shield electrodes 22, 24) may be substantially parallel to the mounting surface 101. Furthermore, the shield electrode region 14 (including the shield electrodes 22, 24) may be located between the active electrode region 14 (including the plurality of active electrodes 106, 108) and the mounting surface 101 in the first orientation, as shown, for example, in Fig. 1E is shown.

[0121] If we focus on Fig. 9, the multilayer ceramic capacitor 100 may be rotated in the second orientation with respect to the first orientation by 180 degrees about the longitudinal direction 136 (in Fig. 1E). Thus, in the second orientation, the dielectric region 16 may be located between the active electrode region 14 and the mounting surface 101 with respect to the Z direction 136.

[0122] The capacitor may have a first insertion loss value in the first orientation at a test frequency greater than about 2 GHz and a second insertion loss value in the second orientation at the test frequency. In some embodiments, the test frequency may be in a range from about 10 GHz to about 30 GHz or higher. The second insertion loss value may differ from the first insertion loss value by at least about 0.3 dB. III. Test procedure

[0123] A test setup can be used to test performance characteristics, such as insertion loss and return loss, of a capacitor according to aspects of the present disclosure. For example, the capacitor can be mounted on a test board. An input line and an output line can each be connected to the test board. The test board can include microstrip lines or test traces that electrically connect the input line and the output lines to respective external terminals of the capacitor. The test traces can be spaced apart by approximately 0.432 mm (0.017 inches) or approximately 0.610 mm (0.024 inches).

[0124] An input signal can be applied to the input line using a source signal generator (e.g., a 1806 Keithley 2400 Series Source Measurement Unit (SMU), for example, a Keithley 2410-C SMU), and the resulting capacitor output signal can be measured at the output line (e.g., using the source signal generator). This test procedure can be repeated for multiple capacitors that have the same construction and nominal dimensions. The insertion loss results can be measured in the first orientation and the second orientation. The difference between these insertion loss results can be calculated and averaged to determine the nominal insertion loss sensitivity values ​​for the group of capacitors.

[0125] This procedure can be repeated for the various capacitor configurations described here. Examples

[0126] Eight multilayer ceramic capacitors with the above for the Fig. The configurations described in Figures 1A to 1E were fabricated and tested for insertion loss response characteristics in the first orientation and the second orientation. The multilayer ceramic capacitors had the following dimensions, which corresponded to the annotated dimensions of the Fig. 1A to 1E. dimension Reference symbol length length 21 1000 µm (0.04 inches) Width - 500 µm (0.02 inches) First shielding gap distance 42 51 µm (0.002 inches) Second shielding gap distance 44 351 µm (0.138 inches) Shielding electrode offset distance 32 150 µm (0.006 inches) Capacitor thickness 56 510 µm (0.020 inches) Ground sign-to-ground distance 63 12.7 µm (0.0005 inch) Thickness of the dielectric region 58 71.1 µm (0.0028 inches)

[0127] Thus, the ratio of the length of the capacitor 21 to the shield electrode offset distance 32 was approximately 6.7. The ratio of the length of the capacitor 21 to the shield electrode offset distance 32 was approximately 6.7. The ratio of the second shield gap distance to the first shield gap distance was approximately 6.9. The ratio of the capacitor thickness to the distance between the bottom shield and the bottom surface was approximately 40.2.

[0128] The insertion loss response was measured for eight multilayer ceramic capacitors of the same construction and nominal dimensions (within manufacturing tolerances). The insertion loss values ​​were measured at 30 GHz and 40 GHz for each of the eight multilayer ceramic capacitors in the first and second orientations. The difference in the insertion loss values ​​for the first and second orientations at 30 GHz and 40 GHz was calculated for each capacitor. The resulting insertion loss delta values ​​at 30 GHz and 40 GHz were averaged to determine the following average insertion loss delta values ​​at 30 GHz and 40 GHz between the first and second orientations, respectively: Test frequency (GHz) Average difference in insertion loss (dB) Standard deviation of insertion loss 30 0,332 0,041 40 0,324 0,051

[0129] As shown in the table above, the average insertion loss for the fabricated multilayer ceramic capacitors is greater than 0.3 dB at both 30 GHz and 40 GHz, with a standard deviation of 0.041 and 0.05 at 30 GHz and 40 GHz, respectively. The standard deviation of the average insertion loss delta values ​​at 30 GHz and 40 GHz for the group of eight multilayer ceramic capacitors was also calculated, as shown in the table above.

[0130] Fig. Figure 10 shows an insertion loss characteristic of one of the multilayer ceramic capacitors that had insertion loss values ​​very close to the above average. The difference between the insertion loss in the first orientation and the insertion loss in the second orientation compared to the insertion loss characteristic of Fig. 10 is as follows: Test frequency (GHz) Insertion loss (dB) 30 0,330 40 0,325

[0131] In addition, the capacitor can exhibit excellent insertion loss characteristics in the first orientation. If we focus on Fig. 10, the insertion loss 302 in the first orientation is greater than about -0.8 dB at approximately 10 GHz, at approximately 20 GHz, at approximately 30 GHz, at approximately 40 GHz, at approximately 50 GHz, and at approximately 60 GHz. The insertion loss 302 in the first orientation is greater than about -0.5 dB at approximately 10 GHz, at approximately 20 GHz, at approximately 30 GHz, and at approximately 40 GHz.

[0132] These and other modifications and variations of the present invention may be made by those skilled in the art without departing from the spirit and scope of the present invention. Furthermore, it should be understood that aspects of the various embodiments may be substituted in whole or in part. Furthermore, those skilled in the art will appreciate that the above description is exemplary only and is not intended to further limit the invention as described in the appended claims.

Claims

[1] A multilayer broadband ceramic capacitor (100) having a first end (119) and a second end (121) spaced from the first end (119) in a longitudinal direction (132) perpendicular to a lateral direction (134), the lateral direction (134) and the longitudinal direction (132) each being perpendicular to a Z direction (136), the multilayer broadband ceramic capacitor (100) comprising: a monolithic body comprising a plurality of dielectric layers; a first outer terminal (118) located along the first end (119); a second outer terminal (120) located along the second end (121); comprising a plurality of active electrodes (106, 108) arranged within the monolithic body and parallel to the longitudinal direction (132); a first shielding electrode (22) arranged within the monolithic body and parallel to the longitudinal direction (132), wherein the first shielding electrode (22) is connected to the first external terminal (118), wherein the first shielding electrode (22) has a first longitudinal edge (28) oriented in the lateral direction (134) and facing away from the first external terminal (118), wherein the first shielding electrode (22) has a second longitudinal edge (30) oriented in the lateral direction (134) and facing away from the first external terminal (118), and wherein the second longitudinal edge (30) is offset in the longitudinal direction (132) by a shielding electrode offset distance (32) from the first longitudinal edge (28); and a second shield electrode (24) connected to the second external terminal (120), the second shield electrode (24) being approximately aligned with the first shield electrode (22) in the Z direction (136). [2] A multilayer broadband ceramic capacitor (100) according to claim 1, wherein the capacitor (100) has a capacitor length (21) in the longitudinal direction (132) between the first end (119) and the second end (121) of the capacitor (100), and wherein the ratio of the capacitor length (21) to the shield electrode offset distance (32) is greater than about 2. [3] A multilayer broadband ceramic capacitor (100) according to claim 1, wherein the second shield electrode (24) has a first longitudinal edge (28) oriented in the lateral direction (134) and facing away from the second external terminal (120), the second shield electrode (24) has a second longitudinal edge (30) oriented in the lateral direction (134) and facing away from the second external terminal (120), and the second longitudinal edge (30) is offset in the longitudinal direction (132) from the first longitudinal edge (28) by approximately a shield electrode offset distance (32). [4] Multilayer broadband ceramic capacitor (100) according to claim 3, wherein a first shielding gap distance (42) is formed in the longitudinal direction (132) between the first longitudinal edge (28) of the first shielding electrode (22) and the first longitudinal edge (28) of the second shielding electrode (24). [5] A multilayer broadband ceramic capacitor (100) according to claim 4, wherein the capacitor (100) has a capacitor length (21) in the longitudinal direction (132) between the first end (119) and the second end (121) of the capacitor (100), and wherein the ratio of the capacitor length (21) to the first shield gap distance (42) is greater than about 2. [6] A multilayer broadband ceramic capacitor (100) according to claim 3, wherein a second shielding gap distance (44) is formed in the longitudinal direction (132) between the second longitudinal edge (30) of the first shielding electrode (22) and the second longitudinal edge (30) of the second shielding electrode (24), and the ratio of the second shielding gap distance (44) to the first shielding gap distance (42) is in a range of about 0.5 to about 40. [7] A multilayer broadband ceramic capacitor (100) according to claim 3, wherein the first shielding electrode (22) has a third longitudinal edge (48) oriented in the lateral direction (134) and facing away from the first external terminal (118), and the second shielding electrode (24) has a third longitudinal edge (48) oriented in the lateral direction (134) and facing away from the second external terminal (120), and wherein a third shielding gap distance (46) is formed in the longitudinal direction (132) between the third longitudinal edge (48) of the first shielding electrode (22) and the third longitudinal edge (48) of the second shielding electrode (24). [8] A multilayer broadband ceramic capacitor (100) according to claim 1, wherein the first shield electrode (22) is symmetrical in the lateral direction about a longitudinal centerline extending in the longitudinal direction (132). [9] The multilayer broadband ceramic capacitor (100) of claim 1, wherein the capacitor (100) has a capacitor thickness in the Z direction (136) between the top surface (18) and the bottom surface (20), and wherein the ratio of the capacitor thickness to the distance between the shield and the bottom surface (20) is greater than about 2. [10] The multilayer broadband ceramic capacitor (100) according to claim 1, wherein the multilayer broadband ceramic capacitor (100) is configured for mounting on the mounting surface (101) such that the first and second shield electrodes (22, 24) are present between the plurality of active electrode layers (102, 104) and the mounting surface (101). [11] A multilayer broadband ceramic capacitor (100) according to claim 1, wherein the multilayer broadband ceramic capacitor (100) is free of shielding electrodes (22, 24) above the plurality of active electrode layers (102, 104) in the Z direction (136). [12] A multilayer broadband ceramic capacitor (100) according to claim 1, wherein the multilayer broadband ceramic capacitor (100) is free of shielding electrodes (22, 24) above a lowest electrode layer of the plurality of active electrode layers (102, 104) in the Z direction (136). [13] A multilayer broadband ceramic capacitor (100) according to claim 1, wherein at least one of the active electrode layers (102, 104) comprises a third electrode (106) comprising a base portion (114) electrically connected to the first external terminal (118), a first electrode arm (110) extending from the base portion (114) in the longitudinal direction (132) and a central portion (122) extending from the base portion (114) in the longitudinal direction (132). [14] A multilayer broadband ceramic capacitor (100) according to claim 13, wherein the central portion (122) has a first width (27) at a first location and a second width (29) greater than the first width (27) at a second location, and wherein the second location is offset from the first location in the longitudinal direction (132). [15] A multilayer broadband ceramic capacitor (100) according to claim 1, wherein the at least one of the active electrode layers (102, 104) comprises a second electrode (108) comprising a base portion (114) electrically connected to the second external terminal (120), wherein a central end gap distance is formed in the longitudinal direction (132) between the central portion (122) of the first electrode (22) and the base portion (114) of the second electrode (24). [16] A multilayer broadband ceramic capacitor (100) according to claim 1, wherein the at least one of the active electrode layers (102, 104) comprises a second electrode (108) comprising a base portion (114) electrically connected to the second external terminal (120), wherein a central edge gap distance (23) is formed in the lateral direction (134) between the central portion (122) of the first electrode (22) and the second electrode arm (110). [17] The multilayer broadband ceramic capacitor (100) of claim 1, wherein the multilayer broadband ceramic capacitor (100) has an insertion loss greater than about -0.4 dB at about 10 GHz. [18] A multilayer broadband ceramic capacitor (100) according to claim 1, wherein the multilayer broadband ceramic capacitor (100) has an insertion loss greater than about -0.4 dB at about 20 GHz. [19] The multilayer broadband ceramic capacitor (100) of claim 1, wherein the multilayer broadband ceramic capacitor (100) has an insertion loss greater than about -0.4 dB at about 30 GHz. [20] The multilayer broadband ceramic capacitor (100) of claim 1, wherein the multilayer broadband ceramic capacitor (100) has an insertion loss ranging from about -0.05 dB to about -0.4 dB from about 5 GHz to about 20 GHz. [21] The multilayer broadband ceramic capacitor (100) of claim 1, wherein the multilayer broadband ceramic capacitor (100) has an insertion loss ranging from about -0.05 dB to about -0.5 dB from about 20 GHz to about 40 GHz. [22] A method of forming a multilayer broadband ceramic capacitor (100), the method comprising: forming a plurality of active electrodes (22, 24) on a plurality of active electrode layers (102, 104); and forming a first shielding electrode (22) on a shielding electrode layer, the first shielding electrode (22) extending to a first end (119) of a monolithic body of the capacitor (100), the first shielding electrode (22) having a first longitudinal edge (28) oriented in the lateral direction (134) and facing away from the first external terminal (118), the first shielding electrode (22) having a second longitudinal edge (30) oriented in the lateral direction (134) and facing away from the first external terminal (118), and the second longitudinal edge (30) being offset in the longitudinal direction (132) by a shielding electrode offset distance (32) from the first longitudinal edge (28); forming a second shielding electrode (24) on the shielding electrode layer, extending to the second end (121) of the monolithic body and approximately aligned with the first shielding electrode (22) in the Z direction (136); and stacking the plurality of active electrode layers (102, 104) and the shielding electrode layer to form the monolithic body, so that the plurality of active electrode layers (102, 104) and the plurality of shielding electrodes (22, 24) run parallel to a longitudinal direction (132) of the capacitor.

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