Power conversion device and method for controlling the power conversion device

Abstract

Power conversion device (100) comprising: a power conversion circuit (60) including an upper circuit branch and a lower circuit branch corresponding to each phase of a motor (20) having a plurality of phases and converting a DC current into AC currents of the plurality of phases; a control circuit (40) that outputs a PWM signal to the upper circuit branch and the lower circuit branch; a simulated DC current calculation unit (451) that calculates first simulated downtime DC currents based on AC current values ​​of remaining phases when one phase of the plurality of phases fails, based on the AC currents output from the power conversion circuit (60), and a duty ratio of the PWM signal; and a failure determination unit (452) that detects a failure of the upper circuit arm or the lower circuit arm of any phase based on a DC current input to the power conversion circuit (60) or a DC current based on an AC current value output from the power conversion circuit (60), the duty ratio of the PWM signal, and the first simulated failure time DC current.

Description

Technical area

[0001] The present invention relates to a power conversion device and a method for controlling a power conversion device. State of the art

[0002] A hybrid or electric vehicle is equipped with a power conversion device configured to drive a motor. The power conversion device converts a DC current supplied from a battery into an AC current by switching power semiconductors that form an upper circuit branch and a lower circuit branch corresponding to each phase of the motor, thereby driving the motor.

[0003] In recent years, there has been an increasing demand for detecting anomalies and failures in power conversion devices based on automotive functional safety standards. Therefore, it is necessary to perform diagnostics capable of detecting anomalies and failures even for power semiconductors.

[0004] PTL 1 discloses an apparatus including a drive circuit for turning ON / OFF a power semiconductor for each power semiconductor and outputting an abnormality notification signal to an external abnormality notification device when it is determined that a failure has occurred in a power conversion device. Citation listPatent literature

[0005] PTL 1: JP 2017-208893 A Summary of the inventionTechnical problem

[0006] In the device described in PTL 1, it is difficult to identify which point of power semiconductors constituting an upper circuit arm and a lower circuit arm has failed. Solution to the task

[0007] A power conversion device according to the present invention includes: a power conversion circuit that includes an upper circuit arm and a lower circuit arm corresponding to each phase of a motor having multiple phases, and converts a DC current into AC currents of the multiple phases; a control circuit that outputs a PWM signal to the upper circuit arm and the lower circuit arm; a simulated DC current calculation unit that calculates first simulated downtime DC currents based on AC current values ​​of remaining phases when one phase among the multiple phases fails, based on the AC currents output from the power conversion circuit, and a duty ratio of the PWM signal;and a failure determination unit that detects a failure of the upper circuit arm or the lower circuit arm of any phase based on a DC current input to the power conversion circuit or a DC current based on an AC current value output from the power conversion circuit, the duty ratio of the PWM signal, and the first simulated failure time DC current.;

[0008] A method for controlling a power conversion device according to the present invention includes: forming a power conversion circuit having an upper circuit arm and a lower circuit arm corresponding to each phase of a motor having multiple phases, and converting a DC current into AC currents of the multiple phases; outputting a PWM signal to the upper circuit arm and the lower circuit arm; calculating first simulated downtime DC currents based on AC current values ​​of remaining phases when one phase among the multiple phases fails, based on the AC currents output from the power conversion circuit and a duty ratio of the PWM signal;and detecting a failure of the upper circuit branch or the lower circuit branch of any phase based on a DC current input to the power conversion circuit or a DC current based on an AC current value output from the power conversion circuit, the duty cycle of the PWM signal, and the first simulated failure time DC current.; Advantageous effects of the invention

[0009] According to the present invention, it is possible to identify which point of power semiconductors forming an upper circuit branch and a lower circuit branch has failed. Brief description of the drawings [ Fig. 1] Fig. 1 is a circuit configuration diagram of a power conversion device according to a first embodiment. [ Fig. 2] Fig. 2 is a circuit configuration diagram of the power conversion circuit. [ Fig. 3] Fig. 3 is a flowchart illustrating failure determination processing according to the first embodiment. [ Fig. 4] Fig. 4 is a flowchart illustrating failure handling processing. [ Fig. 5] Fig. 5(A), Fig. 5(B) and Fig. 5(C) are graphs of an AC current, a duty cycle, and a DC current when an off-stuck failure occurred in an upper U-phase circuit branch during power operation. [ Fig. 6] Fig. 6 is a circuit configuration diagram of a power conversion device according to a second embodiment. [ Fig. 7] Fig. 7 is a flowchart illustrating failure determination processing according to the second embodiment. [ Fig. 8] Fig. 8 is a circuit configuration diagram of a power conversion device according to a third embodiment. [ Fig. 9] Fig. 9 is a flowchart illustrating failure determination processing according to the third embodiment. [ Fig. 10] Fig. 10 is a flowchart illustrating failure determination processing according to a fourth embodiment. [ Fig. 11] Fig. 11 is a flowchart illustrating failure determination processing according to a fifth embodiment. Description of Embodiments[First Embodiment]

[0010] Fig. 1 is a circuit configuration diagram of a power conversion device 100 according to a first embodiment.

[0011] The power conversion device 100 converts DC power supplied from a DC power supply 10 into AC power to drive a motor 20 during power operation. The DC power supply 10 is a power supply configured to drive the motor 20. In addition, the power conversion device 100 converts the power of the motor 20 into DC power to charge the DC power supply 10 during regeneration.

[0012] The motor 20 is a three-phase motor having three windings therein. Additionally, an angle sensor (not shown) configured to measure a rotation angle of the motor 20 is mounted on the motor 20. The angle sensor outputs the measured rotation angle to the power conversion device 100 as an angle sensor value. The power conversion device 100 detects a failure, which will be described later, and reports the failure to a failure reporting device 30.

[0013] The power conversion device 100 includes a control circuit 40, a drive circuit 50, and a power conversion circuit 60. The control circuit 40 includes a motor speed calculation unit 41, a target current calculation unit 42, a duty cycle calculation unit 43, a PWM signal generation unit 44, and a power semiconductor diagnosis unit 45. The power semiconductor diagnosis unit 45 includes a simulated DC current calculation unit 451 and a failure determination unit 452.

[0014] The voltage sensor 70 is a sensor that measures an output voltage of the DC power supply 10 and outputs the measured voltage value as a voltage sensor value to the target current calculation unit 42 in the control circuit 40.

[0015] The DC current sensor 80 measures a DC current flowing between the DC power supply 10 and the power conversion circuit (inverter circuit) 60, and outputs the measured current value to the failure determination unit 452 as a DC current sensor value Idcs. Note that the DC current sensor 80 is installed to measure the current flowing from the DC power supply 10 into the power conversion circuit 60 as a positive current value in the present embodiment, but the DC current sensor may be installed to measure a current value in the opposite direction as a positive current value.

[0016] The AC current sensor 90 is a sensor configured to measure an AC current flowing through each of the phases (U-phase, V-phase, and W-phase) of the motor 20. Specifically, an AC current lu flowing through the U-phase is measured, and an AC current sensor value lus is output to the duty cycle calculation unit 43 and the simulated DC current calculation unit 451. Similarly, an AC current Iv flowing through the V-phase is measured, and an AC current sensor value Ivs is output to the duty cycle calculation unit 43 and the simulated DC current calculation unit 451. Similarly, an AC current Iw flowing through the W-phase is measured, and an AC current sensor value Iws is output to the duty cycle calculation unit 43 and the simulated DC current calculation unit 451.

[0017] The motor speed calculation unit 41 calculates a motor speed value from a change in the angle sensor value in the motor 20 and outputs the calculated motor speed value to the target current calculation unit 42.

[0018] The control circuit 40 communicates with an electronic control unit (not shown) provided outside the power conversion device 100, receives a target torque from the external electronic control unit, and inputs the target torque to the target current calculation unit 42.

[0019] The target current calculation unit 42 calculates a current value to be supplied to the motor 20 using the target torque, the voltage sensor value, and the motor speed value output from the motor speed calculation unit 41, and outputs the current value as a target current value to the duty cycle calculation unit 43. The target current value is expressed, for example, in the form of a d-axis target current value and a q-axis target current value.

[0020] The duty calculation unit 43 calculates a U-phase duty value Du, a V-phase duty value Dv, and a W-phase duty value Dw based on the target current value output from the target current calculation unit 42 and the AC current sensor values ​​lus, Ivs, and Iws, and outputs the calculated values ​​to the PWM signal generation unit 44 and the simulated DC current calculation unit 451.

[0021] In the present embodiment, the U-phase duty value Du indicates an ON-time ratio of an upper U-phase circuit arm power semiconductor, and an ON-time ratio of a lower U-phase circuit arm power semiconductor is indicated by 1-Du. Similarly, the V-phase duty value Dv indicates an ON-time ratio of an upper V-phase circuit arm power semiconductor, and an ON-time ratio of a lower V-phase circuit arm power semiconductor is indicated by 1-Dv. The W-phase duty value Dw indicates an ON-time ratio of an upper W-phase circuit arm power semiconductor, and an ON-time ratio of a lower W-phase circuit arm power semiconductor is indicated by 1-Dw.

[0022] The PWM signal generation unit 44 includes therein a timer (not shown), generates a pulse width modulation (PWM) signal based on a value of the timer, the U-phase duty value Du, the V-phase duty value Dv, and the W-phase duty value Dw, and outputs the PWM signal to the drive circuit 50.

[0023] When an abnormality notification signal is output from the power semiconductor diagnosis unit 45, the PWM signal generation unit 44 controls the PWM signal so that the motor 20 is not driven. Examples of the state in which the motor 20 is not driven include a state in which all six power semiconductors in the power conversion circuit 60 are turned off (referred to as a freewheeling state in the present embodiment).Other examples include a state in which three power semiconductors of the upper circuit arm among the six power semiconductors are turned on and three power semiconductors of the lower circuit arm are turned off (referred to as an upper-arm active short-circuit state in the present embodiment), and an opposite state in which the three power semiconductors of the upper circuit arm are turned off and the three power semiconductors of the lower circuit arm are turned on (referred to as a lower-arm active short-circuit state in the present embodiment).

[0024] The drive circuit 50 receives the PWM signal output from the PWM signal generation unit 44 and outputs a drive signal for turning the power semiconductor ON / OFF to the power conversion circuit 60.

[0025] The power conversion circuit 60 includes a smoothing capacitor and six power semiconductors, and converts DC power received from the DC power supply 10 into AC power to drive the motor 20 during power operation. Additionally, the power of the motor 20 is converted into DC power to charge the DC power supply 10 during regeneration.

[0026] The power semiconductor diagnosis unit 45 performs failure diagnosis of the power semiconductor in the power conversion circuit 60. The simulated DC current calculation unit 451 in the power semiconductor diagnosis unit 45 calculates first simulated failure-time DC current values ​​of the respective phases based on the duty cycle values ​​Du, Dv, and Dw and the AC current sensor values ​​lus, Ivs, and Iws of the corresponding phases, and outputs the first simulated failure-time DC current values ​​to the failure determination unit 452.

[0027] The failure determination unit 452 determines which point of the power semiconductor in the power conversion circuit 60 has failed using the first simulated failure-time DC current values ​​of the respective phases, the DC current sensor value Idcs, the duty cycle values ​​Du, Dv, and Dw of the corresponding phases, and the target torque, and outputs a failure notification signal corresponding to the failure point to the failure notification device 40 and the PWM signal generation unit 44. Note that the failure determination unit 452 determines the target torque to identify whether it is the power operation time or the regeneration time. Specifically, a positive target torque indicates the power operation time, and a negative target torque indicates the regeneration time.As another identification method, the power operation time can be identified when the DC current sensor value Idcs is positive, and the regeneration time can be identified when the DC current sensor value Idcs is negative.

[0028] Fig. 2 is a circuit configuration diagram of the power conversion circuit 60.

[0029] The power conversion circuit 60 includes upper and lower U-phase, V-phase, and W-phase branch series circuits. The upper and lower U-phase branch series circuit 61 includes a U-phase upper arm power semiconductor Tuu and a U-phase upper arm diode Duu, and a U-phase lower arm power semiconductor Tul and a U-phase lower arm diode Dul. The upper and lower V-phase branch series circuit 62 includes a V-phase upper arm power semiconductor Tvu and a V-phase upper arm diode Dvu, and a V-phase lower arm power semiconductor Tvl and a V-phase lower arm diode Dvl. The upper and lower W-phase branch series circuit 63 includes a W-phase upper arm power semiconductor Twu and a W-phase upper arm diode Dwu, and a W-phase lower arm power semiconductor Twl and a W-phase lower arm diode Dwl.

[0030] An upper circuit branch 64 includes the U-phase upper branch power semiconductor Tuu, the U-phase upper branch diode Duu, the V-phase upper branch power semiconductor Tvu, the V-phase upper branch diode Dvu, the W-phase upper branch power semiconductor Twu, and the W-phase upper branch diode Dwu. The lower circuit branch 65 includes the U-phase lower branch power semiconductor Tul, the U-phase lower branch diode Dul, the V-phase lower branch power semiconductor Tvl, the V-phase lower branch diode Dvl, the W-phase lower branch power semiconductor Twl, and the W-phase lower branch diode Dwl. The power semiconductor is, for example, a power metal-oxide-semiconductor field-effect transistor (power MOSFET) or an insulated-gate bipolar transistor (IGBT).

[0031] A smoothing capacitor 66 smoothes a current generated by the ON / OFF of the power semiconductor and suppresses ripple in the DC current supplied to the power conversion circuit 60 from the DC power supply 10. For example, an electrolytic capacitor or a film capacitor is used as the smoothing capacitor 66.

[0032] Fig. 3 is a flowchart illustrating the power semiconductor failure determination processing in the power semiconductor diagnosis unit 45.

[0033] As in step S10 of Fig. 3, the power semiconductor diagnostic unit 45 detects the AC current sensor values ​​lus, Ivs and Iws and the DC current sensor value Idcs.

[0034] In step S11, the simulated DC current calculation unit 451 calculates a first simulated downtime DC current value Idcu of the U-phase, a first simulated downtime DC current value Idcv of the V-phase, and a first simulated downtime DC current value Idcw of the W-phase based on the following formulas (1) to (3) from the duty cycle values ​​Du, Dv, and Dw and the AC current sensor values ​​lus, Ivs, and Iws of the respective phases, and outputs the calculated values ​​to the downtime determination unit 452. First simulated downtime DC current value of the U phase Idcu=Dv×Ivs+Dw×Iws First simulated downtime DC current value of the V phase Idcv=Du×Ius+Dw×Iws First simulated downtime DC current value of the W phase Idcw=Du×Ius+Dv×Ivs

[0035] In step S12, if a difference between the DC current sensor value Idcs and the first simulated downtime DC current value Idcu of the U-phase is smaller than a threshold value 1, the failure determination unit 452 determines that a failure has occurred in the U-phase power semiconductor. When an off-stuck failure of a power semiconductor occurs, a first simulated downtime DC current of a corresponding phase is substantially equal to an actual DC current value in a time zone where current is supposed to flow to the failed power semiconductor. The threshold value 1 is set to a value that satisfies such a relationship. As a result, it is possible to determine in which phase the failure occurred.

[0036] In step S13, the failure determination unit 452 determines whether the engine 20 is in a power operation state or in a regeneration state based on the input target torque or the like.

[0037] If it is determined that the motor 20 is in the power operating state, the processing proceeds to step S14, and the failure determination unit 452 determines in step S14 whether the U-phase duty cycle value Du is greater than a threshold value 2. If the U-phase duty cycle value Du is greater than the threshold value 2, it is determined in step S16 that an off-stuck failure of the power semiconductor of the upper circuit arm of the U-phase occurs. If the U-phase duty cycle value Du is not greater than the threshold value 2, it is determined in step S17 that an off-stuck failure of the power semiconductor of the lower circuit arm of the U-phase occurs. If the U-phase duty cycle value Du is in the range of 0 to 1, the threshold value 2 is set to 0.5, for example. As a result, it is determined to which of the upper circuit branch and the lower circuit branch the current should flow.

[0038] If it is determined in step S13 that the motor 20 is in the regeneration state, the processing proceeds to step S15, and the failure determination unit 452 determines in step S15 whether the U-phase duty value Du is equal to or less than the threshold value 2. If the U-phase duty value Du is equal to or less than the threshold value 2, it is determined in step S16 that the OFF-stuck failure of the power semiconductor of the upper circuit arm of the U-phase occurs. If the U-phase duty value Du is not equal to or less than the threshold value 2, it is determined in step S17 that the OFF-stuck failure of the power semiconductor of the lower circuit arm of the U-phase occurs.

[0039] In step S18, the failure determination unit 452 outputs a failure notification signal corresponding to a failure point to the PWM signal generation unit 44 and the failure notification device 30.

[0040] In this way, no current flows through the failed power semiconductor, and the DC current becomes substantially equal to the first simulated downtime DC current of the failed phase when the current is expected to flow to the failure point. At this time, the duty cycle of the failed phase can be determined by the duty cycle value of the failed phase, which of the upper and lower arms is mainly switched on. The failure point of the upper and lower arms can be determined based on the duty cycle. Note that the phase of the voltage (i.e., the duty cycle) and the phase of the current are the same during power operation. A time zone where the duty cycle is greater than the threshold of 0.5 coincides with a time zone where the current is expected to flow to the upper arm.On the other hand, the phase of the voltage (i.e., the duty cycle) and the phase of the current are shifted by 180° during regeneration, a time zone in which the duty cycle is less than the threshold of 0.5 coincides with the time zone in which the current should flow to the upper branch.

[0041] Steps S22 to S27 indicate the V-phase failure determination processing, and steps S32 to S37 indicate the W-phase failure determination processing.

[0042] In step S12, if the difference between the DC current sensor value Idcs and the first simulated downtime DC current value Idcu of the U-phase is not less than the threshold value 1, the processing proceeds to step S22. In step S22, if a difference between the DC current sensor value Idcs and the first simulated downtime DC current value Idcv of the V-phase is less than the threshold value 1, the failure determination unit 452 determines that a failure has occurred in the V-phase power semiconductor. Hereinafter, steps S22 to S27 are similar to steps S12 to S17 corresponding to the U-phase failure determination processing, and thus their description is omitted.

[0043] In step S22, if the difference between the DC current sensor value Idcs and the first simulated downtime DC current value Idcv of the V phase is not less than the threshold value 1, the processing proceeds to step S32. In step S32, if a difference between the DC current sensor value Idc and the first simulated downtime DC current value Idcw of the W phase is less than the threshold value 1, the failure determination unit 452 determines that a failure has occurred in the W-phase power semiconductor. Hereinafter, steps S32 to S37 are similar to steps S12 to S17 corresponding to the U-phase failure determination processing, and thus their description is omitted.

[0044] If the difference between the DC current sensor value Idcs and the first simulated downtime DC current value Idcw of the W phase is not less than the threshold value 1 in step S32, the failure determination unit 452 proceeds to step S39. In step S39, it is determined that no off-stuck failure exists in the power semiconductor.

[0045] Fig. 4 is a flowchart illustrating failure handling processing of the PWM signal generating unit 44.

[0046] When receiving the failure notification signal from the failure determination unit 452, the PWM signal generation unit 44 starts the failure handling processing. If the failure notification signal is Fig. 3 is received and it is determined that the OFF-Stuck failure has occurred in the upper arm of any one of the U-phase, the V-phase and the W-phase, which is performed in step S40 of Fig. 4, processing proceeds to step S41.

[0047] In step S41, a PWM signal is generated to set the lower branch to the freewheeling state or the active short-circuit state. Since the failure makes it difficult to turn on the power semiconductor of the upper branch, the upper branch is not brought into the active short-circuit state.

[0048] When it is determined in step S42 that the OFF-stuck failure has occurred in the lower arm of any one of the U-phase, the V-phase, and the W-phase, the processing proceeds to step S43.

[0049] In step S43, a PWM signal is generated to establish the freewheeling state or the active short-circuit state of the upper branch. Since the failure makes it difficult to turn on the power semiconductor of the lower circuit branch, the lower circuit branch is not brought into the active short-circuit state.

[0050] In a case corresponding to no failure in step S40 and step S42, processing proceeds to step S44. Since no failure has occurred, the PWM signal generation unit 44 continues PWM operation, generates a PWM signal according to the duty values ​​Du, Dv, and Dw of the respective phases, and outputs the PWM signal to the drive circuit 50 in step S44.

[0051] Fig. 5(A), Fig. 5(B) and Fig. 5(C) are graphs of an AC current, a duty cycle, and a DC current when an OFF-stuck failure occurred in the upper circuit arm of the U-phase during power operation.

[0052] Fig. 5(A) represents the AC current, Fig. 5(B) represents the duty cycle, Fig. Figure 5(C) depicts the DC current, and the horizontal axis of each graph represents time. It shows a case where an off-stuck failure occurred in the upper circuit arm of the U-phase at time t during power operation.

[0053] The AC current sensor value lus flowing through the U-phase becomes zero because the OFF-stuck failure occurred in the upper circuit branch of the U-phase at time t, as shown in Fig. 5(A). As shown in Fig. 5(C), a time zone occurs in which the first simulated downtime DC current Idcu of the U-phase is close to the DC current value Idcs. In this time zone, it is determined that the difference between the DC current sensor value Idcs and the first simulated downtime DC current value Idcu of the U-phase is smaller than the threshold value 1, as in step S13 of Fig. 3. Then the U-phase duty cycle value Du in this time zone exceeds 0.5, as shown in Fig. 5(B). Therefore, it is determined that the U-phase duty value Du is greater than the threshold value 2, as in step S14 of Fig. 3. As a result, in step S16 of Fig. 3 the OFF-stuck failure of the power semiconductor of the upper circuit branch of the U-phase is determined. [Second embodiment]

[0054] Fig. 6 is a circuit configuration diagram of a power conversion device 200 according to a second embodiment.

[0055] The power conversion device 200 according to the second embodiment does not include a DC current sensor 80 and a different power semiconductor diagnostic unit 46 compared to the power conversion device 100 according to the first embodiment shown in Fig. 1. The same points as those of the power conversion device 100 according to the first embodiment are denoted by the same reference numerals, their description will be omitted, and different parts will be described below.

[0056] A simulated DC current calculation unit 461 of the power semiconductor diagnostic unit 46 calculates a first simulated downtime DC current of each phase based on formulas (1) to (3) described in the first embodiment. Furthermore, a simulated normal-time DC current value is calculated using the duty cycles Du, Dv, and Dw of the respective phases and the AC current sensor values ​​Ius, Ivs, and Iws of the corresponding phases. That is, a DC current at the normal time can be calculated by the following formula (4), and thus, the value calculated by this formula (4) is used instead of a DC current sensor. DC current=(Du×Ius)+(Dv×Ivs)+(Dv×Iws)

[0057] Here, Du is a U-phase duty cycle, Dv is a U-phase duty cycle of V-phase, Dw is a W-phase duty cycle, lus is a U-phase AC current sensor value, Ivs is a V-phase current sensor value, and Iws is a W-phase current sensor value.

[0058] The simulated DC current calculation unit 461 outputs the calculated DC current to a failure determination unit 462. The failure determination unit 462 determines which point of the power semiconductor in the power conversion circuit 60 has failed using the first simulated downtime DC current values ​​of the respective phases, the simulated normal-time DC current value, the duty cycle values ​​Du, Dv, and Dw of the corresponding phases, and a target torque, and outputs a failure notification signal corresponding to the failure point to the failure notification device 30 and the PWM signal generation unit 44. Note that the failure determination unit 462 determines the target torque to identify whether it is the power operation time or the regeneration time. Specifically, a positive target torque indicates the power operation time, and a negative target torque indicates the regeneration time.As another identification method, the power operation time may be identified when the simulated normal-time DC current calculated by the simulated DC current calculation unit 461 is positive, and the regeneration time may be identified when the simulated normal-time DC current calculated by the simulated DC current calculation unit 461 is negative.

[0059] Fig. 7 is a flowchart illustrating the power semiconductor failure determination processing in the power semiconductor diagnosis unit 46.

[0060] In the failure determination processing in the power semiconductor diagnosis unit 46 according to the second embodiment, the same points as those in the flowchart illustrating the failure determination processing according to the first embodiment shown in Fig. 3 are designated by the same reference numerals, and their description will be omitted, and different parts will be described below.

[0061] As in step S10' in Fig. As shown in Figure 7, the power semiconductor diagnostic unit 46 detects the AC current sensor values ​​lus, Ivs and Iws.

[0062] In step S11', the simulated DC current calculation unit 461 calculates a first simulated downtime DC current value Idcu of the U phase, a first simulated downtime DC current value Idcv of the V phase, and a first simulated downtime DC current value Idcw of the W phase based on formulas (1) to (3) from the duty cycle values ​​Du, Dv, and Dw and the AC current sensor values ​​lus, Ivs, and Iws of the respective phases, and outputs the calculated values ​​to the downtime determination unit 462. Further, a simulated normal-time DC current Idce, which is a DC current at the normal time, is calculated based on formula (4) and output to the downtime determination unit 462.

[0063] In step S12', if a difference between the simulated normal-time DC current Idce and the first simulated downtime DC current value Idcu of the U-phase is smaller than a threshold value 1, the failure determination unit 462 determines that a failure has occurred in the U-phase power semiconductor. When an off-stuck failure of a power semiconductor occurs, a first simulated downtime DC current of a corresponding phase is substantially equal to an actual DC current value in a time zone where the current is to flow to the failed power semiconductor. The threshold value 1 is set to a value that satisfies such a relationship. As a result, it is possible to determine in which phase the failure occurred.

[0064] In step S13, the failure determination unit 462 determines whether the engine 20 is in a power operation state or in a regeneration state based on the input target torque or the like. The following is similar to the flowchart illustrating the failure determination processing according to the first embodiment shown in Fig. 3 is shown.

[0065] If, in step S12', the difference between the simulated normal-time DC current Idce and the first simulated downtime DC current value Idcu of the U-phase is not less than the threshold value 1, the processing proceeds to step S22'. In step S22', if a difference between the simulated normal-time DC current Idce and the first simulated downtime DC current value Idcv of the V-phase is less than the threshold value 1, the failure determination unit 462 determines that a failure has occurred in the V-phase power semiconductor. Hereinafter, steps S23 to S27 are similar to steps S13 to S17 in the U-phase failure determination processing, and thus their description is omitted.

[0066] If, in step S22', the difference between the simulated normal-time DC current Idce and the first simulated downtime DC current value Idcv of the V phase is not less than the threshold value 1, the processing proceeds to step S32'. In step S32', if a difference between the simulated normal-time DC current Idce and the first simulated downtime DC current value Idcw of the W phase is less than the threshold value 1, the failure determination unit 462 determines that a failure has occurred in the W-phase power semiconductor. Hereinafter, steps S33 to S37 are similar to steps S13 to S17 in the U-phase failure determination processing, and thus their description is omitted.

[0067] If, in step S32', the difference between the simulated normal-time DC current Idce and the first simulated downtime DC current value Idcw of the W phase is not less than the threshold value 1, the failure determination unit 462 proceeds to step S39. In step S39, it is determined that no off-stuck failure exists in the power semiconductor. [Third Embodiment]

[0068] Fig. 8 is a circuit configuration diagram of a power conversion device 300 according to a third embodiment.

[0069] The power conversion device 300 according to the third embodiment is different from the power conversion device 100 according to the first embodiment shown in Fig. 1, with respect to a power semiconductor diagnosis unit 47. The same points as those of the power conversion device 100 according to the first embodiment are denoted by the same reference numerals, their description will be omitted, and different parts will be described below.

[0070] A simulated DC current calculation unit 471 of the power semiconductor diagnostic unit 47 calculates a first simulated downtime DC current of each phase based on formulas (1) to (3) described in the first embodiment. Furthermore, second simulated downtime DC currents of the respective phases are calculated based on the following formulas (5) to (7). Second simulated downtime DC current of the U phase Idcu2=K×Ius+Dv×Ivs+Dw×Iws Second simulated downtime DC current of the V phase Idcv2=Du×Ius+K×Ivs+Dw×Iws Second simulated downtime DC current of the W phase Idcw2=Du×Ius+Dv×Ivs+K×Iws

[0071] Here, Du is a duty cycle of the U phase, Dv is a duty cycle of the V phase, Dw is a duty cycle of the W phase, Ius is a U-phase AC current sensor value, Ivs is a V-phase current sensor value, Iws is a W-phase current sensor value, and K is a coefficient. The coefficient K is set within the range 0 < K ≤ 1. The first simulated downtime DC currents of formulas (1) to (3) shown in the first embodiment correspond to a case where formulas (5) to (7) are calculated with K = 0. To avoid erroneous detection in normal time, it is desirable to set K to a value significantly different from 0 (for example, K = 1).

[0072] The first simulated downtime DC current and the second simulated downtime DC current of each phase calculated by the simulated DC current calculation unit 471 are output to the downtime determination unit 472.

[0073] The failure determination unit 472 determines which point of the power semiconductors in the power conversion circuit 60 has failed using the first simulated failure-time DC current values ​​of the respective phases, the second simulated failure-time DC current values ​​of the corresponding phases, a DC current sensor value Idcs, the duty cycle values ​​Du, Dv, and Dw of the corresponding phases, and a target torque, and outputs a failure notification signal corresponding to the failure point to the failure notification device 30 and the PWM signal generation unit 44.

[0074] In the present embodiment, the failure determination unit 472 determines whether a difference between the DC current sensor value Idcs and the first simulated failure time DC current value is smaller than a threshold value 1 and a difference between the DC current sensor value Idcs and the second simulated failure time DC current value is smaller than the threshold value 1.

[0075] Since no current flows through a failed power semiconductor, the second simulated downtime DC currents using all three phase AC currents and the DC currents are also equal. Therefore, a failure point can be identified even if the second simulated downtime DC current is also used. If only the difference between the DC current sensor value Idcs and the first simulated downtime DC current value is determined, the DC current will approach the first simulated downtime DC current value, which is not a failed phase, at the time when the duty cycle is small (duty cycle ≈ 0), which may cause false detection of a failure.On the other hand, it is possible to eliminate erroneous detection of the failure by determining whether the difference between the DC current sensor value Idcs and the first simulated failure time DC current value is smaller than the threshold value 1 and the difference between the DC current sensor value Idcs and the second simulated failure time DC current value is smaller than the threshold value 1 in the present embodiment.

[0076] Fig. 9 is a flowchart illustrating the power semiconductor failure determination processing in the power semiconductor diagnosis unit 47.

[0077] In the failure determination processing in the power semiconductor diagnosis unit 47 according to the third embodiment, the same points as those in the flowchart illustrating the failure determination processing according to the first embodiment shown in Fig. 3 are designated by the same reference numerals, their description will be omitted, and different parts will be described below.

[0078] In step S10 of Fig. 9, the power semiconductor diagnosis unit 45 acquires the AC current sensor values ​​lus, Ivs, and Iws and the DC current sensor value Idcs, and in step S11, the simulated DC current calculation unit 471 calculates the first simulated downtime DC current value Idcu of the U-phase, the first simulated downtime DC current value Idcv of the V-phase, and the first simulated downtime DC current value Idcw of the W-phase from the duty cycle values ​​Du, Dv, and Dw and the AC current sensor values ​​lus, Ivs, and Iws based on the formulas (1) to (3) described in the first embodiment, and outputs the calculated values ​​to the downtime determination unit 472.Further, the simulated DC current calculation unit 471 calculates the second simulated downtime DC current value Idcu2 of the U-phase, the second simulated downtime DC current value Idcv2 of the V-phase, and the second simulated downtime DC current value Idcw2 of the W-phase based on the formulas (5) to (7), and outputs the calculated values ​​to the downtime determination unit 472.

[0079] In step S12, the failure determination unit 472 determines that a failure has occurred in the U-phase power semiconductor when the difference between the DC current sensor value Idcs and the first simulated failure-time DC current value Idcu of the U-phase is smaller than the threshold value 1, and the difference between the DC current sensor value Idcs and the second simulated DC current value Idcu2 of the U-phase is smaller than the threshold value 1.

[0080] In step S13, the failure determination unit 462 determines whether the engine 20 is in a power operation state or in a regeneration state based on the input target torque or the like. Hereinafter, steps S13 to S18 are similar to those of the flowchart illustrating the failure determination processing according to the first embodiment shown in Fig. 3 is shown.

[0081] The failure determination unit 472 proceeds to a process of step S22" if a condition that the difference between the DC current sensor value Idcs and the first simulated downtime DC current value Idcu of the U-phase is smaller than the threshold value 1 and the difference between the DC current sensor value Idcs and the second simulated downtime DC current value Idcu2 of the U-phase is smaller than the threshold value 1 is not satisfied in step S12". In step S22, the failure determination unit 472 determines that a failure has occurred in the V-phase power semiconductor when the difference between the DC current sensor value Idcs and the first simulated downtime DC current value Idcv of the V-phase is smaller than the threshold value 1, and the difference between the DC current sensor value Idcs and the second simulated downtime DC current value Idcv2 of the V-phase is smaller than the threshold value 1.Hereinafter, steps S23 to S27 are similar to steps S13 to S17 in the U-phase failure determination processing, and thus their description is omitted.

[0082] If a condition that the difference between the DC current sensor value Idcs and the first simulated downtime DC current value Idcv of the V-phase is smaller than the threshold value 1 and the difference between the DC current sensor value Idcs and the second simulated downtime DC current value Idcv2 of the V-phase is smaller than the threshold value 1 is not met in step S22", the processing proceeds to a process of step S32". In step S32", the failure determination unit 472 determines that a failure has occurred in the W-phase power semiconductor when the difference between the DC current sensor value Idcs and the first simulated downtime DC current value Idcw of the W-phase is smaller than the threshold value 1 and the difference between the DC current sensor value Idcs and the second simulated downtime DC current value Idcw2 of the W-phase is smaller than the threshold value 1.Hereinafter, steps S33 to S37 are similar to steps S13 to S17 in the U-phase failure determination processing, and thus their description is omitted.

[0083] The failure determination unit 462 proceeds to a process of step S39 if a condition that the difference between the DC current sensor value Idcs and the first simulated downtime DC current value Idcw of the W phase is smaller than the threshold value 1 and the difference between the DC current sensor value Idcs and the second simulated downtime DC current value Idcw2 of the W phase is smaller than the threshold value 1 is not satisfied in step S32. In step S39, it is determined that no OFF-stuck failure exists in the power semiconductor. [Fourth Embodiment]

[0084] Since the power conversion device 100 according to a fourth embodiment is similar to the power conversion device 100 according to the first embodiment shown in Fig. 1, the same points are denoted by the same reference numerals, and their description is omitted.

[0085] Fig. Fig. 10 is a flowchart illustrating power semiconductor failure determination processing according to the present embodiment. In the present embodiment, there is a difference in the failure determination processing from the flowchart illustrating the failure determination processing according to the first embodiment shown in Fig. 3. The same points as those of the flowchart illustrating the failure determination processing according to the first embodiment shown in Fig. 3 are denoted by the same reference numerals, their description is omitted, and different parts are described below.

[0086] In the first embodiment, in step S12 of Fig. 3 determines whether the difference between the DC current sensor value Idcs and the first simulated downtime DC current value Idcu of the U-phase is smaller than a threshold value 1. In the present embodiment, in step S12''' of Fig. 10 determines whether a state in which a difference between a DC current sensor value Idcs and a first simulated downtime DC current value Idcu of the U-phase is smaller than a threshold value has continued for a specific period of time or longer. When an AC current of a specific phase is zero, a DC current sensor value coincides with a first simulated downtime DC current value of the corresponding phase even if there is no failure in a power semiconductor, so there is a possibility that the failure will be erroneously detected. Therefore, in the present embodiment, a failure is detected when the state in which the difference between the DC current sensor value Idcs and the first simulated downtime DC current value Idcu of the U-phase is smaller than the threshold value 1 continues for a specific period of time or longer, thereby avoiding erroneous detection of the failure.

[0087] In step S22''' of Fig. 10, it is determined whether a state in which the difference between the DC current sensor value Idcs and a first simulated downtime DC current value Idcv of the V phase is smaller than the threshold value 1 has continued for a specific period of time or longer.

[0088] In step S32''' of Fig. 10, it is determined whether a condition in which the difference between the DC current sensor value Idcs and a first simulated downtime DC current value Idcw of the W phase is smaller than the threshold value 1 has continued for a specific period of time or longer. [Fifth Embodiment]

[0089] Since the power conversion device 300 according to a fifth embodiment is similar to the power conversion device 300 according to the third embodiment shown in Fig. 8, the same points are denoted by the same reference numerals, and their description is omitted.

[0090] Fig. Fig. 11 is a flowchart illustrating power semiconductor failure determination processing according to the present embodiment. In the present embodiment, there is a difference in the failure determination processing from the flowchart illustrating the failure determination processing according to the third embodiment shown in Fig. 9. The same points as those of the flowchart showing the failure determination processing according to the third embodiment shown in Fig. 9 are denoted by the same reference numerals, their description is omitted, and different parts are described below.

[0091] In the third embodiment, in step S12'' of Fig. 9 determines whether the difference between the DC current sensor value Idcs and the first simulated downtime DC current value Idcu of the U-phase is smaller than a threshold value 1 and the difference between the DC current sensor value Idcs and the second simulated downtime DC current value Idcu2 of the U-phase is smaller than the threshold value 1. In the present embodiment, in step S12''' of Fig. 11 determines whether a difference between a first simulated downtime DC current value Idcu of the U-phase and a second simulated downtime DC current value Idcu2 of the U-phase is smaller than a threshold value 1. In the third embodiment, when a condition that a difference between a DC current sensor value Idcs and the first simulated downtime DC current value Idcu of the U-phase is smaller than the threshold value 1 and a difference between the DC current sensor value Idcs and the second simulated downtime DC current value Idcu2 of the U-phase is smaller than the threshold value 1 is satisfied, the difference between the first simulated downtime DC current value Idcu of the U-phase and the second simulated downtime DC current value Idcu2 of the U-phase also falls within a specific range.Therefore, it is possible to perform a determination equivalent to the determination condition of the third embodiment using the determination condition of the present embodiment while simplifying the determination condition compared to the third embodiment.

[0092] In step S22''' in Fig. 11, it is determined whether a difference between a first simulated downtime DC current value Idcv of the V-phase and a second simulated downtime DC current value Idcv2 of the V-phase is smaller than the threshold value 1.

[0093] In step S32''' in Fig. 11, it is determined whether a difference between a first simulated downtime DC current value Idcw of the W phase and a second simulated downtime DC current value Idcw2 of the W phase is smaller than the threshold value 1.

[0094] According to the embodiments described above, the following operational effects are obtained.

[0095] (1) The power conversion device 100 includes: the power conversion circuit 60, which includes an upper circuit arm and a lower circuit arm corresponding to each phase of the motor 20 having multiple phases, and converts a DC current into AC currents of the multiple phases; the control circuit 40, which outputs a PWM signal to the upper circuit arm and the lower circuit arm; the simulated DC current calculation unit 451, which calculates first simulated downtime DC currents based on AC current values ​​of remaining phases when one phase among the multiple phases fails, based on the AC currents output from the power conversion circuit 60 and a duty ratio of the PWM signal;and the failure determination unit 452, which detects a failure of the upper circuit arm or the lower circuit arm of any phase based on a DC current input to the power conversion circuit 60 or a DC current based on an AC current value output from the power conversion circuit 60, the duty ratio of the PWM signal, and the first simulated failure-time DC current. As a result, it is possible to identify which point of power semiconductors constituting an upper circuit arm and a lower circuit arm has failed.

[0096] (2) A method for controlling the power conversion device 100 includes: forming the power conversion circuit 60 including an upper circuit arm and a lower circuit arm corresponding to each phase of the motor 20 having a plurality of phases, and converting a DC current into AC currents of the plurality of phases; outputting a PWM signal to the upper circuit arm and the lower circuit arm; calculating first simulated downtime DC currents based on AC current values ​​of remaining phases when one phase among the plurality of phases fails, based on the AC currents output from the power conversion circuit 60 and a duty ratio of the PWM signal;and detecting a failure of the upper circuit arm or the lower circuit arm of any phase based on a DC current input to the power conversion circuit 60 or a DC current based on an AC current value output from the power conversion circuit 60, the duty ratio of the PWM signal, and the first simulated failure-time DC current. As a result, it is possible to identify which point of power semiconductors constituting an upper circuit arm and a lower circuit arm has failed. (Modifications)

[0097] The present invention can be modified by modifying the above-described first to fifth embodiments as follows.

[0098] (1) The motor 20 has been described as an example of three phases having three internal windings, but it may be a multi-phase motor without being limited to three phases. Even in this case, it is possible to detect a failure of an upper circuit arm or a lower circuit arm of any phase.

[0099] (2) The power conversion device 100 includes the AC current sensor 90 for the three phases therein, but may include an AC current sensor for only two phases. In this case, an AC current of the remaining one phase can be calculated using a fact that the sum of the AC currents of the three phases becomes zero, and the failure of the upper circuit arm or the lower circuit arm of any phase can be detected in a manner similar to the case including the AC current sensor 90 for the three phases.

[0100] The present invention is not limited to the embodiments described above, and other modes that can be conceived within the scope of the technical idea of ​​the present invention are also included within the scope of the present invention, as long as the characteristics of the present invention are not impaired. In addition, the invention can be configured by combining the embodiments and modifications. List of reference symbols 10 DC power supply 20 engine 40 control circuit 41 Engine speed calculation unit 42 Target current calculation unit 43 Duty cycle calculation unit 44 PWM signal generation unit 45 Power semiconductor diagnostic unit 50 control circuit 60 power conversion circuit 100 power conversion device 451 Calculation unit for simulated DC current 452 Failure Determination Unit

Claims

[1] Power conversion device (100) comprising: a power conversion circuit (60) including an upper circuit branch and a lower circuit branch corresponding to each phase of a motor (20) having a plurality of phases and converting a DC current into AC currents of the plurality of phases; a control circuit (40) that outputs a PWM signal to the upper circuit branch and the lower circuit branch; a simulated DC current calculation unit (451) that calculates first simulated downtime DC currents based on AC current values ​​of remaining phases when one phase of the plurality of phases fails, based on the AC currents output from the power conversion circuit (60), and a duty ratio of the PWM signal; and a failure determination unit (452) that detects a failure of the upper circuit arm or the lower circuit arm of any phase based on a DC current input to the power conversion circuit (60) or a DC current based on an AC current value output from the power conversion circuit (60), the duty ratio of the PWM signal, and the first simulated failure time DC current. [2] The power conversion device (100) of claim 1, further comprising: a DC current sensor (80) that measures a DC current input to the power conversion circuit (60), wherein the failure determination unit (452) detects a failure of the upper circuit arm or the lower circuit arm of any phase based on the DC current measured by the DC current sensor (80). [3] The power conversion device (100) according to claim 1, wherein the simulated DC current calculation unit (451) calculates the DC current based on the AC current value output from the power conversion circuit (60) and the duty ratio of the PWM signal, and the failure determination unit (452) detects a failure in the upper circuit arm or the lower circuit arm of any phase based on the calculated DC current. [4] The power conversion device (100) according to any one of claims 1 to 3, wherein the simulated DC current calculation unit (451) calculates second simulated downtime DC currents based on all AC current values ​​of the plurality of phases, and detects a failure of the upper circuit arm and the lower circuit arm of any phase based on the first simulated downtime DC current and the second simulated downtime DC current. [5] The power conversion device (100) according to any one of claims 1 to 3, wherein, when a difference between the DC current and the first simulated downtime DC current of a specific phase is equal to or less than a specific value, the failure determination unit (452) determines that the upper circuit arm of the phase has failed if the duty cycle of the phase during power operation of the motor (20) is equal to or greater than a threshold value or the duty cycle of the phase during regeneration of the motor (20) is equal to or less than the threshold value. [6] The power conversion device (100) according to claim 5, wherein, when a state in which a difference between the DC current and the first simulated downtime DC current of a specific phase is equal to or less than a specific value continues for a specific period of time or longer, the failure determination unit (452) determines that the upper circuit arm of the phase has failed if the duty ratio of the phase during power operation of the motor (20) is equal to or greater than a threshold value or the duty ratio of the phase during regeneration of the motor (20) is equal to or less than the threshold value. [7] The power conversion device (100) according to claim 5, wherein the control circuit (40) outputs the PWM signal for turning off all the power semiconductors constituting the upper circuit arm and the lower circuit arm of the power conversion circuit (60) or turning on all the power semiconductors constituting the lower circuit arm of the power conversion circuit (60) when the failure determination unit (452) determines that the upper circuit arm has failed. [8] The power conversion device (100) according to any one of claims 1 to 3, wherein, when a difference between the DC current and the first simulated downtime DC current of a specific phase is equal to or less than a specific value, the failure determination unit (452) determines that the lower circuit arm of the phase has failed if the duty cycle of the phase during power operation of the motor (20) is equal to or less than a threshold value or the duty cycle of the phase during regeneration of the motor (20) is equal to or greater than the threshold value. [9] The power conversion device (100) according to claim 8, wherein, when a state in which a difference between the DC current and the first simulated downtime DC current of a specific phase is equal to or less than a specific value continues for a specific period of time or longer, the failure determination unit (452) determines that the lower circuit arm of the phase has failed if the duty ratio of the phase during power operation of the motor (20) is equal to or less than a threshold value or the duty ratio of the phase during regeneration of the motor (20) is equal to or greater than the threshold value. [10] The power conversion device (100) according to claim 8, wherein the control circuit (40) outputs the PWM signal for turning off all the power semiconductors constituting the upper circuit arm and the lower circuit arm of the power conversion circuit (60) or the PWM signal for turning on all the power semiconductors constituting the upper circuit arm of the power conversion circuit (60) when the failure determination unit (452) determines that the lower circuit arm has failed. [11] A method for controlling a power conversion device (100), comprising: Forming a power conversion circuit (60) having an upper circuit branch and a lower circuit branch corresponding to each phase of a motor (20) having a plurality of phases, and converting a DC current into AC currents of the plurality of phases; Outputting a PWM signal to the upper circuit branch and the lower circuit branch; Calculating first simulated downtime DC currents based on AC current values ​​of remaining phases when one of the multiple phases fails, based on the AC currents output from the power conversion circuit (60) and a duty cycle of the PWM signal; and Detecting a failure of the upper circuit branch or the lower circuit branch of any phase based on a DC current input to the power conversion circuit (60) or a DC current based on an AC current value output from the power conversion circuit (60), the duty cycle of the PWM signal, and the first simulated failure time DC current. [12] A method for controlling a power conversion device (100) according to claim 11, wherein a DC current sensor (80) which measures a DC current input to the power conversion circuit (60) is provided, and a failure of the upper circuit branch or the lower circuit branch of any phase is detected based on the DC current measured by the DC current sensor (80). [13] A method for controlling a power conversion device (100) according to claim 11, wherein the DC current is calculated based on the AC current value output from the power conversion circuit (60) and the duty cycle of the PWM signal, and a failure in the upper circuit branch or the lower circuit branch of any phase is detected based on the calculated DC current. [14] A method for controlling a power conversion device (100) according to any one of claims 11 to 13, further comprising: Calculating second simulated downtime DC currents based on all AC current values ​​of the plurality of phases and detecting a failure of the upper circuit branch and the lower circuit branch of any phase based on the first simulated downtime DC current and the second simulated downtime DC current. [15] A method for controlling a power conversion device (100) according to any one of claims 11 to 13, wherein when a difference between the DC current and the first simulated downtime DC current of a specific phase is equal to or less than a specific value, it is determined that the upper circuit arm of the phase has failed if the duty cycle of the phase during power operation of the motor (20) is equal to or greater than a threshold value or the duty cycle of the phase during regeneration of the motor (20) is equal to or less than the threshold value. [16] A method for controlling a power conversion device (100) according to claim 15, wherein when a state in which a difference between the DC current and the first simulated downtime DC current of a specific phase is equal to or less than a specific value continues for a specific period of time or longer, it is determined that the upper circuit arm of the phase has failed if the duty cycle of the phase during power operation of the motor (20) is equal to or greater than a threshold value or the duty cycle of the phase during regeneration of the motor (20) is equal to or less than the threshold value. [17] A method for controlling a power conversion device (100) according to claim 15, wherein the PWM signal for switching off all power semiconductors constituting the upper circuit branch and the lower circuit branch of the power conversion circuit (60) or switching on all power semiconductors constituting the lower circuit branch of the power conversion circuit (60) is output when it is determined that the upper circuit branch has failed. [18] A method for controlling a power conversion device (100) according to any one of claims 11 to 13, wherein when a difference between the DC current and the first simulated downtime DC current of a specific phase is equal to or less than a specific value, it is determined that the lower circuit branch of the phase has failed if the duty cycle of the phase during power operation of the motor (20) is equal to or less than a threshold value or the duty cycle of the phase during regeneration of the motor (20) is equal to or greater than the threshold value. [19] A method for controlling a power conversion device (100) according to claim 18, wherein when a state in which a difference between the DC current and the first simulated downtime DC current of a specific phase is equal to or less than a specific value continues for a specific period of time or longer, it is determined that the lower circuit arm of the phase has failed if the duty cycle of the phase during power operation of the motor (20) is equal to or less than a threshold value or the duty cycle of the phase during regeneration of the motor (20) is equal to or greater than the threshold value. [20] A method for controlling a power conversion device (100) according to claim 18, wherein the PWM signal for turning off all the power semiconductors constituting the upper circuit arm and the lower circuit arm of the power conversion circuit (60) or the PWM signal for turning on all the power semiconductors constituting the upper circuit arm of the power conversion circuit (60) is output when it is determined that the lower circuit arm has failed.

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