Semiconductor device and manufacturing process for it

Abstract

Semiconductor device (100) comprising: a semiconductor element (10) comprising a first insulating layer (15) with an opening section (15a) and a front electrode (12) exposed by the opening section (15a) of the first insulating layer (15); a relay conductor (21) which is bonded to the front electrode (12); a bond layer (41, 42, 43, 44, 45) that bonds the front electrode (12) and the relay conductor (21); a second insulating layer (31, 31a) which covers at least a section of the first insulating layer (15) and is provided in contact with at least one circumference of the bonding layer (41, 42, 43, 44, 45); a conductor connected to the relay conductor (21); and Sealing resin (32) with which a space between the conductor and the second insulating layer (31, 31a) is filled, wherein a gap is provided between a circumferential edge section of the opening section (15a) and the perimeter of the bond layer (41, 42, 43, 44, 45), and the gap is filled with the second insulating layer (31, 31a).

Description

Technical area

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. Technical background

[0002] As a power semiconductor device with a power conversion unit that drives a motor or the like, there is a power semiconductor device having a structure in which a power semiconductor element is sandwiched between a pair of metal plates, and a space between the metal plates is filled with a resin to seal the semiconductor element. Specifically, a metal block is bonded to one electrode of the semiconductor element, the metal block is connected to one metal plate, and the other electrode of the semiconductor element is connected to the other metal plate. Each metal plate is formed to have an area larger than the front and back surfaces of the semiconductor element, and the space between the two metal plates is filled with a resin by a molding method such as a transfer molding method to seal the semiconductor element (see, for example, PTL 1).

[0003] PTL 2 discloses a method for manufacturing a semiconductor device equipped with two or more semiconductor elements.

[0004] PTL 3 discloses a semiconductor device in which a metal film for soldering connection is provided with an electrode on the main surface of a semiconductor substrate.

[0005] PTL 4 discloses a semiconductor device and a manufacturing method thereof.

[0006] PTL 5 discloses a manufacturing method for a semiconductor device. List of citationsPatent literature PTL 1: JP 2011-114176 A PTL 2: JP 2016 - 197 706A PTL 3: JP 2016 - 48 760 A PTL 4: WO 2018 / 173 511 A1 PTL 5: JP 2018 - 32 835 A Summary of the inventionTechnical problem

[0007] A defective portion, such as a void, is likely to be generated in the sealing resin formed by the molding process. In the power semiconductor device, a high voltage is applied to the power semiconductor element. Consequently, an electric field concentrates at the defective portion when the defective portion, such as a void, is located in the sealing resin, and partial discharge may occur. If the partial discharge condition continues, the sealing resin may deteriorate, eventually causing dielectric breakdown and failure in the power semiconductor device. Solution to the problem

[0008] According to a first aspect of the present invention, a semiconductor device includes a semiconductor element including a first insulating layer having an opening portion and a front electrode exposed from the opening portion of the first insulating layer, a relay conductor bonded to the front electrode, a bonding layer bonding the front electrode and the relay conductor, a second insulating layer covering at least a portion of the first insulating layer and provided in contact with at least a periphery of the bonding layer, a conductor connected to the relay conductor, and a sealing resin filling a space between the conductor and the second insulating layer. A gap is provided between a peripheral edge portion of the opening portion and the periphery of the bonding layer, and the gap is filled with the second insulating layer.

[0009] According to a second aspect of the present invention, a semiconductor device includes a plurality of semiconductor elements, each including a first insulating layer having an opening portion and a front electrode exposed from the opening portion of the first insulating layer, a relay conductor bonded to the front electrode of each of the semiconductor elements, a bonding layer bonding the front electrode and the relay conductor, a second insulating layer covering at least a portion of the first insulating layer and provided in contact with at least a periphery of the bonding layer, and a conductor connecting the relay conductor. A gap is provided between a peripheral edge portion of the opening portion and the periphery of the bonding layer, and the gap is filled with the second insulating layer.

[0010] According to a third aspect of the present invention, a manufacturing method of a semiconductor device includes manufacturing a semiconductor element including a first insulating layer having an opening portion and a front electrode exposed from the opening portion of the first insulating layer, bonding the front electrode and the relay conductor through a bonding layer, providing a second insulating layer covering at least a portion of the first insulating layer and in contact with at least a periphery of the bonding layer, connecting a conductor to the relay conductor, and filling a space between the conductor and the second insulating layer with a sealing resin. A gap is provided between a peripheral edge portion of the opening portion and the periphery of the bonding layer, and the gap is filled with the second insulating layer. Advantageous effects of the invention

[0011] According to the present invention, occurrence of partial discharges is suppressed even if a cavity is present. Brief description of the drawings Fig. 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment of the present invention. Fig. 2(A) and Fig. 2(B) are cross-sectional views showing the semiconductor device in the respective steps for explaining a Fig. 1 illustrate the manufacturing method of a semiconductor device 100. Fig. 3A and Fig. 3B are cross-sectional views showing the semiconductor device in the respective steps subsequent to the steps in Fig. 2 illustrate. Fig. 4 is a cross-sectional view illustrating a semiconductor device according to a second embodiment of the present invention. Fig. Fig. 5 is a cross-sectional view for explaining a process in which a strong electric field is applied to a cavity in a sealing resin and consequently a partial discharge occurs, wherein Fig. 5(A) is a cross-sectional view illustrating a semiconductor device 100R in a comparative example, and Fig. 5(B) is a cross-sectional view illustrating the semiconductor device in the present embodiment. Fig. 6 is an exploded perspective view illustrating a semiconductor device according to a third embodiment of the present invention. Fig. 7 is an enlarged exploded perspective view showing the Fig. 6 illustrated semiconductor device. Fig. 8 is a cross-sectional view showing the Fig. 6 illustrated semiconductor device, wherein Fig. 8(A) is a cross-sectional view before resin sealing and Fig. 8(B) is a cross-sectional view after resin sealing. Description of the embodiments

[0012] Embodiments of the present invention will be described below with reference to the drawings. The following description and the drawings are examples for describing the present invention and are omitted and simplified as appropriate for clarity of description. The present invention may be embodied in various other forms. Unless otherwise specified, each component may be present in the singular or plural.

[0013] The positions, sizes, shapes, areas, and the like of the components illustrated in the drawings may not represent the actual positions, sizes, shapes, areas, and the like in order to facilitate understanding of the invention. Therefore, the present invention is not necessarily limited to the positions, sizes, shapes, areas, etc. illustrated in the drawings. -First embodiment-

[0014] In the following, a first embodiment of the present invention will be described with respect to the Fig. 1 to 3.

[0015] Fig. 1 is a cross-sectional view illustrating a semiconductor device according to the first embodiment of the present invention.

[0016] A semiconductor device 100 includes a semiconductor element 10. The semiconductor element 10 is, for example, a SiC (silicon carbide) metal oxide semiconductor field-effect transistor (MOSFET). The semiconductor element 10 includes a semiconductor substrate 11, a source electrode 12, a drain electrode 13, an internal wiring 14, and a first insulating layer 15. Although this is Fig. 1 is not illustrated, the semiconductor element 10 includes a gate electrode 17 (see Fig. 7). The semiconductor device 100 includes the semiconductor element 10, a relay conductor 21, a front surface conductor 22, a back surface conductor 23, a second insulating layer 31, and a sealing resin 32.

[0017] The first insulating layer 15 is an insulating film provided to protect the internal wiring 14 and an impurity region for forming a semiconductor element formed in the semiconductor substrate 11. The first insulating layer 15 is formed of an inorganic material such as silicon oxide or silicon nitride. The first insulating layer 15 is provided with an opening portion 15a (see also Fig. 2(B)). The source electrode 12 is formed to be slightly larger than the opening portion 15a of the first insulating layer 15. The inner side of the peripheral edge portion of the source electrode 12 is exposed from the opening portion 15a of the first insulating layer 15. The first insulating layer 15 is formed of, for example, a resin such as polyimide or polybenzoxazole. The first insulating layer 15 is manufactured by a semiconductor element manufacturer and generally has a thickness of about several μm.

[0018] The relay conductor 21 has an area slightly smaller than the opening portion 15a of the first insulating layer 15. The relay conductor 21 is bonded to the entire surface of a portion of the source electrode 12 exposed from the opening portion 15a of the first insulating layer 15 through the bonding layer 41. The bonding layer 41 has substantially the same area as the relay conductor 21. Consequently, a gap G (see Fig. 2(B)) is formed between the peripheral edge portion of the bonding layer 41 and the peripheral edge portion of the opening portion 15a of the first insulating layer 15. The relay conductor 21 may be formed of a copper-based metal. Additionally, the relay conductor 21 may be formed using a plated material such as CIC (Copper-Invar-Copper). Invar (registered trademark) is an alloy of iron and nickel and is a material with a low thermal expansion coefficient. Consequently, by forming the relay conductor 21 of a material containing Invar, it is possible to suppress peeling of the semiconductor element 10 from the sealing resin 32 even when the temperature of the semiconductor element 10 becomes high during operation.

[0019] The second insulating layer 31 is formed on the first insulating layer 15. The second insulating layer 31 is not formed on the entire surface of the first insulating layer 15. The peripheral edge portion side of the first insulating layer 15 is exposed from the second insulating layer 31. The gap G between the peripheral edge portion of the bonding layer 41 and the peripheral edge portion of the opening portion 15a of the first insulating layer 15 is also filled with the second insulating layer 31. The second insulating layer 31 is in contact with the peripheral edge portion of the bonding layer 41 and the peripheral edge portion of a portion of the relay conductor 21 close to the bonding layer 41 side. As described later, the second insulating layer 31 is formed by coating using a molding method, a printing method, or the like. The second insulating layer 31 is made of, for example, a resin such asPolyamideimide, polyimide, polyetheramideimide, or polyetheramide. The first insulating layer 15 and the second insulating layer 31 can be formed from the same resin. The thickness of the second insulating layer 31 is approximately several tens of µm and is preferably thicker than the thickness of the first insulating layer 15.

[0020] The front surface conductor 22 has a front surface area of ​​the semiconductor element 10, i.e., an area that is larger in plan view than the area of ​​the first insulating layer 15. The front surface conductor 22 is bonded to the relay conductor 21 by a bonding layer 42. The bonding layer 42 has substantially the same area as the relay conductor 21. The front surface conductor 22 can be formed from a copper-based metal or an aluminum-based metal.

[0021] The back surface conductor 23 is bonded to the drain electrode 13 provided on the back side of the semiconductor substrate 11 so as to face the source electrode 12 through a bonding layer 43. The back surface conductor 23 has the same area as the front surface conductor 22. A space between the front surface conductor 22 and the back surface conductor 23 is filled with the sealing resin 32. That is, the peripheral side surface of the semiconductor element 10, the second insulating layer 31, and the peripheral side surface of the relay conductor 21 are sealed with the sealing resin 32. The back surface conductor 23 can be made of a copper-based metal or an aluminum-based metal.

[0022] A solder or a sintered metal material can be used for the bonding layers 41 to 43.

[0023] An epoxy resin or the like can be used as the sealing resin 32. For sealing with the sealing resin 32, a molding method such as transfer molding is suitable, but a potting method or a printing method such as silkscreen printing, seal printing, inkjet printing, or thermal transfer printing can also be used.

[0024] Next, a process for suppressing the deterioration of the sealing resin due to the presence of a void in the semiconductor device 100 according to the above embodiment will be described.

[0025] Fig. 5 is a cross-sectional view for explaining a process in which a strong electric field is applied to a cavity in the sealing resin and consequently a partial discharge occurs. Fig. 5(A) is a cross-sectional view illustrating a cavity created in the sealing resin of a semiconductor device 100R in a comparative example. Fig. 5(B) is a cross-sectional view illustrating a cavity created in the sealing resin of the semiconductor device 100 in the present embodiment.

[0026] The semiconductor device 100R in the Fig. The comparative example illustrated in Fig. 5(A) does not include the relay conductor 21 of the semiconductor device 100 in the present embodiment.

[0027] In the semiconductor device 100R, a front surface conductor 22R has a protrusion 25 facing a portion of the source electrode 12 exposed from the opening portion 15a of the first insulating layer 15. The protrusion 25 is integrally formed with the front surface conductor 22R. That is, after the protrusion 25 and the source electrode 12 are bonded to each other by the bonding layer 41, the peripheral region of the gap G between the inner peripheral edge of the opening portion 15a of the first insulating layer 15 and the bonding layer 41 is covered by the front surface conductor 22R via the sealing resin 32.

[0028] Therefore, if a second insulating layer 31R is applied to the first insulating layer 15 before filling a space between the front surface conductor 22R and the back surface conductor 23 with the sealing resin 32, the front surface conductor 22R becomes an obstacle, making it difficult to form the second insulating layer 31R in contact with the peripheral edge portion of the bonding layer 41 and the peripheral edge portion of the protrusion 25. That is, the gap G between the inner peripheral edge portion of the opening portion 15a of the first insulating layer 15 and the bonding layer 41 is not covered by either the first insulating layer 15 or the second insulating layer 31R.

[0029] If in Fig. 5(A) , the second insulating layer 31R is filled before the front surface conductor 22R is bonded to the source electrode 12, it is necessary to perform a process for preventing the second insulating layer 31R from entering a region where the front surface conductor 22R is bonded to the source electrode 12 (the second insulating layer 31R into a region bonded to the front surface conductor). In addition, in this step, it is necessary to provide a small gap G between the region of the source electrode 12 bonded to the front surface conductor and the inner peripheral edge portion of the opening portion 15a of the first insulating layer 15. It is not possible to sufficiently fill the small gap G with an insulating material, and it is not possible to prevent deterioration of the sealing resin due to a strong electric field of a cavity A. V to avoid.

[0030] In a MOSFET or the like, a strong electric field is generated around the source electrode 12. In particular, in a SiC MOSFET, a strong electric field is generated with a dielectric breakdown field strength that is about 10 times that of the Si MOSFET. When it fills the cavity A V in the sealing resin 32 around the source electrode 12, a strong electric field can be generated in the cavity A V concentrate, whereby a partial discharge may occur. If the condition in which the partial discharge occurs continues, the sealing resin 32 deteriorates, eventually causing dielectric breakdown and consequently failure of the semiconductor element 10.

[0031] In particular, it is difficult to fill a narrow space where the protrusion 25 is bonded to the source electrode 12 with the sealing resin by the molding process. Consequently, the probability that the cavity A Voccurs, high.

[0032] As in Fig. As illustrated in Fig. 5(B), the semiconductor device 100 in the present embodiment includes the relay conductor 21 provided between the source electrode 12 and the front surface conductor 22. Therefore, the gap G between the peripheral edge of the first insulating layer 15 and the bonding layer 41 can be filled with the second insulating layer 31 before the front surface conductor 22 is bonded to the relay conductor 21 in a state where the relay conductor 21 is bonded to the source electrode 12 through the bonding layer 41. When there is the cavity A V in the sealing resin 32 in a state in which the gap G between the peripheral edge portion of the first insulating layer 15 and the bonding layer 41 is covered by the second insulating layer 31, a strong electric field generated around the source electrode 12 is converted into a field directed to the cavity A Vapplied voltage and a voltage applied to the second insulating layer 31.

[0033] The cavity A V , which is an air layer, applied voltage is based on the relative dielectric constant of the second insulating layer 31 with respect to the dielectric constant of the air layer and the relationship between the thickness of the cavity A V and the thickness of the second insulating layer 31. When the thickness of the second insulating layer 31 increases and the thickness of the cavity A V decreases, the pressure in the cavity A V concentrated stress. Therefore, by setting a thickness of the second insulating layer 31 equal to or greater than a predetermined thickness, it is possible to apply the voltage applied to the cavity A Vapplied voltage so that it is smaller than a partial discharge starting voltage. Consequently, it is possible to suppress the occurrence of a partial discharge even if the cavity A V in the sealing resin 32 when the second insulating layer 31 is formed to have a predetermined thickness or more, and then the front surface conductor 22 is bonded to the relay conductor 21 through the bonding layer 42 and the space between the front surface conductor 22 and the back surface conductor 23 is filled with the sealing resin 32.

[0034] Next, a manufacturing method for the semiconductor device 100 will be described.

[0035] The Fig. 2(A) and Fig. 2(B) are cross-sectional views illustrating the semiconductor device in the respective steps for explaining the Fig. 1 illustrated manufacturing method of the semiconductor device 100. The Fig. 3(A) and Fig. 3(B) are cross-sectional views showing the semiconductor device in the respective steps subsequent to the steps in Fig. 2 illustrate.

[0036] First, the semiconductor element 10 is prepared. As described above, the semiconductor element 10 includes the semiconductor substrate 11, the source electrode 12, the drain electrode 13, the internal wiring 14, and the first insulating layer 15.

[0037] Then, as in Fig. As illustrated in Fig. 2(A), the drain electrode 13 of the semiconductor element 10 and the back surface conductor 23 are bonded to each other by the bonding layer 43. As described above, a solder or a sintered metal material can be used for the bonding layer 43. The sintered metal material has a powder or paste form and becomes a sintered metal by heating. A sintered metal bonding paste containing copper or silver is preferably used as the sintered metal material. Bonding is performed by interposing the bonding layer 43 between the drain electrode 13 of the semiconductor element 10 and the back surface conductor 23, and performing thermocompression bonding.

[0038] Then, as in Fig. As illustrated in Fig. 2(B), the source electrode 12 of the semiconductor element 10 and the relay conductor 21 are bonded to each other by the bonding layer 41. A material similar to the bonding layer 43 is used as the bonding layer 41.

[0039] The bonding is performed by interposing the bonding layer 41 between the source electrode 12 of the semiconductor element 10 and the relay conductor 21, and performing thermocompression bonding. The bonding layer 41, which bonds the source electrode 12 of the semiconductor element 10 and the relay conductor 21, is provided in the opening portion 15a of the first insulating layer 15 of the semiconductor element 10. That is, the bonding layer 41 is smaller than the opening portion 15a of the first insulating layer 15 of the semiconductor element 10. Therefore, a gap G is formed between the peripheral edge portion of the first insulating layer 15 and the bonding layer 41.

[0040] The process after Fig. 2(A) and the process according to Fig. 2(B) can be reversed. Additionally, the processes can be performed in the same operating cycle. In a case of performing the same process, the bonding layer 43 is interposed between the drain electrode 13 of the semiconductor element 10 and the back surface conductor 23, while the bonding layer 41 is interposed between the source electrode 12 of the semiconductor element 10 and the relay conductor 21. In this state, the entire assembly is thermocompression bonded.

[0041] Then, as in Fig. 3(A), the second insulating layer 31 is applied to the first insulating layer 15. The gap G (see Fig. 2(B)) between the peripheral edge portion of the bonding layer 41 and the peripheral edge portion of the opening portion 15a of the first insulating layer 15 is filled with the second insulating layer 31 so as to be in contact with the peripheral edge portion of the bonding layer 41. The second insulating layer 31 may be provided so as to be in contact with the lower end portion side of the relay conductor 21, in other words, with the peripheral edge portion of the relay conductor 21 on the bonding layer 41 side. The second insulating layer 31 may be formed using a molding method using a dispenser or a printing method. As the printing method, silk printing, seal printing, inkjet printing, thermal transfer printing, and the like can be used.

[0042] Then, as in Fig. As illustrated in Fig. 3(B), the front surface conductor 22 is bonded to the relay conductor 21 through the bonding layer 42. A material similar to the bonding layers 41 and 43 is used as the bonding layer 42. The bonding is performed by interposing the bonding layer 42 between the relay conductor 21 and the front surface conductor 22, and performing thermocompression bonding.

[0043] Then, a space between the front surface conductor 22 and the rear surface conductor 23 is filled with the sealing resin 32. Consequently, the Fig. 1 is formed, in which the peripheral side surface of the semiconductor element 10, the second insulating layer 31, and the peripheral side surface of the relay conductor 21 are sealed with the sealing resin 32. As described above, the transfer molding method is suitable for forming the sealing resin 32, but a molding method or a printing method may be used.

[0044] According to the first embodiment, the effects are obtained as follows. (1) A semiconductor device 100 includes: a semiconductor element 15 including a first insulating layer 15 having an opening portion 10a and a source electrode (front electrode) 12 exposed from the opening portion 15a of the first insulating layer 15; a relay conductor 21 bonded to the source electrode 12; a bonding layer 41 bonding the source electrode 12 and the relay conductor 21; a second insulating layer 31 covering at least a portion of the first insulating layer 15 and provided in contact with at least a periphery of the bonding layer 41; a front surface conductor (conductor) 22 connected to the relay conductor 21; and a sealing resin 32 with which a space between the front surface conductor 22 and the second insulating layer 31 is filled.As described above, the source electrode 12 exposed from the opening portion 15a of the first insulating layer 15 is covered by the second insulating layer 31 provided in contact with the periphery of the bonding layer 41. Therefore, it is possible to suppress the occurrence of partial discharge and suppress the deterioration of the sealing resin 32 even when it covers the cavity A. V in the sealing resin 32. -Second embodiment-

[0045] Fig. 4 is a cross-sectional view illustrating a semiconductor device according to a second embodiment of the present invention.

[0046] A semiconductor device 100 according to the second embodiment has a structure in which a second insulating layer 31a extends on the outer peripheral side surface of a semiconductor element 10 and is in contact with a back surface conductor 23.

[0047] In the first embodiment, the second insulating layer 31 is formed only on the front surface side of the semiconductor element 10 and does not extend to contact the back surface conductor 23. With such a structure, there is a possibility that when the front surface conductor 22 is bonded to the relay conductor 21 through the bonding layer 42, the bonding layer 41 is melted by heating during thermocompression bonding, and the relay conductor 21 becomes misaligned. In the second embodiment, the second insulating layer 31a extends to a position in contact with the back surface conductor 23.Because the second insulating layer 31a is in contact with the relay conductor 21, the movement of the relay conductor 21 is restricted by the second insulating layer 31a being in contact with the back surface conductor 23 even if the bonding layer 41 is melted by heating during thermocompression bonding.

[0048] The other components in the second embodiment are similar to those in the first embodiment. The corresponding components are denoted by the same reference numerals, and their descriptions will not be repeated.

[0049] In addition, in the second embodiment, similar effects to those of the first embodiment are obtained.

[0050] Further, according to the second embodiment, it is possible to suppress misalignment of the relay conductor 21 when the front surface conductor 22 is bonded to the relay conductor 21. - Third embodiment-

[0051] A third embodiment of the present invention is described with respect to the Fig. 6 to 8 described.

[0052] Fig. 6 is an exploded perspective view illustrating a semiconductor device according to the third embodiment of the present invention.

[0053] A semiconductor device 200 includes four semiconductor devices 300, an outer front-side surface conductor 222, and an outer back-side surface conductor 223. The four semiconductor devices 300 are arranged so that they are spaced apart from each other in a matrix of two rows in a left-right direction and two columns in an up-down direction. The outer front-side surface conductor 222 and the outer back-side surface conductor 223 each have a size that covers the entire area of ​​the four semiconductor devices 300 arranged in a matrix. All four semiconductor devices 300 have the same structure.

[0054] Each of the two semiconductor devices 300 has an upper arm circuit. Each of the remaining two semiconductor devices 300 has a lower arm circuit. The semiconductor device 300 having the upper arm circuit and the semiconductor device 300 having the lower arm circuit are connected in series to form a series circuit of the upper and lower arms. A power conversion device in which AC outputs with different phases are obtained from the connection portion between the upper arm circuit and the lower arm circuit can be formed.

[0055] Fig. 7 is an enlarged exploded perspective view showing the Fig. 6 illustrated semiconductor device. Fig. 8 is a cross-sectional view showing the Fig. 6 illustrated semiconductor device. Fig. 8(A) is a cross-sectional view before resin sealing, and Fig. 8(B) is a cross-sectional view after resin sealing.

[0056] The semiconductor device 300 includes four semiconductor elements 10, a front-side surface conductor 122, and a back-side surface conductor 123. The four semiconductor elements 10 are arranged so that they are spaced apart from each other in a matrix of two rows in the left-right direction and two columns in the up-down direction. That is, the semiconductor device 300 is configured as a 4-in-1 package. Each of the front-side surface conductor 122 and the back-side surface conductor 123 has a size that covers the entire area of ​​the four semiconductor elements 10 arranged in a matrix.

[0057] All four semiconductor elements 10 have the same structure as the semiconductor element in the first embodiment. That is, the semiconductor element 10 includes the semiconductor substrate 11, the source electrode 12, the drain electrode 13, the internal wiring 14, and the first insulating layer 15, as shown in Fig. 8. As shown in Fig. As illustrated in Fig. 8, the relay conductor 21 is bonded to the source electrode 12 of each semiconductor element 10 via the bonding layer 41. The second insulating layer 31, which is in contact with the peripheral edge portion of the bonding layer 41 and the peripheral edge portion of a region of the relay conductor 21 close to the bonding layer 41 side, is formed on the first insulating layer 15 of each semiconductor element 10.

[0058] As in Fig. As illustrated in Figure 7, the front surface conductor 122 includes a rectangular main body covering the four semiconductor elements 10, and a sensing connection portion 131 at a tip of a leg portion extending from each of the four corner portions of the rectangular main body. The sensing connection portion 131 protrudes toward the back surface conductor 123. The sensing connection portion 131 has a quadrangular prism shape and a cross-sectional area larger than a bonding wire. The reason why the sensing connection portion 131 has a large cross-sectional area is to ensure strength that can withstand a load acting on the front surface conductor 122 and the back surface conductor 123 and to reduce inductance.

[0059] The back surface conductor 123 is a member corresponding to the back surface conductor 23 in the first embodiment. In the third embodiment, the back surface conductor 123 has a size in which the four semiconductor elements 10 are bonded via the bonding layer 43. In the back surface conductor 123, an insulating layer 151 is provided on the entire surface except for a region where the four semiconductor elements 10 are bonded. A resin or a ceramic can be used for the insulating layer 151.

[0060] A gate wiring 152 and a scanning wiring 153 are provided on the insulating layer 151 formed on the back surface conductor 123. The gate wiring 152 and the scanning wiring 153 are connected to a control unit (not shown).

[0061] The control unit (not shown) applies a voltage to the source electrode 12 of the semiconductor element 10 via the gate wiring 152 connected to the source electrode 12 of the semiconductor element 10 via the sensing wiring 153 as the ground, that is, a reference potential. Reducing the inductance is exemplified as the reason for increasing the cross-sectional area of ​​the sensing connection portion 131. To be more specific, the reason is to reduce the inductance in a connection with the source electrode 12 of the semiconductor element 10 via the sensing wiring 153.

[0062] In Fig. 7, the gate wiring 152 is formed on the insulating layer 151 provided on the back surface conductor 123 between two pairs of semiconductor elements 10 separated into the left and right semiconductor elements, in other words, midway between the left and right sides of the back surface conductor 123, so as to extend in the up-down direction of the back surface conductor 123. The gate electrode 17 of each semiconductor element 10 is connected to the gate wiring 152 via a bonding wire 161. The scanning wiring 153 is formed to surround the outside of the gate wiring 152 with a small gap from the gate wiring 152.The scanning wiring 153 has a portion extending in the up-down direction of the back surface conductor 123 and a portion extending near the corner portion of the back surface conductor 123 along the side surface on the top side and the side surface on the bottom side of the back surface conductor 123.

[0063] The scanning wiring 153 has a scanning contact area 153a to which the lower end surface of the scanning connection portion 131 of the front surface conductor 122 is bonded. The scanning contact area 153a is provided near each corner portion. The scanning contact area 153a is a portion of the scanning wiring 153. In practice, there is no dividing line indicating the area, but in Fig. 7, the scanning contact area 153a is illustrated by a rectangular solid line for easy understanding. The front surface conductor 122 is bonded to the source electrode 12 of each semiconductor element 10 through the bonding layer 42 (see the Fig. 8(a) and Fig. 8(b)). Consequently, the scanning wiring 153 is connected to the source electrode 12 of each semiconductor element 10 via the front surface conductor 122.

[0064] When the four semiconductor elements 10 are arranged close to each other, the heat emitted by each semiconductor element 10 is concentrated in a narrow area, and the back surface conductor 123 has a high temperature. Therefore, as shown in Fig. 7, the four semiconductor elements 10 are arranged to be spaced apart from each other by a predetermined width or more to prevent heat concentration. However, when the semiconductor elements 10 are arranged to be spaced apart from each other by the predetermined width or more, the area of ​​the back surface conductor 123, in other words, the area of ​​the semiconductor device 300, increases. Consequently, by routing the gate wiring 152 and the scanning wiring 153 to a central space where the semiconductor elements 10 are spaced apart from each other, the space is effectively utilized, and the area of ​​the back surface conductor 123 is reduced.

[0065] As in the Fig. 7 and Fig. As illustrated in FIG. 8, the sensing contact area 153a, to which the lower end surface of the sensing connection portion 131 of the front-side surface conductor 122 is bonded, is arranged outside a rectangular outer peripheral area in which the four semiconductor elements 10 are arranged. Therefore, it is possible to reduce the inductance associated with the source electrode 12 of the semiconductor element 10 via the sensing wiring 153.

[0066] As in Fig. 8(a), the four semiconductor devices 300 that form the Fig. 6, arranged between the outer front surface conductor 222 and the outer back surface conductor 223.

[0067] The front surface conductor 122 of each semiconductor device 300 is bonded to the outer front surface conductor 222 by a bonding layer 44. The back surface conductor 123 of each semiconductor device 300 is bonded to the outer back surface conductor 223 by a bonding layer 45. The bonding layers 44 and 45 can be formed using the same material as the bonding layers 41 to 43.

[0068] The Fig. The state illustrated in FIG. 8(a) is a state in which the four semiconductor devices 300 constituting the semiconductor device 200 are not filled with the sealing resin 32. That is, each semiconductor element 10, the second insulating layer 31, and the like are not sealed with the sealing resin 32. However, the second insulating layer 31, which is in contact with the peripheral edge portion of the bonding layer 41 and the peripheral edge portion of a portion of the relay conductor 21 close to the bonding layer 41 side, is formed on the first insulating layer 15 of each semiconductor element 10. Therefore, in this state, it is possible to perform a strong electric field application test for applying a strong electric field to the source electrode 12.By applying a strong electric field to the source electrode 12, it is possible to check whether a partial discharge is occurring, whether the semiconductor element 10 is damaged, or whether its properties are deteriorated, and to remove or repair a defective product. Consequently, it is possible to improve productivity compared to a case where testing is performed after resin sealing.

[0069] After the test of applying a strong electric field, a space between the outer front surface conductor 222 and the outer rear surface conductor 223 is filled with the sealing resin 32, thus sealing the peripheral side surface of each semiconductor element 10, the second insulating layer 31, and the peripheral side surface of the relay conductor 21 with the sealing resin 32. Consequently, it is possible to Fig. 8(b) to form semiconductor device 200.

[0070] The test of applying a strong electric field can be carried out in the state in Fig. 8(b) or may be executed in the state in Fig. 8(a) and then again in the state in Fig. 8(b).

[0071] In the third embodiment, the structure in which the scanning wiring 153 and the source electrode 12 are connected by the scanning connection portion 131 integrally provided with the front surface conductor 122 has been described as an example. However, the scanning wiring 153 and the source electrode 12 may be connected by a bonding wire.

[0072] In the third embodiment, an example was described in which the semiconductor device 300 is a 4-in-1 package in which four branch circuits are integrated. However, the semiconductor device 300 only needs to be a package in which multiple branch circuits are integrated and can be widely applied to an N-in-1 package (N ≥ 2).

[0073] In the above embodiments, an example in which a MOSFET is used as a switching element has been described.

[0074] However, other semiconductor elements, such as an insulated gate bipolar transistor (IGBT), can be used instead of the MOSFET.

[0075] In the above embodiments, a SiC (silicon carbide) MOSFET is preferred as the switching element. However, the present invention can also be applied to a semiconductor element containing gallium nitride, gallium oxide, or diamond as a base material in addition to silicon carbide. The present invention can also be applied to a conventional Si MOSFET.

[0076] Although various embodiments and modifications have been described above, the present invention is not limited to these contents. Other embodiments considered within the scope of the technical idea of ​​the present invention are also included within the scope of the present invention. List of reference symbols 10 semiconductor element 12 Source electrode (front electrode) 13 Drain electrode (back electrode) 15 first insulation layer 15a Opening section 21 relay conductors 22 front surface conductors (conductors) 23 Rear surface conductor (facing conductor) 31, 31a second insulating layer 32 Sealing resin 41 to 45 bond layer 100 semiconductor devices 122 Front surface conductors (conductors) 123 Rear surface conductors 200 semiconductor devices 222 outer front surface conductor (outer conductor) 223 outer rear surface conductor 300 semiconductor devices A V cavity G gap

Claims

[1] A semiconductor device (100) comprising: a semiconductor element (10) including a first insulating layer (15) having an opening portion (15a) and a front electrode (12) exposed from the opening portion (15a) of the first insulating layer (15); a relay conductor (21) bonded to the front electrode (12); a bonding layer (41, 42, 43, 44, 45) bonding the front electrode (12) and the relay conductor (21); a second insulating layer (31, 31a) covering at least a portion of the first insulating layer (15) and provided in contact with at least a periphery of the bonding layer (41, 42, 43, 44, 45); a conductor connected to the relay conductor (21); and Sealing resin (32) with which a space between the conductor and the second insulating layer (31, 31a) is filled, wherein a gap is provided between a peripheral edge portion of the opening portion (15a) and the periphery of the bonding layer (41, 42, 43, 44, 45), and the gap is filled with the second insulating layer (31, 31a). [2] The semiconductor device (100) according to claim 1, wherein the second insulating layer (31, 31a) is in contact with a periphery of the relay conductor (21) on at least the side of the bonding layer (41, 42, 43, 44, 45). [3] The semiconductor device (100) according to claim 1, further comprising a bonding layer (41, 42, 43, 44, 45) that bonds the conductor and the relay conductor (21). [4] A semiconductor device according to claim 1, wherein the conductor has a surface covering an entirety of the first insulating layer (15) of the semiconductor element (10), and the sealing resin (32) seals a periphery of the semiconductor element (10). [5] A semiconductor device according to claim 1, wherein the second insulating layer (31, 31a) is provided to be thicker than the first insulating layer (15). [6] The semiconductor device (100) according to claim 1, wherein the relay conductor (21) contains Invar. [7] The semiconductor device (100) according to claim 1, wherein the bonding layer (41, 42, 43, 44, 45) is a sintered metal obtained by sintering a metal bonding paste. [8] A semiconductor device according to claim 1, wherein the semiconductor element (10) contains a back electrode on a side facing the front electrode (12), the semiconductor device (100) further comprises a facing conductor connected to the back electrode, and the second insulating layer (31, 31a) is in contact with the facing conductor. [9] The semiconductor device (100) according to any one of claims 1 to 8, wherein the semiconductor element (10) contains one of silicon carbide, gallium nitride, gallium oxide and diamond as a base material. [10] A semiconductor device (100) comprising: a plurality of semiconductor elements (10) each including a first insulating layer (15) having an opening portion (15a) and a front electrode (12) exposed from the opening portion (15a) of the first insulating layer (15); a relay conductor (21) bonded to the front electrode (12) of each of the semiconductor elements (10); a bonding layer (41, 42, 43, 44, 45) bonding the front electrode (12) and the relay conductor (21); a second insulating layer covering at least a portion of the first insulating layer (15) and provided in contact with at least a periphery of the bonding layer (41, 42, 43, 44, 45); and a conductor connecting the relay conductor (21), wherein a gap is provided between a peripheral edge portion of the opening portion (15a) and the periphery of the bonding layer (41, 42, 43, 44, 45), and the gap is filled with the second insulating layer (31, 31a). [11] The semiconductor device (100) according to claim 10, further comprising a sealing resin (32) with which a space between the conductor and the second insulating layer (31, 31a) is filled. [12] A semiconductor device (100) comprising: a plurality of the semiconductor devices (100) according to claim 10; and an outer conductor connecting the conductors of the semiconductor devices (100). [13] A manufacturing method of a semiconductor device (100), the manufacturing method comprising: Producing a semiconductor element (10) including a first insulating layer (15) having an opening portion (15a) and a front electrode (12) exposed from the opening portion (15a) of the first insulating layer (15); Bonding the front electrode (12) and a relay conductor (21) through a bonding layer (41, 42, 43, 44, 45); Providing a second insulating layer covering at least a portion of the first insulating layer (15) and in contact with at least a periphery of the bonding layer (41, 42, 43, 44, 45); Connecting a conductor to the relay conductor (21); and Filling a space between the conductor and the second insulating layer (31, 31a) with a sealing resin (32), wherein a gap is provided between a peripheral edge portion of the opening portion (15a) and the periphery of the bonding layer (41, 42, 43, 44, 45), and the gap is filled with the second insulating layer (31, 31a).

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