Semiconductor device and method for manufacturing a semiconductor device

Abstract

Semiconductor device comprising: a gate electrode (20); a semiconductor layer (50) including a source region (50S) and a drain region (50D), the gate electrode (20) being provided therebetween along a lateral direction (X); Contact plugs (60S, 60D) provided on the source region (50S) and the drain region (50D); first metals (M1) stacked on the respective contact plugs (60S, 60D); a first low-permittivity region (70) provided in at least one region located between the first metals (M1) in a direction in the plane of the semiconductor layer (50) and below a lower surface of the first metal (M1) in a stacking direction (Z) of the semiconductor layer (50), wherein the first region (70) is arranged in direct extension along the stacking direction (Z) of the semiconductor layer (50) with respect to a center of the gate electrode (20) along the lateral direction (X); and a second low-permittivity region (71) provided in at least one region located between the contact plugs (60S, 60D) and having the surface orientation of the plane of the semiconductor layer (50) and, starting from the semiconductor layer (50), in the stacking direction below the first low-permittivity region (70), wherein the second low permittivity region (71) is provided, in plan view, in a planar region that is at least partially different from a planar region provided with the first low permittivity region (70), and wherein a width (W70) of the first region (70) is smaller than a width of the second region (71).

Description

TECHNICAL FIELDThe present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device.BACKGROUND ARTThe front end of mobile communication terminals such as mobile phones is equipped with a radio frequency switch (RF-SW) that processes radio frequency (RF) electrical signals.In such a high-frequency switch, in order to reduce the loss of electric signals passing therethrough, it is desired that a resistance (also referred to as on-resistance) of a field effect transistor (FET) in an on-state and a capacitance (also referred to as off-capacitance) of the FET in an off-state are reduced. That is, in the high-frequency switch, it is desired that the product of the on-resistance and the off-capacitance (Ron*Coff) is reduced, and various studies have been made (e.g., JP 2015-207 640 A).Exemplary high-frequency switches are known from the publications U.S. Pat. No. 2016 / 0 141 240 A1, DE 10 2017 207 873 and U.S. Pat. No. 2012 / 0 037 962 A1.SUMMARY OF THE INVENTIONTherefore, in a semiconductor device such as a field effect transistor to be used in a high frequency switch, it is desirable that the product of on-resistance and off-capacitance is reduced.Therefore, it is desirable to provide a semiconductor device that enables to further reduce the off-capacitance and a method of manufacturing the semiconductor device.The invention is defined in the independent claims. Further developments are the subject matter of the dependent patent claims.BRIEF DESCRIPTION OF THE DRAWINGS[FIG. 1 ] FIG. 1 is a schematic diagram illustrating a configuration of a high-frequency switch in which the number of input / output terminals is one to ten.[FIG. 2 ] FIG. 2 is a schematic diagram illustrating a configuration of a high-frequency switch in which the number of input / output terminals is one to one.[FIG. 3] FIG. 3 is a circuit diagram illustrating an equivalent circuit of the high-frequency switch illustrated in FIG. 2.[FIG. 4] FIG. 4 is a circuit diagram illustrating the equivalent circuit diagram in a case where the high-frequency switch illustrated in FIG. 2 is in an on state.[FIG. 5 ] FIG. 5 is a circuit diagram illustrating the equivalent circuit diagram in a case where the high-frequency switch illustrated in FIG. 2 is in an off state.[FIG. 6 ] FIG. 6 is a plan view of an overall configuration of a semiconductor device according to a first embodiment of the present disclosure.[FIG. 7 ] FIG. 7 is a longitudinal cross-sectional view of a cross-sectional configuration, taken along a line VII-VII in FIG. 6, of the semiconductor device according to the embodiment.[FIG. 8] FIG. 8 is a schematic longitudinal cross-sectional view of an element-divided off capacitance of a typical field effect transistor.[FIG. 9] FIG. 9 is a longitudinal cross-sectional view of a stacked structure of a semiconductor device according to a comparative example.[FIG. 10] FIG. 10 is a graph illustrating results of simulation of the extrinsic component sizes Cex of the semiconductor device illustrated in FIG. 7 and the semiconductor device illustrated in FIG. 9 according to the comparative example.[FIG. 11 ] FIG. 11 is a schematic diagram illustrating the positional relationship in a Z stacking direction between a first low-permittivity region and a second low-permittivity region and a multilayer wiring part in the semiconductor device illustrated in FIG. 7.[FIG. 12] FIG. 12 is a schematic diagram illustrating the positional relationship in a direction in the XY plane between the first low-permittivity region and the second low-permittivity region and the multilayer wiring part in the semiconductor device illustrated in FIG. 7.[FIG. 13 ] FIG. 13 is a longitudinal cross-sectional view of a cross-sectional configuration taken along a line XV-XV in FIG. 12.[FIG. 14] FIG. 14 is a longitudinal cross-sectional view of a cross-sectional configuration taken along a line XVIA-XVIB in FIG. 12.[FIG. 15] FIG. 15 is a longitudinal cross-sectional view of a cross-sectional configuration taken along a line XVIIB-XVIIC in FIG. 12.[FIG. 16] FIG. 16 is a longitudinal cross-sectional view of a cross-sectional configuration taken along a line XVIIIC-XVIIID in FIG. 12.[FIG. 17] FIG. 17 is a longitudinal cross-sectional view of a step of manufacturing the semiconductor device according to the embodiment.[FIG. 18] FIG. 18 is a longitudinal cross-sectional view of a step of manufacturing the semiconductor device according to the embodiment.[FIG. 19] FIG. 19 is a longitudinal cross-sectional view of a step of manufacturing the semiconductor device according to the embodiment.[FIG. 20] FIG. 20 is a longitudinal cross-sectional view of a step of manufacturing the semiconductor device according to the embodiment.[FIG. 21] FIG. 21 is a longitudinal cross-sectional view of a step of manufacturing the semiconductor device according to the embodiment.[FIG. 22] FIG. 22 is a longitudinal cross-sectional view of a step of manufacturing the semiconductor device according to the embodiment.[FIG. 23] FIG. 23 is a longitudinal cross-sectional view of a step of manufacturing the semiconductor device according to the embodiment.[FIG. 24] FIG. 24 is a longitudinal cross-sectional view of a step of manufacturing the semiconductor device according to the embodiment.[FIG. 25] FIG. 25 is a longitudinal cross-sectional view of a step of manufacturing the semiconductor device according to the embodiment.[FIG. 26] FIG. 26 is a longitudinal cross-sectional view of a step of manufacturing the semiconductor device according to the embodiment.[FIG. 27] FIG. 27 is a longitudinal cross-sectional view of a step of manufacturing the semiconductor device according to the embodiment.[FIG. 28] FIG. 28 is a longitudinal cross-sectional view of a step of manufacturing the semiconductor device according to the embodiment.[FIG. 29] FIG. 29 is a longitudinal cross-sectional view of a step of manufacturing the semiconductor device according to the embodiment.[FIG. 30] FIG. 30 is a longitudinal cross-sectional view of a cross-sectional configuration of a semiconductor device according to a second embodiment of the present disclosure.[FIG. 31] FIG. 31 is a longitudinal cross-sectional view of a cross-sectional configuration of a semiconductor device according to a third embodiment of the present disclosure.[FIG. 32] FIG. 32 is a longitudinal cross-sectional view of a cross-sectional configuration of a semiconductor device according to a fourth embodiment of the present disclosure.[FIG. 33] FIG. 33 is a longitudinal cross-sectional view of a cross-sectional configuration of a semiconductor device according to a fifth embodiment of the present disclosure.[FIG. 34] FIG. 34 is a longitudinal cross-sectional view of a cross-sectional configuration of a semiconductor device according to a sixth embodiment of the present disclosure.[FIG. 35] FIG. 35 is a longitudinal cross-sectional view of a cross-sectional configuration of a semiconductor device according to a seventh embodiment of the present disclosure.[FIG. 36] FIG. 36 is a schematic diagram illustrating an example of a configuration of a wireless communication device to which the semiconductor devices according to the first to seventh embodiments of the present disclosure are applied.MODES FOR CARRYING OUT THE INVENTIONHereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The embodiments described below are specific examples of the present disclosure, and the technology according to the present disclosure is not intended to be limited to the following embodiments. Further, arrangements, dimensions, dimensional relationships, and the like of each component illustrated in the drawings of the present disclosure are not limited to those illustrated in the drawings.It is to be noted that the description is given in the following order. 1. first embodiment 1.1 Configuration of high-frequency switch 1.2 Configuration of semiconductor device 1.3 Method of manufacturing semiconductor device 2. second embodiment 3. third embodiment 4. fourth embodiment 5. fifth embodiment 6. sixth embodiment 7. seventh embodiment 8. application example<1 First Embodiment>(1.1. Configuration of a High-Frequency Switch)First, with reference to FIGS. 1 to 5, a configuration of a high-frequency switch including a semiconductor device according to a first embodiment of the present disclosure will be described. FIG. 1 is a schematic diagram illustrating a configuration of a high-frequency switch in which the number of input / output terminals is one to ten, and FIG. 2 is a schematic diagram illustrating a configuration of a high-frequency switch in which the number of input / output terminals is one to one.A high-frequency switch is an electronic component mainly used for signal processing in the high-frequency (RF) band. For example, the high-frequency switch is used in the front end or the like of a mobile information terminal such as a mobile phone. The high-frequency switch may take various configurations, depending on the number of input / output terminals, such as SPST (single pole single throw), SPDT (single pole double throw), SP3T,..., and SPNT (N is a real number).For example, a high-frequency switch 1 illustrated in FIG. 1 is an SP10T switch. The high-frequency switch 1, which is an SP10T switch, includes, for example, a pole coupled to an antenna ANT and ten contacts, and can control the contact to be coupled among the ten contacts. Further, a high-frequency switch 1A illustrated in FIG. 2 is an example of an SPST switch. The high-frequency switch 1A, which is an SPST switch, includes, for example, a pole coupled to an antenna ANT and a contact, and can control on / off of the one contact.Note that the high-frequency switch may also assume a configuration other than the configurations illustrated in FIGS. 1 and 2. Specifically, the high-frequency switch may take a variety of configurations by combining the circuits of the SPST switch illustrated in FIG. 2.Now, FIGS. 3 to 5 illustrate an equivalent circuit of the high-frequency switch 1A illustrated in FIG. 2. FIG. 3 is a circuit diagram illustrating the equivalent circuit of the high-frequency switch 1A illustrated in FIG. 2. FIG. 4 is a circuit diagram illustrating the equivalent circuit in a case where the high-frequency switch 1A illustrated in FIG. 2 is in an on state, and FIG. 5 is a circuit diagram illustrating the equivalent circuit in a case where the high-frequency switch 1A illustrated in FIG. 2 is in an off state.As illustrated in FIG. 3, the high-frequency switch 1A, which is an SPST, includes, for example, a first terminal Port 1 coupled to the antenna ANT, a second terminal Port 2 on the output side, a first switching device FET 1, and a second switching device FET 2. The first switching device FET 1 is provided between the first terminal Port 1 and the ground, and the second switching device FET 2 is provided between the first terminal Port 1 and the second terminal Port 2.Such a high-frequency switch 1A can control the on-state or the off-state of the switch by applying control voltages Vc 1 and Vc 2 to gates of the first switching device FET 1 and the second switching device FET 2 via resistors.When the high-frequency switch 1A is in the on state, the second switching device FET 2 is in a conductive state and the first switching device FET 1 is in a non-conductive state, as illustrated in FIG. 4. Further, when the high-frequency switch 1A is in the off state, the first switching device FET 1 is in the conductive state and the second switching device FET 2 is in the non-conductive state, as illustrated in FIG. 5.The first switching device FET 1 and the second switching device FET 2 are equivalent to resistors in the conductive state and capacitors in the non-conductive state. Therefore, in the first switching device FET 1 and the second switching device FET 2, a resistance called on-resistance is generated in the conductive state, and a capacitance called off-capacitance is generated in the non-conductive state.Here, the on-resistances and off-capacitances of the first switching device FET 1 and the second switching device FET 2 may be expressed as Ron / Wg 1, Ron / Wg 2, Cof* Wg 1 and Cof* Wg 2 using Ron [Ωmm] and Coff [fF / mm] per unit length of the field effect transistors, and gate widths Wg 1 and Wg 2[ mm] of the field effect transistors, respectively. That is, in the field effect transistors, the on-resistance is inversely proportional to the gate widths Wg 1 and Wg 2 and the off-capacitance is proportional to the gate widths Wg 1 and Wg 2.Therefore, in the field effect transistor, in a case where the gate width Wg is increased to reduce loss due to the on-resistance, loss due to the off-capacitance increases. Further, although the on-resistance of the field effect transistor does not depend on a signal frequency, the off-capacitance increases as the signal frequency increases. Therefore, in the high-frequency switch that processes high-frequency signals, the loss due to the off-capacitance further increases.Therefore, in order to reduce the loss of the field effect transistor to be used in the high frequency switch, it is important to reduce both Ron and Coff per unit length, that is, to reduce Ron*Coff (product).The technology according to the present disclosure has been developed in view of the above circumstances. The technology according to the present disclosure reduces a parasitic capacitance of a semiconductor device such as a field effect transistor, thereby reducing the on-resistance and off-capacitance of the field transistor. The technology according to the present disclosure can be suitably used for a high-frequency switch or the like to be provided in an electronic device that processes high-frequency signals.(1.2. Configuration of Semiconductor Device)Next, with reference to FIGS. 6 and 7, a configuration of a semiconductor device according to a first embodiment of the present disclosure will be described. FIG. 6 is a plan view of the overall configuration of the semiconductor device according to the present embodiment.As illustrated in FIG. 6, a semiconductor device 10 according to the present embodiment includes, for example, a gate electrode 20 provided on a semiconductor layer not illustrated, a source electrode 30S, and a drain electrode 30D. Note that the gate electrode 20 is shaded in FIG. 6.The semiconductor device 10 is, for example, a field effect transistor for a high-frequency device that constitutes the first switching device FET 1 or the second switching device FET 2 included in the high-frequency switch 1A illustrated in FIG. 3.The gate electrode 20 is provided with a multi-finger structure including a plurality of finger parts 21 extending in one direction and a connection part 22 connecting the plurality of finger parts 21 to each other. In order to reduce the loss, a gate width Wg of the field effect transistor to be used in the high-frequency switch is larger than that of a field effect transistor to be used in a logic circuit or the like, and is, for example, several hundreds of micrometers to several millimeters. Further, a length (finger length) L 21 of the finger part 21 is, for example, several tens of micrometers. Note that the connection part 22 is coupled to a gate contact not illustrated.In the following description, the direction in which the finger part 21 of the gate electrode 20 extends is referred to as a Y direction. Further, a direction orthogonal to the Y direction in which the connection part 22 extends is referred to as an X direction. Moreover, a direction orthogonal to both the X direction and the Y direction (a direction perpendicular to a plane of the semiconductor layer not illustrated) is referred to as a Z direction.As with the gate electrode 20, the source electrode 30S includes finger parts 31S extending in one direction (e.g., the Y direction) and a connection part 32S connecting the plurality of connection parts 31S and coupled to a source contact, not illustrated.As with the gate electrode 20, the drain electrode 30D includes finger parts 31D extending in one direction (e.g., the Y direction) and a connection part 32D connecting the plurality of finger parts 31D and coupled to a drain contact, not illustrated.The finger part 21 of the gate electrode 20, the finger part 31S of the source electrode 30S, and the finger part 31D of the drain electrode 30D are disposed within an active region AA activated by an introduced impurity of a conductivity type. Specifically, the finger part 31S of the source electrode 30S and the finger part 31D of the drain electrode 30D are alternately arranged between the finger parts 31 of the gate electrode 20. On the other hand, the connection part 22 of the gate electrode 20, the connection part 32S of the source electrode 30S, and the connection part 32D of the drain electrode 30D are disposed in a device isolation region (not illustrated) provided outside the active region AA.Referring now to FIG. 7, a cross-sectional configuration of the semiconductor device 10 according to the present embodiment will be described. FIG. 7 is a longitudinal cross-sectional view of the cross-sectional configuration taken along a line VII-VII in FIG. 6, FIG. 7 illustrates the cross-sectional configuration including one of the finger parts 21 of the gate electrode 20 and the finger part 31S of the source electrode 30S and the finger part 31D of the drain electrode 30D disposed on both sides of the finger part 21.As illustrated in FIG. 7, the semiconductor device 10 includes, for example, the gate electrode 20 described above, a semiconductor layer 50, contact plugs 60S and 60D, first metals M 1 including the source electrode 30S and the drain electrode 30D described above, a first low-permittivity region 70 and a second low-permittivity region 71.The gate electrode 20 is provided on the semiconductor layer 50 via a gate insulating film 23. The gate electrode 20 may include, for example, polysilicon having a thickness of 100 nm to 200 nm. The gate insulating film 23 may include, for example, silicon oxide (SiO x) having a thickness of 5 nm to 15 nm.The semiconductor layer 50 may include, for example, a semiconductor such as silicon (Si). In the semiconductor layer 50, a source region 50S and a drain region 50D containing silicon of a first conductivity type (n+) are provided on both sides via the gate electrode 20. Further, on the surface side of the source region 50D and the drain region 50D, low resistance regions 51S and 51D containing silicon of a first conductivity type (n++) having a higher concentration or silicide are provided for connection to the contact plugs 60S and 60D. In addition, extension regions 52S and 52D containing silicon of a first conductivity type having a low concentration (n-) are provided between the source region 50S and the gate electrode 20 and between the drain region 50D and the gate electrode 20.The semiconductor layer 50 is provided on a support substrate 53 via a buried oxide film 54, for example. The support substrate 53 may include, for example, a high resistance silicon (Si) substrate, and the buried oxide film 54 may include, for example, silicon oxide (SiO x). That is, the support substrate 53, the buried oxide film 54, and the semiconductor layer 50 may form a so-called SOI (Silicon On Insulator) substrate 55.Although a case where the support substrate 53 of the SOI substrate 55 is a high resistance silicon substrate is described above, the technology according to the present disclosure is not limited to the above example. The support substrate 53 may be a sapphire substrate. In such a case, the SOI substrate 55 may form a so-called SOS (Silicon On Sapphire) substrate. Because the sapphire substrate has an insulating property, a field effect transistor formed on the SOS substrate exhibits properties that approach a compound (e.g., GaAs) based field effect transistor. Further, the technology according to the present disclosure is not limited to the case where the support substrate 53 is an SOI substrate or an SOS substrate, and is similarly applicable to a case where the support substrate 53 is a substrate having silicon as a main component.The contact plugs 60S and 60D are provided on the low resistance regions 51S and 51D on the surfaces of the source region 50S and the drain region 50D. The contact plugs 60S and 60D may be formed by sequentially stacking, from the semiconductor layer 50 side, a titanium (Ti) layer, a titanium nitride (TiN) layer, and a tungsten (W) layer, for example. Note that the titanium layer is provided to reduce contact resistance between the contact plugs 60S and 60D and the low resistance regions 51S and 51D in the lower layer. Further, the titanium nitride layer is provided as a barrier metal that suppresses diffusion of silicon or the like from the semiconductor layer 50 to the tungsten layer.The first metals M 1 include, for example, the source electrode 30S provided on the contact plug 60S and the drain electrode 30D provided on the contact plug 60D. The first metal M 1 may include, for example, aluminum (Al) having a thickness of 500 nm to 1000 nm.The first low-permittivity region 70 is provided, for example, in at least any region that is between the first metals M 1 in a direction in the XY plane of the semiconductor layer 50 and below a lower surface of the first metal M 1 in a Z stacking direction of the semiconductor layer 50. Specifically, the first low-permittivity region 70 is provided in a region that is between the source electrode 30S and the drain electrode 30D in the direction in the XY plane of the semiconductor layer 50 and below the lower surface of the first metal M 1 and above the gate electrode 20 in the Z stacking direction of the semiconductor layer 50.Further, the first low-permittivity region 70 may be provided continuously up to a region further above the above-described region in the Z-stacking direction. Specifically, the first low-permittivity region 70 may be further provided in a region that is between the first metals M 1 in the direction in the XY plane of the semiconductor layer 50 and between the lower surface and an upper surface of the first metal M 1 in the Z stacking direction. Further, the first low-permittivity region 70 may be further provided in a region that is between the first metals M 1 in the direction in the XY plane of the semiconductor layer 50 and above the upper surface of the first metal M 1 in the Z stacking direction.The second low-permittivity region 71 is provided in at least any region that is between each of the contact plugs 60S and 60D and the gate electrode 20 in the direction in the XY plane of the semiconductor layer 50 and below the first low-permittivity region 70 in the Z stacking direction of the semiconductor layer 50. Specifically, the second low-permittivity region 71 is provided on the sides of both side surfaces of the gate electrode 20 in the direction in the XY plane of the semiconductor layer 50. Note that the second low-permittivity region 71 may be provided continuously with the first low-permittivity region 70 or may be provided separately from the first low-permittivity region 70.At least a portion of the second low-permittivity region 71 is provided in a region different from a region provided with the first low-permittivity region 70 when the semiconductor layer 50 is viewed from the stacking direction Z in plan view. Specifically, at least a portion of the second low-permittivity region 71 is provided in a region around the periphery of a region provided with the first low-permittivity region 70 in the direction in the XY plane of the semiconductor layer 50. Thus, in the semiconductor device 10, it is possible to configure the first low-permittivity region 70 and the second low-permittivity region 71 into more complicated shapes.Referring to FIG. 8, the off-capacitance of a field effect transistor will be described here. FIG. 8 is a schematic longitudinal cross-sectional view of the element-divided off capacitance of a typical field effect transistor 11.As illustrated in FIG. 8, the off capacitance of the field effect transistor 11 having a typical structure includes an intrinsic (inherent) component Cin generated in the source region 50S and the drain region 50D, SOI substrate 55, and the like, and an extrinsic (external) component Cex generated in the gate electrode 20, the contact plugs 60S and 60D, the first metals M 1, and the like.Examples of the intrinsic component Cin include capacitances Cssub and Cdsub generated between the source region 50S or the drain region 50D and the support substrate 53, capacitances Csg and Cdg generated between the source region 50S or the drain region 50D and the gate electrode 20, a capacitance Cds generated between the source region 50S and the drain region 50D, capacitances Csb and Cdb generated between the source region 50S or the drain region 50D and a lower portion (body) of the semiconductor layer 50, and the like.Examples of the extrinsic component Cex include a capacitance CgM between the gate electrode 20 and the contact plugs 60S and 60D or the first metals M 1, a capacitance CMM 1 generated between the first metals M 1, and the like.In order to reduce these off-capacitances, it is particularly effective to reduce the extrinsic component Cex. In the semiconductor device 10 according to the present embodiment, the first low-permittivity region 70 and the second low-permittivity region 71 having a lower relative permittivity than the surrounding region are provided in the above-described regions. This makes it possible to reduce the extrinsic component Cex of the off capacitance generated between the gate electrode 20, the contact plugs 60S and 60D, and the first metals M 1. Therefore, by reducing the extrinsic component Cex more effectively, the semiconductor device 10 makes it possible to reduce the product of the on-resistance and the off-capacitance (Ron*Coff). Consequently, the semiconductor device 10 used for the high-frequency switch makes it possible to further reduce loss of the high-frequency switch.FIG. 10 illustrates the results of a simulation of the size of the extrinsic component Cex of the off-capacitance for the semiconductor device 10 illustrated in FIG. 7 and a semiconductor device 12 illustrated in FIG. 9 according to a comparative example.FIG. 9 is a longitudinal cross-sectional view of a cross-sectional configuration of the semiconductor device 12 according to the comparative example. As illustrated in FIG. 9, the semiconductor device 12 according to the comparative example is different from the semiconductor device 10 according to the present embodiment in that no second low-permittivity region is provided between each of the contact plugs 60S and 60D and the gate electrode 20 in the direction in the XY plane of the semiconductor layer 50 and below the first low-permittivity region 70 in the Z-stacking direction of the semiconductor layer 50. That is, the semiconductor device 12 according to the comparative example is different from the semiconductor device 10 according to the present embodiment in that although the similar first low-permittivity region 70 is provided, the second low-permittivity region 71 is not provided on both sides of the gate electrode 20 in the direction in the XY plane of the semiconductor layer 50.FIG. 10 illustrates a simulation result of the extrinsic component Cex in the semiconductor device 10 according to the present embodiment as an example, and illustrates a simulation result of the extrinsic component Cex in the semiconductor device 12 according to the comparative example as a comparative example. As illustrated in FIG. 10, the results indicate that the size of the extrinsic component Cex in the example is reduced with respect to the size of the extrinsic component Cex in the comparative example. Therefore, the results indicate that the semiconductor device 10 according to the present embodiment enables to further reduce the off-capacitance by providing the second low-permittivity region 71.Returning to FIG. 7, the description of the configuration of the semiconductor device 10 according to the present embodiment will be resumed here.The semiconductor device 10 illustrated in FIG. 7 further includes at least one or more insulating films 80 provided on the semiconductor layer 50 to cover the gate electrode 20, and an opening P provided from an upper surface of the at least one or more insulating films 80 toward an upper surface of the gate electrode 20.The opening P is provided in a planar region corresponding to the gate electrode 20 when the at least one or more insulating films 80 are viewed from the stacking direction Z in plan view. Since the opening P is provided between the source electrode 30S and the drain electrode 30D, an opening width WP of the opening P is, for example, about 100 nm to about 1000 nm.The first low-permittivity region 70 is preferably provided within such an opening P. Further, it is preferable that the second low-permittivity region 71 is provided to be spatially continuous with the opening P and provided to be spatially continuous with the first low-permittivity region 70 provided inside the opening P. In either the X direction or the Y direction, the first low-permittivity region 70 and the second low-permittivity region 71 may be provided so that the centers of the regions coincide with each other, or may be provided in mutually independent regions.The at least one or more insulating films 80 preferably include a plurality of insulating films containing materials having different etch rates. Accordingly, by utilizing the difference in etching rate between the insulating films, the at least one or more insulating films 80 enable an etching stop position of the opening P to be controlled with high accuracy in manufacturing steps to be described later.Specifically, the at least one or more insulating films 80 may include a first insulating film 81, a second insulating film 82, and a third insulating film 83.The first insulating film 81 is provided to cover a surface of the gate electrode 20 (i.e., the upper surface and the side surface of the gate electrode 20) and an upper surface of the semiconductor layer 50.The second insulating film 82 is provided to cover a surface of the first insulating film 81. Note that the second insulating film 82 is not provided on the surface of the insulating film 81 provided on the surface of the gate electrode 20 (i.e., the upper surface and the side surface of the gate electrode 20), and exposes the first insulating film 81 to the second low-permittivity region 71. This is because, in the semiconductor device 10, the second low-permittivity region 71 is formed between the first insulating film 81 and the third insulating film 83 by removing the second insulating film 82, as described in the manufacturing steps to be described later.The third insulating film 83 is provided between a surface of the second insulating film 82 and the lower surface of the first metal M 1. The third insulating film 83 is provided to bury the gate electrode 20, and forms the second low-permittivity region 71 between the first insulating film 81 and the third insulating film 83.Here, the second insulating film 82 preferably includes a material having an etching rate different from a material included in the first insulating film 81 and the third insulating film 83. For example, it is preferable that the second insulating film 82 includes a silicon nitride (SiN) film, and the first insulating film 81 and the third insulating film 83 include a silicon oxide (SiO x-) film having an etching rate different from silicon nitride (SiN). Thus, by making the second insulating film 82 function as an etch stop layer in the semiconductor device 10, this makes it possible to easily form the opening P penetrating the third insulating film 83 to reach an upper surface of the second insulating film 82. Further, selectively removing the second insulating film 82 by performing isotropic etching via the opening P makes it possible to easily form the second low-permittivity region 71 below the opening P.Moreover, the at least one or more insulating films 80 may further include a fourth insulating film 84. Specifically, the fourth insulating film 84 may be provided to cover an upper surface of the third insulating film 83 and a surface of the first metal M 1 (i.e., the upper surface and a side surface of the first metal M 1). In such a case, the opening P is provided from an upper surface of the fourth insulating film 84 so as to penetrate the fourth insulating film 84 and the third insulating film 83. The fourth insulating film 84 may include, for example, a silicon oxide (SiO x-) film.Moreover, the at least one or more insulating films 80 may further include a fifth insulating film 85. Specifically, the fifth insulating film 85 may be provided on the fourth insulating film 84 and may block an upper portion of the opening P. The fifth insulating film 85 may include, for example, a silicon oxide (SiO x-) film.Moreover, a sixth insulating film 86 including, for example, a silicon oxide (SiO x-) film may be provided in an upper layer of the fifth insulating film 85, as necessary.In the semiconductor device 10 according to the present embodiment, an air gap AG (Air Gap) may be provided as the first low-permittivity region 70 in at least a portion of the interior of the opening P. For example, the air gap AG of the first low-permittivity region 70 may be provided so as to be spatially continuous with the second low-permittivity region 71 formed below the first low-permittivity region 70 similarly to an air gap AG.The first low-permittivity region 70 and the second low-permittivity region 71 are not particularly limited in the configuration inside the region as long as the regions have a lower relative permittivity than the film of silicon oxide (SiO x: relative permittivity 3.9) included in the third insulating film 83 and the fourth insulating film 84. For example, the first low-permittivity region 70 and the second low-permittivity region 71 may be configured such that the inside of the air gap AG contains air (relative permittivity 1.0), or may be configured such that the inside of the air gap AG is an air-less space. Further, the first low-permittivity region 70 and the second low-permittivity region 71 may be configured by filling a portion of the inside of the air gap AG or the whole with a low-permittivity material. Note that the low-permittivity material refers to, for example, a dielectric material having a relative permittivity of 3 or less.If the first low-permittivity region 70 and the second low-permittivity region 71 include the air gap AG, the air gap AG is hermetically sealed by the fifth insulating film 85 by blocking an upper portion of the air gap AG by the fifth insulating film 85. Note that when the air gap AG is blocked, a part of the fifth insulating film 85 may enter the inside of the air gap AG. In such a case, the fifth insulating film 85 covers a portion of a side surface or a bottom surface of the opening P.In the direction in the XY plane, widths at which the first low-permittivity region 70 and the second low-permittivity region 71 are formed are not particularly limited. Note that the width with which the first low-permittivity region 70 is formed in a cross section taken in the stacking direction Z may be smaller than a width of the first insulating film 81 provided on the surface of the gate electrode 20, for example. Specifically, a width W 70 of the first low-permittivity region 70 may be smaller than a width W 81 of the first insulating film 81 covering the upper surface and the side surface of the gate electrode 20.In a case where the second insulating film 82 is formed on the surface of the first insulating film 81 on the upper surface and the side surface of the gate electrode 20, the width W 70 of the first low permittivity region 70 may be smaller than widths of the first insulating film 81 and the second insulating film 82 covering the upper surface and the side surface of the gate electrode 20. Moreover, if the first insulating film 81 is not provided on the upper surface and the side surface of the gate electrode 20, the width W 70 of the first low-permittivity region 70 may be smaller than a width of the gate electrode 20.Further, the width with which the second low-permittivity region 71 is formed may be larger than the width of the first insulating film 81 provided on the surface of the gate electrode 20 in a cross section taken in the stacking direction Z. Specifically, a width W 71 of the second low-permittivity region 71 may be larger than the width W 81 of the first insulating film 81 covering the upper surface and the side surface of the gate electrode 20 and smaller than a width between the contact plugs 60S and 60D.If the second insulating film 82 is formed on the surface of the first insulating film 81 on the upper surface and the side surface of the gate electrode 20, the width W 71 of the second low-permittivity region 71 may be larger than the widths of the first insulating film 81 and the second insulating film 82 covering the upper surface and the side surface of the gate electrode 20. Moreover, if the first insulating film 81 is not formed on the upper surface and the side surface of the gate electrode 20, the width W 71 of the second low-permittivity region 71 may be larger than the width of the gate electrode 20.Moreover, referring to FIGS. 11 and 12, the positional relationship between the first low-permittivity region 70 and the second low-permittivity region 71 and a multilayer wiring part 90 in the semiconductor device 10 according to the present embodiment will be described. The multilayer wiring part 90 is provided with wiring lines that transmit signals taken from the electrodes of the semiconductor device 10.FIG. 11 is a schematic diagram illustrating the positional relationship in the Z stacking direction between the first low-permittivity region 70 and the second low-permittivity region 71 and the multilayer wiring part 90 in the semiconductor device 10 illustrated in FIG. 7.As illustrated in FIG. 11, the multilayer wiring part 90 includes, for example, a first wiring layer 91 and a second wiring layer 92 The first wiring layer 91 is provided, for example, in the same layer as the first metals M 1 including the source electrode 30S and the drain electrode 30D. The second wiring layer 92 is provided above the first wiring layer 91, and is coupled to the first wiring layer 91, for example, via a contact plug 93.The first low-permittivity region 70 and the second low-permittivity region 71 in the semiconductor device 10 are provided inside a device region AA 1 of the active region AA activated by introducing the impurity of a conductivity type into the semiconductor layer 50. On the other hand, the multilayer wiring part 90 is provided inside a wiring region AA 2 that is inside the active region AA and outside the device region AA 1. The device region AA 1 and the wiring region AA 2 are insulated from each other by, for example, a device isolation layer 100 formed by an STI (Shallow Trench Isolation) method.Note that the first low-permittivity region 70 and the second low-permittivity region 71 may not be provided between wiring lines of the first wiring layer 91 and between wiring lines of the second wiring layer 92 of the multilayer wiring layer 90. That is, the first low-permittivity region 70 and the second low-permittivity region 71 are provided at least in the semiconductor device 10 in the device region AA 1 of the active region AA.FIG. 12 is a schematic diagram illustrating the positional relationship in the direction in the XY plane between the first low-permittivity region 70 and the second low-permittivity region 71 and the multilayer wiring part 90 in the semiconductor device 10 illustrated in FIG. 7.As illustrated in FIG. 12, the semiconductor device 10, the first low-permittivity region 70, and the second low-permittivity region 71 are provided inside the active region AA. On the other hand, in a device isolation region AB outside the active region AA, the device isolation layer 100 formed by the STI method is provided over the entire surface instead of the semiconductor layer 50, and a gate contact GC is provided.More specifically, the active region AA is provided with the finger part 21 of the gate electrode 20, the finger part 31S of the source electrode 30S, and the finger part 31D of the drain electrode 30D.The finger part 21 of the gate electrode 20 is provided to extend in one direction (e.g., the Y direction). The finger part 31S of the source electrode 30S and the finger part 31D of the drain electrode 30D are provided on both sides of the finger part 21 of the gate electrode 20 so as to extend in a direction parallel to the extending direction of the finger part 21 of the gate electrode 20.The contact plugs 60S and 60D are provided below the finger part 31S of the source electrode 30S and the finger part 31D of the drain electrode 30D so as to extend in a direction parallel to the extending direction of the finger part 21 of the gate electrode 20.The first low-permittivity region 70 is provided above the finger part 21 of the gate electrode 20 so as to extend in a direction parallel to the extending direction of the finger part 21 of the gate electrode 20. Further, the second low-permittivity region 71 is provided on the finger part 21 side of the gate electrode 20 so as to extend in a direction parallel to the extending direction of the finger part 21 of the gate electrode 20. That is, when the semiconductor layer 50 is viewed from the Z stacking direction in plan view, the first low-permittivity region 70 is provided in a region overlapping the finger part 21 of the gate electrode 20 in the direction in the XY plane, and the second low-permittivity region 71 is provided in regions on both sides of the finger part 21 of the gate electrode 20 in the direction in the XY plane.The device isolation region AB is provided with the connection part 22 of the gate electrode 20, the connection part 32S of the source electrode 30S, and the connection part 32D of the drain electrode 30D.The connection part 22 of the gate electrode 20 is coupled to the gate contact GC. Further, the connection part 32S of the source electrode 30S is coupled to the non-illustrated source contact, and the connection part 32D of the drain electrode 30D is coupled to the non-illustrated drain contact.Referring to FIGS. 13 to 16, cross-sectional configurations, in the Z-stacking direction, of the configuration illustrated in FIG. 12 will be described herein. FIG. 13 is a longitudinal cross-sectional view of the cross-sectional configuration taken along a line XV-XV in FIG. 12, FIG. 14 is a longitudinal cross-sectional view of the cross-sectional configuration taken along a line XVIA-XVIB in FIG. 12, FIG. 15 is a longitudinal cross-sectional view of the cross-sectional configuration taken along a line XVIIB-XVIIC in FIG. 12, FIG. 16 is a longitudinal cross-sectional view of the cross-sectional configuration taken along a line XVIIIC-XVIIID in FIG. 12.As illustrated in FIG. 13, the gate contact GC may be configured by sequentially providing the connection part 22 of the gate electrode 20, a gate contact plug 24, and a gate contact layer 25 on the device isolation layer 100 formed by the STI method. The gate contact plug 24 has a configuration similar to those of the contact plugs 60S and 60D, and is provided in the same layer as the contact plugs 60S and 60D. The gate contact layer 25 has a configuration similar to those of the source electrode 30S and the drain electrode 30D, and is provided in the same layer as the first metals M 1 including the source electrode 30S and the drain electrode 30D.As illustrated in FIGS. 12 to 16, the first low-permittivity region 70 is preferably provided so as to avoid the gate contact GC. One reason for this is that it is difficult to provide the gate contact plug 24 on the connection part 22 if the first low-permittivity region 70 is provided on the connection part 22 of the gate contact GC. Moreover, if the first low-permittivity region 70 is not provided on the connection part 22 of the gate contact GC, the second low-permittivity region 71 is also not provided. As with the gate electrode 20, the gate contact GC is further preferably covered by the at least one or more insulating films 80 (i.e., the first insulating film 81 to the sixth insulating film 86). This allows protection of the gate contact GC by the at least one or more insulating films 80 without exposing the gate contact GC, which makes it possible to maintain the reliability of the gate contact GC.(1.3. Method of Manufacturing Semiconductor Device)Referring now to FIGS. 17 to 29, a method of manufacturing the semiconductor device 10 according to the present embodiment will be described. FIGS. 17 to 29 are longitudinal cross-sectional views of the respective steps for manufacturing the semiconductor device 10.As illustrated in FIG. 17, first, the SOI substrate 55 is prepared in which the buried oxide film 54 and the semiconductor layer 50 are stacked on the support substrate 53. Next, the device region AA 1 is defined in the active region AA by forming the device isolation layer 100 in the semiconductor layer 50 of the SOI substrate 55 by the STI method.Next, as illustrated in FIG. 18, the gate electrode 20 is formed on the semiconductor layer 50 via the gate insulating film 23.Specifically, for example, after forming an implantation-through film (Implantation-through film) including a silicon oxide film by a thermal oxidation method, well implantation and channel implantation of a second conductivity type impurity (e.g., a p-type impurity such as boron (B) or aluminum (Al)) are performed on the active region AA, and thereafter the implantation-through film is removed. The gate insulating film 23 containing, for example, silicon oxide is then formed to a thickness of 5 nm to about 15 nm by the thermal oxidation method.Subsequently, a polysilicon-containing gate electrode material film (not illustrated) having a thickness of about 100 nm to about 200 nm is formed on the semiconductor layer 50 and the gate insulating film 23 by a CVD (chemical vapor deposition) method. Next, the gate electrode material film formed is patterned by photolithography and etching to form the gate electrode 20 on the upper surface of the semiconductor layer 50.Subsequently, as illustrated in FIG. 19, implantation S / D IMPL of the impurity of a first conductivity type (e.g., an n-type impurity such as arsenic (As) or phosphorus (P)) is performed by using the gate electrode 20 and offset spacers not illustrated as a mask. Thus, extension regions 52S and 52D are formed in the semiconductor layer 50 on both sides of the gate electrode 20. Sidewalls not illustrated are next formed on the both side surfaces of the gate electrode 20, and the implantation S / D IMPL of the impurity of a first conductivity type is performed again. This makes it possible to form the source region 50S and the drain region 50D in the semiconductor layer 50 on both sides of the gate electrode 20. Note that the sidewall is removed after the formation of the source region 50S and the drain region 50D.Next, as illustrated in FIG. 20, the first insulating film 81 including silicon oxide is formed to a thickness of about 10 nm to about 100 nm on the surface of the gate electrode 20 and that on the upper surface of the semiconductor layer 50 by, for example, the CVD method.Next, as illustrated in FIG. 21, the second insulating film 82 containing silicon nitride having a different etching rate from the silicon oxide constituting the first insulating film 81 is formed to a thickness of about 10 nm to about 100 nm on the surface of the first insulating film 81, for example, by the CVD method. Thereafter, the third insulating film 83 containing silicon oxide is formed to a thickness of about 500 nm to about 1500 nm on the second insulating film 82, for example, by the CVD method.Next, as illustrated in FIG. 22, the third insulating film 83, the second insulating film 82, and the first insulating film 81 are removed at positions corresponding to the source region 50S and the drain region 50D by photolithography and etching. Thus, contact holes H 1 exposing the source region 50S and the drain region 50D are formed. As illustrated in FIG. 12, the contact holes H 1 are provided to extend in a direction parallel to the extending direction of the finger part 21 of the gate electrode 20.Thereafter, as illustrated in FIG. 23, implantation Cnt IMPL of the impurity of a first conductivity type (e.g., an n-type impurity such as arsenic (As) or phosphorus (P)) is performed at a high concentration via the contact holes H 1 on the source region 50S and the drain region 50D. Thus, low resistance regions 51S and 51D are formed in the semiconductor layer 50.Next, as illustrated in FIG. 24, in the contact holes H 1 of the row near the titanium layer, the titanium nitride layer, and the tungsten layer, are stacked to form the contact plugs 60S and 60D having a stacked structure. This allows the contact plugs 60S and 60D to be electrically coupled to the source region 50S and the drain region 50D via the low resistance regions 51S and 51D. As illustrated in FIG. 12, the contact plugs 60S and 60D are provided so as to extend in a direction parallel to the extending direction of the finger part 21.Thereafter, as illustrated in FIG. 25, the source electrode 30S and the drain electrode 30D containing aluminum (Al) are formed as the first metals M 1 on the contact plugs 60S and 60D. As illustrated in FIG. 12, the finger part 31S of the source electrode 30S and the finger part 31D of the drain electrode 30D are provided so as to extend in a direction parallel to the extending direction of the finger part 21 of the gate electrode 20.Next, as illustrated in FIG. 26, the fourth insulating film 84 including silicon oxide is formed on the upper surface of the third insulating film and the surface of the first metal M 1, for example, by the CVD method.Then, as illustrated in FIG. 27, the opening P is formed, which penetrates the fourth insulating film 84 and the third insulating film 83 and exposes the second insulating film 82.Specifically, first, a resist 65 forming a low permittivity region is patterned by photolithography. Thereafter, the opening P is formed by removing a part of the fourth insulating film 84 and the third insulating film 83 by dry etching using the patterned low-permittivity region forming resist 65 as a mask. Note that etching in forming the opening P is performed by a highly anisotropic dry etching. The use of such a highly anisotropic etching enables the opening P having an aspect ratio to be formed in a desired region with high accuracy.Here, the opening P is provided in a region between the first metals M 1 in the direction in the XY plane of the semiconductor layer 50. Specifically, the opening P is provided in a region between the source electrode 30S and the drain electrode 30D (i.e., above the gate electrode 20). The opening width WP of the opening P is, for example, about 100 nm to about 1000 nm. In forming the opening P, since the second insulating film 82 serves as an etching stopper, etching of the opening P proceeds to the fourth insulating film 84 and the third insulating film 83 containing silicon oxide, stopping at the upper surface of the second insulating film 82. The air gap AG inside the opening P formed in this step serves as the first low-permittivity region 70.Subsequently, as illustrated in FIG. 28, a part of the second insulating film 82 is etched via the opening P with the left resist 65 forming a low-permittivity region. Thus, the air gap AG is formed continuously with the air gap AG provided between the first metals M 1 on the gate electrode 20 side. Note that etching in removing a portion of the second insulating film 82 is performed by isotropic dry etching, wet etching, or the like. The use of such isotropic etching makes it possible to efficiently etch the second insulating film 82 provided on the upper surface and the side surface of the gate electrode 20 and form the air gap AG in a wider area.In this step, the air gap AG formed by removing the second insulating film 82 serves as the second low-permittivity region 71. That is, the air gap AG serving as the first low-permittivity region 70 is formed above the gate electrode 20, and the air gap AG serving as the second low-permittivity region 71 is formed on the gate electrode 20 side. Thus, the semiconductor device 10 enables to further reduce the extrinsic component of the off-capacitance.Next, as illustrated in FIG. 29, after peeling off the low-permittivity region forming resist 65, the fifth insulating film 85 containing silicon oxide is formed on the fourth insulating film 84 by, for example, the CVD method under a condition where the ability to fill the inside of the air gap AG is low. In the CVD method under such a condition, the fifth insulating film 85 is deposited while overhanging on the upper portion of the opening P. Thus, the upper portion of the opening P is blocked by the fifth insulating film 85 before the inside of the opening P is filled with the fifth insulating film 85. Consequently, the hermetically sealed air gap AG is formed inside the opening P. At this time, the side surface of the opening P and the upper surface of the first insulating film 81 covering the gate electrode 20 may be covered with the fifth insulating film 85 that has penetrated inside the opening P.The air gaps AG serve as the first low-permittivity region 70 and the second low-permittivity region 71 because they have a lower relative permittivity than the silicon oxide (relative permittivity 3.9) constituting the third insulating film 83, the fourth insulating film 84, and the fifth insulating film 85. The interior of the air gap AG may be an air empty space or air (relative permittivity 1.0) may be present. Alternatively, the inside of the air gap AG may be filled with a material having a lower relative permittivity than the silicon oxide (relative permittivity 3.9) constituting the third insulating film 83, the fourth insulating film 84, and the fifth insulating film 85.Through the above steps, the air gaps AG are provided in regions corresponding to the first low-permittivity region 70 including at least any region interposed between the first metals M 1 in the direction in the XY plane and below the lower surface of the first metal M 1 in the Z stacking direction, and the second low-permittivity region 71 including at least any region between the contact plugs 60S and 60D below the gate electrode 20 in the direction in the XY plane and below the first low-permittivity region 70 in the Z stacking direction. At this time, the air gap AG of the first low-permittivity region 70 and the air gap AG of the second low-permittivity region 71 are formed so as to be spatially continuous with each other.Thereafter, the sixth insulating film 86 is formed on the fifth insulating film 85, as needed. In this way, the semiconductor device 10 illustrated in FIG. 7 is formed. Note that, although not illustrated, it is also possible to form second metals M 2 and other third metals M 3 by sequentially forming a metal layer and an insulating film on the fifth insulating film 85 as with the first metals M 1 and the fourth insulating film 84.As described above, in the semiconductor device 10, the first low-permittivity region 70 and the second low-permittivity region 71 are provided in the above-described regions. This makes it possible to reduce the capacitance CgM between the gate electrode 20 and the contact plugs 60S and 60D and the first metals M 1 and the capacitance CMM 1 generated between the first metals M 1. Therefore, the semiconductor device 10 can reduce the extrinsic component Cex of the off capacitance. Consequently, the semiconductor device 10 enables to reduce the product of the on-resistance and the off-capacitance (Ron*Coff). This helps promote a reduction in loss, which is an important characteristic of a high-frequency switch.In the semiconductor device 10, moreover, the first low-permittivity region 70 may be provided so as to further extend to a region between the lower surface and the upper surface of the first metal M 1 and a region above the upper surface of the first metal M 1 in the Z-stacking direction. In such a case, the semiconductor device 10 enables to further reduce the capacitance CgM between the gate electrode 20 and the contact plugs 60S and 60D and the first metals M 1 and the capacitance CMM 1 generated between the first metals M 1.Moreover, the semiconductor device 10 is preferably configured by providing, on the semiconductor layer 50, the at least one or more insulating films 80 including insulating films containing materials having different etching rates. Thus, in the semiconductor device 10, utilizing the difference in etching rate between the insulating films enables the etch stop position of the opening P used to form the first low-permittivity region 70 and the second low-permittivity region 71 to be controlled with high accuracy. According to the present embodiment, therefore, it is possible to manufacture the semiconductor device 10 more stably and with higher reliability.Note that the filling state of the opening P with the fifth insulating film 85 and the covering state of the side surface of the opening P and the upper surface of the first insulating film 81 covering the gate electrode 20 illustrated in the longitudinal cross-sectional view of FIG. 7, etc. are only examples and do not limit the structure of the semiconductor device 10 according to the present embodiment.<2 Second Embodiment>Next, with reference to FIG. 30, a configuration of a semiconductor device according to a second embodiment of the present disclosure will be described. FIG. 30 is a longitudinal cross-sectional view of a cross-sectional configuration of a semiconductor device 10A according to the present embodiment. As with FIG. 7, FIG. 30 illustrates the cross-sectional configuration along a line VII-VII in FIG. 6.As illustrated in FIG. 30, the semiconductor device 10A according to the present embodiment is different from the semiconductor device 10 illustrated in FIG. 7 in that the air gaps AG serving as the first low-permittivity region 70 and the second low-permittivity region 71 are widened by widening a range of isotropic etching of the second insulating film 82 performed via the opening P.Specifically, in the semiconductor device 10A, the air gap AG can be formed to a larger extent by removing, in addition to the second insulating film 82, the first insulating film 81 covering the upper surface of the gate electrode 20, and further the third insulating film 83 and the fourth insulating film 84 on the side surface of the opening P. Thus, the semiconductor device 10A makes it possible to further reduce the extrinsic component Cex of the off-capacitance including the capacitance CgM between the gate electrode 20 and the contact plugs 60S and 60D or the first metals M 1, the capacitance CMM 1 generated between the first metals M 1, and the like.In the semiconductor device 10A according to the present embodiment, since the opening width WP of the opening P is widened, the fifth insulating film 85 can be deposited with a thicker film thickness than in the semiconductor device 10 illustrated in FIG. 7 on the side surface and the bottom surface (i.e., the upper surface of the gate electrode 20) of the opening P. This time, the fifth insulating film 85 deposited on the bottom surface of the opening P has a function of protecting the upper surface of the gate electrode 20 exposed within the opening P by the isotropic etching.Note that, as also mentioned in the first embodiment, the filling state of the opening P with the fifth insulating film 85 and the covering state of the side surface of the opening P and the upper surface of the gate electrode 20 illustrated in FIG. 30 are only examples and do not limit the structure of the semiconductor device 10A according to the present embodiment.<3 Third Embodiment>Referring now to FIG. 31, a configuration of a semiconductor device according to a third embodiment of the present disclosure will be described. FIG. 31 is a longitudinal cross-sectional view of a cross-sectional configuration of a semiconductor device 10B according to the present embodiment. As with FIG. 7, FIG. 31 illustrates the cross-sectional configuration along a line VII-VII in FIG. 6.As illustrated in FIG. 31, in the semiconductor device 10B according to the present embodiment, the air gap AG serving as the second low-permittivity region 71 can be widened from the semiconductor device 10A illustrated in FIG. 30 while making the width W 70 of the air gap AG serving as the first low-permittivity region 70 substantially equal to that in the semiconductor device 10 illustrated in FIG. 7.Specifically, in the semiconductor device 10B, the opening is formed with a narrower opening width WP by narrowing an opening width of the low-permittivity region forming resist 65 used in forming the opening P. In addition, in the semiconductor device 10B, the range of isotropic etching of the second insulating film 82 performed via the opening P is expanded to remove, in addition to the second insulating film 82, the first insulating film 81 covering the upper surface and the side surface of the gate electrode 20 and further the third insulating film 83 and the fourth insulating film 84 on the side surface of the opening P. This makes it possible to form the air gap AG to a larger extent.Isotropic etching of the first insulating film 81, the second insulating film 82, the third insulating film 83 and the fourth insulating film 84 via the opening P is performed for a long time to expand the air gap AG. Therefore, the opening width WP of the opening P becomes wider between before and after the etching. In the semiconductor device 10B according to the present embodiment, the opening P is formed with the opening width WP narrowed in advance. This makes it possible to prevent the blocking of the upper portion of the opening P by the fifth insulating film 85 from becoming difficult by the opening width WP of the opening P becoming excessively wider in etching when forming the air gap AG.Note that in the semiconductor device 10B, the isotropic etching for forming the air gap AG is performed by controlling an etching amount to prevent the semiconductor layer 50 from being exposed. Specifically, isotropic etching for forming the air gap AG is performed by controlling the etching amount to the extent that the first insulating film 81 provided on the upper surface of the semiconductor layer 50 does not disappear. One reason for this is that variations in gate length and threshold voltage may increase if the semiconductor layer 50 is exposed in the vicinity of the gate insulating film 23 or the gate insulating film 23 is laterally etched.In the semiconductor device 10B, it is possible to form the air gap AG in a wider range by removing, in addition to the second insulating film 82, the first insulating film 81 covering the upper surface and the side surface of the gate electrode 20, and further the third insulating film 83 and the fourth insulating film 84 on the side surface of the opening P. Thus, the semiconductor device 10B enables to further reduce the extrinsic component Cex of the off-capacitance including the capacitance CgM between the gate electrode 20 and the contact plugs 60S and 60D or the first metals M 1, the capacitance CMM 1 generated between the first metals M 1, and the like.In the semiconductor device 10B according to the present embodiment, since the opening width WP is substantially the same as in the semiconductor device 10 illustrated in FIG. 7, it is possible to reduce the film thickness of the fifth insulating film 85 deposited on the side surface and the bottom surface (i.e., the upper surface of the gate electrode 20) of the opening P. Thus, in the semiconductor device 10B, it is possible to suppress excessive filling of the air gaps AG serving as the first low-permittivity region 70 and the second low-permittivity region 71 with the fifth insulating film 85.Note that, as also mentioned in the first embodiment, the filling state of the opening P with the fifth insulating film 85 and the covering state of the side surface of the opening P and the upper surface of the gate electrode 20 illustrated in FIG. 31 are only examples and do not limit the structure of the semiconductor device 10B according to the present embodiment.<4 Fourth Embodiment>Next, with reference to FIG. 32, a configuration of a semiconductor device according to a fourth embodiment of the present disclosure will be described. FIG. 32 is a longitudinal cross-sectional view of a cross-sectional configuration of a semiconductor device 10C according to the present embodiment. As with FIG. 7, FIG. 32 illustrates the cross-sectional configuration along a line VII-VII in FIG. 6.As illustrated in FIG. 32, the semiconductor device 10C according to the present embodiment is different from the semiconductor device 10 illustrated in FIG. 7 in that the first low-permittivity region 70 and the second low-permittivity region 71 are insulated from each other by a portion of the opening P filled with the fifth insulating film 85 without being spatially related.Specifically, in the semiconductor device 10C, when the fifth insulating film 85 blocking the upper portion of the opening P is formed, the fifth insulating film 85 is more deposited inside the opening P by forming the fifth insulating film 85 by the CVD method under a condition in which the opening P can be highly filled. Thus, in the semiconductor device 10C, the fifth insulating film 85 deposited on the side surface and the bottom surface (i.e., the upper surface of the first insulating film 81) of the opening P may be combined to isolate the first low-permittivity region 70 and the second low-permittivity region 71 from each other. Thus, the first low-permittivity region 70 is provided above the gate electrode 20, and the second low-permittivity region 71 is provided separately therefrom so as to surround the side surface of the gate electrode 20.Therefore, even with the configuration of the semiconductor device 10C according to the present embodiment, as in the semiconductor device 10 illustrated in FIG. 7, the semiconductor device 10C enables the extrinsic component Cex of the off capacitance including the capacitance CgM between the gate electrode 20 and the contact plugs 60S and 60D or the first metals M 1, the capacitance CMM 1 generated between the first metals M 1, and the like to be reduced.Note that, as also mentioned in the first embodiment, the filling state of the opening P with the fifth insulating film 85 and the covering state of the side surface of the opening P and the upper surface of the first insulating film 81 illustrated in FIG. 32 are only examples and do not limit the structure of the semiconductor device 10C according to the present embodiment.<5. Fifth Embodiment>Now, with reference to FIG. 33, a configuration of a semiconductor device according to a fifth embodiment of the present disclosure will be described. FIG. 33 is a longitudinal cross-sectional view of a cross-sectional configuration of a semiconductor device 10D according to the present embodiment. As with FIG. 7, FIG. 33 illustrates the cross-sectional configuration along a line VII-VII in FIG. 6.As illustrated in FIG. 33, the semiconductor device 10D according to the present embodiment is different from the semiconductor device 10 illustrated in FIG. 7 in that a region corresponding to the first low-permittivity region 70 is filled with the fifth insulating film 85 by filling the opening P with the fifth insulating film 85.Specifically, in the semiconductor device 10D, when the fifth insulating film 85 blocking the upper portion of the opening P is formed, a region of the opening P from the upper surface of the first insulating film 81 to an opening area is filled with the five insulating film 85 by forming the fifth insulating film 85 by the CVD method under a condition in which the opening P can be filled largely. Consequently, the opening P below the lower surface of the first metal M 1 and above the upper surface of the first insulating film 81 is filled with the fifth insulating film 85. However, it is possible to cause the above region to function as the first low-permittivity region 70 by forming the fifth insulating film 85 using a material having a lower relative permittivity than the third insulating film 83 and the fourth insulating film 84, as in the semiconductor device 10 illustrated in FIG. 7. Further, the second low-permittivity region 71 includes the air gap AG surrounding the side surface of the gate electrode 20.Therefore, even with the configuration of the semiconductor device 10D according to the present embodiment, as in the semiconductor device 10 illustrated in FIG. 7, the semiconductor device 10D enables to reduce the extrinsic component Cex of the off capacitance including the capacitance CgM between the gate electrode 20 and the contact plugs 60S and 60D or the first metals M 1, the capacitance CMM 1 generated between the first metals M 1, and the like.Note that, as also mentioned in the first embodiment, the filling state of the opening P with the fifth insulating film 85 illustrated in FIG. 33 is only an example, and does not limit the structure of the semiconductor device 10D according to the present embodiment.<6. Sixth Embodiment>Next, with reference to FIG. 34, a configuration of a semiconductor device according to a sixth embodiment of the present disclosure will be described. FIG. 34 is a longitudinal cross-sectional view of a cross-sectional configuration of a semiconductor device 10E according to the present embodiment. As with FIG. 7, FIG. 34 illustrates the cross-sectional configuration along a line VII-VII in FIG. 6.As illustrated in FIG. 34, the semiconductor device 10E according to the present embodiment is different from the semiconductor device 10D illustrated in FIG. 33 in that the fifth insulating film 85 is formed using a material having fluidity. Specifically, in the semiconductor device 10E, the upper portion of the opening P is blocked by forming the fifth insulating film 85 by applying an SOG (spin on glass) or an organic resin film which is a low dielectric constant film or bonding an organic resin film. Since the SOG and the organic resin film have fluidity, it is possible to fill a region of the opening P from the opening surface to the upper surface of the first insulating film 81 with the fifth insulating film 85 more easily than by the CVD method.Thus, the opening P below the lower surface of the first metal M 1 and above the upper surface of the first insulating film 81 is filled with the fifth insulating film 85 containing the SOG and the organic resin which is a low dielectric constant film. Thus, as in the semiconductor device 10 illustrated in FIG. 7, it can function as the first low-permittivity region 70. Further, the second low-permittivity region 71 includes the air gap AG surrounding the side surface of the gate electrode 20.Therefore, even with the configuration of the semiconductor device 10E according to the present embodiment, as in the semiconductor device 10 illustrated in FIG. 7, the semiconductor device 10E enables the extrinsic component Cex of the off capacitance including the capacitance CgM between the gate electrode 20 and the contact plugs 60S and 60D or the first metals M 1, the capacitance CMM 1 generated between the first metals M 1, and the like to be reduced.Note that, as also mentioned in the first embodiment, the filling state of the opening P with the fifth insulating film 85 illustrated in FIG. 34 is only an example and does not limit the structure of the semiconductor device 10E according to the present embodiment.<7 Seventh Embodiment>Referring now to FIG. 35, a configuration of a semiconductor device according to a seventh embodiment of the present disclosure will be described. FIG. 35 is a longitudinal cross-sectional view of a cross-sectional configuration of a semiconductor device 10F according to the present embodiment. As with FIG. 7, FIG. 35 illustrates the cross-sectional configuration along a line VII-VII in FIG. 6.As illustrated in FIG. 35, the semiconductor device 10F according to the present embodiment is different from the semiconductor device 10 illustrated in FIG. 7 in that the second metal M 2 provided between the fourth insulating film 84 and the fifth insulating film 85 and a seventh insulating film 87 covering a surface of the second metal M 2 and the upper surface of the fourth insulating film 84 are further provided.Specifically, in the semiconductor device 10F, the fourth insulating film 84 is formed to bury the first metal M 1 and a contact plug 61 provided on the upper surface of the first metal M 1. Further, the second metal M 2 coupled to the first metal M 1 via the contact plug 61 is provided on the fourth insulating film 84, and the seventh insulating film 87 is provided on the surface of the second metal M 2 and the upper surface of the fourth insulating film. The opening P is formed on an upper surface of the seventh insulating film 87, and the upper portion thereof is blocked by the fifth insulating film 85 provided on the seventh insulating film 87.Materials included in the second metal M 2, the seventh insulating film 87, and the contact plug 61 are substantially similar to those of the first metal M 1, the fourth insulating film 84, and the contact plugs 60S and 60D, respectively, and description thereof is therefore omitted.In the semiconductor device 10F according to the present embodiment, it is possible to allow the first low-permittivity region 70 including the air gap AG to extend also between the second metals M 2 provided on the first metals M 1. Thus, the semiconductor device 10F makes it possible to reduce a capacitance Cg between the gate electrode 20 and the second metals M 2 and a capacitance CMM 2 generated between the second metals M 2, in addition to the capacitance CgM between the gate electrode 20 and the contact plugs 60S and 60D or the first metals M 1 and the capacitance CMM 1 generated between the first metals M 1. Therefore, the semiconductor device 10F can reduce the extrinsic component Cex of the off-capacitance including these capacitances.Note that, as also mentioned in the first embodiment, the filling state of the opening P with the fifth insulating film 85 and the covering state of the side surface of the opening P and the upper surface of the first insulating film 81 illustrated in FIG. 35 are only examples and do not limit the structure of the semiconductor device 10F according to the present embodiment.<8. Application Example>Further, with reference to FIG. 36, a configuration of a wireless communication device that is an application example of the semiconductor devices according to the first to seventh embodiments of the present disclosure will be described. FIG. 36 is a schematic diagram illustrating an example of a configuration of the wireless communication device.As illustrated in FIG. 36, a wireless communication device 3 includes, for example, an antenna ANT, the high-frequency switch 1, a high-power amplifier HPA, a high-frequency integrated circuit (RFIC), a baseband unit BB, a voice output unit MIC, a data output unit DT, and an interface unit I / F (e.g., a wireless local area network (W-LAN), Bluetooth (registered trademark), etc.). The wireless communication device 3 is, for example, a high-frequency module to be used in a mobile telephone system having a plurality of functions such as voice and data communication and a LAN (Local Area Network) connection.The high-frequency switch 1 includes any one of the semiconductor devices 10 and 10A to 10F according to the first to seventh embodiments.In the case of outputting a transmission signal from a transmission system of the wireless communication device 3 to the antenna ANT (i.e., in transmission), the wireless communication device 3 outputs the transmission signal output from the baseband unit BB to the antenna ANT via the high-frequency integrated circuit RFIC, the high-power amplifier HPA, and the high-frequency switch 1.On the other hand, if a received signal received by the antenna ANT is input to a receiving system of the wireless communication device 3 'm' (i.e., upon receiving), the wireless communication device 3 inputs the received signal to the baseband unit BB via the high-frequency switch 1 and the high-frequency integrated circuit RFIC. The received signal processed by the baseband unit BB is output from an output unit such as the voice output unit MIC, the data output unit DT, or the interface unit I / F.Although the technology according to the present disclosure has been described above with reference to the first to seventh embodiments, the technology according to the present disclosure is not limited to the above embodiments, and various modifications may be made.Although the above embodiments assume that the impurity of a first conductivity type is an n-type impurity such as arsenic (As) or phosphorus (P) and the impurity of a second conductivity type is a p-type impurity such as boron (B) or aluminum (Al), these conductivity types may be interchanged, for example. That is, the impurity of a first conductivity type may be a p-type impurity such as boron (B) or aluminum (Al), and the impurity of a second conductivity type may be an n-type impurity such as arsenic (As) or phosphorus (P).For example, the above embodiments specifically describe, as embodiments of the technology according to the present disclosure, the configurations of the high-frequency switch 1, the semiconductor device 10 such as a field effect transistor, and the wireless communication device 3.Further, although the above embodiments describe an example of application of the semiconductor device 10 to the high-frequency switch 1 of the wireless communication device 3, the semiconductor device 10 is also applicable to another high-frequency device such as a PA (power amplifier) in addition to a high-frequency switch (RF-SW).Moreover, the shape, material, and thickness or the film forming method, etc. of each layer described in the above embodiments are not limited to the above, and may be another shape, material, and thickness or may be another film forming method.Not all the configurations and operations described in the embodiments are necessary as the configurations and operations of the present disclosure. For example, components in the embodiments should be understood to mean the component not described in the independent claim that demonstrates the most general concept of the present disclosure as an optional component.The terms used throughout this specification and the appended claims should be construed as "non-limiting" terms. For example, the term "including" or "containing" should be construed as "not limited to what is described as being included.". The term "comprising" should be construed as "not limited to what is described as included.". Further, it will be apparent to those skilled in the art that modifications may be made to the embodiments of the present disclosure without departing from the scope of the appended claims.Terms used in this specification include terms used only for convenience of description and do not limit the configurations and operations. For example, terms such as "right", "left", "on", and "below" indicate only directions on the drawing to which reference is made. Further, the terms "inside" and "outside" indicate a direction toward the center of a component of interest and a direction away from the center of a component of interest, respectively. The same applies to terms similar to these and to terms with the same purpose.It should be noted that the technology according to the present disclosure may have the following configurations. According to the technology according to the present disclosure having the following configurations, it is possible to reduce the off-capacitance of a field effect transistor. Effects of the technology according to the present disclosure are not necessarily limited to the effects described herein, and may be any of the effects described in the present disclosure. (1) A semiconductor device including:a gate electrode;a semiconductor layer including a source region and a drain region with the gate electrode provided therebetween;contact plugs provided on the source region and the drain region;first metals stacked on the respective contact plugs;a first low-permittivity region provided in at least any region sandwiched between the first metals in an in-plane direction of the semiconductor layer and below a lower surface of the first metal in a stacking direction of the semiconductor layer; anda second low-permittivity region provided in at least any region that is between the contact plug and the gate electrode in the in-plane direction and below the first low-permittivity region in the stacking direction,wherein the second low-permittivity region is provided in a planar region at least partially different from a planar region provided with the first low-permittivity region.(2) The semiconductor device according to (1), wherein the first low-permittivity region is provided to further extend to at least any region between an upper surface and the lower surface of the first metal in the stacking direction. (3) The semiconductor device according to (2), wherein the first low-permittivity region is provided so as to further extend to at least any region above the upper surface of the first metal in the stacking direction. (4) The semiconductor device according to any one of (1) to (3), wherein the second low-permittivity region is provided to be continuous with the first low-permittivity region. (5) The semiconductor device according to (4), wherein the first low-permittivity region and the second low-permittivity region each include an air gap, and the air gap included in the first low-permittivity region and the air gap included in the second low-permittivity region are provided so as to be continuous with each other. (6) The semiconductor device according to any one of (1) to (5), further including:one or more insulating films provided on the semiconductor layer to cover the gate electrode; andan opening provided in a planar region corresponding to the gate electrode from an upper surface of the one or more insulating films, whereinthe first low-permittivity region is provided inside the opening.(7) The semiconductor device according to (6), wherein the one or more insulating films include insulating films containing materials having different etching rates. (8) The semiconductor device according to (7), wherein the one or more insulating filmsa first insulating film covering a surface of the gate electrode and a surface of the semiconductor layer,a second insulating film covering a surface of the first insulating film; anda third insulating film provided between a surface of the second insulating film and the lower surface of the first metal; and the first insulating film includes a material having a different etching rate from a material of the second insulating film. (9) The semiconductor device according to (8), wherein in a cross section in the stacking direction, the first low-permittivity region has a width smaller than a width of the first insulating film provided on the surface of the gate electrode. (10) The semiconductor device according to (8) or (9), wherein the opening is provided so as to penetrate at least the third insulating film on the gate electrode. (11) The semiconductor device according to (10), wherein the opening is provided to further penetrate the second insulating film or the second insulating film and the first insulating film on the gate electrode. (12) The semiconductor device according to (10) or (11), wherein the one or more insulating films further include a fourth insulating film covering an upper surface of the third insulating film and a surface of the first metal, and the opening is provided from an upper surface of the fourth insulating film. (13) The semiconductor device according to (12), wherein the one or more insulating films further include a fifth insulating film provided on the fourth insulating film, and the fifth insulating film blocks an upper portion of the opening. (14) The semiconductor device according to (13) further including a second metal provided between the fourth insulating film and the fifth insulating film, wherein the one or more insulating films further include a seventh insulating film covering the upper surface of the fourth insulating film and a surface of the second metal, and the opening is provided from an upper surface of the seventh insulating film. (15) The semiconductor device according to (13) or (14), wherein the fifth insulating film covers at least a portion of a side surface of the opening. (16) The semiconductor device according to any one of (13) to (15), wherein the fifth insulating film includes a material having a lower permittivity than a material included in the third insulating film and the fourth insulating film, and the first low permittivity region includes at least a portion of the opening filled with the fifth insulating film. (17) The semiconductor device according to (6), wherein the one or more insulating filmsa first insulating film covering a surface of the gate electrode and a surface of the semiconductor layer,a second insulating film covering a surface of the first insulating film,a third insulating film provided between a surface of the second insulating film and the lower surface of the first metal,a fourth insulating film covering an upper surface of the third insulating film and a surface of the first metal; anda fifth insulating film provided on the fourth insulating film and blocking the opening; and the second low-permittivity region includes an air gap in the stacking direction provided in a region provided with at least any one of the first insulating film, the second insulating film, and the third insulating film. (18) The semiconductor device according to (17), wherein the air gap included in the second low-permittivity region exposes at least a portion of the first insulating film. (19) The semiconductor device according to (18), wherein the air gap included in the second low-permittivity region exposes the first insulating film provided on the surface of the semiconductor layer. (20) The semiconductor device according to (19), wherein the air gap included in the second low-permittivity region further exposes at least a portion of the gate electrode. (21) The semiconductor device according to any one of (17) to (20), wherein the air gap included in the second low-permittivity region is provided so as to be continuous with the opening provided from an upper surface of the fourth insulating film so as to penetrate at least the third insulating film on the gate electrode. (22) The semiconductor device according to (21), wherein the fifth insulating film covers at least a portion of a side surface or a bottom surface of the air gap included in the second low-permittivity region. (23) The semiconductor device according to any one of (17) to (22), wherein in a cross section in the stacking direction, a region provided with the second low-permittivity region has a width larger than a width of the first insulating film provided on the surface of the gate electrode. (24) The semiconductor device according to any one of (17) to (23), wherein the fifth insulating film includes a material having a lower permittivity than a material included in the third insulating film and the fourth insulating film, and the second low permittivity region includes a region filled with the fifth insulating film. (25) The semiconductor device according to any one of (1) to (24, wherein the gate electrode is provided to extend in a direction in the in-plane direction, and the contact plug, the first metal, the first low-permittivity region, and the second low-permittivity region are provided to extend in a direction parallel to the extending direction of the gate electrode in the in-plane direction. (26) The semiconductor device according to (25), wherein the first low-permittivity region and the second low-permittivity region are provided so as to extend in a direction crossing the extending direction of the gate electrode in the in-plane direction. (27) The semiconductor device according to any one of (1) to (26), wherein the gate electrode includes a plurality of finger parts extending in a same direction and a connection part connecting the plurality of finger parts, the first low-permittivity region is provided above the finger part or above at least a portion of the connection part, and the second low-permittivity region is provided on a side wall of the finger part or a side wall of at least a portion of the connection part. (28) The semiconductor device according to any one of (1) to (27), wherein the semiconductor device includes in the in-plane directiona device region including the source region and the drain region; anda wiring region including a multilayer wiring part and separated from the device region by a device isolation layer; and the first low-permittivity region and the second low-permittivity region are provided in the device region. (29) The semiconductor device according to (28), wherein the semiconductor device includes in the in-plane directionan active region including the device region and the wiring region; anda device isolation region including the device isolation layer and provided outside the active region, a gate contact coupled to the gate electrode is provided on the device isolation layer of the device isolation region, and the first low-permittivity region and the second low-permittivity region are provided so as to avoid the gate contact. (30) The semiconductor device according to any one of (1) to (29), wherein the semiconductor device is used as a field effect transistor for a high-frequency device. (31) A method of manufacturing a semiconductor device, the method comprising:a step of forming a gate electrode on a side of an upper surface of a semiconductor layer;a step of forming, in the semiconductor layer, a source region and a drain region with the gate electrode therebetween;a step of forming contact plugs on the source region and the drain region;a step of stacking first metals on the respective contact plugs;a step of forming a first low-permittivity region in at least any region interposed between the first metals in an in-plane direction of the semiconductor layer and below a lower surface of the first metal in a stacking direction of the semiconductor layer; anda step of forming a second low-permittivity region in at least any region that is between the contact plug and the gate electrode in the in-plane direction and below the first low-permittivity region in the stacking direction,wherein the second low-permittivity region is formed in a planar region that is at least partially different from a planar region in which the first low-permittivity region is formed.

Claims

A semiconductor device, comprising: a gate electrode (20); a semiconductor layer (50) including a source region (50S) and a drain region (50D), the gate electrode (20) being provided therebetween along a lateral direction (X); contact plugs (60S, 60D) provided on the source region (50S) and the drain region (50D); first metals (M1) stacked on the respective contact plugs (60S, 60D); a first low-permittivity region (70) provided in at least one region interposed between the first metals (M1) in an in-plane direction of the semiconductor layer (50) and below a lower surface of the first metal (M1) in a stacking direction (Z) of the semiconductor layer (50), the first region (70) being disposed in direct extension along the stacking direction (Z) of the semiconductor layer (50) with respect to a center of the gate electrode (20) along the lateral direction (X); and a second low-permittivity region (71) provided in at least one region interposed between the contact plugs (60S, 60D) and having the plane orientation of the plane of the semiconductor layer (50) and, starting from the semiconductor layer (50), being below the first low-permittivity region (70) in the stacking direction, wherein the second low-permittivity region (71) is provided in a planar region at least partially different from a planar region provided with the first low-permittivity region (70), in plan view, and wherein a width (W 70) of the first region (70) is smaller than a width of the second region (71).The semiconductor device according to claim 1, wherein the first low-permittivity region (70) is provided to further extend to at least one region between an upper surface and the lower surface of the first metal (M1) in the stacking direction (Z).The semiconductor device according to claim 2, wherein the first low-permittivity region (70) is provided to further extend to at least one region above the upper surface of the first metal (M1) in the stacking direction (Z).The semiconductor device according to any one of the preceding claims, wherein the second low-permittivity region (71) is provided to be continuous with the first low-permittivity region (70).The semiconductor device according to claim 4, wherein the first low-permittivity region (70) and the second low-permittivity region (71) each include an air gap (AG), and the air gap (AG) included in the first low-permittivity region (70) and the air gap (AG) included in the second low-permittivity region (71) are provided so as to be continuous with each other.The semiconductor device according to any one of the preceding claims, further comprising: one or more insulating films (81, 82, 83, 84, 85, 86, 87) provided on the semiconductor layer (50) to cover the gate electrode; and an opening (P) provided in a planar region corresponding to the gate electrode (20) from an upper surface of the one or more insulating films (81, 82, 83, 84, 85, 86, 87), wherein the first low-permittivity region (70) is provided inside the opening (P).The semiconductor device of claim 6, wherein the one or more insulating films (81, 82, 83, 84, 85, 86, 87) comprise insulating films containing materials having different etching rates.The semiconductor device according to claim 7, wherein the one or more insulating films (81, 82, 83, 84, 85, 86, 87) include a first insulating film (81) covering a surface of the gate electrode (20) and a surface of the semiconductor layer (50), a second insulating film (82) covering a surface of the first insulating film (81), and a third insulating film (83) provided between a surface of the second insulating film (82) and the bottom surface of the first metal (M1), and the first insulating film (81) includes a material having a different etching rate from a material of the second insulating film (82).The semiconductor device according to claim 8, wherein in a cross section in the stacking direction, the first low-permittivity region (70) has a width (W70) smaller than a width (W81) of the first insulating film (81) provided on the surface of the gate electrode (20).The semiconductor device according to claim 8 or 9, wherein the opening (P) is provided so as to penetrate at least the third insulating film (83) on the gate electrode (20).The semiconductor device according to claim 10, wherein the opening (P) is provided to further penetrate the second insulating film (82) or the second insulating film (82) and the first insulating film (81) on the gate electrode (20).The semiconductor device according to claim 10 or 11, wherein the one or more insulating films (81, 82, 83, 84, 85) further comprise a fourth insulating film (84) covering an upper surface of the third insulating film (83) and a surface of the first metal (M1), and the opening (P) is provided from an upper surface of the fourth insulating film (84).The semiconductor device according to claim 12, wherein the one or more insulating films (81, 82, 83, 84, 85, 86, 87) further comprise a fifth insulating film (85) provided on the fourth insulating film (84), and the fifth insulating film (85) blocks an upper portion of the opening (P).The semiconductor device according to claim 13, further comprising a second metal (M2) provided between the fourth insulating film (84) and the fifth insulating film (85), wherein the one or more insulating films (81, 82, 83, 84, 85, 86, 87) further comprise a seventh insulating film (87) covering the upper surface of the fourth insulating film (84) and a surface of the second metal (M2), and the opening (P) is provided from an upper surface of the seventh insulating film (87).The semiconductor device according to claim 13 or 14, wherein the fifth insulating film (85) covers at least a portion of a side surface of the opening (P).The semiconductor device according to any one of claims 13 to 15, wherein the fifth insulating film (85) includes a material having a lower permittivity than a material included in the third insulating film (83) and the fourth insulating film (84), and the first low permittivity region (70) includes at least a portion of the opening (P) filled with the fifth insulating film (85).The semiconductor device according to claim 6, wherein the one or more insulating films (81, 82, 83, 84, 85, 86, 87) include a first insulating film (81) covering a surface of the gate electrode (20) and a surface of the semiconductor layer (50), a second insulating film (82) covering a surface of the first insulating film (81), a third insulating film (83) provided between a surface of the second insulating film (82) and the bottom surface of the first metal (M1), a fourth insulating film (84) covering a top surface of the third insulating film (83) and a surface of the first metal (M1), and a fifth insulating film (85) provided on the fourth insulating film (84) and blocking the opening (P), and the second low-permittivity region ( 71) includes an air gap (AG) provided in a region provided with at least any one of the first insulating film ( 81), the second insulating film ( 82), and the third insulating film ( 83) in the stacking direction (Z).The semiconductor device according to claim 17, wherein the air gap (AG) included in the second low-permittivity region (71) exposes at least a portion of the first insulating film (81).The semiconductor device according to claim 18, wherein the air gap (AG) included in the second low-permittivity region (71) exposes the first insulating film (81) provided on the surface of the semiconductor layer (50).The semiconductor device of claim 19, wherein the air gap (AG) included in the second low-permittivity region (71) further exposes at least a portion of the gate electrode (20).The semiconductor device according to any one of claims 17 to 20, wherein the air gap (AG) included in the second low-permittivity region (71) is provided so as to be continuous with the opening (P) provided from an upper surface of the fourth insulating film (84) so as to penetrate at least the third insulating film (83) on the gate electrode (20).The semiconductor device according to claim 21, wherein the fifth insulating film (85) covers at least a portion of a side surface or a bottom surface of the air gap (AG) included in the second low-permittivity region (71).The semiconductor device according to any one of claims 17 to 22, wherein in a cross section in the stacking direction (Z), a region provided with the second low-permittivity region (71) has a width larger than a width of the first insulating film (81) provided on the surface of the gate electrode (20).The semiconductor device according to any one of claims 17 to 23, wherein the fifth insulating film (85) includes a material having a lower permittivity than a material included in the third insulating film (83) and the fourth insulating film (84), and the second low permittivity region (71) includes a region filled with the fifth insulating film (85).The semiconductor device according to any one of the preceding claims, wherein the gate electrode (20) is provided to extend in a direction in the in-plane direction, and the contact plug (60S), the first metal (M1), the first low-permittivity region (70), and the second low-permittivity region (71) are provided to extend in a direction parallel to the extending direction of the gate electrode (20) in the in-plane direction.The semiconductor device according to claim 25, wherein the first low-permittivity region (70) and the second low-permittivity region (71) are provided to extend in a direction crossing the extending direction of the gate electrode (20) in the in-plane direction.The semiconductor device according to any one of the preceding claims, wherein the gate electrode (20) comprises a plurality of finger parts extending in a same direction and a connection part connecting the plurality of finger parts, the first low-permittivity region (70) is provided above the finger part or above at least a portion of the connection part, and the second low-permittivity region (71) is provided on a side wall of the finger part or a side wall of at least a portion of the connection part.The semiconductor device according to any one of the preceding claims, wherein the semiconductor device is provided in the in-plane direction with a device region including the source region (50S) and the drain region (50D) and a wiring region including a multilayer wiring part and separated from the device region by a device isolation layer (100), and the first low-permittivity region (70) and the second low-permittivity region (71) are provided in the device region.The semiconductor device according to claim 28, wherein the semiconductor device is provided in the in-plane direction with an active region (AA) including the device region (AA1) and the wiring region and a device isolation region including the device isolation layer (100) and provided outside the active region, a gate contact (GC) coupled to the gate electrode (20) is provided on the device isolation layer of the device isolation region, and the first low permittivity region (70) and the second low permittivity region (70) are provided so as to avoid the gate contact (GC).A semiconductor device according to any preceding claim, wherein the semiconductor device is used as a field effect transistor for a high frequency device.A method of manufacturing a semiconductor device, the method comprising: a step of forming a gate electrode (20) on a side of an upper surface of a semiconductor layer (50); a step of forming, in the semiconductor layer (50), a source region (50S) and a drain region (50D) with the gate electrode (20) along a lateral direction (X) therebetween; a step of forming contact plugs (60S, 60D) on the source region (50S) and the drain region (50D); a step of stacking first metals (M1) on the respective contact plugs (50S, 50D); a step of forming a first low-permittivity region (70) in at least one region interposed between the first metals (M1) in an in-plane direction of the semiconductor layer (50) and below a lower surface of the first metal (M1) in a stacking direction (Z) of the semiconductor layer (50), wherein the first region (70) is disposed in direct extension along the stacking direction (Z) of the semiconductor layer (50) with respect to a center of the gate electrode (20) along the lateral direction (X); and a step of forming a second low-permittivity region (71) in at least one region interposed between the contact plugs (60S, 60D) and with the planar orientation of the plane of the semiconductor layer (50) and, starting from the semiconductor layer (50), being below the first low-permittivity region (70) in the stacking direction, wherein the second low-permittivity region (71) is formed in a planar region at least partially different from a planar region in which the first low-permittivity region (70) is formed, in plan view, and wherein a width (W 70) of the first region (70) is smaller than a width of the second region (71).

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