SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

Abstract

A semiconductor device (100) having a transistor section (70) and a diode section (80), comprising: a drift region (18) of a first conductivity type arranged in a semiconductor substrate (10); a collection region (16) of a first conductivity type arranged with respect to the drift region (18) on a front surface side (21) of the semiconductor substrate (10) in the transistor section (70) and in the diode section (80), the collection region (16) comprising: a first collection region (16a) arranged closer to the front surface side (21) than the drift region (18); and a second collection area (16b) arranged below the first collection area (16a); and a first lifetime control region (150) arranged on the front surface side (21) of the semiconductor substrate (10) in the transistor section (70) and in the diode section (80), wherein the doping concentrations of the first collection region (16a) and the second collection region (16b) are identical, and a sum of integrated concentrations obtained by integrating the doping concentrations of the first collection region (16a) and the second collection region (16b) over a depth direction of the first collection region (16a) and the second collection region (16b) is 1 × 10 12 cm -3 up to 1 × 10 13 cm -3 amounts.

Description

TECHNICAL BACKGROUND1. TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. 2. STATE OF THE ART

[0002] A conventional semiconductor device having a transistor section and a diode section is known (see, for example, Patent Documents 1 to 8). Patent Document 1: Japanese Patent Application No. JP 2015-138801 A Patent Document 2: Japanese Patent Application No. JP 2017-011 000 A Patent document 3: WO 2018 / 030 440 A1 Patent document 4: WO 2019 / 142 706 A1 Patent document 5: US 2018 / 0 108 737 A1 Patent document 6: US 2018 / 0 151 557 A1 Patent document 7: US 2019 / 0 287 961 A1 Patent document 8: WO 2019 / 244 485 A1 TASKS TO BE SOLVED

[0003] In the conventional semiconductor device, it is preferred to improve the balance of carriers between the transistor portion and the diode portion. GENERAL REVELATION

[0004] A first aspect of the present invention relates to a semiconductor device according to claim 1.

[0005] The first lifetime control region may be arranged in the entire surface of the semiconductor substrate.

[0006] The semiconductor device may include the second lifetime control region arranged on the entire back surface side of the semiconductor substrate.

[0007] The semiconductor device may include a plurality of trench portions arranged in the front surface of the semiconductor substrate. The depth of the first lifetime control region may be deeper than the depths of the plurality of trench portions.

[0008] The depth of the collection area may be within the trench depths of the plurality of trench sections.

[0009] The depth of the first lifetime control region may be deeper than twice the depth of the boundary with the drift region of the collection region.

[0010] The depth of the first lifetime control region can be 5 µm to 20 µm.

[0011] The dosage of the lifetime killer in the first lifetime control area can be 0.5 × 10 10 cm -2 up to 1 × 10 13 cm -2 be.

[0012] The first lifetime control region can be implanted from the back surface side of the semiconductor substrate.

[0013] The collection region includes a first collection region disposed on the front surface side of the drift region and a second collection region disposed below the first collection region.

[0014] The dosage of ion implantation in the collection area can be 1 × 10 12 cm -2 up to 1 × 10 13 cm -2 be.

[0015] The depth of the collection area can be 1 µm to 5 µm.

[0016] The transistor section may include an emitter region of a first conductivity type having a higher doping concentration than the drift region. The collection region may be arranged in a wider region than the region where the emitter region is arranged in plan view.

[0017] The transistor portion may include a boundary portion adjacent to the diode portion and a dummy trench portion electrically connected to the emitter electrode. The trench portion of the trench portion may be a dummy trench portion.

[0018] The boundary portion may include the collection region, a base region of a second conductivity type arranged on the front surface side, a contact region arranged on the front surface side of the base region and having a higher doping concentration than the base region, and a plug region of a second conductivity type arranged on a front surface side of the contact region and having a higher doping concentration than the contact region.

[0019] The boundary section cannot have an emitter region.

[0020] A second aspect of the present invention relates to a method of manufacturing a semiconductor device according to claim 16. Further aspects of the invention are the subject of the subclaims, the drawings and the description of embodiments.

[0021] Disposing the first lifetime control region may include irradiating impurities from the back surface side of the semiconductor substrate.

[0022] The arrangement of the first lifetime control region may allow implanting impurities with a dosage in the range of 0.5 × 10 10 cm -2 up to 1 × 10 13 cm -2 include.

[0023] Arranging the collection area can perform ion implantation with a dosage in the range of 3 × 10 12 cm -2 up to 6 × 10 12 cm -2 include.

[0024] The summary does not necessarily describe all necessary features of the embodiments of the present invention. The present invention may also be a subcombination of the features described above. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A illustrates an example of a top view of a semiconductor device 100 according to an embodiment. Fig. Figure 1B is a diagram showing an example of a cross section along the line aa' in Fig. 1A illustrated. Fig. Figure 1C is a diagram showing an example of a cross section along the line bb' in Fig. 1A illustrated. Fig. 2A illustrates an example of a top view of the semiconductor device 100 according to an embodiment. Fig. Figure 2B is a diagram showing an example of a cross section along the line cc' in Fig. 2A illustrated. Fig. Figure 2C is a diagram showing an example of a cross section along the line dd' in Fig. 2A illustrated. Fig. 2D is a diagram for describing a difference in properties depending on the number of stages of a collection area 16. Fig. 3 is an example of an enlarged sectional view in the vicinity of a mesa section 71. Fig. 4 illustrates an example of a top view of a chip finish of the semiconductor device 100. Fig. 5 is an example of a sectional view of a semiconductor device 500 according to a comparative example. DESCRIPTION OF THE EMBODIMENTS

[0025] The present invention is described below using exemplary embodiments of the invention. The following exemplary embodiments do not limit the invention disclosed in the claims. Furthermore, not all combinations of features described in the exemplary embodiments are essential to the inventive solution.

[0026] As used in this specification, one side in a direction parallel to a depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." One surface of two main surfaces of a substrate, layer, or other member is referred to as an upper surface, and the other surface is referred to as a lower surface. The "top," "bottom," "front," and "back" directions are not limited to a direction of gravity or a direction of attachment to a substrate, or the like, when the semiconductor device is mounted.

[0027] In this specification, technical matters may be described using orthogonal coordinate axes X, Y, and Z. In this specification, a plane parallel to a top surface of the semiconductor substrate is defined as an XY plane, and a depth direction of the semiconductor substrate is defined as a Z axis. In this specification, a case where the semiconductor substrate is viewed in the Z axis direction is referred to as a plan view.

[0028] In each embodiment, an example in which a first conductivity type is N-type and a second conductivity type is P-type is shown, but the first conductivity type may be P-type and the second conductivity type may be N-type. In this case, the conductivity types of a substrate, a layer, and the like in each embodiment have opposite polarities.

[0029] In this specification, when a layer or region is designated with n or p, it means that electrons or holes are the majority charge carriers. Additionally, a + or - added to n or p means that the doping concentration is higher or lower than that of an n or p layer or region without addition, ++ means that the doping concentration is higher than +, and -- means that the doping concentration is lower than -.

[0030] In this specification, the doping concentration refers to the concentration of the dopant as donor or acceptor. The unit is therefore / cm 3. In the present specification, a concentration difference between donor and acceptor (i.e., a net doping concentration) may be referred to as a doping concentration. In this case, the doping concentration may be measured by the srp method. In addition, the chemical concentrations of the donor and the acceptor may be the doping concentration. In this case, the doping concentration may be measured by a SIMS method. Any of the above may be used as the doping concentration unless otherwise specified. Unless otherwise specified, the peak value of the doping concentration distribution in the doping region may be used as the doping concentration in the doping region.

[0031] Furthermore, in this specification, the dosage refers to the number of ions per unit area where ions are implanted into the wafer when ion implantation is performed. The unit is therefore / cm 2 Note that the doping concentration of the semiconductor region can be an integrated concentration obtained by integrating the doping concentration along the depth direction of the semiconductor region. The unit of the integrated concentration is / cm 2 . The dosage and the integrated concentration can thus be considered equal. The integrated concentration can be an integrated value up to the half-width, and if the integrated concentration overlaps with the spectrum of another semiconductor region, the integrated concentration can be derived by excluding the influence of the other semiconductor region.

[0032] Therefore, in the present description, the doping concentration level can be understood as the dosage level. That is, if a doping concentration of one region is higher than the doping concentration of the other region, this can be understood to mean that the dosage of that one region is higher than the dosage of the other region.

[0033] Fig. 1A illustrates an example of a top view of a semiconductor device 100 according to an embodiment. The semiconductor device 100 of the present example is a semiconductor chip including a transistor section 70 and a diode section 80. For example, the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT).

[0034] The transistor section 70 is a region formed by projecting the collector region 22 arranged on the back surface side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The collector region 22 is of a second conductivity type. The collector region 22 of the present example is, for example, P + -like. The transistor section 70 includes a transistor, such as an IGBT. The transistor section 70 includes a boundary section 90 disposed at a boundary between the transistor section 70 and the diode section 80.

[0035] The diode portion 80 is a region formed by projecting the cathode region 82 disposed on the back surface of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The cathode region 82 has a first conductivity type. The cathode region 82 of the present example is, for example, N +-like. The diode section 80 comprises a diode, such as a freewheeling diode (FWD), arranged adjacent to the transistor section 80 on the upper surface of the semiconductor substrate 10.

[0036] In Fig. 1A illustrates a region around a chip end portion, which is an edge side of the semiconductor device 100, and omits other regions. For example, an edge termination structure portion may be disposed in a region on the negative side in the Y-axis direction of the semiconductor device 100 of the present example. The edge termination structure portion reduces the electric field strength on the upper surface side of the semiconductor substrate 10. The edge termination structure portion 90 includes, for example, a guard ring, a field plate, a RESURF, and a combination thereof. Note that, in the present example, for simplicity, the edge on the negative side in the X-axis direction is described, but the same applies to other edges of the semiconductor device 100.

[0037] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, or the like. The semiconductor substrate 10 of the present example is a silicon substrate.

[0038] The semiconductor device 100 of the present example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on the front surface of the semiconductor substrate 10. Furthermore, the semiconductor device 100 of the present example includes an emitter electrode 52 and a gate metal layer 50 arranged above the front surface of the semiconductor substrate 10.

[0039] The emitter electrode 52 is arranged above the gate trench section 40, the dummy trench section 30, the emitter region 12, the base region 14, the contact region 15, and the drain region 17. The gate metal layer 50 is arranged above the gate trench section 40 and the drain region 17.

[0040] The emitter electrode 52 and the gate metal layer 50 are formed from a material that contains metal. For example, at least a portion of the emitter electrode 52 may be formed from aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. At least a portion of the gate metal layer 50 may be formed from aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. The emitter electrode 52 and the gate metal layer 50 may include a metal barrier made of titanium, a titanium composite, or the like, disposed in a lower layer of a portion made of aluminum or the like. The emitter electrode 52 and the gate metal layer 50 are spaced apart from each other.

[0041] The emitter electrode 52 and the gate metal layer 50 are arranged above the semiconductor substrate 10 with an interlayer dielectric film 38 therebetween. The interlayer dielectric film 38 was Fig. 1A is omitted. A contact hole 54, a contact hole 55, and a contact hole 56 are provided through the interlayer dielectric film 38.

[0042] The contact hole 55 connects the gate metal layer 50 and the gate line portion in the transistor portion 70. A plug made of tungsten or the like may be formed in the contact hole 55.

[0043] The contact hole 56 connects the emitter electrode 52 and the dummy line portion in the dummy trench portion 30. A plug made of tungsten or the like may be formed in the contact hole 56.

[0044] The connecting portion 25 electrically connects the electrode on the front surface side, such as the emitter electrode 52 or the gate metal layer 50, to the semiconductor substrate 10. In one example, the connecting portion 25 is disposed between the gate metal layer 50 and the gate line portion. The connecting portion 25 is also disposed between the emitter electrode 52 and the dummy line portion. The connecting portion 25 is a material with conductivity, such as polysilicon doped with impurities. Here, the connecting portion 25 is polysilicon (N+) doped with N-type impurities. The connecting portion 25 is disposed above the front surface of the semiconductor substrate 10 via a dielectric film, such as an oxide film or the like.

[0045] The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (in the present example, the X-axis direction). The gate trench portion 40 in the present example may include two extension portions 41 extending along an extension direction (in the present example, the Y-axis direction) parallel to the front surface of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connecting portion 43 connecting the two extension portions 41.

[0046] Preferably, at least a part of the connecting portion 43 is formed in a curved shape. By connecting the end portions of the two extension portions 41 of the gate trench portion 40, the electric field strength at the end portion of the extension portion 41 can be reduced. The gate metal layer 50 can be connected to the gate line portion at the connecting portion 43 of the gate trench portion 40.

[0047] The dummy trench portion 30 is a trench portion electrically connected to the emitter electrode 52. Similar to the gate trench portion 40, the dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (in the present example, the X-axis direction). Similar to the gate trench portion 40, the dummy trench portion 30 of the present example may have a U-shape on the front surface of the semiconductor substrate 10. That is, the dummy trench portion 30 may have two extension portions 31 extending along the extension direction and a connecting portion 33 connecting the two extension portions 31.

[0048] The transistor section 70 of the present example has a structure in which two gate trench sections 40 and three dummy trench sections 30 are repeatedly arranged. That is, the transistor section 70 of the present example includes the gate trench section 40 and the dummy trench section 30 in a ratio of 2:3. For example, the transistor section 70 includes an extension section 31 between the two extension sections 41. The transistor section 70 includes two extension sections 31 adjacent to the gate trench section 40.

[0049] However, the ratio between the gate trench portion 40 and the dummy trench portion 30 is not limited to the present example. The ratio between the gate trench portion 40 and the dummy trench portion 30 may be 1:1 or 2:4. Furthermore, the transistor portion 70 may have a so-called full gate structure in which the dummy trench portion 30 is not disposed and the gate trench portion 40 is disposed throughout.

[0050] The well region 17 is a second conductivity type region located closer to the front surface side of the semiconductor substrate 10 than the drift region 18 described later. The well region 17 is an example of a well region located on the edge side of the semiconductor device 100. The well region 17 is P in an example. +-like. The well region 17 is formed in a predetermined range from the end portion of the active region, on the side where the gate metal layer 50 is arranged. The diffusion depth of the well region 17 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. A partial area of ​​the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side is formed in the well region 17. The bottoms of the ends of the gate trench portion 40 and the dummy trench portion 30 in the extension direction may be covered by the well region 17.

[0051] The contact hole 54 is formed over each emitter region 12 and contact region 17 in the transistor section 70. Furthermore, the contact hole 54 is disposed over the base region 14 in the diode section 80. The contact hole 54 is disposed over the contact region 15 in the boundary section 90. The contact hole 54 is disposed over the base region 14 in the diode section 80. None of the contact holes 54 is disposed over the well regions 17 located at both ends of the Y-axis direction. As described above, one or more contact holes 54 are formed in the interlayer dielectric film. One or a plurality of contact holes 54 may be arranged extending in the extension direction. A plug region 19 may be disposed under the contact hole 54. The plug region 19 will be described later.

[0052] The boundary portion 90 is a region located in the transistor portion 70 and adjacent to the diode portion 80. The boundary portion 90 includes the contact region 15. The boundary portion 90 of the present example does not include the emitter region 12. In one example, the trench portion of the boundary portion 90 is a dummy trench portion 30. The boundary portion 90 of the present example is arranged such that both ends in the X-axis direction become dummy trench portions 30.

[0053] A mesa portion 71, a mesa portion 91, and a mesa portion 81 are mesa portions arranged adjacent to the trench portions in a plane parallel to the front surface of the semiconductor substrate 10. The mesa portion is a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions and may be a portion extending from the front surface of the semiconductor substrate 10 to the depth of the deepest bottom portion of each trench portion. The extension portion of each trench portion may be a trench portion. That is, a region sandwiched between the two extension portions may be a mesa portion.

[0054] The mesa section 71 is arranged next to at least one dummy trench section 90 and / or gate trench section 40 in the transistor section 70. The mesa section 71 comprises the well region 17, the emitter region 12, the base region 14, and the contact region 15 on the front surface of the semiconductor substrate 10. In the mesa section 71, the emitter regions 12 and the contact regions 15 are arranged alternately in the extension direction.

[0055] The mesa section 91 is arranged in the boundary section 90. The mesa section 91 includes the contact region 15 and the well region 17 on the front surface of the semiconductor substrate 10.

[0056] The mesa section 81 is arranged in a region enclosed between the adjacent dummy trench sections 30 in the diode section 80. The mesa section 81 includes the base region 14, the contact region 15, and the well region 17 on the front surface of the semiconductor substrate 10.

[0057] The base region 14 is a region of the second conductivity type arranged on the front surface side of the semiconductor substrate 10 in the transistor section 70 and the diode section 80. The base region 14 is P in one example. - -like. The base region 14 may be arranged at both end portions of the mesa portion 71 and the mesa portion 91 in the Y-axis direction on the front surface of the semiconductor substrate 10. Fig. 1A illustrates only one end portion of the base region 14 in the Y-axis direction.

[0058] The emitter region 12 is a region of the first conductivity type, which has a higher doping concentration than the drift region 18. The emitter region 12 of the present example is, for example, an N +-type emitter region. An example of the dopant of emitter region 12 is arsenic (As). Emitter region 12 is arranged in contact with gate trench portion 40 on the front surface of mesa portion 71. Emitter region 12 may be arranged extending in the X-axis direction from one of the two trench portions enclosing mesa portion 71 to the other portion. Emitter region 12 is also arranged below contact hole 54.

[0059] Furthermore, the emitter region 12 may or may not be connected to the dummy trench portion 30. The emitter region 12 of the present example is connected to the dummy trench portion 30. The emitter region 12 may not be arranged in the mesa portion 91 of the boundary portion 90.

[0060] The contact region 15 is a region of the second conductivity type, which has a higher doping concentration than the base region 14. The contact region 15 of the present example is, for example, P +-like. The contact region 15 of the present example is arranged in front surfaces of the mesa section 71 and the mesa section 91. The contact region 15 may be arranged extending in the X-axis direction from one of the two trench sections including the mesa section 71 or the mesa section 91 to the other section. The contact region 15 may or may not be connected to the gate trench section 40. Furthermore, the contact region 15 may or may not be connected to the dummy trench section 30. In the present example, the contact region 15 is connected to the dummy trench section 30 and the gate trench section 40. The contact region 15 is also arranged below the contact hole 54. Note that the contact region 15 may also be arranged in the mesa section 81.

[0061] Fig. Figure 1B is a diagram showing an example of a cross section along the line aa' in Fig. 1A. Cross section aa' is an XZ plane passing through the emitter region 12 in the transistor section 70. The semiconductor device 100 of the present example includes, in cross section aa', the semiconductor substrate 10, the interlayer dielectric film 38, the emitter electrode 52, and the collector electrode 24. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer dielectric film 38.

[0062] The drift region 18 is a region of the first conductivity type disposed in the semiconductor substrate 10. The drift region 18 of the present example is, for example, N--type. The drift region 18 may be a region that remains without another doping region disposed in the semiconductor substrate 10. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0063] The buffer region 20 is a region of the first conductivity type located below the drift region 18. The buffer region 20 of the present example is, for example, N + -like. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 can serve as a field stop layer that prevents a depletion layer spreading from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type and the cathode region 82 of the first conductivity type.

[0064] The collector region 22 is disposed below the buffer region 20 in the transistor section 70. The cathode region 82 is disposed below the buffer region 20 in the diode section 80. A boundary between the collector region 22 and the cathode region 82 is a boundary between the transistor section 70 and the diode section 80.

[0065] The collector electrode 24 is formed on a backside 23 of the semiconductor substrate 10. The collector electrode 24 is formed of a conductive material such as metal.

[0066] The base region 14 is a second conductivity type region disposed above the drift region 18 in the mesa section 71, the mesa section 91, and the mesa section 81. The base region 14 is connected to the gate trench section 40. The base region 14 is connected to the dummy trench section 30.

[0067] The emitter region 12 is disposed between the base region 14 and the front surface 21 in the mesa section 71. The emitter region 12 is connected to the gate trench section 40. The emitter region 12 may or may not be connected to the dummy trench section 30. The emitter region 12 may not be located in the mesa section 91.

[0068] The contact region 15 is arranged above the base region 14 in the mesa section 91. The contact region 15 is connected to the gate trench section 40 in the mesa section 91. In another cross-section, the contact region 15 can be arranged in the front surface 21 of the mesa section 71.

[0069] The plug region 19 is a region of the second conductivity type, which has a higher doping concentration than the contact region 15. The plug region 19 of the present example is, for example, P ++ -like. The connector region 19 of the present example is arranged in the front surface 21. In the mesa section 91, the connector region 19 is arranged above the contact region 15. In the mesa section 81, the connector region 19 is arranged above the base region 14. The connector region 19 can be arranged in the mesa section 91 and in the mesa section 81, extending in the Y-axis direction along the contact hole 54.

[0070] The collection region 16 is a region of the first conductivity type, which is arranged closer to the front surface side 21 of the semiconductor substrate 10 than the drift region 18. The collection region 16 of the present example is, for example, N + -like. The collection region 16 is arranged in the transistor section 70 and the diode section 80. The collection region 16 of the present example is also arranged in the boundary section 90. As a result, the semiconductor device 100 can prevent the mask from deviating from the collection region 16.

[0071] The collection region 16 is arranged connected to the gate trench section 40. The collection region 16 may or may not be connected to the dummy trench section 30. The doping concentration of the collection region 16 is higher than the doping concentration of the drift region 18. The ion implantation dosage of the collection region 16 may be 1 × 10 12 cm -2 up to 1 × 10 13 cm -2In addition, the dosage of ion implantation of the collection area can be 16 3 × 10 12 cm -2 up to 6 × 10 12 cm -2 By providing the collection region 16, the injection enhancement (IE) effect can be enhanced and the ON voltage of the transistor section 70 can be reduced. Note that E in Fig. 2D denotes a power to the base 10, and for example 1E12 cm -2 means 1 × 10 12 cm -2 .

[0072] One or more gate trench portions 40 and one or more dummy trench portions 30 are arranged on the front surface 21. Each trench portion is arranged from the front surface 21 to the drift region 18. In a region where at least one of the emitter region 12, the base region 14, the contact region 15, and the collection region 16 is arranged, each trench portion also penetrates these regions and reaches the drift region 18. The trench portion penetrating the impurity region is not limited to those formed in the order of forming the impurity region and then forming the trench portion. A case where an impurity region is formed between the trench portions after the trench portion is formed is also included in a case where the trench portion penetrates the impurity region.

[0073] The gate trench portion 40 includes a gate trench on the front surface 21, a gate dielectric film 42, and a gate line portion 44. The gate dielectric film 42 is formed to cover the inner wall of the gate trench. The gate dielectric film 42 can be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate line portion 44 is formed within the gate dielectric film 42 in the gate trench. The gate dielectric film 42 insulates the gate line portion 44 from the semiconductor substrate 10. The gate line portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered with the interlayer dielectric film 38 on the front surface 21.

[0074] The gate line portion 44 includes a region facing the base region 14 adjacent to the mesa portion 71, with the gate dielectric film 42 interposed therebetween in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate line portion 44, a channel is formed by an inversion layer of electrons in a surface layer of an interface in contact with the gate trench in the base region 14.

[0075] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 includes a dummy trench formed on the front surface 21 side, a dummy dielectric film 32, and a dummy wiring portion 34. The dummy dielectric film 32 is formed covering the inner wall of the dummy trench. The dummy wiring portion 34 is formed in the dummy trench and within the dummy dielectric film 32. The dummy dielectric film 32 insulates the dummy wiring portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered by the interlayer dielectric film 38 on the front surface 21.

[0076] The interlayer dielectric film 38 is disposed on the front surface 21. The emitter electrode 52 is disposed above the interlayer dielectric film 38. The interlayer dielectric film 38 has one or more contact holes 54 for electrically connecting the emitter electrode 52 and the semiconductor substrate 10. Similarly, the contact hole 55 and the contact hole 56 may be disposed through the interlayer dielectric film 38.

[0077] The lifetime control region 150 is a region where a lifetime killer is intentionally formed, for example, by implanting impurities into the semiconductor substrate 10. The lifetime killer is the recombination center of the charge carrier. The lifetime killer may be a crystal defect. For example, the lifetime killer may be a vacancy, a double vacancy, a defect complex of these and an element constituting the semiconductor substrate 10, or a dislocation. Furthermore, the lifetime killer may be a rare gas element such as helium or neon, a metal element such as platinum, or the like. A lifetime control region 150 may be formed by implanting helium or the like into the semiconductor substrate 10.

[0078] The lifetime control region 150 is arranged on the front surface side 21 of the semiconductor substrate 10. The lifetime control region 150 is arranged in both the transistor section 70 and the diode section 80. The lifetime control region 150 can be formed by implanting impurities from the front surface side 21 or by implanting impurities from the back surface side 23. The lifetime control region 150 is an example of a first lifetime control region arranged on the front surface side 21.

[0079] The lifetime control region 150 of the present example is arranged on the entire surface of the semiconductor substrate 10. Thus, the lifetime control region 150 can be formed without using a mask. The dosage of impurities for forming the lifetime control region 150 can be 0.5 × 10 10 cm -2 up to 1 × 10 13 cm -2The dosage of impurities to form the lifetime control region 150 can be 5 × 10 10 cm -2 up to 5 × 10 11 cm -2 be.

[0080] Furthermore, the lifetime control region 150 of the present example is formed by implantation from the back surface 23 side. For example, the lifetime control region 150 is formed by irradiating helium from the back surface 23 side. This makes it possible to avoid the influence of the front surface 21 side of the semiconductor device 100. Whether the lifetime control region 150 is formed by implantation from the front surface 21 side or implantation from the back surface 23 side can be determined by detecting the state of the front surface 21 side by the SRP method or by measuring the leakage current.

[0081] A lifetime control region 160 is disposed on the back surface side 23 of the semiconductor substrate 10. The lifetime control region 160 is disposed in both the transistor section 70 and the diode section 80. The lifetime control region 160 is disposed closer to the front surface side 21 than the buffer region 20. The lifetime control region 160 may be disposed in the buffer region 20.

[0082] The lifetime control region 160 is disposed on the entire back surface 23 of the semiconductor substrate 10. That is, the lifetime control region 160 can be formed without a mask. The lifetime control region 160 can be formed by any method for forming the lifetime control region 150. It can be formed by implanting impurities from the back surface 23 of the semiconductor substrate 10. The lifetime control region 160 is an example of a second lifetime control region disposed on the back surface 23 of the semiconductor substrate 10.

[0083] Fig. Figure 1C is a diagram showing an example of a cross section along the line bb' in Fig. 1A. The cross section bb' is an XZ plane passing through the contact area 15 in the transistor section 70.

[0084] The mesa section 71 includes the base region 14, the contact region 15, the collection region 16, and the plug region 19. By providing the plug region 19, the RBSOA ("Reverse Bias Safe Operation Region") resistance is improved. As in the case of the aa' cross section, the mesa section 91 includes the base region 14, the contact region 15, the collection region 16, and the plug region 19. In the bb' cross section, the mesa section 71 has the same structure as the mesa section 91. As in the case of the aa' cross section, the mesa section 81 includes the base region 14, the collection region 16, and the plug region 19.

[0085] The lifetime control region 150 and the lifetime control region 160 are arranged in both the transistor section 70 and the diode section 80, as in the case of the aa' cross section.

[0086] Since the semiconductor device 100 of the present example includes the lifetime control region 150 in both the transistor section 70 and the diode section 80, holes are uniformly removed at the time of turn-off, and the carrier balance between the transistor section 70 and the diode section 80 is improved. Then, the RBSOA resistance and the short-circuit resistance are improved, and the latch-up strength is also improved.

[0087] Fig. 2A illustrates an example of a top view of the semiconductor device 100 according to an embodiment. In the semiconductor device 100 of the present example, the arrangement of the dummy trench portion 30 and the gate trench portion 40 differs from the semiconductor device 100 of the Fig. 1A. In the present example, the embodiment of the Fig. 1A. In the present example, the proportion of the dummy trench section 30 is larger than that in the embodiment of the Fig. 1A.

[0088] In the transistor section 70, the gate trench section 40 and the dummy trench section 30 are repeatedly arranged so that the ratio between the gate trench section 40 and the dummy trench section 30 is 2:4. A set of dummy trench sections 30 connected by the connecting section 33 is arranged in a set of gate trench sections 40 connected by the connecting section 43.

[0089] Fig. Figure 2B is a diagram showing an example of a cross section along the line cc' in Fig. 2A. The cross section cc' is an XZ plane passing through the emitter region 12 in the transistor section 70. The semiconductor device 100 of the present example differs from the semiconductor device 100 of Fig. 1B in that a two-stage collection area 16, which is formed by the collection area 16a and the collection area 16b, is present. In the present example, in particular, the embodiment of the Fig. 1B different points are described.

[0090] The collection region 16a and the collection region 16b are arranged in both the transistor section 70 and the diode section 80. The doping concentrations of the collection region 16a and the collection region 16b may be identical or different. The doping concentration of the collection region 16a may be higher than or similar to the doping concentration of the collection region 16b. The doping concentration of the collection region 16b may refer to a peak value of the doping concentration of the collection region 16.

[0091] The collection region 16a is a first collection region located closer to the front surface side 21 than the drift region 18. The collection region 16a is located below the base region 14. In one example, the dosage of ion implantation in the collection region 16a is 1 × 10 12 cm -2 up to 1 × 10 13 cm -2 For example, the collection area 16a is filled with a dosage of 3 × 10 12 cm -2 and an acceleration energy of 2.6 MeV.

[0092] The collection region 16b is a second collection region located below the collection region 16a. In one example, the ion implantation dosage in the collection region 16b is 1 × 10 12 cm -2 up to 1 × 10 13 cm -2 For example, the collection area 16b is filled with a dosage of 3 × 10 12 cm -2and an acceleration energy of 3.9 MeV. The drift region 18 may be disposed between the collection region 16a and the collection region 16b. Note that the semiconductor device 100 of the present example includes the collection regions 16 with two stages, but it may include the collection regions 16 in three or more stages.

[0093] Fig. Figure 2C is a diagram showing an example of a cross section along the line dd' in Fig. 2A. The cross section dd' is an XZ plane passing through the contact region 15 in the transistor section 70. The semiconductor device 100 of the present example differs from the semiconductor device 100 of Fig. 1C by including the collection area 16a and the collection area 16b. In the present example, reference is made in particular to the example of Fig. 1C deviating points are described.

[0094] Collecting region 16a and collecting region 16b are arranged in both transistor section 70 and diode section 80, similar to the cc' cross section. Collecting region 16a and collecting region 16b can be arranged under conditions similar to those in the cc' cross section.

[0095] By disposing the collection region 16 in two stages, the IE effect in the semiconductor device 100 can be improved, so that the ON resistance of the transistor section 70 is easily reduced. Furthermore, the semiconductor device 100 can suppress a decrease in resistivity by disposing the lifetime control region 150 over the entire surface. Therefore, the semiconductor device 100 of the present example can suppress a decrease in resistivity while reducing the ON resistance.

[0096] Fig. Figure 2D is a diagram for describing a difference in characteristics depending on the number of stages of the collection region 16. The vertical axis denotes a turn-off loss Eoff (mJ) and the horizontal axis denotes a collector-emitter saturation voltage Vce(sat) (V).

[0097] A curve 101 describes a characteristic in a case where the collection region 16 has a step. That is, the curve 101 corresponds to the semiconductor device 100 in Fig. 1A to Fig. 1C. A curve 102 describes a characteristic in a case where the collection region 16 has two stages. The curve 102 corresponds to the semiconductor device 100 in Fig. 2A to Fig. 2C.

[0098] The doping concentration is adjusted so that the sum of the doping concentrations of the collection region 16a and the collection region 16b in two stages is equal to the doping concentration of the collection region 16 in the case of one stage. In addition, the doping concentration of the collection region 16a is the same as the doping concentration of the collection region 16b. For example, if the doping concentration of the collection region 16 in one stage is 1 × 10 12 cm -3 , the doping concentration in the corresponding two stages is 0.5 × 10 12 cm -3 . In this drawing, the doping concentration corresponding to the respective graph is described. The graph of the present example shows the case where the doping concentration of the collection region 16 is 1 × 10 12 cm -3 , 3 × 10 12 cm -3 , 6 × 10 12 cm -3 , 1 × 10 13 cm -3 or 1.2 × 1013 cm -3 amounts.

[0099] The collector-emitter saturation voltage Vce(sat) tends to decrease with increasing doping concentration of the collection region 16. However, in a region where the doping concentration of the collection region 16 is large, the turn-off loss Eoff tends to increase due to the IE effect.

[0100] In a region where the collector-emitter saturation voltage Vce(sat) is relatively large, curve 101 and curve 102 overlap, and the difference in characteristics is small. On the other hand, in a region where the collector-emitter saturation voltage Vce(sat) is relatively small, the turn-off loss Eoff of curve 102 is smaller than that of curve 101.

[0101] Therefore, in the semiconductor device 100, a case where the accumulation region 16 has a two-stage structure slightly reduces the turn-off loss Eoff while suppressing the collector-emitter saturation voltage Vce(sat). Furthermore, in the semiconductor device 100, a case where the accumulation region 16 has the two-stage structure can increase the doping concentration of the accumulation region 16 without increasing the turn-off loss Eoff.

[0102] Fig. 3 is an example of an enlarged sectional view in the vicinity of the mesa section 71. In this example, the mesa section 71 enclosed between the dummy trench section 30 and the gate trench section 40 is shown.

[0103] A depth D1 is the trench depth of the dummy trench portion 30 or the gate trench portion 40. The depth D1 may be the depth of the bottom end of the dummy dielectric film 32 or the gate dielectric film 42. The depth D1 is approximately set according to the characteristics and the like of the semiconductor device 100.

[0104] A depth D2 is the depth of the lifetime control region 150 from the front surface 21. The depth D2 in this example is deeper than the depth D1. That is, the lifetime control region 150 is located below the dummy trench portion 30 and the gate trench portion 40. For example, the depth D2 is 5 µm to 20 µm.

[0105] A depth D3 is the depth of the collection region 16 from the front surface 21. In one example, the depth D3 is the depth of the bottom of the collection region 16. If the collection region 16 has a plurality of steps, the depth D3 may be the depth of the bottom of the collection region 16 located at the deepest position. The depth of the bottom of the collection region 16 is the depth of the boundary between the collection region 16 and the drift region 18. That is, the bottom of the collection region 16 is at a position where the doping concentration of the collection region 16 becomes the doping concentration of the drift region 18. Further, the depth D3 may be the depth of the peak position of the doping concentration of the collection region 16. For example, the depth D3 is 1 μm to 5 μm. In one example, the depth D3 is 3 μm.

[0106] The depth D2 is deeper than the depth D1. The depth D2 may be deeper than twice the depth D3. In this case, a gap equal to or greater than the depth D3 is arranged between the lifetime control region 150 and the accumulation region 16. As described above, by arranging the gap between the lifetime control region 150 and the accumulation region 16, the withstand capability of the lifetime control region 150 can be improved without sacrificing the effect of reducing the ON resistance of the accumulation region 16.

[0107] The depth of the lifetime control region 150 from the front surface 21 is within 20 µm. In one example, the depth from the front surface 21 of the lifetime control region 150 is 10 µm.

[0108] The depth D3 lies within the trench depth of the trench section. The case within the trench depth includes a case of the same depth as the trench depth and a case of it being lower than the trench depth. The collection area 16 cannot be located at a deeper position than the trench section. That is, the depth D3 is less than or equal to the depth D1.

[0109] Fig. 4 illustrates an example of a plan view of the chip finish of the semiconductor device 100. In this example, a plan view of the negative end portion of the emitter electrode 52 in the X-axis direction and in the Y-axis direction is shown.

[0110] The emitter electrode 52 is arranged covering the dummy trench portion 30 and the gate trench portion 40. The gate trench portion 40 of the present example is electrically connected to the gate metal layer 50 via a gate slider 45.

[0111] The gate runner 45 electrically connects the gate metal layer 50 and the gate trench portion 40 via a contact hole provided in the interlayer dielectric film 38. The gate runner 45 of the present example is electrically connected to the gate wiring portion 44 in the front surface 21. The gate runner 45 is not connected to the dummy wiring portion in the dummy trench portion 30. For example, the gate runner 45 is formed of polysilicon doped with an impurity or the like.

[0112] A region R12 denotes a region where the emitter region 12 and the contact region 15 are repeatedly arranged. That is, the emitter region 12 does not need to be arranged in the entire surface of the region R12. The outer periphery of the region R12 is defined by the emitter region 12 on the outermost side in plan view. For example, the region R12 serves as an active region through which the main current of the transistor section 70 flows.

[0113] A region R16 is a region where the collection region 16 is arranged. In the region R16, the collection region 16 can be arranged over the entire surface. However, even in the region R16, the collection region 16 cannot be arranged in the region where the dummy trench portion 30 and the gate trench portion 40 are arranged. The region R16 of the present example is arranged over a wider area in plan view than the region R12.

[0114] A region R15 is a region where the contact region 15 is arranged. The region R15 may include a region where the emitter region 12 and the contact region 15 are repeatedly arranged as in the region R12. The plug region 19 may be repeatedly arranged in the region R15.

[0115] In the semiconductor device 100 of the present example, the region R16 is arranged to cover the region R12. As a result, the active area of ​​the transistor section 70 is less likely to be affected by the deviation of the mask of the collection region 16. Furthermore, in the semiconductor device 100, the region R15 is arranged to cover the region R16. Furthermore, the lifetime control region 150 is arranged so that the lifetime control region 150 covers the region R15, so that the influence of the deviation of the mask of the lifetime control region 150 can be avoided. If the lifetime control region 150 is arranged on the entire surface of the semiconductor substrate 10, the influence of the deviation of the mask of the lifetime control region 150 is absent.

[0116] Fig.5 is an example of a cross-sectional view of a semiconductor device 500 according to a comparative example. In this example, a cross-sectional view of a boundary portion between a transistor portion 570 and a diode portion 580 in the semiconductor device 500 is shown.

[0117] The semiconductor device 500 includes a collection region 516 in the transistor section 570. The semiconductor device 500 does not include a collection region 516 in the diode section 580 and may be affected by the mask deviation of the collection region 516.

[0118] Furthermore, the semiconductor device 500 includes a lifetime control region 550 arranged on the front surface side 21 of the semiconductor substrate 10. The semiconductor device 500 includes a lifetime control region 560 arranged on the back surface side 23 of the semiconductor substrate 10.

[0119] The lifetime control region 550 is disposed in the diode section 580 but not in the transistor section 570. That is, the lifetime control region 550 is formed by partial irradiation instead of complete irradiation with impurities. Partial irradiation of the lifetime control region 550 requires a mask, such as a resist mask or a metal mask. Thus, the semiconductor device 500 may be affected by the mask variation of the lifetime control region 550.

[0120] On the other hand, in the semiconductor device 100 according to the embodiment, since the lifetime control region 150 is provided in the transistor section 70 and the diode section 80, the mask deviation can be avoided. Furthermore, since it is not necessary to form a mask for forming the lifetime control region 150, the processing step can be simplified. In the semiconductor device 100, holes are uniformly removed at the time of turn-off, and the carrier balance between the transistor section 70 and the diode section 80 is improved.

[0121] The operations, procedures, steps, and stages of each process performed by an apparatus, system, program, and method illustrated in the claims, embodiments, or drawings may be performed in any order, as long as the order is not indicated by "previous," "before," or similar terms, and as long as the output of a previous process is not used in a subsequent process. Even if the process flow is described in the claims, embodiments, or figures by terms such as "first" or "next," this does not necessarily mean that the process must be performed in that order. LIST OF REFERENCE SYMBOLS 10 Semiconductor substrate 12 Emitter area 14 Basic area 15 Contact area 16 Collection area 17 Sink area 18 Drift area 19 Plug area 20 Buffer area 21 Front surface 22 Collector area 23 back surface 24 Collector electrode 25 connecting section 30 Dummy trench section 31 extension section 32 dielectric dummy film 33 connecting section 34 Dummy line section 38 dielectric interlayer film 40 gate ditch section 41 extension section 42 dielectric gate film 43 connecting section 44 gate line section 45 gate runners 50 gate metal layer 52 Emitter electrode 54 contact hole 55 contact hole 56 contact hole 70 transistor section 71 Mesa section 80 diode section 81 Mesa section 82 Cathode area 90 border section 91 Mesa section 100 semiconductor devices 101 Curve 102 Curve 150 lifetime control range 160 lifetime control range 500 semiconductor devices 516 Collection area 550 lifetime control range 560 lifetime control range 570 transistor section 580 diode section

Claims

[1] A semiconductor device (100) having a transistor section (70) and a diode section (80), comprising: a drift region (18) of a first conductivity type arranged in a semiconductor substrate (10); a collection region (16) of a first conductivity type arranged with respect to the drift region (18) on a front surface side (21) of the semiconductor substrate (10) in the transistor section (70) and in the diode section (80), the collection region (16) comprising: a first collection region (16a) arranged closer to the front surface side (21) than the drift region (18); and a second collection area (16b) arranged below the first collection area (16a); and a first lifetime control region (150) arranged on the front surface side (21) of the semiconductor substrate (10) in the transistor section (70) and in the diode section (80), wherein the doping concentrations of the first collection region (16a) and the second collection region (16b) are identical, and a sum of integrated concentrations obtained by integrating the doping concentrations of the first collection region (16a) and the second collection region (16b) over a depth direction of the first collection region (16a) and the second collection region (16b) is 1 × 10 12 cm -3 up to 1 × 10 13 cm -3 amounts. [2] The semiconductor device (100) according to claim 1, wherein the first lifetime control region (150) is arranged over the entire surface of the semiconductor substrate (10). [3] A semiconductor device (100) according to claim 1 or 2, comprising: a second lifetime control region (160) arranged on an entire back surface side (23) of the semiconductor substrate (10). [4] Semiconductor device (100) according to one of claims 1 to 3, comprising: a plurality of trench sections arranged on the front surface of the semiconductor substrate (10), wherein a depth of the first lifetime control region (150) is deeper than depths of the plurality of trench sections. [5] The semiconductor device (100) according to any one of claims 1 to 4, wherein a depth of the collection region (16) is within trench depths of a plurality of trench sections. [6] The semiconductor device (100) according to any one of claims 1 to 5, wherein a depth of the first lifetime control region (150) is deeper than twice a depth of a boundary between the accumulation region (16) and the drift region (18). [7] The semiconductor device (100) according to any one of claims 1 to 6, wherein a depth of the first lifetime control region (150) is 5 µm to 20 µm. [8] The semiconductor device (100) according to any one of claims 1 to 7, wherein an integrated concentration obtained by integrating a doping concentration of a lifetime killer over a depth direction of the first lifetime control region (150) is 0.5 × 10 10 cm -2 up to 1 × 10 13 cm -2 amounts. [9] The semiconductor device (100) according to claim 8, wherein the first lifetime control region (150) is implanted from a back surface side of the semiconductor substrate (10). [10] The semiconductor device (100) according to any one of claims 1 to 9, wherein an integrated concentration of ion implantation obtained by integrating a doping concentration of the collection region (16) in the depth direction is 1 × 10 12 cm -2 up to 1 × 10 13 cm -2 amounts. [11] The semiconductor device (100) according to any one of claims 1 to 10, wherein a depth of the collection region (16) is 1 µm to 5 µm. [12] The semiconductor device (100) according to any one of claims 1 to 11, wherein the transistor section (70) comprises: an emitter region (12) of a first conductivity type having a higher doping concentration than the drift region (18), and wherein the collecting region (16) is arranged in a wider region than a region where the emitter region (12) is arranged in plan view. [13] The semiconductor device (100) according to any one of claims 1 to 12, wherein the transistor section (70) comprises: a boundary section (90) disposed adjacent to the diode section (80); and a dummy trench portion electrically connected to an emitter electrode, and wherein a trench section at the boundary section (90) is the dummy trench section. [14] The semiconductor device (100) according to claim 13, wherein the boundary portion (90) comprises: the collection area (16); a base region (14) of a second conductivity type arranged on the front surface side (21); a contact region (15) arranged on the front surface side of the base region (14) and having a higher doping concentration than the base region (14); and a plug region (19) of a second conductivity type, which is arranged on a front surface side of the contact region (15) and has a higher doping concentration than the contact region (15). [15] The semiconductor device (100) according to claim 13 or 14, wherein the boundary portion (90) does not have an emitter region (12). [16] A method of manufacturing a semiconductor device (100) having a transistor section (70) and a diode section (80), the method comprising: Arranging a drift region (18) of a first conductivity type in a semiconductor substrate (10); Arranging a collection region (16) of a first conductivity type with respect to the drift region (18) on a front surface side (21) of the semiconductor substrate (10) in the transistor section (70) and in the diode section (80), wherein the arranging of the collection region (16) comprises: Arranging a first collection region (16a) closer to the front surface side (21) than the drift region (18); and Arranging a second collection area (16b) below the first collection area (16a); and Arranging a first lifetime control region (150) on the front surface side (21) of the semiconductor substrate (10) in the transistor section (70) and in the diode section (80), wherein the doping concentrations of the first collection region (16a) and the second collection region (16b) are identical, and a sum of integrated concentrations obtained by integrating the doping concentrations of the first collection region (16a) and the second collection region (16b) over a depth direction of the first collection region (16a) and the second collection region (16b) is 1 × 10 12 cm -3 up to 1 × 10 13 cm -3 amounts. [17] The manufacturing method according to claim 16, wherein disposing the first lifetime control region (150) comprises irradiating impurities from a back surface side (23) of the semiconductor substrate (10). [18] A manufacturing method according to claim 16 or 17, wherein the disposing of the first lifetime control region (150) comprises implanting impurities with a dosage in the range of 0.5 × 10 10 cm -2 up to 1 × 10 13 cm -2 includes. [19] A manufacturing method according to any one of claims 16 to 18, wherein arranging the collection region (16) comprises performing ion implantation with a dosage in the range of 3 × 10 12 cm -2 up to 6 × 10 12 cm -2 includes.

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