ALIGNMENT BEAM FOR AN INTERMEDIATE BRIDGE STRUCTURE

Abstract

Assembly comprising: a first semiconductor chip (50L) comprising a plurality of first bond contacts (52L) located at a peripheral region of the first semiconductor chip, first solder balls (54L) located in a low-density interconnection region (LDI region) of the first semiconductor chip, and first bond contacts (56L) located in a high-density interconnection region (HDI region) of the first semiconductor chip; a second semiconductor chip (50R) located laterally adjacent to the first semiconductor chip, comprising a plurality of second bond contacts (52R) located at a peripheral region of the second semiconductor chip, second solder balls (54R) located in an LDI region of the second semiconductor chip, and second bond contacts (56R) located in an HDI region of the second semiconductor chip;and an alignment carrier (10) comprising a substrate and a plurality of solder balls located on the substrate, wherein a first set of solder balls (14X) located on the substrate is aligned towards and in contact with the first bond contact points located at the peripheral region of the first semiconductor chip, and wherein a second set of solder balls (14Y) located on the substrate is aligned towards and in contact with the second bond contact points located at the peripheral region of the second semiconductor chip; and wherein the solder balls of the alignment carrier have a dimension larger than that of the first solder balls present in the first LDI region of the first semiconductor chip and than that of the second solder balls present in the second LDI region of the second semiconductor chip.

Description

BACKGROUNDThe invention relates to semiconductor technology and more particularly to the alignment and construction of two or more semiconductor chips using an interconnect bridge.Semiconductor chips (i.e., chips) have become more continuously complex and have increased in size. This resulted in the semiconductor chips having a lower yield although the defect density remained the same, but there is a higher probability of being affected by random defects due to the semiconductor chip size. To reduce yield losses, the semiconductor chips are sized but now need to have a larger amount of inputs / outputs (I / O) for data exchange between chips at sufficiently fast rates.In order to enable a fast data exchange between semiconductor chips, wiring dimensions are necessary, which can be achieved during semiconductor production. In the past, attempts have been made with interconnect bridges, such as silicon (Si) bridges. However, prior art interconnect bridges may result in significant design challenges. For example, a plurality of interconnect bridges are usually necessary for a construction of a plurality of semiconductor chips. This makes it difficult to align an interconnect bridge region between the semiconductor chips and attach the interconnect bridge to a plurality of semiconductor chips during assembly.Since the interconnect bridge interconnect region can be plated first and the large bump regions can be plated second, there is usually some mis-detection between the low density interconnect regions (the LDI regions) and the high density interconnect regions (the HDI regions) due to this two-step plating process. This does not make use of the controlled collapse chip connection (C4) solder with a large pitch ideal for alignment in interconnect bridges. At the same time, it is necessary to properly handle aligned semiconductor chips while a very thin interconnect bridge is attached thereto.There is a need to provide alignment and construction of two or more semiconductor chips using an interconnect bridge that avoids the problems noted above.US 2010 / 0 327 424 A1 relates to a multichip package comprising: a substrate having a first side, an opposite second side, and a third side extending from the first side to the second side; a first chip attached to the first side of the substrate and a second chip attached to the first side of the substrate; and a bridge adjacent to the third side of the substrate and attached to the first chip and the second chip, wherein no part of the substrate is under the bridge and wherein the bridge creates a connection between the first chip and the second chip, wherein the bridge is attached to the first chip and the second chip using flip-chip connections; the bridge comprises an active chip constituting a third chip of the multi-chip package; and the bridge is attached to the first side of the substrate using a wire bond, and wherein the first chip and the second chip cross an outer edge of the first side of the substrate.WO 2020 / 021 402 A1 relates to a package structure comprising: a package substrate; an interconnection bridge unit connected to the package substrate; a first integrated circuit die connected to the interconnection bridge unit and to the package substrate; and a second integrated circuit die connected to the interconnection bridge unit and to the package substrate; wherein the interconnection bridge unit comprises wiring for providing die-to-die connections between the first and second integrated circuit dies and wiring for providing die-to-die connections between the package substrate and the first and second integrated circuit dies, the package-to-die connections comprising power connections; wherein the interconnect bridge unit comprises a structure of multiple layers of an inorganic dielectric material and a patterned metallization to provide interlayer vias and lateral traces to form the interconnect bridge unit wiring; wherein the interconnect bridge unit comprises at least one organic dielectric layer with a patterned metallization that provides the package-to-die wiring.SUMMARYThe invention relates to a structure according to claim 1 and to a method according to claim 7, by which the precise alignment and the structure of two or more semiconductor chips is made possible using an interconnection bridge which avoids the problems noted above. Embodiments of the invention are set forth in the dependent claims.An alignment carrier is provided that may be used for alignment and construction of two or more semiconductor chips (i.e., chips) using an interconnect bridge. In one embodiment, the alignment carrier includes a substrate having a coefficient of thermal expansion (CTE) substantially matching that of an interconnect bridge. The alignment carrier further comprises a plurality of solder balls located on a surface of the substrate and configured for alignment of two or more semiconductor chips. In an embodiment, the solder balls provided on the substrate of the alignment carrier are formed at locations corresponding to a peripheral region of each semiconductor chip to be subsequently aligned therewith.When the interconnection bridge is made of silicon, the substrate is made of silicon or glass. In some embodiments, the solder balls of the alignment carrier are located on a surface of the substrate corresponding to the corners of each of the semiconductor chips to be aligned. In some embodiments, the alignment carrier includes a window (i.e., an opening) located in a central region of the substrate. In such an embodiment, the window is configured for placement of and access to the interconnect bridge. The presence of the window provides access to the high density interconnect region (the HDI region) of the semiconductor chip for an arrangement of the interconnect bridge.The plurality of solder balls present on the substrate have a dimension larger than that of the solder balls present in a low density interconnection region (an LDI region) of the two or more semiconductor chips. This dimensional difference of the solder balls allows the solder balls present on the substrate of the alignment carrier to be in contact with sacrificial bond pads located at a peripheral region of the semiconductor chip without allowing the solder balls present on the semiconductor chip to be in contact with the alignment carrier. In some embodiments, each solder ball of the plurality of solder balls is a controlled collapse chip connection (C4) solder ball.A structure is provided. In an embodiment, the structure includes a first semiconductor chip including a plurality of first sacrificial bond pads located at a peripheral region of the first semiconductor chip, first solder balls located in a low density interconnect region (an LDI region) of the first semiconductor chip, and first bond pads located in a high density interconnect region (an HDI region) of the first semiconductor chip. A second semiconductor chip is laterally adjacent to the first semiconductor chip and includes a plurality of second sacrificial bond pads located at a peripheral region of the second semiconductor chip, second solder balls located at an LDI region of the second semiconductor chip, and second bond pads located at an HDI region of the second semiconductor chip.The assembly further includes an alignment carrier having a substrate with a coefficient of thermal expansion substantially matching that of an interconnect bridge, and a plurality of solder balls located on the substrate corresponding to the peripheral portion of the first semiconductor chip and the second semiconductor chip being aligned. According to an embodiment, a first set of the plurality of solder balls located on the substrate is aligned with and in contact with the plurality of first sacrificial bond pads located on the peripheral region of the first semiconductor chip, and a second set of the plurality of solder balls located on the substrate is aligned with and in contact with the plurality of second sacrificial bond pads located on the peripheral region of the second semiconductor chip.For example, the alignment carrier comprises a window provided in the central portion of the substrate corresponding to the HDI portion of the first semiconductor chip and the HDI portion of the second semiconductor chip, thus allowing access for an arrangement of the interconnect bridge. In some embodiments, the interconnect bridge present in the assembly is silicon and the substrate of the alignment carrier is silicon or glass. In some embodiments, the plurality of first sacrificial bond pads is at each corner of the first semiconductor die, and the plurality of second sacrificial bond pads is at each corner of the second semiconductor die. In some embodiments, the plurality of solder balls of the alignment carrier have a dimension that is larger than those of the solder balls present in the first LDI region of the first semiconductor chip and the second LDI region of the second semiconductor chip. In some embodiments, a support structure may be attached to a back side of the first semiconductor chip and the second semiconductor chip.For example, an interconnect bridge is present in the structure spanning the first semiconductor die and the second semiconductor die. In an embodiment, the interconnect bridge connects the HDI region of the first semiconductor chip to the HDI region of the second semiconductor chip.A method is provided for aligning and constructing two or more semiconductor chips (i.e., semiconductor chips) using an interconnect bridge. In a first embodiment, the method includes providing a first structure including a first semiconductor chip, a second semiconductor chip laterally adjacent to the first semiconductor chip, and an alignment carrier. The first semiconductor chip includes a plurality of first sacrificial bond pads located at a peripheral region of the first semiconductor chip, first solder balls located in a low density interconnect region (an LDI region) of the first semiconductor chip, and first bond pads located in a high density interconnect region (an HDI region) of the first semiconductor chip. The second semiconductor chip includes a plurality of second sacrificial bond pads located at a peripheral region of the second semiconductor chip, second solder balls located in an LDI region of the second semiconductor chip, and second bond pads located in an HDI region of the second semiconductor chip. The alignment carrier includes a substrate having a thermal expansion coefficient substantially matching that of an interconnection bridge, and a plurality of solder balls located on the substrate corresponding to the peripheral portion of both the first semiconductor chip and the second semiconductor chip. In the first configuration, a first set of the plurality of solder balls located on the substrate is aligned with and in contact with the plurality of first sacrificial bond pads located at the peripheral region of the first semiconductor chip, and a second set of the plurality of solder balls located on the substrate is aligned with and in contact with the plurality of second sacrificial bond pads located at the peripheral region of the second semiconductor chip.In a first example, furthermore, a first attachment of a support structure to a rear side of the first semiconductor chip and of the second semiconductor chip. Next, the alignment carrier is removed so as to provide a second structure comprising the first semiconductor chip, the second semiconductor chip and the support structure. The method of the first embodiment continues with a second attachment of the interconnect bridge between the first semiconductor chip and the second semiconductor chip, so as to provide a third structure including the first semiconductor chip, the second semiconductor chip, the support structure, and the interconnect bridge. In the third configuration, the interconnection bridge connects the HDI region of the first semiconductor chip to the HDI region of the second semiconductor chip. The method of the first embodiment continues with third applying a laminate to the third assembly.In a second example, the method includes providing a first structure including a first semiconductor chip, a second semiconductor chip laterally adjacent to the first semiconductor chip, and an alignment carrier. The first semiconductor chip includes a plurality of first sacrificial bond pads located at a peripheral region of the first semiconductor chip, first solder balls located in a low density interconnect region (an LDI region) of the first semiconductor chip, and first bond pads located in a high density interconnect region (an HDI region) of the first semiconductor chip. The second semiconductor chip includes a plurality of second sacrificial bond pads located at a peripheral region of the second semiconductor chip, second solder balls located in an LDI region of the second semiconductor chip, and second bond pads located in an HDI region of the second semiconductor chip. The alignment carrier includes a substrate having a thermal expansion coefficient substantially matching that of an interconnection bridge, a window located in a central portion of the substrate, and a plurality of solder balls located on the substrate corresponding to the peripheral portion of both the first semiconductor chip and the second semiconductor chip. In the first configuration, a first set of the plurality of solder balls located on the substrate is aligned with and in contact with the plurality of first sacrificial bond pads located at the peripheral region of the first semiconductor chip, and a second set of the plurality of solder balls located on the substrate is aligned with and in contact with the plurality of second sacrificial bond pads located at the peripheral region of the second semiconductor chip.In the second example, further includes: forming the interconnect bridge through the window and spanning the first semiconductor chip and the second semiconductor chip so as to provide a second structure including the first semiconductor chip, the second semiconductor chip, and the interconnect bridge, the interconnect bridge connecting the HDI region of the first semiconductor chip to the HDI region of the second semiconductor chip, and thereafter first attaching a support structure to a back side of the first semiconductor chip and the second semiconductor chip of the second structure. Next, the alignment carrier is removed so as to provide a third structure comprising the first semiconductor chip, the second semiconductor chip, the interconnect bridge and the support structure. The method of the second embodiment continues with a second application of a laminate to the third assembly.In a third example, a method is provided that is similar to the method of the second example method, but without attaching a support structure to the first semiconductor chip and the second semiconductor chip during the assembly process.In each of the above-mentioned methods, the plurality of first sacrificial bond pads are formed at the same time as the first bond pads in the HDI region of the first semiconductor chip, and the plurality of second sacrificial bond pads are formed at the same time as the second bond pads in the HDI region of the second semiconductor chip. By forming the sacrificial bond pads at the same time as the bond pads in the HDI region of the semiconductor chip, mis-detection between the low density interconnect regions (the LDI regions) and the high density interconnect regions (the HDI regions) of the semiconductor chip is no longer important for alignment of the HDI regions of the semiconductor chip due to a two-step plating process.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a top-down view of an alignment carrier. FIG. 2 is a top-down view of two semiconductor chips. FIG. 3 is a cross-sectional view of a first structure including the two semiconductor chips of FIG. 2 aligned with and attached to the alignment carrier of FIG. 1. FIG. 4 is a cross-sectional view of the first structure of FIG. 3 after a first attachment of a support structure to a back side of the first and second chips. FIG. 5 is a cross-sectional view of the first structure of FIG. 4 after removing the alignment carrier so as to provide a second structure including the first chip and the second chip as well as the support structure. FIG. 6 is a cross-sectional view of the second structure of FIG. 5 after a second attachment of an interconnect bridge between the first and second chips so as to provide a third structure including the first and second chips, the support structure, and the interconnect bridge, the interconnect bridge connecting a high density interconnect region of the first chip to a high density interconnect region of the second chip. FIG. 7 is a cross-sectional view of the third structure of FIG. 6 after a third application of a laminate to the third structure so as to provide a fourth structure. FIG. 8 is a cross-sectional view of the fourth structure of FIG. 7 after performing underfill and removing the support structure. FIG. 9 is a cross-sectional view of a first assembly including a first semiconductor die, a second semiconductor die laterally adjacent to the first die, and an alignment carrier including a window. FIG. 10 is a cross-sectional view of the first structure of FIG. 9 after forming an interconnect bridge through the window and spanning the first and second chips so as to provide a second structure including the first and second chips and the interconnect bridge, the interconnect bridge connecting a high density interconnect region of the first chip to a high density interconnect region of the second chip. FIG. 11 is a cross-sectional view of the second structure of FIG. 10 after a first attachment of a support structure to a back side of the first and second chips of the second structure. FIG. 12 is a cross-sectional view of the second structure of FIG. 11 after removing the alignment carrier so as to provide a third structure including the first and second chips, the interconnect bridge, and the support structure. FIG. 13 is a cross-sectional view of the third structure of FIG. 12 after a second application of a laminate to the third structure so as to provide a fourth structure. FIG. 14 is a cross-sectional view of the fourth structure of FIG. 13 after performing underfill and removing the support structure. FIG. 15 is a cross-sectional view of a first assembly including a first semiconductor die, a second semiconductor die laterally adjacent to the first die, and an alignment carrier including a window. FIG. 16 is a cross-sectional view of the first structure of FIG. 15 after forming an interconnect bridge through the window and spanning the first and second chips so as to provide a second structure including the first and second chips and the interconnect bridge, the interconnect bridge connecting a high density interconnect region of the first chip to a high density interconnect region of the second chip. FIG. 17 is a cross-sectional view of the second structure of FIG. 16 after removal of the alignment carrier so as to provide a third structure including the first and second chips and the interconnect bridge. FIG. 18 is a cross-sectional view of the third structure of FIG. 17 after attaching a laminate to the third structure so as to provide a fourth structure and after performing underfilling.DETAILED DESCRIPTIONEmbodiments of the invention will now be described in more detail with reference to the following discussion and the accompanying drawings. It should be noted that the drawings are provided for illustrative purposes only and the drawings are therefore not drawn to scale. It should also be noted that the same and corresponding elements are denoted by the same reference numerals.In the following description, numerous details are set forth, such as specific structures, components, materials, dimensions, process steps, and techniques, for providing an understanding of the various embodiments. However, it should be appreciated by one of ordinary skill in the art that the various embodiments may be practiced without these specific details. In other instances, well-known structures or process steps have not been described in detail in order to avoid obscuring the invention.It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "over" another element, it may be directly on the other element or intervening elements may also be present. On the other hand, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "below" or "below" another element, it may be directly below or below the other element or intervening elements may be present. On the other hand, when an element is referred to as being "directly below" or "directly below" another element, there are no intervening elements present.Referring first to FIG. 1, an alignment carrier 10 is used for the precise alignment and construction of semiconductor chips. The alignment carrier 10 includes a substrate 12 that includes a plurality of solder balls 14 located on a surface of the substrate 12. In an embodiment, the solder balls are configured for alignment of two or more semiconductor chips. In particular, the solder balls 14 present on the substrate 12 are located in regions of the substrate 12 corresponding to the peripheral region of each of the semiconductor chips being aligned therewith. By a "peripheral region" is meant a region of material that is remote from a central (or middle) region of the material; the peripheral region of material is usually located near the edges of the material. In some embodiments, the plurality of solder balls 14 are located on the substrate 12 in regions that each correspond to a corner of the semiconductor chip to be subsequently aligned therewith.The substrate 12 providing an alignment carrier 10 has a coefficient of thermal expansion (CTE) substantially matching that of an interconnect bridge; the CTE is a measure of the change in a length of a material in response to a change in the temperature of the material. By "substantially consistent" is meant that the substrate 12 has a CTE that deviates from the CTE of the interconnect bridge by ±10%, preferably by ±5%, more preferably by ±2%. The substantial matching of the CTE of the substrate 12 to that of the interconnect bridge reduces misalignment during chip construction. The term "interconnect bridge" is used herein to refer to a structure used during chip construction to connect a high density interconnect region (an HDI region) of one semiconductor chip to an HDI region of another semiconductor chip.In one embodiment, and if the interconnect bridge is made of silicon (Si), then the substrate 12 is made of silicon or glass. Other materials for the substrate 12 may be used as long as the material chosen for the substrate 12 has a CTE that substantially matches the CTE of the interconnect bridge.In some embodiments, a window 16 (i.e., an opening) is located in a central region of the substrate 12 and is configured for placement of and access to the interconnect bridge. If present, the window 16 may be formed by lithography and etching. The window 16 extends completely through the substrate 12. The formation of the window can take place before formation of the solder ball 14 or after this. The window 16 is configured to have a dimension that is greater than a dimension of the interconnect bridge.In some embodiments, the plurality of solder balls 14 present on the substrate 12 have a dimension that is larger than that of the solder balls present in an LDI region of the semiconductor chip. The plurality of solder balls 14 present on the substrate 12 may be made of any conventional solder ball material. The solder ball material may contain lead or may be lead-free. In some embodiments, each solder ball of the plurality of solder balls 14 is a controlled collapse chip connection (C4) solder ball. In other embodiments, the solder balls 14 may be made of a low temperature solder (150° C. or lower). The solder balls 14 present on the substrate 12 may be formed using conventional techniques well known to those skilled in the art. In some embodiments, the solder balls 14 may be formed directly on the surface of the substrate 12. In other embodiments (not shown), the solder balls 14 may be formed on a bond pad, such as a bond pad with under bump metallization (UBM).Referring now to FIG. 2, FIG. 2 shows a first semiconductor chip 50L and a second semiconductor chip 50R. The first and second die (50L, 50R) comprise materials and components well known to those skilled in the art. The first and second chips (50L, 50R) may be formed using techniques also well known to those skilled in the art. In order not to obscure any aspect of the invention, details regarding the materials / components of the chips and the method used in forming the same are not provided herein. It should be noted that although two chips are described and illustrated, a plurality of chips may be used.The first chip 50L includes a plurality of first sacrificial bond pads 52L located at a peripheral region of the first chip 50L, first solder balls 54L located in a low density interconnect region (an LDI region) of the first chip 50L, and first bond pads 56L located in a high density interconnect region (an HDI region) of the first chip 50L.The second die 50R includes a plurality of sacrificial bond pads 52R located at a peripheral region of the second die 50R, second solder balls 54R located at an LDI region of the second die 50R, and second bond pads 56R located at an HDI region of the second die 50R.The term "LDI region" is used herein to refer to a region of a semiconductor chip in which solder bonds (54L, 54R) are present and those solder balls (54L, 54R) are disposed far from each other. In some embodiments, the distance between the solder balls (54L, 54R) present in the LDI region may be from 100 micrometers to 200 micrometers, respectively.The term "HDI region" denotes a region of a semiconductor chip in which bond pads (56L, 56R) are present and those bond pads (56L, 56R) are arranged close to one another. In some embodiments, the distance between the bond pads (56L, 56R) present in the HDI region may be from 10 micrometers to 100 micrometers, respectively.The sacrificial bond pads (52L, 52R) are dummy elements of the chips (50L, 50R) used for alignment purposes. That is, the sacrificial bond pads (52L, 52R) may be connected to the solder balls 14 located on the substrate 12 providing the alignment carrier 10. The chips (50L, 50R) align using the self-centering feature of a mass reflow. The term "self-centering" refers to the wetting force associated with the surface tension of the solder ball by which the component is drawn into the proper position on the bond pad during a solder reflow process. This allows proper alignment of the HDI regions of the chips (50L, 50R) that must have interconnect bridge attachment.In some embodiments, the sacrificial bond pads (52L, 52R) are present at the corners of each of the chips (50L, 50R). Placement for the sacrificial bond pads (52L, 52R) at the corners will not affect the LDI or HDI regions of the chips (50L, 50R) and in some cases provide the best alignment. The distance between the sacrificial bond pads (52L, 52R) located at the peripheral portion of the chips (50L, 50R) may be from 100 micrometers to 400 micrometers, respectively.In an embodiment, the plurality of first sacrificial bond pads 52L are formed at the same time as the first bond pads 56L in the HDI region of the first die 50L, and the plurality of second sacrificial bond pads 52R are formed at the same time as the second bond pads 56R in the HDI region of the second die 50R. By forming the sacrificial bond pads (52L, 52R) at the same time as the bond pads (56L, 56R) in the HDI region of the chip, mis-detection between the LDI regions and the HDI regions of the chips due to a two-stage plating process is avoided. In cases where the elements formed during the patterning of the LDI regions of the chips for alignment of the HDI regions are necessary for an arrangement of the interconnect bridge, mis-sensing between the patterning of the LDI regions and the HDI regions may introduce alignment errors.In some embodiments, the sacrificial bond pads (52L, 52R) may have a same dimension as the bond pads (56L, 56R). In other embodiments, the sacrificial bond pads (52L, 52R) may have a dimension that is greater than a dimension of the bond pads (56L, 56R). In one example, the sacrificial bond pads (52L, 52R) are 2 times larger than the bond pads (56L, 56R).The sacrificial bond pads (52L, 52R) and the bond pads (56L, 56R) may be made of any conventional bond pad material (i.e., copper) or a stack of bond pad materials. The sacrificial bond pads (52L, 52R) and the bond pads (56L, 56R) may be formed by depositing the bond pad material or stack of bond materials and subsequently subjecting the deposited layer(s) to a patterning process(s). The sacrificial bond pads (52L, 52R) and the bond pads (56L, 56R) present in the HDI region of the semiconductor chips (50R, 50L) are formed at the same time, again.The solder balls (54L, 54R) present in the LDI region of the chip (50L, 50R) are made of any conventional solder ball material. The solder balls (54L, 54R) may be compositionalally the same as or may be compositionalally different from the solder balls 14. In some embodiments, the solder balls (54L, 54R) present in the LDI region of the dies (50L, 50R) are a controlled collapse die connection (C4) solder ball. The solder balls (54L, 54R) present in the LDI region of the chips (50L, 50R) may be formed using conventional techniques well known to those skilled in the art. The solder balls (54L, 54R) present in the LDI region of the chips (50L, 50R) generally have a dimension that is less than the dimension of the plurality of solder balls 14 present on the substrate 12 of the alignment carrier 10. A smaller dimension of the solder balls (54L, 54R) compared to the solder balls 14 prevents undesirable interference between the solder balls (54L, 54R) and the alignment carrier 10 in the LDI regions of the chips.Reference is now made to Figures 3 to 8 which illustrate a method according to a first embodiment. In the first embodiment, first, a first structure A 1 is provided as shown in FIG. 3. The first structure comprises a first semiconductor chip 50L, a second semiconductor chip 50R and an alignment carrier 10. It should be noted that the alignment substrate 10 of this embodiment does not have a window 16. Then, as shown in FIG. 4, a support structure 100 is attached to the chips (50L, 50R) of the first structure A1. Next, the alignment carrier 10 is removed as shown in FIG. 5 so as to provide a second structure A 2 comprising the first chip 50L, the second chip 50R and the support structure 100. Thereafter, an interconnection bridge 102 is disposed between the first chip 50L and the second chip 50R, so as to provide a third structure A 3 as shown in FIG. 6. The third structure A 3 includes the first chip 50L, the second chip 50R, the support structure 100, and the interconnect bridge 102. In an embodiment, the interconnect bridge 102 connects the HDI region of the first die 50L to the HDI region of the second die 50R. Next, as shown in FIG. 7, a laminate 104 is attached to the third structure A 3 so as to provide a fourth structure A 4. An underfill epoxy 106 may be formed, as shown in FIG. 8. In some embodiments, and as also shown in FIG. 8, the support structure 100 may be removed from the structure. The method of the first embodiment will now be described in more detail.Referring first to FIG. 3, a first structure A 1 is illustrated that includes the two semiconductor chips ( 50L, 50R) of FIG. 2 aligned with and attached to the alignment carrier 10 of FIG. without the window 16. In one embodiment, the first structure A 1 may be formed by placing the two chips (50L, 50R) in close contact with the alignment carrier such that a first set of the plurality of solder balls 14X located on the substrate 12 is aligned with and in contact with the plurality of first sacrificial bond pads (not shown for clarity) located at the peripheral region of the first chip 50L and a second set of the plurality of solder balls 14Y on the substrate 12 is aligned with and in contact with the plurality of second sacrificial bond pads (not shown for clarity) located at the peripheral region of the second chip 50R. The solder balls 14X, 14Y correspond to the solder balls 14 of FIG. 1.Thereafter, a mass reflow anneal process may be performed to bond the dies (50L, 50R) to the alignment carrier 10. The chips (50L, 50R) align with each other using the self-centering feature of the mass reflow as described above. The bulk reflow can be performed using conditions well known to those skilled in the art. In one example, the mass reflow may be performed at a peak temperature of 235° C. to 255° C.Referring now to FIG. 4, there is illustrated the first structure A 1 of FIG. 3 after a first attachment of a support structure 100 to a back side of the first chip 50L and the second chip 50R. In one embodiment, the back side of the first and second die (50L, 50R) is the surface opposite a surface that includes the sacrificial bond pads (52L, 52R), the solder balls (54L, 54R), and the bond pads (56L, 56R).The support structure 100 may be made of any material having a CTE substantially matching the CTE of the chips, and such a material is well known to those skilled in the art and includes, for example, silicon, glass, or silicon carbide. In an embodiment, the support structure 100 may be attached to the back side of the first and second chips (50L, 50R) using a strip processable at a high temperature (higher than 260 °C) or a liquid adhesive. In such an embodiment, the support structure 100 may be a temporary structure that can be removed later in the build process. In other embodiments, the support structure 100 may be a permanent structure if the support structure 100 is made of a material that has minimal impact on the final construction. Possible effects on the final structure can be a combination of mechanical and thermal effects.Referring now to FIG. 5, there is illustrated the first structure A 1 of FIG. 4 after removing the alignment carrier 10 so as to provide a second structure A 2 including the first chip 50L, the second chip 50R, and the support structure 100. In some embodiments, the alignment carrier 10 may be removed by reflowing the solder joint formed by the aforementioned bulk reflow. In such an embodiment, the structure may be heated to a temperature at which the solder joint melts, such that the alignment carrier 10 detaches from the second structure A 2. In another embodiment, the alignment carrier 10 may be removed by mechanical shearing. In such an embodiment, a force may be applied whereby the sacrificial bond pads (52L, 52R) break away from the chips (50L, 50R) such that the solder balls (14X, 14Y) remain on the alignment carrier 10 and are not transferred to the chips (50L, 50R).Referring now to FIG. 6, there is illustrated the second structure A 2 of FIG. 5 after a second attachment of an interconnect bridge 102 between the first die 50L and the second die 50R so as to provide a third structure A 3. The third structure A 3 shown in FIG. 6 is rotated by 180° with respect to the second structure shown in FIG. 5. The third structure A 3 includes the first chip 50L, the second chip 50R, the support structure 100, and the interconnect bridge 102. In an embodiment, the interconnect bridge 102 connects the HDI region of the first die 50L to the HDI region of the second die 50R.In one embodiment, the interconnect bridge 102 is made of silicon. Other materials besides silicon may be used for the interconnect bridge 102, such as glass. In the first embodiment, the interconnect bridge 102 may be attached using thermal compression bonding (TCB). TCB allows copper to copper bonding as well as the use of a thin (less than 50 microns) interconnect bridge 102.Referring now to Fig. 7, there is shown the third structure A3 of Fig. 6 after a third application of a laminate 104 to the third structure A3. The third structure A 3 shown in FIG. 7 is rotated by 180° with respect to the third structure shown in FIG. 6. The laminate 104 comprises materials well known to those skilled in the art. For example, the laminate 104 may include a circuit board made of layers of an insulating material and a copper wiring. The laminate 104 can be attached to the third structure shown in FIG. 6 by performing a bulk reflow as described above. During this bulk reflow process, the solder balls (52L, 52R) reflow, and a solder joint is formed between the laminate 104 and the third structure A3 of FIG. 6. The structure shown in FIG. 7 is a fourth structure including the first chip 50L, the second chip 50R, the support structure 100, the interconnection bridge 102, and the laminate 104. In some embodiments, the fourth structure A4 is a final structure of the invention.Referring now to FIG. 8, there is illustrated the fourth structure A 4 of FIG. 7 after performing underfill and removing the support structure 100. In some embodiments, the step of removing the support structure 100 is not performed.The underfill process includes forming an underfill epoxy in the space of the fourth structure A 4 that is between the laminate 104, the first and second semiconductors (50L, 50R), and the interconnect bridge 102. To ensure that the space is completely filled with the underfill epoxy, the fourth assembly is typically heated to improve underflow of the underfill epoxy and initiate curing. In FIG. 8, an element 106 indicates a cured underfill epoxy.In some embodiments, the support structure 100 may be removed from the final assembly using a technique well known to those skilled in the art. In some embodiments, the removal of the support structure 100 may be performed by a lift-off process.Reference is now made to Figures 9 to 14 which illustrate a method according to a second embodiment. In the second embodiment, first, a first structure A 1 is provided as shown in FIG. 9. The first structure A 1 comprises a first semiconductor chip 50L, a second semiconductor chip 50R and an alignment carrier 10 having a window 16 for the arrangement of a bridge and an alignment. Thereafter, an interconnection bridge 102 is formed through the window 16 of the alignment carrier 10, as shown in FIG. 10, and spans the first chip 50L and the second chip 50R, so as to provide a second structure A 2 including the first chip 50L, the second chip 50R, and the interconnection bridge 102. In an embodiment, the interconnect bridge 102 connects the HDI region of the first die 50L to the HDI region of the second die 50R. Subsequently, a support structure 100 is attached to a back surface of the first chip 50R and the second chip 50L of the second structure A 2. Next, and as shown in FIG. 12, the alignment carrier 10 is removed so as to provide a third structure A 3 comprising the first chip 50L, the second chip 50R, the interconnect bridge 102, and the support structure 100. Thereafter, as shown in FIG. 13, a laminate 104 is attached to the third structure so as to provide a fourth structure A4. An underfill epoxy 106 may be formed, as shown in FIG. 14. In some embodiments, and as also shown in FIG. 14, the support structure 100 may be removed from the structure. The method of the second embodiment will now be described in more detail.Referring first to FIG. 9, a first assembly A 1 is illustrated that includes the two chips ( 50L, 50R) of FIG. 2 aligned with and attached to the alignment carrier 10 of FIG. 1 with the window 16. In one embodiment, the first structure A 1 may be formed by placing the two chips (50L, 50R) in close contact with the alignment carrier such that a first set of the plurality of solder balls 14X located on the substrate 12 is aligned with and in contact with the plurality of first sacrificial bond pads (not shown for clarity) located at the peripheral region of the first chip 50L and a second set of the plurality of solder balls 14Y located on the substrate 12 is aligned with and in contact with the plurality of second sacrificial bond pads (not shown for clarity) located at the peripheral region of the second chip 50R. The solder balls 14X, 14Y correspond to the solder balls 14 of FIG. 1.Referring now to FIG. 10, there is illustrated the first structure A 1 of FIG. 9 after forming an interconnect bridge 102 through the window 16 of the alignment carrier 10 and spanning the first die 50L and the second die 50R so as to provide a second structure A 2. The second structure A 2 shown in FIG. 10 is rotated by 180° with respect to the first structure shown in FIG. 9. The second structure A 2 includes the first chip 50L, the second chip 50R, and the interconnect bridge 102. In an embodiment, the interconnect bridge 102 connects the HDI region of the first die 50L to the HDI region of the second die 50R.In one embodiment, the interconnect bridge 102 is made of silicon. Other materials besides silicon may be used for the interconnect bridge 102, such as glass. In the second embodiment, the interconnect bridge 102 may be attached using a mass reflow process. During the mass reflow process, the chips may re-align and self-center with the interconnect bridge 102. In the second embodiment, the window 16 present in the alignment carrier 10 allows access within the first structure A1 for mounting the interconnect bridge 102.Referring now to FIG. 11, there is illustrated the second structure A 2 of FIG. 10 after a first attachment of a support structure 100 to a back side of the first chip 50L and the second chip 50R of the second structure A 2. The second structure A 2 shown in FIG. 11 is rotated by 180° with respect to the second structure shown in FIG. 10. The support structure 100 of this embodiment is the same as the previous embodiment.Referring now to FIG. 12, there is illustrated the second structure A 2 of FIG. 11 after removing the alignment carrier 10 so as to provide a third structure A 3 including the first chip 50L, the second chip 50R, the interconnect bridge 102, and the support structure 100. The third structure A 3 shown in FIG. 12 is rotated by 180° with respect to the second structure shown in FIG. 11. The removal of the alignment carrier 10 used in this embodiment may include a heating process or a mechanical shearing process as mentioned above.Referring now to Figure 13, there is shown the third assembly A3 of Figure 12 after a second application of a laminate 104 to the third assembly A3. The laminate 104 comprises one of the above-mentioned materials. The laminate 104 may be attached to the third structure using a mass reflow anneal process as defined above for the prior attachment of the laminate 104. A fourth structure A 4 is provided, which includes the first chip 50L, the second chip 50R, the interconnect bridge 102, the support structure 100, and the laminate 104. The fourth structure A 3 shown in FIG. 13 is rotated by 180° with respect to the third structure shown in FIG. 12.Referring now to FIG. 14, there is illustrated the fourth structure A 4 of FIG. 13 after performing underfill and removal of the support structure 100. In some embodiments, the step of removing the support structure 100 is not performed.The underfill process includes forming an underfill epoxy in the space of the fourth structure A 4 that is between the laminate 104, the first and second semiconductors (50L, 50R), and the interconnect bridge 102. To ensure that the space is completely filled with the underfill epoxy, the fourth assembly is typically heated to improve flow of the underfill epoxy and initiate curing of the underfill epoxy. In FIG. 14, an element 106 indicates a cured underfill epoxy.In some embodiments, the support structure 100 may be removed from the final assembly using a technique well known to those skilled in the art. In some embodiments, the removal of the support structure 100 may be performed by a lift-off process.Reference is now made to Figs. 15 to 18 which illustrate a method according to a third embodiment. The third embodiment is similar to the second embodiment except that no support structure is employed. In the third embodiment, first, a first structure A 1 is provided as shown in FIG. 15. The first structure A 1 includes a first chip 50L, a second chip 50R, and an alignment carrier 10 having an alignment window 16. Thereafter, as shown in FIG. 16, an interconnect bridge 102 is formed through the window 16 of the alignment carrier 10 and spans the first chip 50L and the second chip 50R, so as to provide a second structure A 2 including the first chip 50L, the second chip 50R, and the interconnect bridge 102. In an embodiment, the interconnect bridge 102 connects the HDI region of the first die 50L to the HDI region of the second die 50R. Next, and as shown in FIG. 17, the alignment carrier 10 is removed so as to provide a third structure A 3 including the first chip 50L, the second chip 50R, and the interconnect bridge 102. Then, a laminate 104 is attached to the third structure so as to provide a fourth structure A4, as shown in FIG. 18. An underfill epoxy 106 may be formed, as shown in FIG. 18.In a preferred embodiment of the present invention, a method is now provided comprising: providing a first assembly comprising a first semiconductor chip, a second semiconductor chip laterally adjacent to the first semiconductor chip, and an alignment carrier, the first semiconductor chip comprising a plurality of first sacrificial bond pads located at a peripheral region of the first semiconductor chip, first solder balls located at a low density interconnect region (an LDI region) of the first semiconductor chip, and first bond pads located at a high density interconnect region (an HDI region) of the first semiconductor chip, the second semiconductor chip comprising a plurality of second sacrificial bond pads located at a peripheral region of the second semiconductor chip, second solder balls, which are located in an LDI region of the second semiconductor chip and second bond pads located in an HDI region of the second semiconductor chip, and wherein the alignment carrier comprises a substrate having a thermal expansion coefficient substantially matching that of an interconnect bridge, a window located in a central region of the substrate, and a plurality of solder balls located on the substrate, wherein a first set of the plurality of solder balls located on the substrate is aligned with and in contact with the plurality of first sacrificial bond pads located on the peripheral region of the first semiconductor chip, and wherein a second set of the plurality of solder balls located on the substrate, the plurality of second sacrificial bond pads aligned with and in contact with the plurality of second sacrificial bond pads located at the peripheral area of the second semiconductor chip; forming the interconnect bridge through the window and spanning the first semiconductor chip and the second semiconductor chip so as to provide a second structure including the first semiconductor chip, the second semiconductor chip, and the interconnect bridge, the interconnect bridge connecting the HDI area of the first semiconductor chip to the HDI area of the second semiconductor chip; first attaching a support structure to a back side of the first semiconductor chip and the second semiconductor chip of the second structure; removing the alignment carrier so as to provide a third structure including the first semiconductor chip, the second semiconductor chip, the interconnect bridge, and the support structure; and a second attaching of a laminate to the third structure. The third attachment preferably comprises a bulk reflow of the first and second solder balls. The plurality of first sacrificial bond pads is preferably formed at the same time as the first bond pads in the HDI region of the first semiconductor chip, and the plurality of second sacrificial bond pads are formed at the same time as the second bond pads in the HDI region of the second semiconductor chip. The method may further comprise removing the support structure after the second application of the laminate.In a preferred embodiment described herein, a method is provided comprising: providing a first assembly comprising a first semiconductor chip, a second semiconductor chip laterally adjacent to the first semiconductor chip, and an alignment carrier, the first semiconductor chip comprising a plurality of first sacrificial bond pads located at a peripheral region of the first semiconductor chip, first solder balls located at a low density interconnect region (an LDI region) of the first semiconductor chip, and first bond pads located at a high density interconnect region (an HDI region) of the first semiconductor chip, the second semiconductor chip comprising a plurality of second sacrificial bond pads located at a peripheral region of the second semiconductor chip, second solder balls, which are located in an LDI region of the second semiconductor chip and second bond pads located in an HDI region of the second semiconductor chip, and wherein the alignment carrier comprises a substrate having a thermal expansion coefficient substantially matching that of an interconnect bridge, a window located in a central region of the substrate, and a plurality of solder balls located on the substrate, wherein a first set of the plurality of solder balls located on the substrate is aligned with and in contact with the plurality of first sacrificial bond pads located on the peripheral region of the first semiconductor chip, and wherein a second set of the plurality of solder balls located on the substrate, the plurality of second sacrificial bond pads aligned with and in contact with the plurality of second sacrificial bond pads located at the peripheral portion of the second semiconductor chip; forming the interconnect bridge through the window and spanning the first semiconductor chip and the second semiconductor chip so as to provide a second structure including the first semiconductor chip, the second semiconductor chip, and the interconnect bridge, the interconnect bridge connecting the HDI portion of the first semiconductor chip to the HDI portion of the second semiconductor chip; removing the alignment carrier so as to provide a second structure including the first semiconductor chip, the second semiconductor chip, and the interconnect bridge; and attaching a laminate to the second structure. The plurality of first sacrificial bond pads is preferably formed at the same time as the first bond pads in the HDI region of the first semiconductor chip, and the plurality of second sacrificial bond pads are formed at the same time as the second bond pads in the HDI region of the second semiconductor chip.

Claims

A structure comprising: a first semiconductor chip (50L) including a plurality of first bond pads (52L) located at a peripheral region of the first semiconductor chip, first solder balls (54L) located in a low density interconnect region (an LDI region) of the first semiconductor chip, and first bond pads (56L) located in a high density interconnect region (an HDI region) of the first semiconductor chip; a second semiconductor chip (50R) laterally adjacent to the first semiconductor chip and having a plurality of second bond pads (52R) located at a peripheral area of the second semiconductor chip, second solder balls (54R) located in an LDI area of the second semiconductor chip, and second bond pads (56R) located in an HDI area of the second semiconductor chip; and an alignment carrier (10) comprising a substrate and a plurality of solder balls located on the substrate, wherein a first set of the solder balls (14X) located on the substrate is aligned with and in contact with the first bond pads located on the peripheral area of the first semiconductor chip, and wherein a second set of the solder balls (14Y) located on the substrate is aligned with and in contact with the second bond pads located on the peripheral area of the second semiconductor chip; and wherein the solder balls of the alignment carrier have a dimension that is larger than those of the first solder balls present in the first LDI region of the first semiconductor chip and than those of the second solder balls present in the second LDI region of the second semiconductor chip.The assembly of claim 1, further comprising a window (16) located in a central portion of the substrate of the alignment carrier.The assembly of claim 2, further comprising an interconnect bridge (102) spanning the first semiconductor die and the second semiconductor die, the interconnect bridge connecting the HDI region of the first semiconductor die to the HDI of the second semiconductor die.The assembly of claim 3, wherein the interconnect bridge is comprised of silicon and the substrate of the alignment carrier is comprised of silicon or glass.The assembly of claim 1, wherein the first bond pads are at each corner of the first semiconductor die and the second bond pads are at each corner of the second semiconductor die.The assembly of claim 1, further comprising a support structure (100) attached to the first semiconductor die and to the second semiconductor die.A method comprising: providing a first structure comprising: a first semiconductor chip (50L) including a plurality of first bond pads (52L) located at a peripheral region of the first semiconductor chip, first solder balls (54L) located in a low density interconnect region (an LDI region) of the first semiconductor chip, and first bond pads (56L) located in a high density interconnect region (an HDI region) of the first semiconductor chip; a second semiconductor chip (50R) laterally adjacent to the first semiconductor chip, the second semiconductor chip including a plurality of second bond pads (52R) located at a peripheral area of the second semiconductor chip, second solder balls (54R) located in an LDI area of the second semiconductor chip, and second bond pads (56R) located in an HDI area of the second semiconductor chip; and an alignment carrier (10), the alignment carrier comprising a substrate and a plurality of solder balls located on the substrate, wherein a first set of the solder balls (14X) located on the substrate is aligned with and in contact with the first bond pads located on the peripheral area of the first semiconductor chip, and wherein a second set of the solder balls (14Y) located on the substrate is aligned with and in contact with the second bond pads located on the peripheral area of the second semiconductor chip; and wherein the solder balls of the alignment carrier have a dimension that is larger than those of the first solder balls present in the first LDI region of the first semiconductor chip and than those of the second solder balls present in the second LDI region of the second semiconductor chip; first attaching a support structure (100) to a back side of the first semiconductor chip and the second semiconductor chip; removing the alignment carrier so as to provide a second structure comprising the first semiconductor chip, the second semiconductor chip and the support structure; second attaching an interconnection bridge between the first semiconductor chip and the second semiconductor chip so as to provide a third structure including the first semiconductor chip, the second semiconductor chip, the support structure, and the interconnection bridge, the interconnection bridge connecting the HDI region of the first semiconductor chip to the HDI region of the second semiconductor chip; and third attaching a laminate (104) to the third structure.The method of claim 7, further comprising: removing the support structure from the third structure.The method of claim 7, wherein the third attaching comprises a bulk reflow of the first and second solder balls.The method of claim 7, wherein the plurality of first bond pads is formed at the same time as the first bond pads in the HDI area of the first semiconductor chip and the plurality of second bond pads is formed at the same time as the second bond pads in the HDI area of the second semiconductor chip.The method of claim 7, further comprising removing the support structure after the third application of the laminate.

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